CN108695331A - Memory and its programmed method, method for deleting and read method, electronic device - Google Patents

Memory and its programmed method, method for deleting and read method, electronic device Download PDF

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Publication number
CN108695331A
CN108695331A CN201710217698.6A CN201710217698A CN108695331A CN 108695331 A CN108695331 A CN 108695331A CN 201710217698 A CN201710217698 A CN 201710217698A CN 108695331 A CN108695331 A CN 108695331A
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CN
China
Prior art keywords
voltage
grid
memory
floating boom
characterized
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CN201710217698.6A
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Chinese (zh)
Inventor
赵祥富
简维廷
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中芯国际集成电路制造(北京)有限公司
中芯国际集成电路制造(上海)有限公司
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Priority to CN201710217698.6A priority Critical patent/CN108695331A/en
Publication of CN108695331A publication Critical patent/CN108695331A/en

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11517Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate
    • H01L27/11521Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors

Abstract

A kind of memory and its programmed method of present invention offer, method for deleting and read method, electronic device, the memory include:Semiconductor substrate;Floating boom, setting is on the semiconductor substrate;Tunnel oxide is arranged on the side wall of the floating boom;First choice grid and the second selection grid, be arranged parallel between the both sides of the floating boom, first choice grid and the floating boom and second selection grid and the floating boom between be isolated by the tunnel oxide.The present invention Memory Storage Unit area it is small, can unrestricted choice data write-in and erasing speed, data stable storage, useful life it is long.

Description

Memory and its programmed method, method for deleting and read method, electronic device

Technical field

The present invention relates to technical field of semiconductors, in particular to a kind of memory and its programmed method, method for deleting With read method, electronic device.

Background technology

Electrically Erasable Programmable Read-Only Memory (Electrically Erasable Programmable Read-Only Memory, abbreviation EEPROM), it is the storage chip that data are not lost after a kind of power down, it can on computers or special equipment Upper erasing has information, reprograms.EEPROM is nonvolatile memory, and flash-EEPROM therein is quickly grown. EEPROM ratios DRAM is complicated, therefore the integrated level of EEPROM is difficult to improve.

Traditional EEPROM data write-in erasing passes through the tunnel oxide (tunnel below floating boom (Floating gate) Oxide) window is realized, since the window area is limited, has fettered the speed of data write-in erasing.

Conventional flash memory (Flash) ETOX (EPROM Tunnel Oxide) technology is directly to pass through tunnel with charge in floating boom It wears oxide layer and tunnelling principle occurs to be written and wipe data.Since floating boom and tunnel oxide contact area are big, thus Flash The speed of ETOX storage units erasing write-in data is quickly.But since direct tunnelling is larger to the damage of tunnel oxide, repeatedly After erasing write-in, the charge of floating boom storage is easily gradually lost by injury region, and storage data failure, same EEPROM are ultimately caused Also there is similar deficiency.

Therefore, it is necessary to propose a kind of new memory, to solve the above technical problems.

Invention content

A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.

In view of the deficiencies of the prior art, one aspect of the present invention provides a kind of memory, including:

Semiconductor substrate;

Floating boom, setting is on the semiconductor substrate;

Tunnel oxide is arranged on the side wall of the floating boom;

First choice grid and the second selection grid are arranged parallel in the both sides of the floating boom, the first choice grid with it is described It is isolated by the tunnel oxide between floating boom and between second selection grid and the floating boom.

Further, the area on the surface of the first choice grid towards the side wall is less than or equal to the face of the side wall Product.

Further, the area on the surface of second selection grid towards the side wall is less than or equal to the face of the side wall Product.

Further, the first choice grid are by the spaced at least two sub- selection grids on the floating gate side walls It constitutes, and/or, second selection grid is by the spaced at least two sub- selection grid structures on the floating gate side walls At.

Further, further include gate dielectric, gate dielectric setting the floating boom, the first choice grid, Between second selection grid and the tunnel oxide and the surface of the semiconductor substrate.

Further, programming operation is carried out from the tunnel oxide of first choice grid side, and erasing operation is from described The tunnel oxide of second selection grid side carries out.

Further, further include:

Dielectric layer between grid is arranged on the surface of the floating boom;

Control gate is arranged between the grid on the surface of dielectric layer.

Further, further include:

Source electrode and drain electrode is separately positioned in the semiconductor substrate of the floating boom both sides, wherein the source electrode and the leakage Pole all has the first conduction type.

Further, it is additionally provided with the well region of the second conduction type, the source electrode and the leakage in the semiconductor substrate Pole is arranged in the well region.

Further aspect of the present invention provides a kind of programmed method of memory above-mentioned, including:

To an application first voltage in the first choice grid and second selection grid;

To another application second voltage in the first choice grid and second selection grid, wherein described first There are potential difference between voltage and the second voltage, electronics low one end of potential from first voltage and second voltage is injected into In the floating boom, to realize the programming.

Further, the numberical range of the first voltage is 6V~12V, the numberical range of the second voltage be 2V~ 5V。

Further, control gate, drain electrode and source electrode is floating.

Further aspect of the present invention provides a kind of method for deleting of memory above-mentioned, including:

To an application tertiary voltage in the first choice grid and second selection grid;

To another the 4th voltage of application in the first choice grid and second selection grid, wherein the third There are potential difference between voltage and the 4th voltage, the electronics that will be stored in the floating boom is electric from tertiary voltage and the 4th One end that potential is high in pressure removes, and realizes the erasing.

Further, the tertiary voltage is higher than the 4th voltage, and the numberical range of the tertiary voltage is 6V~12V, 4th voltage is 0V or negative voltage.

Further, the control gate, the drain electrode and the source electrode are floating.

Further aspect of the present invention provides a kind of read method of memory above-mentioned, and the memory includes being arranged described Control gate on floating boom, and the source electrode and drain electrode that is separately positioned in the semiconductor substrate of the floating boom both sides, the reading Method includes:

Cut-in voltage is applied to the control gate, 0V or negative voltage are applied to the source electrode, to drain electrode application the Five voltages, wherein the cut-in voltage and the 5th voltage are positive voltage, and the 5th voltage is electric less than unlatchings Pressure, to realize the reading.

Further, the first choice grid and second selection grid are floating.

Another aspect of the present invention also provides a kind of electronic device, and the electronic device includes memory above-mentioned.

Memory according to the present invention is arranged first choice grid and the second selection grid in the both sides of floating boom, and floats parallel It is isolated by the tunnel oxide being arranged on floating gate side walls between grid and selection grid, compared with traditional EEPROM, is effectively reduced Memory cell area, and it is possible to the window area of parallel selection grid is adjusted as needed, the write-in of unrestricted choice data and wiping Except speed;And due to both sides selection grid status equivalence, write-in can be carried out from the tunnel oxide of side selection grid, and erasing can To be carried out from the tunnel oxide of other side selection grid, avoids and write-in and erasing are repeated to same tunnel oxide, subtract The rate of slow tunnel oxide being damaged, to promote the useful life of memory;Therefore, memory of the invention storage is single Elemental area is small, can unrestricted choice data write-in and erasing speed, data stable storage, useful life it is long.

Description of the drawings

The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair Bright embodiment and its description, principle used to explain the present invention.

In attached drawing:

Fig. 1 shows the sectional view of the eeprom memory of an existing embodiment;

Fig. 2 shows the sectional views of the Flash cellular constructions of an existing embodiment;

Fig. 3 A show the vertical view of the memory of one embodiment of the present invention;

Fig. 3 B show the sectional view of the memory of one embodiment of the present invention, wherein Fig. 3 B are the AA ' in Fig. 3 A The sectional view that section is obtained;

Fig. 4 A show the sectional view when memory of one embodiment of the present invention is programmed;

Fig. 4 B show the sectional view when memory of one embodiment of the present invention is wiped;

Fig. 5 shows the IV curve graphs when reading memory cell data of an embodiment of the invention;

Fig. 6 shows the schematic diagram of the electronic device in one embodiment of the invention.

Specific implementation mode

In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into Row description.

It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here Embodiment.Disclosure will be made thoroughly and complete on the contrary, providing these embodiments, and will fully convey the scope of the invention to Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the areas Ceng He may be exaggerated.From beginning to end Same reference numerals indicate identical element.

It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly It is connected to " or " being directly coupled to " other elements or when layer, then element or layer between two parties is not present.It should be understood that although can make Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/ Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion Part, area, floor or part are represented by second element, component, area, floor or part.

Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with The relationship of other elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention further includes making With the different orientation with the device in operation.For example, if the device in attached drawing is overturn, then, it is described as " under other elements Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its It is orientated) and spatial description language as used herein correspondingly explained.

The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation, The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related Listed Items and institute There is combination.

It describes to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention Bright embodiment.As a result, it is contemplated that due to caused by such as manufacturing technology and/or tolerance from the variation of shown shape.Therefore, The embodiment of the present invention should not necessarily be limited to the specific shape in area shown here, but include due to for example manufacturing caused shape Shape deviation.For example, be shown as the injection region of rectangle its edge usually there is circle or bending features and/or implantation concentration ladder Degree, rather than the binary from injection region to non-injection regions changes.Equally, the disposal area can be led to by injecting the disposal area formed Some injections in area between the surface passed through when injection progress.Therefore, the area shown in figure is substantially schematic , their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.

In order to thoroughly understand the present invention, detailed structure will be proposed in following description, to illustrate proposition of the present invention Technical solution.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention can be with With other embodiment.

Fig. 1 shows the sectional view of the eeprom memory of an existing embodiment;Fig. 2 shows existing one The sectional view of the Flash cellular constructions of embodiment.

Wherein, traditional EEPROM as shown in Figure 1 includes:Form tunnel oxide on a semiconductor substrate, wherein tunnel The tunnel oxide window 101 that oxide layer includes relatively thin is worn, floating boom 102 is provided on tunnel oxide, in the floating boom It is provided with control gate 104 on 102, is provided with dielectric layer 103 between grid between control gate 104 and floating boom 102, dielectric layer between grid 103 optional ONO (oxide/nitride/oxide, oxide-nitride-oxide) dielectric layers, partly leading on the outside of floating boom It is additionally provided with selection grid 105 in body substrate, there is interval between selection grid and floating boom.Traditional EEPROM data write-in erasing passes through Tunnel oxide (tunnel oxide) window below floating boom (Floating gate) is realized, since the window area is limited, The speed of data write-in erasing is fettered.Tunnel oxide window by being written with after erasing operation, can be damaged for a long time (damage), the charge of floating boom storage is easily gradually lost by injury region, ultimately causes storage data failure.

Conventional flash memory as shown in Figure 2 includes:Gate dielectric 201 on a semiconductor substrate is set, is arranged in grid Floating boom 202 on dielectric layer 201 is arranged dielectric layer 203 between the grid on floating boom 202, and is arranged between grid on dielectric layer 203 Control gate 204.Conventional flash memory (Flash) ETOX (EPROM Tunnel Oxide) technology is directly logical with charge in floating boom It crosses tunnel oxide and tunnelling principle occurs to be written and wipe data.Since floating boom and tunnel oxide contact area are big, thus The speed of Flash ETOX storage units erasing write-in data is quickly.But due to direct tunnelling to the damage of tunnel oxide compared with Greatly, repeatedly after erasing write-in, the charge of floating boom storage is easily gradually lost by injury region, and storage data failure is ultimately caused.

Embodiment one

In order to solve aforementioned technical problem, a kind of memory is provided in the embodiment of the present invention, the memory mainly wraps It includes:

Semiconductor substrate;

Floating boom, setting is on the semiconductor substrate;

Tunnel oxide is arranged on the side wall of the floating boom;

First choice grid and the second selection grid are arranged parallel in the both sides of the floating boom, the first choice grid with it is described It is isolated by the tunnel oxide between floating boom and between second selection grid and the floating boom.

Memory according to the present invention is arranged first choice grid and the second selection grid in the both sides of floating boom, and floats parallel It is isolated by the tunnel oxide being arranged on floating gate side walls between grid and selection grid, compared with traditional EEPROM, is effectively reduced Memory cell area, and it is possible to the window area of parallel selection grid is adjusted as needed, the write-in of unrestricted choice data and wiping Except speed;And due to both sides selection grid status equivalence, write-in can be carried out from the tunnel oxide of side selection grid, and erasing can To be carried out from the tunnel oxide of other side selection grid, avoids and write-in and erasing are repeated to same tunnel oxide, subtract The rate of slow tunnel oxide being damaged, to promote the useful life of memory;Therefore, memory of the invention storage is single Elemental area is small, can unrestricted choice data write-in and erasing speed, data stable storage, useful life it is long.

Specifically, the memory construction of the present invention is described in detail below with reference to Fig. 3 A- Fig. 3 B, wherein Fig. 3 A are shown The vertical view of the memory of one embodiment of the present invention;Fig. 3 B show cuing open for the memory of one embodiment of the present invention View.

As an example, the memory of the present invention can be nonvolatile memory (NVM), specifically, storage of the invention Device is EEPROM, including:Semiconductor substrate 300, and the floating boom 302 that is arranged in the semiconductor substrate 300.

The semiconductor substrate 300 can be following at least one of the material being previously mentioned:Silicon, silicon-on-insulator (SOI), silicon (SSOI), stacking SiGe (S-SiGeOI), germanium on insulator SiClx on insulator are laminated on insulator (SiGeOI) and germanium on insulator (GeOI) etc..As an example, in the present embodiment, the constituent material of semiconductor substrate 300 Select monocrystalline silicon.

In one example, floating boom 302,302 covering part of the floating boom are additionally provided in the semiconductor substrate 300 The semiconductor substrate 300.

Wherein, the material of floating boom 302 can be any suitable material well known to those skilled in the art, such as semiconductor Material, preferably the material of the floating boom 302 includes polysilicon or the polysilicon of doping etc..

In one example, as shown in Figure 3B, it is provided with grid on the semiconductor substrate surface below the floating boom 302 Dielectric layer 301.

Optionally, ONO (oxide/nitride/oxide, oxide-nitride- can be selected in gate dielectric 301 Oxide) dielectric layer.Specifically, gate dielectric 301 can be oxidenitride oxide three layers of ONO sandwiches in total Structure, those skilled in the art is it should be understood that gate dielectric 301 or one layer of nitride or one layer of oxygen The insulation systems such as one layer of oxide are formed in compound or one layer of nitride.Wherein, the thickness of gate dielectric 301 can be It is needed to carry out reasonable set according to practical devices, be not particularly limited herein.

In one example, tunnel oxide 303 is provided on the side wall of the floating boom, wherein the tunnel oxide Layer 303 is located in the opposite two side walls of the floating boom.

Tunnel oxide 303 may include following any conventional dielectric:SiO2,SiON,SiON2And including calcium titanium Other similar oxides of mine type oxide.Wherein, silica can be selected in the material of tunnel oxide 303, and generation type uses Thermal oxidation method.The thickness of the tunnel oxide of formation is on the tens Izods right side, in one example, the thickness of the tunnel oxide It is 80 angstroms to 110 angstroms.Above-mentioned thickness range for other suitable thickness only as an example, be equally applicable to the present invention.

In one example, memory of the invention further includes:The parallel first choice being arranged in the both sides of the floating boom Grid 3041 and the second selection grid 3042, between first choice grid 3041 and the floating boom 302 and second selection grid 3042 Pass through the isolation of the tunnel oxide 303 namely the first choice grid and the second selection grid difference between the floating boom 302 It is arranged on the side of the tunnel oxide 303 of the floating boom both sides.

Further, area of 3041 and second selection grid 3042 of the first choice grid on the floating gate side walls can be with It is adjusted according to actual needs.

In one example, the area on the surface of 3041 side wall towards the floating boom 302 of the first choice grid is less than Or the area equal to the side wall, for example, the top surface of first choice grid 3041 can be made less than the top surface of the floating boom, then it is described The area of first choice grid 3041 is less than the area of the side wall of the floating boom 302 close with it, alternatively, can also make first The length of selection grid 3041 is less than the length of the floating boom, then the area of the first choice grid 3041 is less than close with it The area of the side wall of the floating boom 302.

In one example, the area on the surface of second selection grid, 3041 side wall towards the floating boom 302 is less than Or the area equal to the side wall, for example, the top surface of the second selection grid 3042 can be made less than the top surface of the floating boom, then it is described The area of second selection grid 3042 is less than the area of the side wall of the floating boom 302 close with it, alternatively, can also make second The length of selection grid 3042 is less than the length of the floating boom, then the area of second selection grid 3042 is less than close with it The area of the side wall of the floating boom 302.

Illustratively, first choice grid and the second selection grid can cover the entire side wall of floating boom, can also only cover The partial sidewall of floating boom, wherein when adjusting the area of first choice grid and the second selection grid, connect accordingly with two selection grids The area of tactile tunnel oxide may also change accordingly, and then realize the adjustment to tunnel oxide window area, that is, with choosing The tunnel oxide for selecting grid contact may be defined as tunnel oxide window, by adjusting the area of the tunnel oxide window, Can be with the write-in of unrestricted choice data and erasing speed, the bigger speed of area of usual tunnel oxide window is faster, and area is smaller, Speed is slower.

In one example, the first choice grid and second selection grid can be symmetrical arranged, alternatively, can also make The first choice grid of floating boom both sides and the area of the second selection grid are different, such as the area of one of selection grid is more than another The area of selection grid.

In one example, the first choice grid are by spaced at least two son on the floating gate side walls Selection grid is constituted, and/or, second selection grid is selected by spaced at least two son on the floating gate side walls Grid are constituted.

Specifically, the first choice grid 3041 and the material of second selection grid 3042 can use art technology Any suitable material known to personnel, such as either the polysilicon of doping or others are suitable as selection grid to polysilicon Material, in the present embodiment, the material of 3041 and second selection grid 3042 of the first choice grid includes polysilicon.

In one example, the gate dielectric 301 also further extends to the first choice grid of the floating boom both sides 3041 and second selection grid 3042 lower section, that is, gate dielectric 301 be arranged in the floating boom 302, the first choice grid 3041, between second selection grid 3042 and the tunnel oxide 303 and the surface of the semiconductor substrate 300.

Further, as shown in Figure 3A and Figure 3B, memory of the invention further include source electrode 3071 and drain electrode 3072, it is described Source electrode 3071 and drain electrode 3072 are separately positioned in the semiconductor substrate 300 of 302 both sides of the floating boom, the source electrode and the leakage Pole all has the first conduction type, such as the first conduction type is N-type, preferably, the source electrode 3071 and drain electrode 3072 are N-type The source electrode and drain electrode of impurity heavy doping.

In one example, the outer end of the source electrode 3071 extends to the semiconductor lining in 3041 outside of the first choice grid In bottom 300, the extension of the drain electrode 3072 extends in the semiconductor substrate 300 in second selection grid, 3042 outside.

In one example, the well region of the second conduction type is additionally provided in the semiconductor substrate 300, for example, p-type Well region, the source electrode 3071 and the drain electrode 3072 are arranged in the well region, and second conduction type and described first is led Electric type is opposite conduction type, for example, first conduction type is N-type, then second conduction type is p-type, or Person, first conduction type are p-type, and the second conduction type is N-type.It is mainly N with the first conduction type in the present embodiment The case where type, the second conduction type is p-type, the present invention will be described.

Further, memory of the invention further includes dielectric layer 305 between grid, and dielectric layer 305 is arranged in institute between the grid The surface of floating boom 302 is stated, moreover dielectric layer also extends to the tunnelling to 302 both sides of the floating boom between the grid The surface of oxide layer 303.

Optionally, ONO (oxide/nitride/oxide, oxide-nitride- can be selected in dielectric layer 305 between grid Oxide) dielectric layer.Specifically, dielectric layer 305 can be oxidenitride oxide three layers of ONO sandwiches in total between grid Structure, those skilled in the art is it should be understood that dielectric layer 305 may be one layer of nitride or one layer of oxygen between grid The insulation systems such as one layer of oxide are formed in compound or one layer of nitride.Wherein, the thickness of dielectric layer 305 can be between grid It is needed to carry out reasonable set according to practical devices, be not particularly limited herein.

Further, memory of the invention further includes control gate 306, and the setting of the control gate 306 is situated between the grid On the surface of electric layer 305.

Wherein, the control gate 306 covers the surface of dielectric layer 305 between grid corresponding with the floating boom 302 below.

In one example, the extending direction for defining the line between the source electrode and drain electrode is first direction, is partly being led The direction vertical with the first direction is second direction in the plane of body substrate, and the control gate extends along the second direction And across the floating boom.

Wherein, " across " refers between the grid on the floating boom 302 on the surface of dielectric layer 305 and the floating boom Do not form the first choice grid and the side wall of the second selection grid has been respectively formed on the control gate.

Illustratively, the material of control gate includes polysilicon, can also include any conductive material or semi-conducting material, example It such as include metal material.

The tunnel oxide of the memory of the present invention is arranged on floating gate side walls, and control gate is only used for reading data, added Voltage is smaller, therefore smaller to the damage of the gate dielectric of floating boom bottom, thus the hot carrier note of the memory of the present invention Enter effect (HCI), the useful life of Negative Bias Temperature Instability (NBTI) has significant increase.

Illustratively, various contacts are also respectively formed in the control gate, selection grid, the source electrode, the drain electrode The extractions such as control gate, selection grid, source electrode, drain electrode are realized the electricity with external power supply or external circuit by structure (not shown) Connection.

So far the explanation for completing the key member of the memory construction to the present invention, for complete memory construction, It is also possible that other part, does not do repeating one by one herein.

In conclusion memory according to the present invention, is arranged first choice grid and the second selection parallel in the both sides of floating boom Grid, and be isolated by the tunnel oxide being arranged on floating gate side walls between floating boom and selection grid, compared with traditional EEPROM, have Effect reduces memory cell area, and it is possible to the window area of parallel selection grid is adjusted as needed, unrestricted choice data Write-in and erasing speed;And due to both sides selection grid status equivalence, write-in can from the tunnel oxide of side selection grid into Row, erasing can carry out from the tunnel oxide of other side selection grid, avoid and write-in is repeated to same tunnel oxide And erasing, slow down the rate of tunnel oxide being damaged, to promote the useful life of memory;Therefore, of the invention to deposit Reservoir memory cell area is small, can unrestricted choice data write-in and erasing speed, data stable storage, useful life it is long.

Embodiment two

The present invention also provides the programmed method of the memory as described in previous embodiment one, method for deleting and reading sides Method.In the following, the programmed method, method for deleting and read method of memory are explained and are said with reference to figure 4A- Fig. 4 B and Fig. 5 It is bright, wherein Fig. 4 A show the sectional view when memory of one embodiment of the present invention is programmed;Fig. 4 B show this hair The sectional view when memory of a bright embodiment is wiped;Fig. 5 shows the reading of an embodiment of the invention IV curve graphs when memory cell data;

Specifically, memory of the invention can be nonvolatile memory (NVM), specifically, memory of the invention For EEPROM.

As an example, the programmed method of the memory of the present invention, including:

To an application first voltage in the first choice grid and second selection grid;

To another application second voltage in the first choice grid and second selection grid, wherein described first There are potential difference between voltage and the second voltage, electronics low one end of potential from first voltage and second voltage is injected into In the floating boom, electronics is stored in floating boom, to realize the programming.

In one example, the voltage value of first voltage can be more than second voltage, the numberical range of the first voltage For 6V~12V, for example, 6V, 7V, 8V, 9V, 10V, 11V, 12V etc., the numberical range of the second voltage is 2V~5V, for example, 2V, 3V, 4V, 5V etc., above-mentioned numberical range for other suitable voltages only as an example, be readily applicable to the present invention.

Further, when being programmed operation, control gate, drain electrode and source electrode is floating (floating).

In the present embodiment, as shown in Figure 4 A, first choice grid 3041 are applied with the low-voltage of such as 5V, to the second selection grid 3042 apply the high voltage of such as 12V, and control gate, drain electrode and source electrode is floating, and electronics is passed through from 3041 side of first choice grid The tunnel oxide 303 of the side is injected into floating boom 302, and electronics is stored in floating boom, to realize programming operation.

As an example, the present invention also provides a kind of method for deleting such as the memory in embodiment one, including:

To an application tertiary voltage in the first choice grid and second selection grid;

To another the 4th voltage of application in the first choice grid and second selection grid, wherein the third There are potential difference between voltage and the 4th voltage, the electronics that will be stored in the floating boom is electric from tertiary voltage and the 4th One end that potential is high in pressure removes, and realizes the erasing.

Further, the tertiary voltage is higher than the 4th voltage, the numberical range of the tertiary voltage be 6V~ 12V, for example, 6V, 7V, 8V, 9V, 10V, 11V, 12V etc., the 4th voltage is 0V or negative voltage.

Further, the control gate, the drain electrode and the source electrode are floating.

Specifically, in the present embodiment, as shown in Figure 4 B, the first choice grid are applied with the low-voltage of such as 0V, to institute State the high voltage that the second selection grid applies such as 12V, wherein there are potential difference between the low-voltage of 0V and the high voltage of 12V, with It will be removed from 3042 end of the second selection grid by electronics of the program storage in the floating boom 302, realize erasing operation.

Wherein, since first choice grid and the second selection grid are arranged parallel, both sides selection grid status is of equal value, write-in (namely Programming) it can be carried out from the tunnel oxide (such as tunnel oxide of first choice grid side) of side selection grid, erasing can be with It carries out, is avoided to same tunnelling from the tunnel oxide (such as tunnel oxide of the second selection grid side) of other side selection grid Write-in and erasing is repeated in oxide layer, slows down the rate of tunnel oxide being damaged, to promote the service life of memory Life.

As an example, the read method of the memory as described in previous embodiment one of the present invention, the memory packet Include the control gate of setting on the floating gate, and the source electrode being separately positioned in the semiconductor substrate of the floating boom both sides and leakage Pole, the read method include:

Cut-in voltage is applied to the control gate, 0V or negative voltage are applied to the source electrode, to drain electrode application the Five voltages, the 5th voltage are less than the cut-in voltage, wherein and the cut-in voltage and the 5th voltage are positive voltage, And the 5th voltage is less than the cut-in voltage, to realize the reading.

Wherein, cut-in voltage is the voltage for referring to that memory is made to open.

Further, the first choice grid and second selection grid are floating.

In the present embodiment, cut-in voltage can be the voltage value that memory can arbitrarily opened, specifically can basis The actual conditions of memory are reasonably selected.

Further, the value of the 5th voltage can be set according to the cut-in voltage of memory, and the 5th voltage is electric less than opening Pressure.

Read method through the invention, can be normally into the read operation of line storage.

Further, IV curve graphs when Fig. 5 shows the reading memory cell data of an embodiment of the invention, Wherein, the value that ordinate is Ids (source-drain current) in Fig. 5, abscissa indicate voltage, wherein Vsens indicates to read in abscissa Cut-in voltage when operation, VT0 indicate that the threshold voltage after erasing, VT indicate that the threshold voltage after programming, Vcs indicate gate-source Voltage, as seen from the figure, Vsens have crosspoint with curve, indicate that the memory cell after erasing can be opened and read electricity Ids is flowed, then the state of storage unit is " 1 ";And the memory cell after programming is since Vsens is not yet turned on less than VT, at this time Ids electric currents are very small, and the state of storage unit is " 0 ".

In conclusion can easily realize according to the method for the present invention the programming operation of memory, erasing operation and Read operation.

Embodiment three

The present invention also provides a kind of electronic devices, including the memory described in embodiment one.

The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV Any electronic product such as machine, VCD, DVD, navigator, Digital Frame, camera, video camera, recording pen, MP3, MP4, PSP is set Standby or any intermediate products for including circuit.The electronic device of the embodiment of the present invention, due to the use of above-mentioned storage Device, thus there is better performance.

Wherein, Fig. 6 shows the example of mobile phone handsets.Mobile phone handsets 500, which are equipped with, to be included in shell 501 Display portion 502, operation button 503, external connection port 504, loud speaker 505, microphone 506 etc..

The wherein described mobile phone handsets include the memory described in embodiment one, and the memory includes:

Semiconductor substrate;

Floating boom, setting is on the semiconductor substrate;

Tunnel oxide is arranged on the side wall of the floating boom;

First choice grid and the second selection grid are arranged parallel in the both sides of the floating boom, the first choice grid with it is described It is isolated by the tunnel oxide between floating boom and between second selection grid and the floating boom.

The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by The appended claims and its equivalent scope are defined.

Claims (18)

1. a kind of memory, which is characterized in that including:
Semiconductor substrate;
Floating boom, setting is on the semiconductor substrate;
Tunnel oxide is arranged on the side wall of the floating boom;
First choice grid and the second selection grid are arranged parallel in the both sides of the floating boom, the first choice grid and the floating boom Between and second selection grid and the floating boom between be isolated by the tunnel oxide.
2. memory as described in claim 1, which is characterized in that the face on the surface of the first choice grid towards the side wall Area of the product less than or equal to the side wall.
3. memory as claimed in claim 1 or 2, which is characterized in that the surface of second selection grid towards the side wall Area be less than or equal to the side wall area.
4. memory as described in claim 1, which is characterized in that the first choice grid are by the floating gate side walls Spaced at least two sub- selection grid is constituted, and/or, second selection grid is by the interval on the floating gate side walls At least two sub- selection grids being arranged are constituted.
5. memory as described in claim 1, which is characterized in that further include gate dielectric, the gate dielectric setting In the floating boom, the first choice grid, second selection grid
And between the tunnel oxide and the surface of the semiconductor substrate.
6. memory as described in claim 1, which is characterized in that the tunnelling of the programming operation from first choice grid side Oxide layer carries out, and erasing operation is carried out from the tunnel oxide of second selection grid side.
7. memory as described in claim 1, which is characterized in that further include:
Dielectric layer between grid is arranged on the surface of the floating boom;
Control gate is arranged between the grid on the surface of dielectric layer.
8. memory as described in claim 1, which is characterized in that further include:
Source electrode and drain electrode is separately positioned in the semiconductor substrate of the floating boom both sides, wherein the source electrode and the drain electrode are equal With the first conduction type.
9. memory as claimed in claim 8, which is characterized in that be additionally provided with the second conductive-type in the semiconductor substrate The well region of type, the source electrode and the drain electrode are arranged in the well region.
10. a kind of programmed method of memory as described in one of claim 1 to 9, which is characterized in that including:
To an application first voltage in the first choice grid and second selection grid;
To another application second voltage in the first choice grid and second selection grid, wherein the first voltage There are potential difference between the second voltage, electronics low one end of potential from first voltage and second voltage is injected into described In floating boom, to realize the programming.
11. programmed method as claimed in claim 10, which is characterized in that the numberical range of the first voltage is 6V~12V, The numberical range of the second voltage is 2V~5V.
12. programmed method as claimed in claim 10, which is characterized in that control gate, drain electrode and source electrode is floating.
13. a kind of method for deleting of memory as described in one of claim 1 to 9, which is characterized in that including:
To an application tertiary voltage in the first choice grid and second selection grid;
To another the 4th voltage of application in the first choice grid and second selection grid, wherein the tertiary voltage There are potential differences between the 4th voltage, will be stored in the electronics in the floating boom from tertiary voltage and the 4th voltage The high one end of potential removes, and realizes the erasing.
14. method for deleting as claimed in claim 13, which is characterized in that the tertiary voltage is higher than the 4th voltage, institute The numberical range for stating tertiary voltage is 6V~12V, and the 4th voltage is 0V or negative voltage.
15. method for deleting as claimed in claim 13, which is characterized in that the control gate, the drain electrode and the source electrode are equal It is floating.
16. a kind of read method of memory as described in one of claim 1 to 6, the memory includes being arranged described Control gate on floating boom, and the source electrode and drain electrode that is separately positioned in the semiconductor substrate of the floating boom both sides, feature exist In the read method includes:
Cut-in voltage is applied to the control gate, 0V or negative voltage are applied to the source electrode, the 5th electricity is applied to the drain electrode Pressure, wherein the cut-in voltage and the 5th voltage are positive voltage, and the 5th voltage is less than the cut-in voltage, To realize the reading.
17. read method as claimed in claim 16, which is characterized in that the first choice grid and second selection grid are equal It is floating.
18. a kind of electronic device, which is characterized in that the electronic device includes the storage as described in one of claim 1 to 9 Device.
CN201710217698.6A 2017-04-05 2017-04-05 Memory and its programmed method, method for deleting and read method, electronic device CN108695331A (en)

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