JPS6065576A - Semiconductor memory - Google Patents

Semiconductor memory

Info

Publication number
JPS6065576A
JPS6065576A JP58173199A JP17319983A JPS6065576A JP S6065576 A JPS6065576 A JP S6065576A JP 58173199 A JP58173199 A JP 58173199A JP 17319983 A JP17319983 A JP 17319983A JP S6065576 A JPS6065576 A JP S6065576A
Authority
JP
Japan
Prior art keywords
floating gate
drain
source
semiconductor memory
electric field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58173199A
Other languages
Japanese (ja)
Inventor
Shinji Sugaya
慎二 菅谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58173199A priority Critical patent/JPS6065576A/en
Publication of JPS6065576A publication Critical patent/JPS6065576A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7887—Programmable transistors with more than two possible different levels of programmation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/561—Multilevel memory cell aspects
    • G11C2211/5612—Multilevel memory cell with more than one floating gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To improve the memory capacity by dividing a floating gate into two regions, first applying a high electric field between a source and a drain, and then inverting the source and the drain to implanting lectrons to the floating gates, thereby storing two bits. CONSTITUTION:The floating gate of a semiconductor memory made of EPROM is divided into two regions as th first and second floating gates 41, 42. First, the left side is used as a source 10, the right side is used as a drain 20, a high electric field is applied, and information is written in the second floating gate 42, to which the high electric field is applied. Then, the right side is used as the source 10 and the left side is used as the drain 20, and information is similarly written. Since the two bits can be stored by dividing the floating gate into two regions, the memory capacity can be improved in an EPROM.

Description

【発明の詳細な説明】 ゛　発明の技術分野 本発明はＥＰＲＯＭのセルに２ビツトを蓄えるようにし
た半導体記憶装置に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor memory device in which two bits are stored in an EPROM cell.

従来技術と問題点 従来のＥＰＲＯＭ（Ｅｒａｓａｂｌｅ　Ｐｒｏｇｒａｍ
ｍａｂｌｅ　ＲＯＭ）のセルは、第１図に示すように、
ソース１、ドレイン２コントロールゲート３及びフロー
ティングゲート４から構成されている。第１図に示す従
来のＥＦＲＯＭのセルはソース１とドレイン２、コント
ロールゲート３間に高電界をかけ、高電界にょ）加速さ
れたホットニレブトロンＥをピンチオフ点Ｐの付近から
７０−ティングゲート４に注入し、セルトランジスタの
しきい値を変化させる。Conventional technology and problems Conventional EPROM (Erasable Program
As shown in FIG.
It consists of a source 1, a drain 2, a control gate 3, and a floating gate 4. In the conventional EFROM cell shown in Fig. 1, a high electric field is applied between the source 1, drain 2, and control gate 3. 4 to change the threshold voltage of the cell transistor.

しかし、上記従来のＥＰＲＯＭセルはフローティングゲ
ート４が１つの領域を占めるに過ぎず、情報が１ビツト
しか蓄えることができないので近年の情報量増大に対応
できず、記憶容量が少ないという問題点があった。However, in the above-mentioned conventional EPROM cell, the floating gate 4 occupies only one area and can only store one bit of information, so it cannot cope with the recent increase in the amount of information and has the problem of low storage capacity. Ta.

発明の目的 本発明の目的は、ＥＰＲＯＭのフローティングゲートを
２つの領域に分けることにょシ、２ビツトを蓄えられる
ようにして記憶容量の向上を高めることにある。OBJECTS OF THE INVENTION An object of the present invention is to increase the storage capacity by dividing the floating gate of an EPROM into two areas so that two bits can be stored.

発明の構成 本発明によれば、ＥＰＲＯＭセルのソース及びドレイン
とコントロールゲート間に挿入されているフローティン
グゲートを第１７０−テイングゲートと第２７０−テイ
ングゲートの２つの領域に分け、先ずソースとドレイン
間に高電界をかけて第１フローテイングゲートに電子を
注入し、次に該ソースとドレインを反転して第２フロー
テイングゲートに電子を注入することにより、ＥＰＲＯ
Ｍのセルに２ビツトを蓄えるようにした半導体記憶装置
が提供される。Structure of the Invention According to the present invention, the floating gate inserted between the source and drain of an EPROM cell and the control gate is divided into two regions, the 170th-type gate and the 270th-type gate. EPRO is performed by applying a high electric field to injecting electrons into a first floating gate, then inverting the source and drain and injecting electrons into a second floating gate.
A semiconductor memory device is provided in which 2 bits are stored in M cells.

発明の実施例 以下、本発明を実施例によシ添付図面を参照して説明す
る。Embodiments of the Invention The present invention will now be described by way of embodiments with reference to the accompanying drawings.

第２図は本発明に係る半導体記憶装置の構成図である。FIG. 2 is a configuration diagram of a semiconductor memory device according to the present invention.

本発明装置においては、ＥＰＲＯＭから成る半導体記憶
装置は図面から明らかなように、フローティングゲート
が２つの領域に分けられ第１フローテイングゲート４１
と第２７０−テイングゲート４２から構成されている。In the device of the present invention, as is clear from the drawings, the semiconductor memory device consisting of an EPROM has a floating gate divided into two regions, a first floating gate 41
and a 270th-teing gate 42.

先ず、第２図（１）のように、図面に向かって左側をソ
ース１０として、また右側をドレイン２０として高電界
をかけ、高電界をかけた第２フローテイングゲート４２
に、斜線を施したように、情報を書き込む。First, as shown in FIG. 2 (1), a high electric field is applied with the left side as the source 10 and the right side as the drain 20, and the second floating gate 42 with a high electric field applied thereto.
Write information as indicated by diagonal lines.

次に、右側をソース１０、左側をドレイン２０として上
記と同様に情報を書き込む。Next, information is written in the same way as above, with the source 10 on the right side and the drain 20 on the left side.

第３図は上記方法によシー形成された第１７０−テイン
グゲート４１と第２７０−テイングゲート４２の４つの
状態を示す図である。ソース１０、ドレイン２０を固定
して読み出しを行えば、第３図（１）　、　（２）　、
　（３）　、　（４）の順に大きくなる４通シのしきい
値を示し、２ビツトの情報を蓄え得る多値レベルセルと
して動作する。FIG. 3 is a diagram showing four states of the 170th-tinged gate 41 and the 270th-tinged gate 42 formed by the above method. If reading is performed with the source 10 and drain 20 fixed, the results will be as shown in Fig. 3 (1), (2),
It exhibits four thresholds that increase in the order of (3) and (4), and operates as a multi-level cell capable of storing 2-bit information.

発明の効果 上記の通シ、本発明によれば、７０−ティングゲートを
２つの領域に分けることによシ２ビットを蓄えることが
できるので、ＥＰＲＯＭにおける記憶容量を向上させる
ことができる。Effects of the Invention As described above, according to the present invention, two bits can be stored by dividing the 70-digit gate into two areas, thereby improving the storage capacity of the EPROM.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の半導体記憶装置の構成図、第２口拡本発
明に係る半導体記憶装置の構成図、第３図は本発明の効
果説明図である。 １０・・・ソース、２０・・・ドレイン、３０・・・コ
ントロールゲート、４１・・・第１７０−テイン／ケー
）、４２・・・第２フローテイングゲート。 特許出願人 富士通株式会社 特許出願代理人 弁理士　青　木　朗 弁理士　西舘和之 弁理士　内田幸男 弁理士　山　口　昭　之 第１図 第２図 第３図 （１）　４１ニーコロ＝コ〜４２ （２）　ロ二コロ２夕 （３）　四部コロ＝コ （４）　口＝コ図２コFIG. 1 is a block diagram of a conventional semiconductor memory device, a second enlarged block diagram of a semiconductor memory device according to the present invention, and FIG. 3 is a diagram illustrating the effects of the present invention. DESCRIPTION OF SYMBOLS 10... Source, 20... Drain, 30... Control gate, 41... 170th-TEIN/K), 42... Second floating gate. Patent Applicant Fujitsu Limited Patent Application Agent Akira Aoki Patent Attorney Kazuyuki Nishidate Patent Attorney Yukio Uchida Patent Attorney Akiyuki Yamaguchi Figure 1 Figure 2 Figure 3 (1) 41 Nicoro-Co~42 (2 ) Ronicoro 2 evenings (3) 4 parts Koro=ko (4) Mouth=ko figure 2ko

Claims (1)

【特許請求の範囲】[Claims] ＥＰＲＯＭセルのソース及びドレインとコントロールゲ
ート間に挿入されているフローティングゲートを第１フ
ローテイングゲートと第２ンローテイングゲートの２つ
の領域に分け、先ずソースとドレイン間に高電界をかけ
て第１７０−テイングゲートに電子を注入し、次に該ソ
ースとドレインヲ反転して第２フローテイングゲートに
電子を注入することにより、ＥＰＲＯＭのセルに２ビツ
トを蓄えるようにした半導体記憶装置。The floating gate inserted between the source and drain of the EPROM cell and the control gate is divided into two regions, a first floating gate and a second floating gate, and first, a high electric field is applied between the source and drain. - A semiconductor memory device in which two bits are stored in an EPROM cell by injecting electrons into a floating gate, then inverting the source and drain and injecting electrons into a second floating gate.
JP58173199A 1983-09-21 1983-09-21 Semiconductor memory Pending JPS6065576A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58173199A JPS6065576A (en) 1983-09-21 1983-09-21 Semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58173199A JPS6065576A (en) 1983-09-21 1983-09-21 Semiconductor memory

Publications (1)

Publication Number Publication Date
JPS6065576A true JPS6065576A (en) 1985-04-15

Family

ID=15955937

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58173199A Pending JPS6065576A (en) 1983-09-21 1983-09-21 Semiconductor memory

Country Status (1)

Country Link
JP (1) JPS6065576A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62109368A (en) * 1985-11-07 1987-05-20 Toshiba Corp Semiconductor memory
US5143860A (en) * 1987-12-23 1992-09-01 Texas Instruments Incorporated High density EPROM fabricaiton method having sidewall floating gates
EP0590319A2 (en) * 1992-10-02 1994-04-06 Matsushita Electric Industrial Co., Ltd. A non-volatile memory cell
FR2725309A1 (en) * 1994-09-13 1996-04-05 Mitsubishi Electric Corp NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
GB2300969A (en) * 1995-05-16 1996-11-20 Hyundai Electronics Ind Flash EEPROM cell
EP0851508A1 (en) * 1996-12-27 1998-07-01 SANYO ELECTRIC Co., Ltd. Non volatile semiconductor memory device using a transistor with two floating gates and method for manufacturing it
WO2001016959A1 (en) * 1999-09-01 2001-03-08 Infineon Technologies Ag Floating gate storage cell
WO2001027930A1 (en) * 1999-10-14 2001-04-19 Fujitsu Limited Nonvolatile memory for storing multibit data

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5632464B2 (en) * 1977-10-03 1981-07-28

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5632464B2 (en) * 1977-10-03 1981-07-28

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0341989B2 (en) * 1985-11-07 1991-06-25
JPS62109368A (en) * 1985-11-07 1987-05-20 Toshiba Corp Semiconductor memory
US5143860A (en) * 1987-12-23 1992-09-01 Texas Instruments Incorporated High density EPROM fabricaiton method having sidewall floating gates
EP0590319A2 (en) * 1992-10-02 1994-04-06 Matsushita Electric Industrial Co., Ltd. A non-volatile memory cell
EP0590319A3 (en) * 1992-10-02 1994-12-07 Matsushita Electric Ind Co Ltd A non-volatile memory cell.
US5708285A (en) * 1994-09-13 1998-01-13 Mitsubishi Denki Kabushiki Kaisha Non-volatile semiconductor information storage device
FR2725309A1 (en) * 1994-09-13 1996-04-05 Mitsubishi Electric Corp NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
GB2300969A (en) * 1995-05-16 1996-11-20 Hyundai Electronics Ind Flash EEPROM cell
GB2300969B (en) * 1995-05-16 2000-05-31 Hyundai Electronics Ind Method of reading a flash eeprom cell
EP0851508A1 (en) * 1996-12-27 1998-07-01 SANYO ELECTRIC Co., Ltd. Non volatile semiconductor memory device using a transistor with two floating gates and method for manufacturing it
US6097059A (en) * 1996-12-27 2000-08-01 Sanyo Electric Co., Ltd. Transistor, transistor array, method for manufacturing transistor array, and nonvolatile semiconductor memory
WO2001016959A1 (en) * 1999-09-01 2001-03-08 Infineon Technologies Ag Floating gate storage cell
WO2001027930A1 (en) * 1999-10-14 2001-04-19 Fujitsu Limited Nonvolatile memory for storing multibit data
US6614686B1 (en) 1999-10-14 2003-09-02 Fujitsu Limited Nonvolatile memory circuit for recording multiple bit information

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