JPH09180496A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor memory device in which the storage capacity of parity is reduced by half and in which redundancy is made efficient by a method wherein, when two bits are stored as one unit, the parity of one bit is stored with reference to four bits. SOLUTION: Every cell in cell blocks 1a to 1d stores one-bit data, the blocks 1a to 1d and the blocks 1c and 1d are used respectively as one segment, data which are constituted of two bits are stored in storage regions 10a, 10b in a buffer memory as data of a total of four bits. A parity generation circuit 11 generates parity by an EOR of every bit of four-bit data stored in the memory 10, and the parity is written into a selected cell in a parity cell block 6. Then, the parity stored here is read out to a data correction circuit 12 via a column decoder 5, and three-bit data other than a bit corresponding to a defective cell block in the four-bit data stored in the memory 10 and the EOR of a total of four bits of the parity to be read out from the block 6 are taken so as to be written into a bit corresponding to the defective cell block of the memory 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a flash memory type semiconductor memory device or a read only type semiconductor memory device (ROM).

[0002]

2. Description of the Related Art In recent years, there has been an increasing demand for large capacity floating gate nonvolatile semiconductor memory devices. In particular, the flash memory can be electrically erased without impairing the large capacity of the conventional EPROM,
There is a strong demand for large-capacity memory for replacing magnetic disks.

Flash memory, like EPROM,
Data is erased by writing data by hot-electron injection into the floating gate and drawing out accumulated charges from the floating gate using a tunnel current. In the erase operation, first, hot electrons are injected into the floating gates of all memory cells to write data "1", and then data is erased from all cells.

The NOR type flash memory cell stores data "0" and "1" in correspondence with two thresholds HVth and LVth of the enhancement MOS transistor. The state where negative charges are accumulated in the floating gate arranged between the control gate and the channel is “1”, and the state where negative charges are not accumulated is “0”. Two thresholds HV
th and LVth are, for example, about 7V and 3V.

When 0 V is applied to the source, 1 V is applied to the drain, and 5 V is applied to the control gate, if the MOS transistor is in the high threshold HVth state, it does not conduct, and the low threshold VLth.
If it is in the state of, it conducts. In this way, by applying a voltage between the high threshold value HVth and the low threshold value VLth to the control gate, the data stored in the MOS transistor can be read. In the cells not selected, the drain is floating and the control gate is 0V.

When writing data "1", 6V is applied to the selected drain and 12V is applied to the control gate. Electrons are in a hot state, penetrate through the oxide film on the channel, and are injected into the floating gate, and data "1" is written.

At the time of erasing, after writing data "1" to all cells, 0V is applied to the control gates of all cells, 12V is applied to the sources, and the drains are made floating.
The electrons accumulated in the control gate pass through the oxide film by the tunnel phenomenon and are extracted to the source.

In the memory cell array, the control gates of cells arranged in the same row (row) are connected to the same word line, and the drains arranged in the same column (column) are connected to the same bit line. Connected.

In such a flash memory, 2
One word line may short. If erasing is performed at this time, cells having a threshold value other than the predetermined threshold value may occur. That is, even if 12V is applied to the word line to write "1" in the cell of data "0", 0V is applied to the other short-circuited word lines. for that reason,
The voltage of the word line is not sufficiently high, and the memory cell short-circuited with the word line is insufficiently written.

Next, in order to erase the data of all cells, 0V is applied to all word lines (control gates) and 12 is applied to all sources.
V is applied. In a memory cell in which writing is insufficient, electrons are excessively extracted from the floating gate and become positively charged. This is called over-race (over-erasure).

When data "1" is to be written into the over-race-laced cell next time, the initial state is not 0 but a positive potential, and sufficient voltage cannot be applied to the word line, resulting in insufficient writing. . When the word line is short-circuited in this way, all the memory cells connected to the word line cannot be written.

When a memory cell undergoes over-race, the threshold value of its transistor becomes negative. The transistor of the memory cell that has caused the over-race is in a conductive state even when the word line is not selected and is 0 V, and a current flows through the bit line. Since a current flows through the bit line regardless of the threshold value of the cell to be read, other cells in the same column as the cell in which the over-birace has occurred cannot be read.

When a word line is short-circuited, all the cells connected to that word line undergo overbirace. Further, as described above, all the cells connected to the same bit line as the cell in which the over-birace has occurred cannot be read. That is, when the word line is short-circuited, all cells in the cell block cannot be read.

Therefore, as a redundancy method of the flash memory, it is considered to make the cell block redundant. The entire memory is divided into a plurality of cell blocks, and when a cell block has a defect, a redundant cell block is used. When performing parity redundancy in an 8-bit memory, one redundancy cell block is prepared for eight cell blocks. Therefore, in the case of an 8-Mbyte flash memory, 1-Mbyte redundant cell blocks are required.

[0015]

As described above, when the parity redundancy is performed, a redundant memory for 1 bit is required corresponding to the number of bits which is a unit of reading and writing. If the number of bits per unit decreases, the redundancy efficiency decreases.

An object of the present invention is to provide a semiconductor memory device capable of efficiently performing redundancy in cell block units.

[0017]

According to one aspect of the present invention, there are m segments (m is an integer of 2 or more) each including a plurality of storage areas for storing n-bit (n is a natural number) data. , A storage means in which one storage area in each segment is specified by a storage area selection signal input from the outside, and n bits corresponding to each of the m segments of the storage means, a total of n × m bits A buffer memory having a storage area, the buffer memory capable of transferring data between the storage area in each segment and the corresponding storage area in the buffer memory, and from each of the m segments of the storage means. A storage area for storing one parity for a total of n × m bits of data stored in m storage areas selected one by one corresponds to each storage area of the segment of the storage means. Stored in the parity storage means and n × m-bit data read from m storage areas selected one from each of the m segments of the storage means. There is provided a semiconductor memory device having a data correction unit that corrects data based on parity.

When reading data from a storage area having one segment, the data is transferred to the buffer memory not only from the segment to be read but also from the corresponding storage area of m segments. The data is corrected based on the data transferred to the buffer memory and the parity stored in the parity storage means. Of the corrected data, only the data portion of the segment to be read is taken out.

According to another aspect of the present invention, a segment selection signal is further input, and n × of the buffer memory.
There is provided a semiconductor memory device having an n-bit memory area corresponding to a segment specified by the segment selection signal in the m-bit memory area and an input / output control means for performing data transfer with the outside.

The input / output control means transfers only the data corresponding to the segment to be read out of the data stored in the buffer memory to the outside. According to another aspect of the present invention, the storage means includes n × m cell blocks each having a plurality of cells each storing 1-bit data, and each cell block corresponds to one bit of the buffer memory. Correspondingly, there is provided a semiconductor memory device in which one cell of each cell block is specified by the memory area selection signal.

The n cell blocks form one segment. Of the 1-bit data stored in each cell block, the data of the cell specified by the storage area selection signal is transferred to the corresponding bit of the buffer memory.

According to another aspect of the present invention, when the data correction means has a defective cell block in the n × m cell blocks, a defective cell block storage for storing the defective cell block. A semiconductor memory device including the means is provided.

According to another aspect of the present invention, the data correction means stores n × m data stored in the buffer memory.
Of the bit data, the (n × m−1) bit data excluding the bit corresponding to the defective cell block stored in the defective cell block storage means and the parity stored in the parity storage means Provided is a semiconductor memory device that reproduces data in a defective cell block based on the data.

According to another aspect of the present invention, there is further provided parity generating means for generating a parity based on the n × m bit data stored in the buffer memory and writing the generated parity in the parity storage means. A semiconductor memory device is provided.

The data to be written is temporarily stored in the buffer memory, and the parity is generated based on the data stored in the buffer memory. Since the data of a plurality of segments can be stored in the buffer memory at the same time, one parity can be generated for the data of a plurality of segments.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described by taking a semiconductor memory device that stores data in 2-bit units as an example.

FIG. 1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention. Cell blocks 1a to 1d each including a plurality of cells arranged in a grid are provided with word control circuits 2a to 2d for performing row selection control and bit control circuits 3a to 3d for performing column selection control. Each cell of the cell blocks 1a to 1d stores 1-bit data.

The cell blocks 1a and 1b form one segment, and the cell blocks 1c and 1d form another segment. Each segment stores 2-bit data.

FIG. 2 shows the structure of each cell block in more detail. The cell block 1 is a matrix of non-volatile memory cells and includes a large number of floating gate type memory cells Cij.

The memory cell C11 will be described as an example.
The source S of the MOS transistor having the floating gate FG is connected to the source line, and the drain D is connected to the bit line BL1. In addition, the control gate CG formed on the floating gate FG
Are connected to the word line WL1.

Bit line BL1 and word line WL1
Information can be written in or read from this memory cell C11 by controlling the voltage applied to the memory cell C11. The memory cells arranged in the row direction are connected to a common word line WL, and the drains D of the memory cells arranged in a column manner are connected to a common bit line BL.
Each word line WL is controlled by the word control circuit 2, and each bit line BL is controlled by the bit control circuit 3.

FIG. 3 is a plan view schematically showing a plane structure of the memory matrix as shown in FIG. A source region (source line) 21 continuous in the horizontal direction in the drawing is arranged, and a plurality of nonvolatile memory cells are connected between adjacent source regions 21. The drain region 24 is commonly used by two nonvolatile memory cells formed between the upper and lower source lines.

A floating gate electrode 23 is arranged in an electrically floating state on a channel region formed between the source line 21 and the drain region 24, and a control electrode (word line) 22 is arranged on the floating gate electrode 23 in the figure. It is arranged so as to extend in the direction. Bit lines (not shown) are arranged in the vertical direction in the drawing, and bit contact holes 25
Is connected to the drain region 24 via.

According to the structure of FIG. 3, a memory cell is formed in which word lines are arranged in the horizontal direction and bit lines are arranged in the vertical direction. The source line is arranged in parallel with the word line.

Returning to FIG. 1, the description will be continued. The row decoder 4 is connected to the word control circuit 2 of each cell block 1. The row decoder 4 receives the row address signal from the terminal 17 and decodes the row address signal. The decoded result is sent to the word control circuit 2 and one word line of each cell block 1 is selected.

The column decoder 5 is connected to the bit control circuit 3. The column decoder 5 receives the column address signal from the terminal 18 and decodes the column address signal. The decoded result is sent to the bit control circuit 3, and one bit line of each cell block 1 is selected.

The buffer memory 10 is connected to the bit control circuit 3 of each cell block via the sense amplifier 9 and the column decoder 5. The buffer memory 10 includes a 2-bit storage area 10a corresponding to the cell blocks 1a and 1b and a 2-bit storage area 10b corresponding to the cell blocks 1c and 1d, and stores a total of 4-bit data. That is, 1 for each segment
It has a storage area for the number of bits for a unit.

At the time of data reading, the data stored in the cell selected by the row address and column address signals is transferred to the buffer memory 10 via the column decoder 5 and the sense amplifier 9. At the time of data writing, the data stored in the buffer memory 10 is written to the selected cell via the sense amplifier 9 and the column decoder 5.

Out buffer (input / output control means) 14
Connects the buffer memory 10 to the input / output terminals 16a and 16b. The out buffer 14 receives the segment selection signal input from the terminal 19 and receives the buffer memory 10
Select one of the storage areas 10a and 10b of
Data transfer is performed between the selected storage area and the output terminals 16a and 16b.

The address distribution circuit 15 is connected to the terminals 17, 18 and 19. The address distribution circuit 15 generates a row address signal, a column address signal, and a segment selection signal based on the address signal input from the terminal 20.

A parity cell block 6 having the same structure as the cell block 1 is provided. The word control circuit 7 of the parity cell block 6 is connected to the row decoder 4 and controlled by the row decoder 4, and the bit control circuit 8 is connected to the column decoder 5 and controlled by the column decoder 5.

The parity generation circuit 11 is the buffer memory 1
Connected to 0. The parity generation circuit 11 takes the EOR of each bit of the 4-bit data stored in the buffer memory 10 to generate parity, and writes the parity in the selected cell of the parity cell block 6.

The data correction circuit 12 includes the column decoder 5
And the buffer memory 10. A defective cell block storage circuit 13 is connected to the data correction circuit 12. The defective cell block storage circuit 13 stores a defective cell block in advance when any of the cell blocks 1a to 1d is defective.

The parity stored in the selected cell of the parity cell block 6 is read out to the data correction circuit 12 via the column decoder 5. Data correction circuit 1
2 is 3 other than the bits corresponding to the defective cell block in the 4-bit data stored in the buffer memory 10.
EOR of a total of 4 bits of the bit data and the parity read from the parity cell block 6 is taken. The result is written in the bit corresponding to the defective cell block of the buffer memory 10.

Next, the write operation of the semiconductor memory device shown in FIG. 1 will be described. An address signal for selecting the cell blocks 1a and 1b is applied to the terminal 20 and data to be written is applied to the terminals 16a and 16b. Address distribution circuit 15
Sends a segment selection signal for selecting the cell blocks 1a and 1b to a terminal 19, and sends a row address signal and a column address signal to the terminals 17 and 18, respectively. The out buffer 14 writes the data given to the terminals 16a and 16b into the storage area 10a of the buffer memory 10.

Next, only the segment selection signal changes so as to select the cell blocks 1c and 1d, an address signal that does not change the row address signal and the column address signal is applied to the terminal 20, and the data to be written is supplied to the terminal 16.
a, 16b. The address distribution circuit 15 sends a segment selection signal for selecting the cell blocks 1c and 1d to a terminal 19, and a row address signal and a column address signal to the terminals 17 and 18, respectively. The out buffer 14 writes the data provided to the terminals 16a and 16b into the storage area 10b of the buffer memory 10.

The parity generation circuit 11 generates the parity of the 4-bit data stored in the buffer memory 10. The 4-bit data stored in the buffer memory 10 is written to the selected cells of the cell blocks 1a to 1d, and at the same time, the parity generated by the parity generation circuit 11 is set to the selected cells of the parity cell block 6. Write in. The data writing process to the defective cell block may or may not be performed.

Next, the read operation of the semiconductor memory device shown in FIG. 1 will be described by taking as an example the case of reading 2-bit data stored in the segment composed of the cell blocks 1a and 1b.

An address signal of an address to be read is given to the terminal 20. The address signal distribution circuit 15 sends a segment selection signal for selecting the cell blocks 1a and 1b to the terminal 19, and outputs a row address signal and a column address signal corresponding to the address to be read, respectively to the terminal 1.
Send to 7 and 18.

Not only the data of the selected cells of the cell blocks 1a and 1b, but also the data of the selected cells of the cell blocks 1c and 1d are read into the buffer memory 10. At the same time, the parity stored in the selected cell of the parity cell block 6 is read by the data correction circuit 12.

The data correction circuit 12 uses the buffer memory 1
Based on the parity read from the parity cell block 6 and 3 bits excluding the bit corresponding to the cell block stored in the defective cell block storage circuit 13 among the 4-bit data read out to 0 , Reproduce the data of the defective cell block. The reproduced data is written in the corresponding bit of the buffer memory 10. Out buffer 1
4 outputs the data stored in the storage area 10a of the buffer memory 10 to the input / output terminals 16a and 16b.

Similarly, when reading the data of the segment consisting of the cell blocks 1c and 1d, the data of the two segments are read out and the data of the defective cell block is reproduced based on the data of 4 bits in total.

As described above, in the redundant configuration shown in FIG.
When 2 bits are stored as one unit, 1 bit parity may be stored for 4 bits. The storage capacity of the parity can be halved compared to the conventional case of storing 1-bit parity with respect to 2-bit.

In the above embodiment, the case where the memory space is divided into two segments and stored is described, but it may be divided into three or more segments. For example, if 2 bits are stored as one unit and divided into 16 segments, 1-bit parity may be stored for 32 bits. Increasing the number of segments to be divided enables more efficient redundancy.

In the above embodiment, the case where two bits are stored as one unit has been described, but the number of bits in one unit is not limited to two. For example, 1 bit, 4 bits, 8 bits, 16 bits, 32 bits or the like may be stored as one unit.

When the number of bits per unit is n and the number of divisions of a segment is m, in the case of a combination of n and m such that n × m is 32, that is, (n, m) is (1,32),
(2,16), (4,8), (8,4), or (1
6 and 2), the cell block 1 of FIG.
The number of bits of the buffer memory 10 is 32.
By changing only the configuration of the out buffer 14,
The number of bits n per unit can be changed.

Although the flash memory has been described as an example in the above embodiment, a programmable ROM that cannot be erased once written, or an erasable E that can be erased by irradiation with ultraviolet light or the like.
It can also be applied to a PROM or the like.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0059]

As described above, according to the present invention,
Redundancy can be efficiently performed in units of cell blocks.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a cell block in the semiconductor memory device of FIG.

3 is a schematic plan view showing a planar configuration on a semiconductor chip of the cell block shown in FIG.

[Explanation of symbols]

 1 cell block 2 word control circuit 3 bit control circuit 4 row decoder 5 column decoder 6 parity cell block 7 word control circuit 8 bit control circuit 9 sense amplifier 10 buffer memory 11 parity generation circuit 12 data correction circuit 13 defective cell block storage circuit 14 Out buffer 15 Address signal distribution circuit 16a, 16b Input / output terminal 17, 18, 19, 20 Terminal 21 Source region 22 WL Word line 23 Floating gate electrode BL Bit line C Memory cell

Claims (6)

[Claims] 1. M segments (m is an integer of 2 or more) each including a plurality of storage areas for storing n-bit (n is a natural number) data, each of which is provided by a storage area selection signal input from the outside. Storage means for specifying one storage area in a segment; and a buffer memory having a storage area of n bits corresponding to each of the m segments of the storage means, a total of n × m bits, The buffer memory capable of transferring data between a storage area inside the buffer memory and a corresponding storage area inside the buffer memory, and m storage areas selected one from each of the m segments of the storage means. A storage area for storing one parity for a total of n × m bits of data to be stored,
Parity storage means provided corresponding to each storage area of the segment of the storage means, and n × m bits read from m storage areas selected one from each of the m segments of the storage means And a data correction means for correcting the data based on the parity stored in the parity storage means. 2. A segment selection signal is further input, and an n-bit storage area corresponding to a segment specified by the segment selection signal in the n × m-bit storage area of the buffer memory and data transfer to and from the outside. The semiconductor memory device according to claim 1, further comprising an input / output control unit for performing the above. 3. The storage means includes n × m cell blocks each having a plurality of cells each storing 1-bit data, each cell block corresponding to one bit of the buffer memory, 3. One cell of a cell block is specified by the storage area selection signal.
3. The semiconductor memory device according to claim 1. 4. The data correction means, when there is a defective cell block in the n × m cell blocks,
4. The semiconductor memory device according to claim 3, further comprising defective cell block storage means for storing the defective cell block. 5. The data correcting means removes the bit corresponding to the defective cell block stored in the defective cell block storage means from the n × m bit data stored in the buffer memory ( The semiconductor memory device according to claim 4, wherein the data of the defective cell block is reproduced based on the n × m−1) -bit data and the parity stored in the parity storage means. 6. A parity is generated based on n × m bit data stored in the buffer memory,
6. The semiconductor memory device according to claim 1, further comprising a parity generation unit that writes the generated parity in the parity storage unit.