WO2001016959A1 - Floating gate storage cell - Google Patents

Floating gate storage cell Download PDF

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Publication number
WO2001016959A1
WO2001016959A1 PCT/DE2000/003003 DE0003003W WO0116959A1 WO 2001016959 A1 WO2001016959 A1 WO 2001016959A1 DE 0003003 W DE0003003 W DE 0003003W WO 0116959 A1 WO0116959 A1 WO 0116959A1
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WO
WIPO (PCT)
Prior art keywords
sub
cells
floating gate
memory cell
cell
Prior art date
Application number
PCT/DE2000/003003
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German (de)
French (fr)
Inventor
Eric-Roger BRÜCKLMEIER
Andreas Kux
Ronald Kakoschke
Original Assignee
Infineon Technologies Ag
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Publication of WO2001016959A1 publication Critical patent/WO2001016959A1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7887—Programmable transistors with more than two possible different levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates to a floating gate memory cell for increased reliability requirements.
  • Non-volatile memory cells have a limited lifespan; their function can only be guaranteed for a number of reprogramming cycles. After that, you either fail completely or at least have severely restricted data storage properties.
  • the functionality of the entire circuit depends on the reliability of a single memory cell, for example when using a memory cell as a flag bit, which indicates whether a programming operation has been completed correctly or authorized. At the same time, this memory cell is subjected to a greater load, since this cell can also be reprogrammed with each programming or erasing process in the memory array.
  • the reliability of a given cell configuration can also be increased by using several cells that are monitored by a logic circuit. This variant cannot be used in security-relevant applications, since sensitive data must be read out of EEPRO (electrically erasible programmable read only memory) and routed through switching stages, which entails a security risk against external reading.
  • EEPRO electrically erasible programmable read only memory
  • the object of the present invention is to provide a floating gate memory cell which, with tolerable additional expenditure compared to conventional cells, significantly increases the reliability and is sufficiently secure against unwanted reading. This object is achieved with the floating gate memory cell with the features of claim 1. Refinements result from the dependent claim.
  • a plurality of channel regions are connected in series between a source connection and a drain connection, and a branched high-voltage feed line is provided for programming, with which the sub-cells with the programming voltage can be applied.
  • Figure 1 shows a detail from a memory cell according to the invention in supervision.
  • Figure 2 shows a larger section of the memory cell according to the invention in supervision.
  • FIG. 1 shows a small section of a series connection of a plurality of sub-cells between a source connection S and a drain connection D in the diagram in supervision.
  • Each sub-cell is provided with a floating gate 1.
  • the channel areas of the cell underneath are shown schematically as tunnel windows 2 in this example.
  • the floating gates 1 are covered by a common electrode shown in broken lines as a control gate 3.
  • Each channel area with a floating gate forms a sub-cell of the memory cell. If such a sub-cell fails, it becomes permanently conductive and thus short-circuits itself.
  • the resulting short circuit between the drain and the electrode of the floating gate opens the channel as soon as a positive potential at the drain Connection is present. Since a plurality of sub-cells are connected in series in the arrangement, which form a logical AND circuit, the cell between the source and drain only becomes conductive when all the sub-cells are conductive. If one or more sub-cells fail, the entire memory cell can be blocked by the remaining floating gates, which are all controlled together via the control gate 3. If one or more sub-cells fail, the remaining sub-cells continue to function as the memory cell, since the channel is already blocked by a single functioning floating gate. The reliability of the overall cell can be increased by increasing the number of sub-cells.
  • each sub-cell causes a drop in the programming voltage in the source-drain channel, i.e. between the connections of source S and drain D.
  • a high-voltage lead 4 is used with several leads to the sub-cells in order to be able to apply the programming voltage individually to the sub-cells.
  • two successive sub-cells are structured in opposite directions to one another in this example.
  • a supply line from the high-voltage supply line 4, as shown in FIG. 1. This ensures that the same programming voltage is applied to each sub-cell.
  • any number of sub-cells can therefore be connected in series. So that the current yield of the overall arrangement does not decrease too much, the channel area can be suitably widened, that is to say provided with a larger cross section.

Abstract

The invention relates to a series arrangement of several floating gates (1) between a source connection (S) and a drain connection (D). Two successive partial cells respectively are structured in an opposite direction in relation to each other and are provided with supply lines of a branched and switchable high voltage supply line (4) that allows to impinge all partial cells with a same programming voltage.

Description

Beschreibungdescription
Floating-Gate-SpeicherzelleFloating-gate memory cell
Die vorliegende Erfindung betrifft eine Floating-Gate- Speicherzelle für erhöhte Zuverlässigkeitsanforderungen.The present invention relates to a floating gate memory cell for increased reliability requirements.
Nichtflüchtige Speicherzellen haben eine begrenzte Lebensdauer; ihre Funktion kann nur für eine Anzahl von Umprogrammier- zyklen garantiert werden. Danach fallen Sie entweder ganz aus oder weisen zumindest stark eingeschränkte Datenhaltungseigenschaften auf. Bei bestimmten Anwendungen hängt die Funktionsfähigkeit der gesamten Schaltung von der Zuverlässigkeit einer einzigen Speicherzelle ab, etwa bei Verwendung einer Speicherzelle als Flag-bit, das anzeigt, ob ein Programmiervorgang korrekt abgeschlossen bzw. autorisiert ausgeführt wurde. Gleichzeitig erfährt diese Speicherzelle eine stärkere Belastung, da bei jedem Programmier- oder Löschvorgang im Speicherarray auch diese Zelle umprogrammiert werden kann. Es existieren bereits Zellen mit zwei Floating-Gates, die durch Reihenschaltung der Gates den logischen Zustand der Zelle bewahren, auch wenn eines der beiden Gates die Ladung verliert. Die Zuverlässigkeit einer gegebenen Zellkonfiguration läßt sich auch durch den Einsatz mehrerer Zellen, die mit einer Logikschaltung überwacht werden, erhöhen. Diese Variante kann bei sicherheitsrelevanten Anwendungen nicht eingesetzt werden, da sensible Daten aus dem EEPRO (electrically erasible programmable read only memory) ausgelesen und über Schaltstufen geführt werden müssen, was ein Sicherheitsrisiko gegen externes Auslesen mit sich bringt.Non-volatile memory cells have a limited lifespan; their function can only be guaranteed for a number of reprogramming cycles. After that, you either fail completely or at least have severely restricted data storage properties. In certain applications, the functionality of the entire circuit depends on the reliability of a single memory cell, for example when using a memory cell as a flag bit, which indicates whether a programming operation has been completed correctly or authorized. At the same time, this memory cell is subjected to a greater load, since this cell can also be reprogrammed with each programming or erasing process in the memory array. There are already cells with two floating gates that maintain the logic state of the cell by connecting the gates in series, even if one of the two gates loses its charge. The reliability of a given cell configuration can also be increased by using several cells that are monitored by a logic circuit. This variant cannot be used in security-relevant applications, since sensitive data must be read out of EEPRO (electrically erasible programmable read only memory) and routed through switching stages, which entails a security risk against external reading.
Aufgabe der vorliegenden Erfindung ist es, eine Floating- Gate-Speicherzelle anzugeben, die bei tolerierbarem Mehraufwand gegenüber herkömmlichen Zellen die Zuverlässigkeit we- sentlich erhöht und ausreichend sicher gegen unerwünschtes Auslesen ist. Diese Aufgabe wird mit der Floating-Gate-Speicherzelle mit den Merkmalen des Anspruches 1 gelöst. Ausgestaltungen ergeben sich aus dem abhängigen Anspruch.The object of the present invention is to provide a floating gate memory cell which, with tolerable additional expenditure compared to conventional cells, significantly increases the reliability and is sufficiently secure against unwanted reading. This object is achieved with the floating gate memory cell with the features of claim 1. Refinements result from the dependent claim.
Bei der erfindungsgemäßen Floating-Gate-Speicherzelle sind zwischen einem Source-Anschluß und einem Drain-Anschluß mehrere jeweils mit einem Floating-Gate versehene Kanalbereiche in Reihe geschaltet, und es ist für die Programmierung eine verzweigte HochspannungsZuleitung vorhanden, mit der die Teilzellen mit der Programmierspannung beaufschlagt werden können .In the floating gate memory cell according to the invention, a plurality of channel regions, each provided with a floating gate, are connected in series between a source connection and a drain connection, and a branched high-voltage feed line is provided for programming, with which the sub-cells with the programming voltage can be applied.
Die Erfindung wird erläutert anhand des in den beigefügten Figuren dargestellten Ausführungsbeispiels einer besonders bevorzugten Ausgestaltung.The invention is explained with reference to the embodiment of a particularly preferred embodiment shown in the attached figures.
Figur 1 zeigt ein Detail aus einer erfindungsgemäßen Speicherzelle in Aufsicht.Figure 1 shows a detail from a memory cell according to the invention in supervision.
Figur 2 zeigt einen größeren Ausschnitt aus der erfindungsgemäßen Speicherzelle in Aufsicht.Figure 2 shows a larger section of the memory cell according to the invention in supervision.
In Figur 1 ist im Schema in Aufsicht ein kleiner Ausschnitt aus einer Reihenschaltung mehrerer Teilzellen zwischen einem Source-Anschluß S und einem Drain-Anschluß D dargestellt. Jede Teilzelle ist mit einem Floating-Gate 1 versehen. Die darunter befindlichen Kanalbereiche der Zelle sind in diesem Beispiel als Tunnelfenster 2 schematisch eingezeichnet. Es ist hier auch eine Zelle ohne explizites Tunnelfenster, z. B. eine Flash-Zelle, verwendbar. Die Floating-Gates 1 werden von einer gestrichelt eingezeichneten gemeinsamen Elektrode als Kontroll -Gate 3 überdeckt. Jeder Kanalbereich mit einem Floating-Gate bildet eine Teilzelle der Speicherzelle. Beim Ausfall einer solchen Teilzelle wird diese dauerhaft leitend und schließt sich damit selbst kurz. Der entstehende Kurzschluß zwischen Drain und der Elektrode des Floating-Gate steuert den Kanal auf, sobald ein positives Potential am Drain- Anschluß anliegt. Da in der Anordnung eine Vielzahl von Teilzellen in Reihe geschaltet sind, die eine logische AND- Schaltung bilden, wird die Zelle zwischen Source und Drain nur dann leitend, wenn alle Teilzellen leitend sind. Beim Ausfall einer oder mehrerer Teilzellen kann die gesamte Speicherzelle durch die verbleibenden Floating-Gates gesperrt werden, die alle gemeinsam über das Kontroll-Gate 3 angesteuert werden. Beim Ausfall einer oder mehrerer Teilzellen tragen daher die verbleibenden Teilzellen die Funktion der Spei- cherzelle weiter, da der Kanal bereits durch ein einziges funktionierendes Floating-Gate gesperrt wird. Durch Erhöhung der Anzahl der Teilzellen kann die Zuverlässigkeit der Gesamtzelle erhöht werden.FIG. 1 shows a small section of a series connection of a plurality of sub-cells between a source connection S and a drain connection D in the diagram in supervision. Each sub-cell is provided with a floating gate 1. The channel areas of the cell underneath are shown schematically as tunnel windows 2 in this example. There is also a cell here without an explicit tunnel window, e.g. B. a flash cell can be used. The floating gates 1 are covered by a common electrode shown in broken lines as a control gate 3. Each channel area with a floating gate forms a sub-cell of the memory cell. If such a sub-cell fails, it becomes permanently conductive and thus short-circuits itself. The resulting short circuit between the drain and the electrode of the floating gate opens the channel as soon as a positive potential at the drain Connection is present. Since a plurality of sub-cells are connected in series in the arrangement, which form a logical AND circuit, the cell between the source and drain only becomes conductive when all the sub-cells are conductive. If one or more sub-cells fail, the entire memory cell can be blocked by the remaining floating gates, which are all controlled together via the control gate 3. If one or more sub-cells fail, the remaining sub-cells continue to function as the memory cell, since the channel is already blocked by a single functioning floating gate. The reliability of the overall cell can be increased by increasing the number of sub-cells.
Dabei muß allerdings sichergestellt werden, daß die Teilzellen effizient programmiert und gelöscht werden können. Jede Teilzelle verursacht einen Abfall der Programmierspannung im Source-Drain-Kanal , das heißt zwischen den Anschlüssen von Source S und Drain D. Um zu vermeiden, daß nur eine sehr kleine Anzahl von Teilzellen hintereinander geschaltet werden kann, weil anderenfalls die ProgrammierSpannung für die in Reihe nachgeschalteten Teilzellen nicht mehr ausreicht, wird erfindungsgemäß eine HochspannungsZuleitung 4 mit mehreren Zuleitungen zu den Teilzellen verwendet, um die Teilzellen individuell mit der Programmierspannung beaufschlagen zu können.However, it must be ensured that the sub-cells can be programmed and deleted efficiently. Each sub-cell causes a drop in the programming voltage in the source-drain channel, i.e. between the connections of source S and drain D. In order to avoid that only a very small number of sub-cells can be connected in series, because otherwise the programming voltage for the in Row downstream sub-cells is no longer sufficient, according to the invention a high-voltage lead 4 is used with several leads to the sub-cells in order to be able to apply the programming voltage individually to the sub-cells.
Dazu sind in diesem Beispiel jeweils zwei aufeinanderfolgende Teilzellen gegensinnig zueinander strukturiert. Dazwischen befindet sich jeweils eine Zuleitung von der HochspannungsZuleitung 4, wie das in Figur 1 dargestellt ist. So wird gewährleistet, daß jede Teilzelle mit der gleichen Programmierspannung beaufschlagt wird. Bei der erfindungsgemäßen Speicherzelle lassen sich daher beliebig viele Teilzellen in Reihe schalten. Damit die Stromergiebigkeit der Gesamtanordnung nicht zu stark absinkt, kann der Kanalbereich geeignet aufgeweitet, das heißt mit einem größeren Querschnitt verse- er p-For this purpose, two successive sub-cells are structured in opposite directions to one another in this example. In between there is a supply line from the high-voltage supply line 4, as shown in FIG. 1. This ensures that the same programming voltage is applied to each sub-cell. In the memory cell according to the invention, any number of sub-cells can therefore be connected in series. So that the current yield of the overall arrangement does not decrease too much, the channel area can be suitably widened, that is to say provided with a larger cross section. he p-
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Claims

Patentansprüche claims
1. Floating-Gate-Speicherzelle mit einem Source-Anschluß, einem Drain-Anschluß, mit einem mit einem Floating-Gate (1) versehenen Kanalbereich (2), mit einem Kontroll-Gate (3) zur Ansteuerung und mit einer schaltbaren Hochspannungszuleitung (4) , mit der die Zelle mit einer Programmierspannung beaufschlagt werden kann, dadurch gekennzeichnet, daß mehrere mit Floating-Gates (1) versehene Kanalbereiche oder Abschnitte eines Kanalbereiches als Teilzellen in Reihe hintereinander zwischen dem Source-Anschluß und dem Drain-Anschluß angeordnet sind und daß die HochspannungsZuleitung (4) in mehrere Zuleitungen verzweigt ist, mit denen jeweils mindestens zwei Teilzellen mit der ProgrammierSpannung beaufschlagt werden können.1. Floating gate memory cell with a source connection, a drain connection, with a channel region (2) provided with a floating gate (1), with a control gate (3) for actuation and with a switchable high-voltage supply line ( 4) with which a programming voltage can be applied to the cell, characterized in that a plurality of channel regions or sections of a channel region provided with floating gates (1) are arranged in series as sub-cells between the source connection and the drain connection and that the high-voltage supply line (4) is branched into a plurality of supply lines, each of which can be used to apply the programming voltage to at least two sub-cells.
2. Floating-Gate-Speicherzelle nach Anspruch 1, bei der zwei aufeinanderfolgende Teilzellen gegensinnig zueinander strukturiert sind und bei der die Zuleitungen, in die die HochspannungsZuleitung (4) verzweigt ist, jeweils zu zwei Teilzellen geführt sind. 2. Floating gate memory cell according to claim 1, in which two successive sub-cells are structured in opposite directions to one another and in which the feed lines into which the high-voltage feed line (4) is branched are each led to two sub-cells.
PCT/DE2000/003003 1999-09-01 2000-09-01 Floating gate storage cell WO2001016959A1 (en)

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DE19941664A DE19941664A1 (en) 1999-09-01 1999-09-01 Floating gate memory cell
DE19941664.8 1999-09-01

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US5159570A (en) * 1987-12-22 1992-10-27 Texas Instruments Incorporated Four memory state EEPROM
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EP0903749A2 (en) * 1997-09-18 1999-03-24 SANYO ELECTRIC Co., Ltd. Nonvolatile semiconductor memory device

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JPH0793017B2 (en) * 1987-04-24 1995-10-09 株式会社東芝 Non-volatile semiconductor memory
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JPS56126974A (en) * 1980-03-11 1981-10-05 Chiyou Lsi Gijutsu Kenkyu Kumiai Semiconductor device
JPS6065576A (en) * 1983-09-21 1985-04-15 Fujitsu Ltd Semiconductor memory
US5021999A (en) * 1987-12-17 1991-06-04 Mitsubishi Denki Kabushiki Kaisha Non-volatile semiconductor memory device with facility of storing tri-level data
US5159570A (en) * 1987-12-22 1992-10-27 Texas Instruments Incorporated Four memory state EEPROM
DE19612676A1 (en) * 1996-03-29 1997-10-02 Siemens Ag Highly integrated, non-volatile semiconductor storage cell
EP0903749A2 (en) * 1997-09-18 1999-03-24 SANYO ELECTRIC Co., Ltd. Nonvolatile semiconductor memory device

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