JPS56126974A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS56126974A
JPS56126974A JP3070480A JP3070480A JPS56126974A JP S56126974 A JPS56126974 A JP S56126974A JP 3070480 A JP3070480 A JP 3070480A JP 3070480 A JP3070480 A JP 3070480A JP S56126974 A JPS56126974 A JP S56126974A
Authority
JP
Japan
Prior art keywords
gate
fetq1
floating
fgn
misfet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3070480A
Other languages
Japanese (ja)
Inventor
Takashi Matsumoto
Takaharu Nawata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP3070480A priority Critical patent/JPS56126974A/en
Publication of JPS56126974A publication Critical patent/JPS56126974A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7887—Programmable transistors with more than two possible different levels of programmation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/561—Multilevel memory cell aspects
    • G11C2211/5612—Multilevel memory cell with more than one floating gate

Abstract

PURPOSE:To identify the channel length distribution of a hot carrier trapped in the gate insulator of an MISFET by forming the MISFET in which a gate electrode is connected to the floating gate thereof. CONSTITUTION:An MISFETQ0 having a plurality of floating gates FG1-FGn and MISFETQ1-Q2 in which gate electrodes are connected to the gates FG1-FGn are formed. With such a configuration a gate voltage is effectively applied to the gate electrodes of the FETQ1-Qn in accordance with the channel length distribution of the hot carriers. Then, the gate voltage can be identified by examining, for example, the drain current of the FETQ1-Qn, and the number of the hot carriers trapped to the floating gate can be obtained by the capacity of the gate insulating films of the FETQ1-Qn and the gate voltages.
JP3070480A 1980-03-11 1980-03-11 Semiconductor device Pending JPS56126974A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3070480A JPS56126974A (en) 1980-03-11 1980-03-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3070480A JPS56126974A (en) 1980-03-11 1980-03-11 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS56126974A true JPS56126974A (en) 1981-10-05

Family

ID=12311033

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3070480A Pending JPS56126974A (en) 1980-03-11 1980-03-11 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS56126974A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001016959A1 (en) * 1999-09-01 2001-03-08 Infineon Technologies Ag Floating gate storage cell

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001016959A1 (en) * 1999-09-01 2001-03-08 Infineon Technologies Ag Floating gate storage cell

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