479331 A7 B7 6992twf. doc/006 五、發明說明（/) (請先閱讀背面之注意事項再填寫本頁) 本發明是有關一種半導體元件（Semiconductor Device) 的結構與製造方法，且特別是有關一種雙位元非揮發性記 憶體（Double-bit N〇n-Y〇latile 滅emory (NVM))的結構與製造 方法。 非揮發1、史I己憶體（NVM)是一種速度快、體積小、省電 且不怕振動的永久儲存媒體，故其應用甚爲廣泛’其中最 主要的種類即是快閃記憶體(Flash Memory)，其特色爲資料 係一塊一塊（Block by Block)地抹除，而可以節省抹除操作 所需之時間。 _線· 傳統非揮發性記憶胞的結構請參照第1圖。如第1圖 所示，基底100上有一堆疊閘結構110，且堆疊閘結構110 兩側基底100中有源/汲極區120，此堆疊閘結構110包含 由下而上堆疊之穿隧氧化層（Tunnel 0xide)112、浮置閘極 (Floating Gate)114、閘間介電層116與控制閘極（Control Gate)118。這種記憶胞在程式化時係將電子注入浮置閘極 114中，而抹除時係於控制閘極118上加高負電壓，以將 電子由浮置閘極114中排除。 經濟部智慧財產局員工消費合作社印製 然而，爲使電子能完全地被抹除，上述習知非揮發性 記憶胞在抹除操作時很容易發生過度抹除(over-erase)的現 象，亦即由浮置閘極114排除之電子過多，使得浮置閘極 114帶有正電荷的現象。當正電荷量過多時浮置閘極114 下方之基底100中的通道區即會反轉，並使通道一直保持 在導通的狀態，而在讀取資料時造成誤判。爲此，習知的 解決方法即是形成第2圖所示之分離閘結構（Split-Gate 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 479331 A7 B7 6992twf. doc/006 五、發明說明（乙）479331 A7 B7 6992twf. Doc / 006 V. Description of the Invention (/) (Please read the precautions on the back before filling out this page) The present invention relates to the structure and manufacturing method of a semiconductor device, and more particularly to a semiconductor device Structure and manufacturing method of Double-bit Non-volatile Memory (NVM). Non-volatile 1. History I Memory (NVM) is a fast, small, power-saving, and permanent storage medium that is not afraid of vibration, so it is widely used. 'The most important type is flash memory (Flash Memory) is characterized in that the data is erased block by block, which can save the time required for the erase operation. _Line · Please refer to Figure 1 for the structure of traditional non-volatile memory cells. As shown in FIG. 1, there is a stacked gate structure 110 on the substrate 100, and the active / drain regions 120 in the substrate 100 on both sides of the stacked gate structure 110. The stacked gate structure 110 includes a tunnel oxide layer stacked from bottom to top. (Tunnel 0xide) 112, floating gate 114, inter-gate dielectric layer 116, and control gate 118. Such a memory cell injects electrons into the floating gate 114 during programming, and applies a high negative voltage to the control gate 118 during erasing to exclude electrons from the floating gate 114. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. However, in order to completely erase the electrons, the above-mentioned conventional non-volatile memory cells are prone to over-erase during the erasing operation. That is, too many electrons are excluded by the floating gate 114, so that the floating gate 114 has a positive charge. When the amount of positive charge is too much, the channel region in the substrate 100 under the floating gate 114 will be reversed, and the channel will always be kept in a conductive state, which will cause misjudgment when reading data. For this reason, the conventional solution is to form the split gate structure shown in Figure 2 (Split-Gate. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 479331 A7 B7 6992twf. Doc / 006 V. Description of Invention (B)
Structure)210。如第2圖所示，基底200上具有分離聞結構 210，且分離閘結構210兩側基底200中有源/汲極區220， 此分離閘結構210包含由下而上堆疊之穿隧氧化層212、 浮置閘極214、閘間介電層216與控制閘極218，以及由控 制閘極218延伸至浮置閘極214側邊的轉移閘極(Transfer Gate)218a。因爲轉移閘極218a下方基底200中的通道必須 在控制閘極218/轉移閘極218a上加電壓時才會打開，故 即使浮置閘極214下方通道因過度抹除而持續打開，此記 憶胞仍能在非操作狀態下保持不導通的狀態，而得以防止 資料之誤判。 雖然分離閘結構210之設計能防止因過度抹除所產生 的誤判問題，但其多出之轉移閘極218a卻需佔用額外的 面積，而不利於元件的縮小化。此外，如第2圖所示，由 於在分離閘結構210中控制閘極218與轉移閘極218a二者 相加之寬度與浮置閘極214不同，故浮置閘極214與控制j 閘極218/轉移閘極218a必須分別以兩次微影蝕刻製程來 定義，因此轉移閘極218a之寬度，以及控制閘極 移閘極218a與浮置閘極214之重疊面積皆容易產生目吳M， 使得各記憶胞之電性不一致，從而增加操作時的困難度。 本發明提出一種雙位元非揮發性記憶體的結構， 記憶體之型態例如爲快閃記憶體，且此種記憶體中儲存每 一個位元所需之面積小於採用分離閘結構設計者，但同時 具有防止過度抹除問題的功能。此結構包含一基底、隔離 層、位元線、堆疊閘結構、摻雜區、源/汲極區與字元線。 4 本紙張尺度適用中國國家標準（CNS)A4規格（2.10 x 297公釐） (請先閱讀背面之注音？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -1 --------訂------- i-線！_---------------------- 479331 69 92twf. doc/00 6 _B7_ 五、發明說明（$ ) (請先閱讀背面之注意事項再填寫本頁) 其中，各隔離層係位在基底上，且互相平行；各位元線之 走向係與隔離層垂直，從而圍出一格狀單位陣列；堆疊閘 結構係以兩個爲一組位於一個格狀單位中，且每一個格狀 單位之二堆疊閘結構的連線方向係與隔離層之走向平行， 其中每一個堆屬閘結構皆包含一浮置閘極與其上之一控制 閘極；摻雜區係位於每一格狀單位之二堆疊閘結構之間的 基底中；源/汲極區之摻雜型態與摻雜區相同，且係位於各 格狀單位之間的基底中；字元線係位於堆疊閘結構上方， 且走向與位元線垂直，而每一個格狀單位內之二控制閘極 係分別與相鄰之二條字元線電性連接。 經濟部智慧財產局員工消費合作社印製 本發明並提出一種雙位元非揮發性記憶體的製造方 法，其係用來製造上述本發明之雙位元非揮發性記憶體結 構。此製造方法步驟如下：首先於基底上形成隔離層，再 於基底上形成一多層結構，其係由從下而上堆疊之一穿隧 層、第一導體層、閘間介電層與第二導體層所構成。接著 定義此多層結構以形成數個條狀多層結構，其走向係與隔 離層垂直，且其中每相鄰二條狀多層結構係區分爲一條狀 單位。接著在各條狀單位之間的基底上形成源/汲極區與位 元線，並在每一條狀單位之二條狀多層結構之間形成數個 摻雜區，其中源/汲極區之摻雜型態與摻雜區相同，而各位 元線係與隔離層圍出數個格狀單位。接著定義各條狀多層 結構以形成數個堆疊閘結構，使得每一格狀單位皆具有兩 個堆疊閘結構，其中每一個堆疊閘結構皆包含由第一導體 層所得之一浮置閘極，以及由第二導體層所得之一控制閘 5 本紙張尺度適用中國國家標準（CNS)Al規格（210 X 297公釐) 479331 A7 B7 6992twf. doc/0 06 五、發明說明（外） 極。然後在堆疊閘結構上方形成數條字元線，其走向係與 各位元線垂直，且同一格狀單位之二控制閘極係分別與相 (請先閱讀背面之注意事項再填寫本頁) 鄰二條字元線電性連接。 在上述本發明之雙位元非揮發性記憶體的製造方法 中，位元線的製造方法可分爲兩種，其一是形成埋入式位 元線，其二則是形成位在源/汲極區上且跨越隔離層的位元 線，這兩種方法將在以下本發明之實施例中分別說明，·且 由這兩種方法所得之結構亦可由說明與圖式中得見。 另外，在上述本發明之雙位元非揮發性記憶體結構 中，任一格狀單位內之二堆疊閘結構與其間之一摻雜區、 以及此格狀單位兩側之二源/汲極區合爲一記憶單元，其中 二堆疊閘結構之二控制閘極係分別與相鄰兩條字元線電性 連接，二源/汲極區分別與相鄰兩條位元線電性連接，且源 /汲極區之摻雜型態與二堆疊閘結構之間的摻雜區相同。此 記憶單元之程式化與讀取方法亦將在以下本發明之實施例 中提及，以與習知技藝之非揮發性記憶胞比較。 經濟部智慧財產局員工消費合作社印製 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文中特舉二實施例，並配合所附圖式，作詳細說明如下： 圖式之簡單說明： 第1圖所繪示爲習知堆疊閘設計之非揮發性記憶胞； 第2圖所繪示爲習知分離閘設計之非揮發性記憶胞； 第3〜11圖所繪示爲本發明第一實施例中，採用第一 種字元線製作方法之雙位元非揮發性記憶體的製程剖面 圖’其中爲顯示淸楚起見，各圖所對應之剖面不盡相同； 6 本紙張k度適用中國國家標準（CNS)A4規格（2〗〇 X 297公爱） 479331 A7 B7 6992twf. doc/00 6 五、發明說明（f) 第12圖所繪之剖面圖顯示本發明第一實施例之雙位 元非揮發性記憶體製程的第二種字元線製作方法； 第 3A、5A、6A、7A、9A、11A、12A 圖分別爲第 3、 5、6、7、9、11、12圖之上視圖； 第11B _所繪示爲第11A圖之切線V-V’的剖面圖， 且第12B圖所繪示爲第12A圖之切線ΙΙ-ΙΓ的剖面圖； 第13〜15圖所繪示爲本發明第二實施例之雙位元非揮 發性記憶體的製造方法中，源/汲極區與位元線的製程，其 中第13圖係接續在多層結構形成步驟（對應第一實施例之 第4圖）後，且第15圖後接堆疊閘結構定義步驟(對應第一 實施例之第9A與9圖）； 第13A、14A圖分別爲第13、14圖之上視圖； 第16與17圖分別繪示由本發明實施例之第一種與第 二種字元線製作方法所得之雙位元非揮發性記憶體的電路 圖； 第18圖所繪示爲由本發明實施例所得之非揮發性記 憶單元的結構； 第19圖所繪示爲由本發明實施例所得之非揮發性記 憶單元的一種程式化方法；以及 第20圖所繪示爲由本發明實施例所得之非揮發性記 憶單元的讀取方法。 圖式之標號說明： 100、200、300 :基底（Substrate) 110、310b、310c/d :堆疊閘結構(Stacked Gate Structure) 7 本紙張尺度適用中國國家標準(CNS)A4規格（210 297公t ) (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製Structure) 210. As shown in FIG. 2, the substrate 200 has a separation structure 210 and an active / drain region 220 in the substrate 200 on both sides of the separation gate structure 210. The separation gate structure 210 includes a tunnel oxide layer stacked from bottom to top. 212. A floating gate 214, an inter-gate dielectric layer 216, and a control gate 218, and a transfer gate 218a extending from the control gate 218 to the side of the floating gate 214. Because the channel in the substrate 200 below the transfer gate 218a must be opened when a voltage is applied to the control gate 218 / transfer gate 218a, even if the channel below the floating gate 214 is continuously opened due to over-erase, the memory cell The non-conducting state can still be maintained in a non-operation state, thereby preventing misjudgment of data. Although the design of the separation gate structure 210 can prevent misjudgment caused by excessive erasure, the extra transfer gate 218a needs to occupy additional area, which is not conducive to the reduction of components. In addition, as shown in FIG. 2, since the width of the addition of the control gate 218 and the transfer gate 218 a in the separation gate structure 210 is different from that of the floating gate 214, the floating gate 214 and the control j gate 218 / transfer gate 218a must be defined by two lithographic etching processes respectively. Therefore, the width of transfer gate 218a and the overlap area of control gate shift gate 218a and floating gate 214 are easily generated. The electrical properties of the memory cells are inconsistent, thereby increasing the difficulty in operation. The invention proposes a structure of a two-bit non-volatile memory. The type of the memory is, for example, a flash memory, and the area required for storing each bit in this memory is smaller than that of a designer using a split gate structure. But it also has the function of preventing excessive erasure. The structure includes a substrate, an isolation layer, a bit line, a stacked gate structure, a doped region, a source / drain region, and a word line. 4 This paper size applies Chinese National Standard (CNS) A4 specification (2.10 x 297 mm) (Please read the note on the back? Matters before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -1 ---- ---- Order ------- i-line! _---------------------- 479331 69 92twf. Doc / 00 6 _B7_ V. Description of the invention ($) (Please read the notes on the back before filling in this (Page) Among them, each isolation layer is located on the substrate and parallel to each other; the direction of each element line is perpendicular to the isolation layer, thereby enclosing a grid-like unit array; the stack gate structure is located in a grid of two groups In the grid-like unit, the connection direction of the two stacked gate structures of each grid-like unit is parallel to the direction of the isolation layer. Each of the stacked gate structures includes a floating gate and a control gate thereon; The hetero region is located in the substrate between the two stacked gate structures of each lattice unit; the doping pattern of the source / drain region is the same as the doped region, and is located in the substrate between the lattice units; The element line is located above the stacked gate structure and runs perpendicular to the bit line. The two control gates in each grid-shaped unit are electrically connected to the adjacent two word lines. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics The present invention also proposes a method for manufacturing a two-bit non-volatile memory, which is used to manufacture the above-mentioned two-bit non-volatile memory structure of the present invention. The steps of this manufacturing method are as follows: first, an isolation layer is formed on the substrate, and then a multi-layer structure is formed on the substrate, which is one of a tunneling layer, a first conductor layer, an inter-gate dielectric layer, and a first layer stacked from bottom to top. Consists of two conductor layers. This multilayer structure is then defined to form a number of strip-shaped multilayer structures, the direction of which is perpendicular to the isolation layer, and each of the adjacent two strip-shaped multilayer structures is divided into a strip-shaped unit. Then, source / drain regions and bit lines are formed on the substrate between the stripe units, and several doped regions are formed between the two stripe-shaped multilayer structures of each stripe unit. The heterotype is the same as the doped region, and each element line and the isolation layer surround several grid-shaped units. Then define each stripe multilayer structure to form several stacked gate structures, so that each grid-shaped unit has two stacked gate structures, each of which includes a floating gate electrode obtained from the first conductor layer, And one of the control gates obtained from the second conductor layer 5 This paper size is applicable to the Chinese National Standard (CNS) Al specification (210 X 297 mm) 479331 A7 B7 6992twf. Doc / 0 06 V. Description of the invention (outer) pole. Then, several word lines are formed above the stacked gate structure, the direction of which is perpendicular to each element line, and the two control gates of the same grid unit are respectively related to the phase (please read the precautions on the back before filling this page). The two character lines are electrically connected. In the above-mentioned manufacturing method of the dual-bit non-volatile memory of the present invention, the bit line manufacturing method can be divided into two types, one is to form an embedded bit line, and the other is to form a bit / source These two methods of bit lines on the drain region and across the isolation layer will be described separately in the following embodiments of the present invention, and the structures obtained by these two methods can also be seen from the description and the drawings. In addition, in the above-mentioned two-bit nonvolatile memory structure of the present invention, the two stacked gate structures in one lattice unit and one doped region therebetween, and the two source / drain electrodes on both sides of the lattice unit The area is combined into a memory unit. The two control gates of the two stacked gate structures are electrically connected to two adjacent word lines, and the two source / drain regions are electrically connected to two adjacent bit lines. And the doping pattern of the source / drain region is the same as the doping region between the two stacked gate structures. The programming and reading method of this memory unit will also be mentioned in the following embodiments of the present invention for comparison with non-volatile memory cells of the conventional art. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs in order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following two embodiments are described in detail below in conjunction with the accompanying drawings for detailed description as follows: Brief description: Figure 1 shows the non-volatile memory cells of the conventional stack gate design; Figure 2 shows the non-volatile memory cells of the conventional split gate design; Figures 3 to 11 In the first embodiment of the present invention, a cross-sectional view of a manufacturing process of a two-bit non-volatile memory using the first word line manufacturing method is used. 'For the sake of clarity, the cross sections corresponding to the figures are different; 6 The paper k degree applies to the Chinese National Standard (CNS) A4 specification (2〗 〇 297 public love) 479331 A7 B7 6992twf. Doc / 00 6 V. Description of the invention (f) The cross-section drawing shown in Figure 12 shows the invention The second method for making the second character line of the double-bit nonvolatile memory system of the first embodiment; Figures 3A, 5A, 6A, 7A, 9A, 11A, and 12A are respectively 3, 5, 6, 7, and Top view of Figures 9, 11, and 12; Figure 11B _ shows the tangent line V-V 'of Figure 11A FIG. 12B is a cross-sectional view of the tangent line II-IΓ of FIG. 12A; and FIGS. 13 to 15 are the manufacturing methods of the dual-bit nonvolatile memory according to the second embodiment of the present invention. In the manufacturing process of the source / drain region and the bit line, FIG. 13 is followed by the step of forming a multilayer structure (corresponding to FIG. 4 of the first embodiment), and FIG. 15 is followed by the step of defining the stacked gate structure ( (Corresponding to Figs. 9A and 9 of the first embodiment); Figs. 13A and 14A are top views of Figs. 13 and 14; Figs. 16 and 17 show the first and second words respectively according to the embodiment of the present invention; The circuit diagram of the dual-bit non-volatile memory obtained by the method of making the element line; FIG. 18 shows the structure of the non-volatile memory unit obtained from the embodiment of the present invention; FIG. 19 shows the structure of the non-volatile memory unit obtained from the embodiment of the present invention; A method for programming a non-volatile memory unit; and FIG. 20 illustrates a method for reading a non-volatile memory unit obtained by an embodiment of the present invention. Description of drawing numbers: 100, 200, 300: Substrate 110, 310b, 310c / d: Stacked Gate Structure 7 This paper size applies to China National Standard (CNS) A4 (210 297 g) ) (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs
I · ϋ ϋ H ϋ n ί I n ϋ ϋ ϋ ϋ I I I ϋ ϋ n n I ϋ ϋ ϋ I I I I 1 ϋ I I I I I I n I 479331 A7 B7 6992twf. doc/006 五、發明說明（G ) 112、212、312 :穿隧氧化層（Tunnel 〇X1de) (請先閱讀背面之注意事項再填寫本頁) 114、214、314a、314c、314d :浮置閘極（Floating Gate) 116、216、316 :閘間介電層 118、218、318a、318c、318d :控制閘極（Control Gate) 120、220、330c、330d ··源/汲極區（S/D Region) 210 :分離閘結構（Split-Gate Structure) 218a :轉移閘極(Transfer Gate) 301 :溝渠（Trench) 302 :淺溝渠隔離（Shallow Trench Isolation，STI) 310 ··多層結構（Multi-layer Structure) 310a :條狀多層結構 314、318 :導體層 320 :條狀單位 324 :罩幕層(Mask Layer) 327、527 ··離子植入（Ion Implantation) 330 :埋入式位元線（Buried Bit Line) 經濟部智慧財產局員工消費合作社印製 333、533 :摻雜區 337、340、537 :介電層 339 ·•記憶單元 350 :非著陸介層窗（Unlanded Via) 360、460a、460b、460c :字元線 450 :介層窗(Via) 528 :源/汲極區（S/D Region) 529a :間隙壁（Spacer) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 479331 69 92twf. doc/006 _B7^ 五、發明說明（"]) (請先閱讀背面之注意事項再填寫本頁) 529b :介電材料 530 :位元線 Ι-Γ〜V-V，··切割線標號 X、Y :座標軸標號 a、b、c :〜寬度標號 第一實施例 本第一實施例之雙位元非揮發性記憶體的製造流程剖 面圖係繪示於第3〜11圖（或第3〜10 & 12圖）中，且第3A〜12A 圖分別爲3〜12圖之上視圖，但其中第4、8、10圖並不需 要對應之上視圖，故未繪出。另外，第11B與12B圖分別 爲第11A圖之另一剖面圖與第12A圖之另一剖面圖。 此外，本第一實施例中第11A、11、11B圖爲一組， 其顯示本第一實施例採用之第一種字元線製造方法；第 12A、12、12B圖爲另一組，其顯示本第一實施例採用之 第二種字元線製造方法。 經濟部智慧財產局員工消費合作社印製 請同時參照第3與3A圖，其中第3圖係爲第3A圖之 切割線M’的剖面圖。如第3、3A圖所示，首先在基底300 上形成平行排列之淺溝渠隔離302,其係位於溝渠301中， 而此溝渠301具有傾斜之側壁，其理由將於稍後說明。 請參照第4圖所示之剖面圖，其係與第3圖在同一剖 面上。如第4圖所示，接著依序在基底300上成穿隧氧化 層312、導體層314、閘間介電層316與導體層318，此處 將四者合稱爲多層結構310，其係作爲堆疊結構之前身， 且其中導體層314與318之材質皆例如爲複晶矽，而閘間 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱1 479331 A7 B7 69 92twf. doc/006 五、發明說明（？） 介電層316例如爲一氧化矽/氮化矽/氧化矽（ΟΝΟ)複合層。 (請先閱讀背面之注意事項再填寫本頁) 請參照第5Α與5圖，其中第5圖係爲第5Α圖之切割 線ΙΜΓ的剖面圖。如第5、5Α圖所示，接著定義多層結 構310以形成Υ走向之條狀多層結構310a，其中每相鄰二 條狀多層結構310a係區分爲一條狀單位320，且每一條狀 單位320之二條狀多層結構310a的間距a小於各條狀單位 320之間距b，其理由將於後文中說明。 請參照第6A與6圖，其中第6圖係爲第6A圖之切割 線ΙΙΙ-ΙΙΓ的剖面圖。如第6、6A圖所示，接著在基底300 上形成圖案化之罩幕層324,其例如爲一光阻（Photoresist) 層，此罩幕層324係將各條狀單位320之間的淺溝渠隔離 302暴露出來。然後以此罩幕層324爲罩幕去除暴露出之 淺溝渠隔離302。此製程例如可採用類似自行對準源極 (Self-Aligned Source，SAS)製程的方式，即罩幕層324之 開口的間距c大於條狀單位320之間距b，以達到較佳的 對準效果。 經濟部智慧財產局員工消費合作社印製 請參照第7與7A圖，其中第7圖係爲第7A圖之切割 線ΙΜΓ的剖面圖。如第7、7A圖所示，接著去除殘餘之 罩幕層324，再以條狀多層結構310a與淺溝渠隔離302爲 罩幕進行離子植入327，其所植入者例如爲η型離子’以 在每一條狀單位320之二條狀多層結構310a之間的基底 3〇〇中形成摻雜區333，同時在各條狀單位320之間的基底 3〇〇中形成埋入式位元線330，其中埋入式位元線330的一 部分係位在溝渠301內之基底300的表層，而此溝渠301 本紙張尺度適用中國國家標準（CNS)A‘l規格（210 X 297公釐） 479331 6992twf.doc/〇〇6 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（q) 之邊界係以點線表示。此時請參照第7圖，可看出埋入式 位元線330係作爲各元件的源/汲極區。另外，請同時參照 第3、7與7A圖，由於溝渠301具有傾斜的側壁，所以離 子植入327才能在溝渠301之側壁形成摻雜區以作爲埋入 式位元線330釣一部分。 請參照第8圖，接著以介電層337塡滿各條狀多層結 構310a之間的空隙，其方法例如爲先在基底300上形成一 層介電材料以塡滿各條狀多層結構310a之間的空隙，再 以化學機械硏磨法(Chemical Mechanical Polishing，CMP)除 去高於條狀多層結構310a上緣之介電材料，其中介電材 料之材質例如爲氧化矽，且形成方法例如爲化學氣相沈積 法(CVD) 〇 請參照第9A與9圖，其中第9圖係爲第9A圖之切線 IV-IV’上的的剖面圖。如第9A與9圖所示，接著定義各條 狀多層結構310a，即在Y方向上分開Y走向之條狀多層 結構310a，以形成數個堆疊閘結構310b，其包含由下而上 堆疊之穿隧氧化層312、得自導體層314之浮置閘極314a、 閘間介電層316與得自導體層318之控制閘極318a。如第 9A圖所示，任一條狀單位320中左右一對的堆疊閘結構係 組成一個記憶單元339，而每一記憶單元339可用來儲存 兩位元的資料。此時請一倂參照第8圖所示之剖面圖，.其 可同時作爲第9A圖之切割線ΙΙ-ΙΓ的剖面圖，只是標號略 有不同（310b與310a)而已。如第9A與8圖所示，每一記 憶單元339中更包含摻雜區333，其係位於此記憶單元339 本紙張尺度適用中國國家標準（CNS)/V〗規格（2.】〇x 297公釐） ---------------------訂--------線—AWI (請先閱讀背面之注音？事項再填寫本頁) 479331 A7 6992twf. doc/0 06 _B7_ 五、發明說明（ί〇 ) 之二堆疊閘結構310b之間的基底300中。 請參照第10圖所示之剖面圖，其所對應之剖面係第9 圖相同。如第10圖所示，並同時比對第9A、9圖，接著 在基底300上覆蓋介電層340，並塡滿各堆疊閘結構31〇b 與介電層337所圍出之孔洞。 以下的步驟即是在介電層340中形成介層窗以電性連 接各堆疊閘結構310b之控制閘極318a，再形成與位元線330 垂直之子兀線以電性連接各介層窗，其方法係分爲以下兩 種，但二者之共同特徵是同一記憶單元339之二控制閘極 318a (請見第9A與9圖）必定分別電性連接至相鄰的兩條 字元線。 第一種字元線製作方法 請參照第11A、11與11B圖，其所繪示爲本第一實施 例之第一種介層窗與字元線的形成方法，其中第U圖係 爲第11A圖之切割線IV-IV’的剖面圖，且第11B圖係爲第 11A圖之切割線V-V’的剖面圖。 如第11與11A圖所示，接著在介電層340中形成非 著陸介層窗（Unlanded Via)350，再於介電層340上形成與 位兀線330垂直之字元線360 (第Ha圖）以電性連接位在 同一橫排的所有非著陸介層窗350。其中，每一個非著陸 介層窗350係電性連接相鄰之一對控制閘極3i8a，此二控 制閘極318a係位在同一條狀單位32〇中，但分別屬於相鄰 之二記憶單元339 •，而同一記憶單元339中的二控制閘極 1 2 本紙張尺度適用中國國家標準（CNS)A4規格（2:10 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 479331 A7 B7 6992twf. doc/006 i、發明說明（) (請先閱讀背面之注意事項再填寫本頁) 318a則分別電性連接位在不同橫排的兩個非著陸介層窗 350，並藉此分別電性連接至相鄰之二字元線360上，以 分別接受兩條字元線360的控制。 此外，請參照第11A、11B圖，其中第11B圖係爲第 11A圖之切槔-V-V’的剖面圖。如第11A與11B圖所示，任 一條字元線360係電性連接其兩側之每一記憶單元339中 僅一個控制閘極318a，而電性連接至任一字元線360的每 一個控制閘極318a皆位在其各自所屬之記憶單元339的同 一側（此二圖中爲右側）。不過，只要任一條字元線360僅 與其路經之每一對「相鄰且位在同一條狀單位320內之記 憶單元339」中的一對相鄰之控制閘極318a電性連接，且 字元線360下方之非著陸介層窗350的電性連接方式滿足 上述條件即可’電性連接至同一字元線360的每一個控制 閘極318a亦可位在其各自所屬之記憶單元339的不同側。 第二種字元線製作方法 經濟部智慧財產局員工消費合作社印製 請參照第12A、12、12B圖，其所繪示爲本第一實施 例之第二種介層窗與字元線的形成方法，其中第12圖係 爲第12A圖之切割線IV-IV’的剖面圖，且第12B圖所繪示 爲第12A圖之切割線ΙΜΓ的剖面圖。 如第12A、12、12B圖所示，接著在每一個控制閘極 318a上方之介電層340中各形成一個介層窗450 (第12A 圖中的虛線圓圈）以作電性連接，此處所示者係爲著陸介 層窗，但未完全對準亦有可能。如第12A與12圖所示， 本紙張&度適用中國國家標準（CNS)A4規格（210 X 297公釐） 479331 A7 B7 6992twf.doc/006 五、發明說明（丨2) (請先閱讀背面之注意事項再填寫本頁) 接著在介電層340上形成整體走向與位元線330垂直，但 呈鋸齒狀的字元線460a/b/c，其中任一條字元線460a/b/c 係電性連接相鄰兩橫排之每一個記憶單元339中僅一個控 制閘極318a上方的介層窗450，而連接至同一字元線 460a/b/c之任一對相鄰的二介層窗450均呈對角排列。也 就是說，在同一條狀單位320內之一對相鄰的記憶單元339 中，僅有一對對角排列之控制閘極318a連接至同一條字 元線 460a/b/c。 此外，請參照第12B圖，其顯示任一字元線460a/b/c 係電性連接其路經之每一個記憶單元339中僅一個控制閘 極318a，而電性連接至同一字元線460a/b/c的每一個控制 閘極318a皆位在其各自所屬之記憶單元339的同一側。不 過，只要同一條狀單位320內一對相鄰之記憶單元339中 僅有一對對角排列之控制閘極318a連接至同一條字元線 460a/b/c，而每一個介層窗450僅電性連接一個控制閘極 318a即可，電性連接至同一字元線460a/b/c的每一個控制 閘極318a亦可位在其各自所屬之記憶單元339的不同側。 第二實施例 經濟部智慧財產局員工消費合作社印製 首先需指明的是，由於本第二實施例與第一實施例之 差異僅在於位元線之型式與製造方法，故爲節省篇幅起 見，本第二實施例之前段製程請參照第3A圖之上視圖、 第3至4圖之剖面圖，以及對應之說明。 接著請參照第13A與13圖，其係接續於第一實施例 本紙張尺度適用中國國家標準（CNS)A‘l規格（2】ϋ X 297公釐） 經濟部智慧財產局員工消費合作社印製 479331 6992twf.d〇c/〇〇6 ------B7______ 五、發明說明（g ) 中第4圖的對應步驟之後，其中第13圖係爲第nA圖之 切割線Π-ΙΓ的剖面圖。如第13與13A圖所示，在條狀多 層結構31〇a形成之後，以條狀多層結構31〇a與淺溝渠隔 離302爲罩幕進行離子植入527，以在每一條狀單位32〇 之一條狀多層箱構310a之間的基底3〇〇中形成數個摻雜區 533，其係以淺溝渠隔離302分隔；同時在各條狀單位32〇 之間的基底300中形成數個源/汲極區528，其亦以淺溝渠 隔離302作區隔。 接著請參照第14A與14圖，其中第14圖係爲第14A 圖之切割線ΙΙ-ΙΓ的剖面圖。如第14與14A圖所示，接著 在母一條狀單位320之一條狀多層結構31〇a的外側壁形成 介電材質之間隙壁529a，以隔離條狀多層結構31〇a中的 導體層314與導體層318 ;並以與間隙壁529a相同之介電 材料529b塡滿每一條狀單位320之二條狀多層結構31〇a 間寬度較小的空隙(請比對第一實施例中對應第5A圖之說 明部分，此空隙寬度爲a，其値小於各條狀單位320之間 距b)。然後於各條狀單位320側壁之間隙壁529a之間塡 入導體材料’以作爲fii兀線530’其係跨越淺溝渠隔離302。 此位兀線5 3 0之材質例如爲複晶砂或一*金屬材料，且甘卜 緣尚度低於各條狀多層結構310a之上緣高度。 請參照第15蘭，接著在位元線530上形成介電層537 以填滿各條狀單位320側壁之間隙壁529a之間的空隙，藉 以保護下方之位元線530，此介電層537之材質例如是以 化學氣相沈積法（Chemical Vapor Deposition，CVD)所形成 本紙張尺度適用中國國家標準（CNS)/V丨規格（2]〇χ 297公釐） (請先閱讀背面之注意事項再填寫本頁) ·. 訂---------線！ 479331 A7 B7 69 92twf. doc/0 06 五、發明說明（#) 之氧化砂。 (請先閱讀背面之注意事項再填寫本頁) 接下來，由於本第二實施例與第一實施例之差別僅在 間隙壁529a是否存在與位元線之型式，故後續步驟中定 義各條狀多層結構310a以形成堆疊_結構310b，以及介 層窗/字元線之兩種形成方法只要比對第9A、11A、12A圖 之上視圖、第9〜12圖所不之剖面圖、第11B、12B圖之剖 面圖，以及對應之說明即可，其中第11A、11、11B圖顯 示第一種製造介層窗與字元線的方法，且第12A、12、12B 圖顯示第二種製造介層窗與字元線的方法。 經濟部智慧財產局員工消費合作社印製 接下來請參照第16與17圖，其係分別繪示由本發明 二實施例之第一種與第二種字元線製造方法所得之雙位元 非揮發性記憶體的電路圖。如第16圖所示，在Y方向相 鄰之二記憶單元339中僅有一對X座標相同的控制閘極電 性連接至同一條字元線，而另外兩個控制閘極則分別電性 連接至此字元線兩側之另兩條字元線上。另一方面，如第 17圖所示，在Y方向相鄰之二記憶單元339中僅有一對對 角排列之控制閘極電性連接至一條字元線，而另外兩個控 制閘極則分別電性連接至此字元線兩側之另兩條字元線 上。 以上所述者即爲本發明二實施例之雙位元非揮發性記 憶體的製造方法，而此二實施例之雙位元非揮發性記憶體 之結構亦可由上文與圖式得知。不過，爲方便與習知技藝 之非揮發性記憶胞作比較，以下將第11A、12A圖中所示 之記憶單元339獨立出來，藉以說明本發明之雙位元非揮 本紙張尺度適用中國國家標準（CNS)yVI規格（2】ϋ X 297公釐） 479331 A7 B7 6992twf.doc/006 五、發明說明（If ) 發性記憶體的操作方法及優點，而與記憶單元339之源/汲 極區電性連接的位元線、與控制閘極電性連接之介層窗與 字元線等等則不予繪出以簡化圖式。 本發明之非揮潑件記憶單元的操作方法 請參照第18圖，其所繪示爲本發明二實施例之非揮 發記憶單元339的結構。如第18圖所示，此記憶單元339 包含兩個堆疊閘結構310c與310d、二堆疊閘結構310c與 310d外側之源極/汲極區330c與330d，以及二堆疊閘結構 310c與310d之間的摻雜區333，其中堆疊閘結構310c(d) 包含由下而上堆疊之穿隧氧化層312、浮置閘極314c(d)、 閘間介電層316與控制閘極318c(d)，且源/汲極區330c(d) 之摻雜型態與摻雜區333相同，例如皆爲η型。 接著要說明的是當源/汲極區330c(d)與摻雜區333之 摻雜型態皆爲η型時，用來程式化上述非揮發記憶單元的 一種方法，其係以第19圖作解釋。 稈式化方法 請參照第19圖所示之程式化方法，其係爲一種通道 熱電子（Channel Hot Electron，CHE)注入法。此方法係在分 別在控制閘極318c與318d上施加大於0的偏壓乂1與V2， 以同時打開浮置閘極314c與314d下方之通道。此時如欲 寫入浮置閘極314d，即在控制閘極318c —側之源/汲極區 33〇C上施加偏壓V3，其例如是接地電壓，並在控制閘極318d 一側之源/汲極區330d上施加大於V3的偏壓V4，以使電子 本紙張尺度適用中國國家標準（CNS)A4規格（2】0 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ·--------訂--------^線丨蜂 經濟部智慧財產局員工消費合作社印製 479331 69 92twf. doc/0 06 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（) 由控制閘極318c —側之源/汲極區330c流向控制閘極318d 一側之源/汲極區330d。此處¥4與V3的差異足夠大，使得 浮置閘極314d下方通道中能夠產生熱電子以注入浮置閘 極314d中，但亦不能過大，以免熱電子在浮置閘極314c 下方產生並注入其中。 以此類推，如欲寫入浮置閘極314c，只要在浮置閘極 314c與314d下方通道同時打開之情形下，將兩個源/汲極 區330c與330d的極性倒轉，使熱電子僅在浮置閘極314c 下方通道產生而注入浮置閘極314c中。 此記憶單元的程式化方法除了上述之熱電子注入法 外，尙有利用穿隧效應（Tunnding Effect)的方法，其係在 控制閘極318c (或d)上施加較高偏壓，並在同側之源/汲極 區330c (或d)上施加較低偏壓，此較低偏壓與較高偏壓之 差異足夠大，使電子能藉由FN穿隧現象（Fowler-Norheim Tunneling)從源/汲極區330c (或d)流到浮置閘極314c (或d) 中。 讀取方法 如熟習此技藝者所知，由於負電荷存在之故，浮置閘 極314c及314d在寫入狀態時其下方通道之啓始電壓(通道 打開時控制閘極318c/d上所需之電壓）大於抹除狀態時， 此處將寫入狀態下通道之啓始電壓簡稱爲VTwnie，並將抹 除狀態下的啓始電壓簡稱爲VTenise，而VTwnie〉VTerase。 請參照第20圖，其所繪示爲本發明較佳實施例之非 揮發性記憶單元的讀取方法，此處係以浮置閘極314c中 (請先閱讀背面之注意事項再填寫本頁) 一δϋ. --線_ 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） 479331 A7 B7 ^992twf.doc/006 五、發明說明（/Γ| ) 資料之讀取過程爲例。如第20圖所示，此過程係在控制 閘極318d上施加大於VTwnie的偏壓V6，以打開浮置閘極 3l4d下方之通道；同時於控制閘極318c上施加偏壓v5， 其與 vTerase及 vTwnie 之大小關係爲 vTwnte > v5 > vTei.ase。接 著，在兩個源V汲極區330c與330d上施加不同的偏壓，再 以源/汲極區330c與330d導通與否來判讀浮置閘極314c 中是否寫入資料。此時所發生之現象與判讀方法請見下 段。 由於控制閘極318d之電壓V6 > VTwrite > VTerase，故不 論浮置閘極314d中是否寫入資料，其下方通道皆可以打 開；另一方面，由於控制閘極318c之電壓乂5與VTenise及 ^Twrite 之大小關係爲 VTwrite〉V5〉VTerase ’ 所以當浮置閘極 314c在抹除狀態下通道會打開，而在寫入狀態下通道則不 會打開。此時由於摻雜區333之摻雜型態亦爲n型，故當 源/汲極區330c與330d之間能夠導通時，即表示浮置閘極 314c係處於抹除狀態；而當源/汲極區330c與330d之間不 能導通時，則表示浮置閘極314c係處於寫入狀態。 如上所述，在本發明二實施例之雙位元非揮發性記憶 體的一個記憶單元中，係以兩個堆疊閘結構310c與310d 爲一*組共用一^對源/汲極區330c與330d 5所以只有在浮置 閘極314c與314d下方的通道同時打開時，源/汲極區330c 與330d之間才能導通。由於兩個浮置閘極314c與314d同 時發生過度抹除的機率極低，使得源/汲極區330c與330d 間持續導通的機率也很低，所以與習知堆疊閘設計相較之 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） ---------------------訂---------線-- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 479331 A7 B7 6992twf. doc/006 五、發明說明（β) (請先閱讀背面之注意事項再填寫本頁) 下，發生資料誤判的機會得以大幅降低。此時請一倂參照 前述分離閘結構之說明與第2圖，由於本發明之一個記憶 單元中的一個堆疊閘結構可以防止另一個堆疊閘結構被過 度抹除時所產生的誤判問題，故此堆疊閘結構亦可稱爲一 轉移閘極，其功能如同對第2圖中的轉移閘極218a。 另外，由於本發明之雙位元非揮發性記憶體的任一個 記憶單元皆具有兩個浮置閘極以儲存兩個位元的資料，且 係以一個堆疊閘結構作爲轉移閘極來防止另一個堆疊閘結 構過度抹除時所產生的問題，而非如習知分離閘結構210 般在控制閘極218側邊加上轉移閘極218a，所以與採用分 離閘結構210設計之單位元記憶胞相較之下，使用本發明 時儲存每一個位元所需之面積可以大幅降低。 經濟部智慧財產局員工消費合作社印製 再者，如第9、9A圖所示，本發明係連續定義出控制 閘極318a與浮置閘極314a ;又如第18圖所示，本發明係 以一個堆疊閘結構310c (或d)作爲轉移閘極，以防止浮置 閘極314d (或c)過度抹除時所產生的問題。因此，使用本 發明時不必如習知分離閘結構製程般需以兩次微影製程來 分別定義浮置閘極與控制閘極/轉移閘極，因此是一種自行 對準製程，而不會產生元件電性不一致的問題。 除此之外，請參照第18圖，由於在本發明之雙位元 非揮發性記憶體中摻雜區333僅作爲電流之通路，故其只 要具有和源/汲極區330a與330b相同的摻雜型態即可，而 其寬度a則可以小於源/汲極區330a與330b之寬度b。因 此，與第1圖所示之習知堆疊閘設計相較之下，本發明之 20 本紙張尺度適用中國國家標準（CNS)A4規格⑵0x297公爱) "" " 479331 A7 B7 69 92twf. doc/006 五、發明說明（iq ) 雙位元非揮發性記憶體儲存每一個位元時所需之面積可以 更小。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注咅？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A.4規格（210 x 297公釐）I · ϋ ϋ H ϋ n ί I n ϋ ϋ ϋ ϋ III ϋ ϋ nn I ϋ ϋ ϋ IIII 1 ϋ IIIIII n I 479331 A7 B7 6992twf. Doc / 006 V. Description of the Invention (G) 112, 212, 312: Wear Tunnel oxide layer (Tunnel OX1de) (Please read the notes on the back before filling this page) 114, 214, 314a, 314c, 314d: Floating Gate 116, 216, 316: Inter-gate dielectric layer 118, 218, 318a, 318c, 318d: Control Gate 120, 220, 330c, 330d ·· S / D Region 210: Split-Gate Structure 218a: Transfer Gate 301: Trench 302: Shallow Trench Isolation (STI) 310 · Multi-layer Structure 310a: Strip-like multilayer structure 314, 318: Conductor layer 320: Strip unit 324: Mask Layer 327, 527 · Ion Implantation 330: Buried Bit Line Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 333, 533 : Doped regions 337, 340, 537: dielectric layer 339 • memory cell 350: non-landing dielectric window (Unlande d Via) 360, 460a, 460b, 460c: character line 450: via window (Via) 528: source / drain region (S / D Region) 529a: spacer (Spacer) This paper standard applies to Chinese national standards ( CNS) A4 specification (210 X 297 mm) 479331 69 92twf. Doc / 006 _B7 ^ 5. Description of the invention ("]) (Please read the notes on the back before filling this page) 529b: Dielectric material 530: Bit Element line I-Γ ~ VV, ···· Cutting line numbers X, Y: Coordinate axis numbers a, b, c: ~ Width numbers The drawings are shown in Figures 3 to 11 (or Figures 3 to 10 & 12), and Figures 3A to 12A are top views of Figures 3 to 12, respectively, but Figures 4, 8, and 10 are not Need to correspond to the top view, so it is not drawn. 11B and 12B are another cross-sectional view of FIG. 11A and another cross-sectional view of FIG. 12A. In addition, Figs. 11A, 11, and 11B in the first embodiment are one group, which shows the first type of character line manufacturing method used in the first embodiment; Figs. 12A, 12, 12B are another group, which The second character line manufacturing method used in the first embodiment is shown. Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Please refer to Figures 3 and 3A, where Figure 3 is a cross-sectional view taken along line M' of Figure 3A. As shown in Figs. 3 and 3A, a shallow trench isolation 302 arranged in parallel is first formed on the substrate 300, which is located in the trench 301, and the trench 301 has inclined sidewalls. The reason will be described later. Please refer to the cross-sectional view shown in Figure 4, which is on the same cross-section as Figure 3. As shown in FIG. 4, a tunneling oxide layer 312, a conductor layer 314, an inter-gate dielectric layer 316, and a conductor layer 318 are sequentially formed on the substrate 300. The four are collectively referred to as a multilayer structure 310 here. As the predecessor of the stacked structure, and the materials of the conductor layers 314 and 318 are, for example, polycrystalline silicon, and the gate 9 paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 public love 1 479331 A7 B7 69 92twf doc / 006 V. Description of the Invention (?) The dielectric layer 316 is, for example, a silicon monoxide / silicon nitride / silicon oxide (ΟΝΟ) composite layer. (Please read the precautions on the back before filling this page) Please refer to Section 5A And Figure 5, where Figure 5 is a cross-sectional view of the cutting line lmΓ in Figure 5A. As shown in Figures 5 and 5A, the multi-layer structure 310 is then defined to form a strip-shaped multilayer structure 310a in a Υ direction, where each adjacent The two strip-shaped multilayer structures 310a are divided into strip-shaped units 320, and the pitch a of the two strip-shaped multilayer structures 310a of each strip-shaped unit 320 is smaller than the distance b between the strip-shaped units 320. The reason will be described later. Please refer to Section 6A And Figure 6, where Figure 6 is the cutting line ΙΙΙ- of Figure 6A A cross-sectional view of IΓ. As shown in FIGS. 6 and 6A, a patterned mask layer 324 is formed on the substrate 300, which is, for example, a photoresist layer. The mask layer 324 is a strip unit. The shallow trench isolation 302 between 320 is exposed. Then the mask layer 324 is used as a mask to remove the exposed shallow trench isolation 302. For example, this process can use a similar Self-Aligned Source (SAS) process In this way, the distance c between the openings of the cover layer 324 is greater than the distance b between the strip-shaped units 320 to achieve a better alignment effect. Please refer to Figures 7 and 7A for printing by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 7 is a cross-sectional view of the cutting line lmΓ in Figure 7A. As shown in Figures 7 and 7A, the remaining mask layer 324 is removed, and the strip-shaped multilayer structure 310a is isolated from the shallow trench 302 as the mask. Ion implantation 327, which is implanted by, for example, n-type ions, to form a doped region 333 in the substrate 300 between the two stripe-like multilayer structures 310a of each stripe unit 320, and simultaneously in each stripe unit 320 A buried bit line 330 is formed between the substrates 300, A part of the buried bit line 330 is located on the surface of the substrate 300 in the trench 301, and this trench 301 paper size applies to the Chinese National Standard (CNS) A'l specification (210 X 297 mm) 479331 6992twf. doc / 〇〇6 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The boundary of the invention description (q) is indicated by a dotted line. At this time, please refer to Figure 7 to see the embedded bit line 330 As the source / drain region of each element. In addition, please refer to FIGS. 3, 7 and 7A at the same time. Because the trench 301 has inclined sidewalls, the ion implantation 327 can form a doped region on the sidewall of the trench 301 as part of the buried bit line 330 fishing. Please refer to FIG. 8, and then fill the gaps between the strip-shaped multilayer structures 310 a with the dielectric layer 337. For example, a method is to first form a layer of dielectric material on the substrate 300 to fill the strip-shaped multilayer structures 310 a. And remove the dielectric material higher than the upper edge of the stripe multilayer structure 310a by chemical mechanical polishing (CMP), wherein the material of the dielectric material is, for example, silicon oxide, and the formation method is, for example, chemical gas. Phase deposition method (CVD) Please refer to FIGS. 9A and 9, where FIG. 9 is a cross-sectional view taken along a line IV-IV ′ of FIG. 9A. As shown in FIGS. 9A and 9, each strip-shaped multilayer structure 310 a is defined, that is, the strip-shaped multilayer structure 310 a in the Y direction is separated in the Y direction to form a plurality of stack gate structures 310 b, which include bottom-up stacked stack structures 310 b. The tunnel oxide layer 312, the floating gate electrode 314a obtained from the conductor layer 314, the inter-gate dielectric layer 316, and the control gate electrode 318a obtained from the conductor layer 318. As shown in FIG. 9A, the left and right pair of stacked gate structures in any strip unit 320 constitute a memory unit 339, and each memory unit 339 can be used to store two bits of data. At this time, please refer to the cross-sectional view shown in FIG. 8 at the same time. It can also be used as the cross-sectional view of the cutting line II-IΓ in FIG. 9A, but the number is slightly different (310b and 310a). As shown in FIGS. 9A and 8, each memory cell 339 further includes a doped region 333, which is located in this memory cell 339. The paper size is applicable to the Chinese National Standard (CNS) / V. Specification (2.) 〇x 297 (Mm) --------------------- Order -------- line—AWI (Please read the phonetic on the back? Matters before filling out this page) 479331 A7 6992twf. Doc / 0 06 _B7_ V. Description of the Invention (2) In the base 300 between the stacked gate structures 310b. Please refer to the cross-sectional view shown in Figure 10. The corresponding cross-section is the same as Figure 9. As shown in Fig. 10, and comparing Figs. 9A and 9 at the same time, then a dielectric layer 340 is covered on the substrate 300, and the holes surrounded by the stacked gate structures 310b and the dielectric layer 337 are filled. The following steps are to form a dielectric window in the dielectric layer 340 to electrically connect the control gates 318a of the stacked gate structures 310b, and then form a sub-line perpendicular to the bit line 330 to electrically connect the dielectric windows, The methods are divided into the following two types, but the common feature of the two is that the control gate 318a (see Figures 9A and 9) of the same memory cell 339bis must be electrically connected to two adjacent word lines, respectively. Please refer to FIGS. 11A, 11 and 11B for the first method of making a character line, which shows the method of forming the first type of interlayer window and character line of the first embodiment, where the U-th picture is the first A cross-sectional view of the cutting line IV-IV 'in FIG. 11A, and FIG. 11B is a cross-sectional view of the cutting line V-V' in FIG. 11A. As shown in FIGS. 11 and 11A, a non-landing via window (Unlanded Via) 350 is then formed in the dielectric layer 340, and a word line 360 perpendicular to the bit line 330 is formed on the dielectric layer 340 (the Ha (Figure) All non-landing interstitial windows 350 in the same horizontal row are electrically connected. Among them, each non-landing interstitial window 350 is electrically connected to an adjacent pair of control gates 3i8a. The two control gates 318a are located in the same stripe unit 32, but belong to the adjacent two memory cells. 339 •, and the two control gates in the same memory unit 339 1 2 This paper size applies to China National Standard (CNS) A4 (2:10 X 297 mm) (Please read the precautions on the back before filling this page) Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 479331 A7 B7 6992twf. Doc / 006 i. Description of the invention () (Please read the precautions on the back before filling this page) 318a are respectively electrically connected in different horizontal rows. The two non-landing vias 350 are electrically connected to the adjacent two word lines 360 respectively, so as to receive the control of the two word lines 360 respectively. In addition, please refer to Figs. 11A and 11B, where Fig. 11B is a cross-sectional view taken along the line -V-V 'of Fig. 11A. As shown in FIGS. 11A and 11B, any word line 360 is electrically connected to only one control gate 318a in each memory cell 339 on both sides thereof, and is electrically connected to each of any word line 360 The control gates 318a are all located on the same side of the memory unit 339 to which they belong (the right side in the two figures). However, as long as any one of the character lines 360 is electrically connected to only one pair of adjacent control gates 318a in each pair of “adjacent and located in the memory unit 339 in the same strip unit 320”, and The electrical connection of the non-landing interlayer window 350 below the word line 360 can satisfy the above conditions. Each control gate 318a electrically connected to the same word line 360 can also be located in its own memory unit 339. Different sides. The second method of making character lines is printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics. Please refer to Figures 12A, 12, and 12B, which show the second type of interlayer windows and character lines of the first embodiment. The forming method, wherein FIG. 12 is a cross-sectional view of the cutting line IV-IV ′ of FIG. 12A, and FIG. 12B is a cross-sectional view of the cutting line IM ′ of FIG. 12A. As shown in Figures 12A, 12, and 12B, a dielectric window 450 (a dotted circle in Figure 12A) is formed in each of the dielectric layers 340 above each control gate 318a for electrical connection. Here, The ones shown are landing vias, but it is also possible that they are not perfectly aligned. As shown in Figures 12A and 12, the paper & degree applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 479331 A7 B7 6992twf.doc / 006 V. Description of the invention (丨 2) (Please read first Note on the back side, please fill in this page again) Then, on the dielectric layer 340, a word line 460a / b / c that is perpendicular to the bit line 330 but has a zigzag shape is formed, and any one of the word lines 460a / b / c is electrically connected to only one of each of the two adjacent horizontal memory cells 339 to control the interlayer window 450 above the gate 318a, and is connected to any pair of adjacent two of the same word line 460a / b / c The vias 450 are all arranged diagonally. That is, among a pair of adjacent memory cells 339 in the same strip-shaped unit 320, only a pair of diagonally arranged control gates 318a are connected to the same word line 460a / b / c. In addition, please refer to FIG. 12B, which shows that any word line 460a / b / c is electrically connected to only one control gate 318a in each memory cell 339 of its path, and is electrically connected to the same word line Each control gate 318a of 460a / b / c is located on the same side of the memory unit 339 to which it belongs. However, as long as only a pair of diagonally arranged control gates 318a of a pair of adjacent memory cells 339 in the same strip unit 320 are connected to the same word line 460a / b / c, and each via window 450 only One control gate 318a may be electrically connected, and each control gate 318a electrically connected to the same word line 460a / b / c may also be located on a different side of its respective memory unit 339. The second embodiment is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The first thing to point out is that because the difference between this second embodiment and the first embodiment is only in the type and manufacturing method of the bit line, in order to save space For the manufacturing process of the previous stage of this second embodiment, please refer to the top view of FIG. 3A, the cross-sectional views of FIGS. 3 to 4, and corresponding descriptions. Please refer to Figures 13A and 13 below, which are the continuation of the first embodiment. The paper size is applicable to the Chinese National Standard (CNS) A'l specification (2) ϋ X 297 mm. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 479331 6992twf.d〇c / 〇〇6 ------ B7______ V. After the corresponding step of Figure 4 in the description of the invention (g), Figure 13 is a section of the cutting line Π-ΙΓ of Figure nA Illustration. As shown in Figures 13 and 13A, after the strip-shaped multilayer structure 31oa is formed, the ion-implantation 527 is performed with the strip-shaped multilayer structure 31a and the shallow trench isolation 302 as a mask, so that each stripe unit 32. A plurality of doped regions 533 are formed in the substrate 300 between one of the stripe multilayer box structures 310a, which are separated by a shallow trench isolation 302. At the same time, several sources are formed in the substrate 300 between each stripe unit 32o. / Drain region 528, which is also separated by shallow trench isolation 302. Please refer to FIGS. 14A and 14, where FIG. 14 is a cross-sectional view of the cutting line II-IΓ in FIG. 14A. As shown in FIGS. 14 and 14A, a dielectric material spacer 529a is then formed on the outer side wall of one of the strip-shaped multilayer structures 31oa of the parent strip-shaped unit 320 to isolate the conductor layer 314 in the strip-shaped multilayer structure 31oa. And the conductor layer 318; and the same dielectric material 529b as the spacer 529a fills each of the two strip-shaped multi-layer structures 31a of the strip-shaped multi-layer structure 31a. (Compared to the corresponding 5A in the first embodiment In the explanatory part of the figure, the gap width is a, and 値 is smaller than the distance b between the strip-shaped units 320). A conductive material 'is then inserted between the gaps 529a on the side walls of each strip unit 320 as fii line 530', which is isolated 302 across shallow trenches. The material of this bit line 5 3 0 is, for example, polycrystalline sand or a metal material, and the marginal margin is lower than the height of the upper edge of each strip-shaped multilayer structure 310a. Please refer to the 15th blue, and then form a dielectric layer 537 on the bit line 530 to fill the gap between the spacers 529a on the side walls of each strip unit 320 to protect the bit line 530 below. This dielectric layer 537 The material is, for example, formed by chemical vapor deposition (Chemical Vapor Deposition, CVD). The paper size is applicable to the Chinese National Standard (CNS) / V 丨 Specifications (2) 0 × 297 mm. (Please read the precautions on the back first Fill out this page again) ·. Order --------- line! 479331 A7 B7 69 92twf. Doc / 0 06 V. Oxidized sand of invention description (#). (Please read the precautions on the back before filling this page.) Next, because the difference between this second embodiment and the first embodiment is only whether there is a pattern of the bit wall 529a and the bit line, each item is defined in the subsequent steps. Layered structure 310a to form stacked structure 310b, and the two formation methods of interlayer windows / character lines, as long as the top views of Figures 9A, 11A, and 12A are compared, the cross-sectional views shown in Figures 9 to 12, and Sections 11B, 12B, and corresponding descriptions can be used. Among them, FIGS. 11A, 11, 11B show the first method for manufacturing via windows and word lines, and FIGS. 12A, 12, 12B show the second method. Method for manufacturing via window and word line. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Please refer to Figures 16 and 17 below, which show the two-bit non-volatile obtained by the first and second character line manufacturing methods of the two embodiments of the present invention, respectively. Circuit diagram of sexual memory. As shown in FIG. 16, in the two adjacent memory cells 339 in the Y direction, only a pair of control gates with the same X coordinate are electrically connected to the same word line, and the other two control gates are electrically connected respectively. So far, the other two character lines on both sides of the character line. On the other hand, as shown in FIG. 17, in the two adjacent memory cells 339 in the Y direction, only a pair of diagonally arranged control gates are electrically connected to one word line, and the other two control gates are respectively It is electrically connected to the other two character lines on both sides of the character line. The above is the manufacturing method of the two-bit non-volatile memory of the two embodiments of the present invention, and the structure of the two-bit non-volatile memory of the two embodiments can also be known from the above and the drawings. However, for the convenience of comparison with the non-volatile memory cells of the conventional art, the memory unit 339 shown in Figures 11A and 12A is isolated below to illustrate that the two-dimensional non-volatile paper size of the present invention is applicable to the country of China. Standard (CNS) yVI specification (2) ϋ X 297 mm) 479331 A7 B7 6992twf.doc / 006 V. Description of the invention (If) The operation method and advantages of the memory, and the source / drain of the memory unit 339 The bit lines electrically connected to the area, the interlayer windows and word lines electrically connected to the control gate are not drawn to simplify the diagram. Operation method of the non-volatile memory unit of the present invention Please refer to FIG. 18, which shows the structure of the non-volatile memory unit 339 according to the second embodiment of the present invention. As shown in FIG. 18, the memory cell 339 includes two stacked gate structures 310c and 310d, source / drain regions 330c and 330d outside the two stacked gate structures 310c and 310d, and between the two stacked gate structures 310c and 310d. Doped region 333, where the stacked gate structure 310c (d) includes a tunnel oxide layer 312, a floating gate 314c (d), an inter-gate dielectric layer 316, and a control gate 318c (d) stacked from bottom to top The doping pattern of the source / drain region 330c (d) is the same as that of the doped region 333, for example, they are all n-type. Next, a method for programming the non-volatile memory cell when the doping patterns of the source / drain region 330c (d) and the doped region 333 are n-type is shown in FIG. 19 Explain. Stem method Please refer to the stylized method shown in Figure 19, which is a channel hot electron (CHE) injection method. This method applies bias voltages 乂 1 and V2 to the control gates 318c and 318d, respectively, to simultaneously open the channels under the floating gates 314c and 314d. At this time, if the floating gate 314d is to be written, a bias voltage V3 is applied to the source / drain region 33 ° C on the side of the control gate 318c, which is, for example, a ground voltage, and is on the side of the control gate 318d. A bias voltage V4 greater than V3 is applied to the source / drain region 330d, so that the electronic paper size applies the Chinese National Standard (CNS) A4 specification (2) 0 X 297 mm. (Please read the precautions on the back before filling in this Page) · -------- Order -------- ^ Line 丨 Printed by the Consumer Cooperative of Employees of Intellectual Property Bureau of Ministry of Economic Affairs 479331 69 92twf.doc / 0 06 A7 B7 Employees of Intellectual Property Bureau of Ministry of Economic Affairs Printed by the consumer cooperative V. Description of the invention () The source / drain region 330c on the side of the control gate 318c flows to the source / drain region 330d on the side of the control gate 318d. Here, the difference between ¥ 4 and V3 is large enough to allow hot electrons to be generated in the channel below the floating gate 314d to be injected into the floating gate 314d, but it must not be too large to prevent the generation of hot electrons below the floating gate 314c and Inject it. By analogy, if the floating gate 314c is to be written, as long as the channels under the floating gate 314c and 314d are opened at the same time, the polarities of the two source / drain regions 330c and 330d are reversed, so that the hot electrons only A channel is generated below the floating gate 314c and injected into the floating gate 314c. In addition to the above-mentioned hot electron injection method, the programming method of this memory cell does not use a tunneling effect method. It applies a higher bias voltage to the control gate 318c (or d), and A lower bias voltage is applied to the source / drain region 330c (or d) on the side. The difference between this lower bias voltage and the higher bias voltage is large enough to allow electrons to pass through the Fowler-Norheim Tunneling phenomenon. The source / drain region 330c (or d) flows into the floating gate 314c (or d). The reading method is known to those skilled in the art. Due to the existence of negative charge, the floating gates 314c and 314d have the starting voltage of the channel below them when writing (required to control the gate 318c / d when the channel is open). When the voltage) is greater than the erased state, the starting voltage of the channel in the writing state is referred to as VTwnie, and the starting voltage in the erasing state is referred to as VTenise, and VTwnie> VTerase. Please refer to FIG. 20, which illustrates a method for reading a non-volatile memory cell according to a preferred embodiment of the present invention. Here, the floating gate 314c is used (please read the precautions on the back before filling this page). ) One δϋ. --Line_ This paper size is in accordance with Chinese National Standard (CNS) A4 (210x297 mm) 479331 A7 B7 ^ 992twf.doc / 006 V. Description of the invention (/ Γ |) The process of reading the data is taken as an example . As shown in Figure 20, this process is to apply a bias voltage V6 greater than VTwnie on the control gate 318d to open the channel below the floating gate 314d. At the same time, a bias v5 is applied to the control gate 318c, which is related to vTerase And the relationship between vTwnie and vTwnie is vTwnte > v5 > vTei.ase. Then, different bias voltages are applied to the two source V drain regions 330c and 330d, and the source / drain regions 330c and 330d are turned on or off to determine whether data is written in the floating gate 314c. Please refer to the next paragraph for the phenomenon and interpretation method. Because the voltage V6 of the control gate 318d > VTwrite > VTerase, regardless of whether data is written in the floating gate 314d, the lower channel can be opened; on the other hand, the voltage 控制 5 of the control gate 318c and VTenise The relationship between ^ Twrite and VTwrite is VTwrite> V5> VTerase '. Therefore, when the floating gate 314c is in the erased state, the channel is opened, and in the written state, the channel is not opened. At this time, because the doping type of the doped region 333 is also n-type, when the source / drain regions 330c and 330d can be conducted, it means that the floating gate 314c is in an erased state; and when the source / When the drain regions 330c and 330d cannot be conducted, it indicates that the floating gate electrode 314c is in a writing state. As described above, in a memory cell of the dual-bit non-volatile memory according to the two embodiments of the present invention, two stacked gate structures 310c and 310d are used as a group to share a pair of source / drain regions 330c and 330d 5 Therefore, only when the channels under the floating gates 314c and 314d are opened at the same time, the conduction between the source / drain regions 330c and 330d can be achieved. Because the two floating gates 314c and 314d are over-erased at the same time, the probability of continuous conduction between the source / drain regions 330c and 330d is also very low, so this paper is compared with the conventional stacked gate design. Standards apply to China National Standard (CNS) A4 (210 x 297 mm) --------------------- Order --------- Line- -(Please read the precautions on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 479331 A7 B7 6992twf. Doc / 006 V. Description of the invention (β) (Please read the precautions on the back before filling in this Page), the chance of misjudgment of information is greatly reduced. At this time, please refer to the description of the separation gate structure and FIG. 2 above. Since one stack gate structure in one memory unit of the present invention can prevent the misjudgment problem caused when the other stack gate structure is over-erased, the stacking The gate structure can also be called a transfer gate, and its function is similar to that of the transfer gate 218a in FIG. 2. In addition, since any memory cell of the dual-bit non-volatile memory of the present invention has two floating gates to store two-bit data, and a stacked gate structure is used as a transfer gate to prevent another A problem that arises when a stacked gate structure is over-erased, instead of adding a transfer gate 218a to the side of the control gate 218 as in the conventional split gate structure 210, so it is in contrast to the unit cell memory designed with the split gate structure 210. In comparison, the area required for storing each bit when using the present invention can be greatly reduced. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. As shown in Figures 9 and 9A, the present invention continuously defines a control gate 318a and a floating gate 314a; as shown in Figure 18, the present invention is A stacked gate structure 310c (or d) is used as a transfer gate to prevent problems caused when the floating gate electrode 314d (or c) is over-erased. Therefore, when using the present invention, it is not necessary to define the floating gate and the control gate / transfer gate separately by two lithographic processes as in the conventional separation gate structure process, so it is a self-aligning process without generating Component electrical inconsistencies. In addition, please refer to FIG. 18, since the doped region 333 is only used as a current path in the two-bit non-volatile memory of the present invention, it only needs to have the same The doping type is sufficient, and the width a may be smaller than the width b of the source / drain regions 330a and 330b. Therefore, compared with the conventional stack gate design shown in Fig. 1, the 20 paper sizes of the present invention are applicable to the Chinese National Standard (CNS) A4 specification 0x297 public love) " " " 479331 A7 B7 69 92twf doc / 006 V. Description of the Invention (iq) The dual-bit non-volatile memory requires a smaller area for storing each bit. Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application. (Please read the note on the back? Matters before you fill out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper applies the Chinese National Standard (CNS) A.4 specification (210 x 297 mm)