TWI360201B - Nonvolatile memory having raised source and drain - Google Patents

Description

1360201 . ·· * a

> Three-I-I: TW3191PA; Nine, Invention Description: [References in Related Applications] The present invention claims that the inventor Liao Yijun applied for the application of the US Patent Provisional Application No. 60/806,840 on July 10, 2006. Right, the name of the case "" is the groove channel non-volatile memory cell structure, manufacturing method and operation method (Recess-Channel Non-Volatile Memory Cell Structure,

TECHNICAL FIELD OF THE INVENTION The present invention relates to non-volatile memory, and more particularly to non-volatile memory having a varying channel region interface, such as changing the channel region interface. The source of the rise and the bungee or a recessed channel area. [Prior Art] Electrically programmable and erasable volatile memory technology based on a charge storage structure called EEPROM and flash memory. It is used in various modern applications. ^Multiple memory cell structures are £EPR〇m is used with flash memory. When the size of the integrated circuit is reduced, the importance of the memory cell structure based on the charge trapping dielectric layer is gradually increasing, because of the ability to adjust the size and the simplicity of the process. The memory cell structure based on the charge trapping dielectric layer contains a structure known as the industrial name PHINES 'SONOS or NROM. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as xenon nitride. When the negative charge is captured, the memory 5 1360201 a . . . __ '

Sanwei: The threshold voltage of the TW3191PA unit will increase. The threshold voltage of the memory cell is reduced by removing the negative charge from the charge trapping layer. The conventional non-volatile nitride cell structure is planar so that an oxidant-nitride-oxide structure is formed on the surface of the substrate. However, this planar structure is associated with poorly tunable size, high power stylization and erase operations, and high chip resistance values. This structure is described in ΥΕΗ, CC et al., "PHINES: New low-power stylized / φ erase, small interval, 2-Bit flash memory per unit has two digits (PHINES. A Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory)”, Electronic Devices Conference, 2002, IEDM 02. Digest. International, 8-11, December 2002, Pages: 931-934. 'The planar structure of this conventional non-volatile nitride cell structure needs to be modified to handle one or more disadvantages. [Summary of the Invention] (IV) Non-volatile memory in a rotating heteropolar region. One of the inventions __-j-^. The unit product body is a non-volatile memory early enthalpy circuit, which includes - charge storage and a plurality of dielectric structures. Charge storage ^ and polar regions In the embodiment, the charge is in the wrong state. In various different embodiments, the charge position is several or more. In the material structure of the storage structure, the charge trap 6 1360201

'Three ^^: TW3191PA ^ catch structure or a nano crystal structure. The source and drain regions are separated by a channel that is part of a circuit that undergoes inversion to electrically connect the source and drain regions. In the absence of an electric field, the dielectric structure electrically isolates a plurality of portions of the circuit to overcome these dielectric structures. The dielectric structure is at least partially located between the charge storage structure and the channel region and at least partially between the charge storage structure and a gate voltage source. An interface separates a portion of the one or more dielectric structures from the pass region. One of the first ends of the interface ends in an intermediate portion of one of the source regions, and one of the second ends of the interface ends in an intermediate portion of one of the drain regions. Since the source and drain regions are lifted off a substrate of the non-volatile memory cell integrated circuit, the first end of the interface ends in the middle portion of the source region, and the second end of the interface ends The middle part of the bungee area. To implement this interface, various embodiments of the lifted source and drain regions are located in polysilicon or epitaxial germanium. Some embodiments include a plurality of spacers separated from the source and drain regions of the substrate φ and the charge storage structure and dielectric structure. In various embodiments, the non-volatile memory cell integrated circuit is part of a NOR structure or a NAND structure. According to a second aspect of the present invention, a method for fabricating a non-volatile memory-cell integrated circuit is provided, comprising the steps of: forming a charge storage structure for each non-volatile memory cell in the array One or more dielectric structures. The charge storage structure stores charge to control the logic state stored by the non-volatile memory cell integrated circuit. In various embodiments, the charge storage structure stores one bit 7 1360201

Sanda number: TW3191PA or multiple bits. In various embodiments, the material of the charge storage structure is a charge trapping structure or a nanocrystalline structure. The dielectric structure is: 1) at least partially between the charge storage structure and a channel region; and 2) at least partially between the charge storage structure and a gate voltage source; forming a charge storage structure and one or more dielectrics After the structure, the drain and source regions of each non-volatile memory cell are formed in the array. The channel regions of each of the non-volatile memory cells in the array extend between the drain and source regions of the non-volatile memory cells in the array. The step of forming the drain and source regions of each of the non-volatile memory cells includes: adding a material layer to a substrate of the integrated circuit such that the gate and source regions are lifted off the substrate. Various embodiments add a polysilicon layer or an epitaxial layer to form the source and drain of the lift. Wherein, with respect to each of the non-volatile memory cells of the array, one interface separates one of the one or more dielectric structures from the channel region, and one of the first ends of the interface ends in an intermediate portion of the source region, and The second end of one of the interfaces ends in an intermediate portion of one of the drain regions. Some embodiments form a plurality of spacers for separating the source and drain regions lifted off the substrate from the charge storage structure and the dielectric structure. Some embodiments form a layer of dielectric material for separating the bit lines and word lines and forming the word lines as a gate voltage source. In various embodiments, the non-volatile memory cell integrated circuit is part of a NOR structure or a NAND structure. In other embodiments of the invention, the dielectric structure at least partially located between the charge trapping structure and the channel region comprises, as disclosed herein, a junction 8 Γ 360201

1 三^||号: TW3191PA ^. In order to make the above description of the present invention more comprehensible, a preferred embodiment will be described below in detail with reference to the accompanying drawings. FIG. 1 is a non-volatile memory. Schematic of the unit, the non-volatile memory unit has a recessed channel between the source and the drain region. Φ Gate 102, in most embodiments a partial word line, has a gate voltage Vg. In some embodiments the 'gate structure comprises a material' having a work function greater than the eigen work function of the N-type germanium, or greater than about 4.1 eV, and preferably greater than about 4.25 eV, including, for example, greater than about 5 eV. Representative gate materials include P-type polycrystalline stellite, titanium oxide, and other high work function metals and materials. Other materials having a relatively high work function suitable for embodiments of the present invention include: metals including, but not limited to, ruthenium (Ru), indium (Ir), nickel (Ni), and cobalt (Co); metal alloys, including But not limited to bismuth-titanium and nickel-titanium; _ metal nitrides; and metal oxides, including but not limited to yttrium oxide (Ru〇2) 〇 to work function gate materials produce a typical N-type polycrystalline dream gate Very high electron tunneling implant barrier. The implantation barrier of the N-type polysilicon gate with erbium dioxide as the external dielectric layer is around 3.15 eV. Thus, the embodiment of the present invention uses a material for the gate and the external dielectric layer, having an implantation barrier that is above about 3.15 eV, such as above about 3.4 eV, and preferably high. At about 4 eV. Regarding a P-type polysilicon gate having a ceria external dielectric layer, the implantation barrier is about 4.25 eV, and is produced relative to a cell having an N-type polysilicon gate with an outer dielectric layer containing ceria. 9 m Two-face number: TW3191Pa The original value of the It is reduced by approximately 2 volts. "Electric structure 104 is located in _1〇2. Another dielectric structure 1 is stored between 114 and 114 of the structure. The partial charge charge storage structure is vain, the first material 'which contains, for example, oxidation, although 12 〇 3) / he (4), the high dielectric constant of the electricity storage structure 106 stores the logical state of storage of the charge unit. First: = system is non-volatile memory is conductive, such as θ less. Β, the real charge of the storage structure of the storage structure of the storage structure of the second two: 矽 'with the two internal charge expansion throughout the electricity and nano The crystal ^ & example of the electric city structure is the charge trapping charge Ϊ = the new embodiment is not like the conductive material, will be ::: = r stored in the logical state: : = structure contains about 3 to 9 Nai The thickness of the nitride eve. -, ; ^ The primary region U 〇 has a source voltage Vs, and the non-polar region 112 and has a medium pressure of 2 . The source region 110 and the non-polar region 112 are in a plurality of bit lines of the embodiment ^ and are characterized by a junction depth 120. In the embodiment of the body region, the embossing number is a substrate or a well' and has a body. A channel 114 is electrically connected to source 110 and drain 112 in response to a suitable biasing configuration applied to gate 102, source 11 〇, drain 112, and body I22. The upper edge of the source and drain regions U6 is higher than the interface 118 between the via 114 and the dielectric 108. However, the interface 118 between the channel 114 and the dielectric structure 108 is maintained above the lower edge of the source and drain regions. 1360201

, Sanda number: TW3191PA " Therefore, the interface 118 between the channel 114 and the dielectric structure 108 ends in the middle region between the source region 110 and the non-polar region 112. ~ The source region 丨10 and the upper edge of the drain region 112 are aligned with the upper edge of the body region 122. Thus, the non-volatile memory cell of the first diagram is an embodiment of a recessed channel. Figure 2 is a schematic diagram of a non-volatile memory cell with a non-volatile § memory that has a source region and a non-polar φ region lifted off the semiconductor substrate. The non-volatile memory cells of Figures 1 and 2 are substantially similar. However, the source regions 210 and i: and the upper edge of the polar region 212 are located above the upper edge of the body region 122. Therefore, the non-volatile memory cell of Figure 2 is an embodiment of the source and drain of the lift. The interface 218 between the channel 214 and the dielectric structure 208 still ends in the middle region of the source region 210 and the drain region 212. Source region 210 and drain region 212 are characterized by a junction depth 220. Figure 3A is a schematic illustration of the injection of electrons from a gate into a charge storage structure in a non-volatile memory cell # with a recessed channel. The gate region 302 has a gate voltage Vg of -10V. The source region 3〇4 has a ιον or floating source voltage vp drain region 306 having a 1〇v or floating gate voltage Vd. The body region 308 has a body voltage of i 〇 V. • The figure is a representation of the electrons injected from the gate to the charge storage junction bridge in a non-volatile memory cell with lifted source and drain regions. The bias configuration of Figure 3B is similar to Figure 3A. . "Heart 4th is a schematic diagram of electron injection from a substrate into a charge storage structure in a non-volatile memory cell having a recessed channel. 1360201

Sanda number: TW3191PA Gate region 402 has a gate voltage Vg of 10V. The source region 4〇4 has -ιόν or a floating source voltage Vs. The drain region 406 has a -1 〇 v or floating drain voltage Vd. The body region 408 has a body voltage vb of -10V. Figure 4B is a schematic illustration of the injection of electrons from a substrate into a charge storage structure in a non-volatile memory cell having lifted source and drain regions. The bias configuration of Figure 4B is similar to Figure 4A. Figure 5A is a non-volatile memory cell with a recessed channel

Medium, band-to-band hot electron injection into the charge storage structure. ', the closed region 502 has a gate voltage of 10V. The Vgop+ type source region 5〇4 has a source voltage Vs of -5V. The p+ type drain region 5〇6 has 〇v or a floating drain voltage Vc^N type body region 508 has a body voltage vb of 〇v. Figure 5B is a diagram of a non-volatile memory cell towel with a raised source region and a non-polar region, with a hot electron injection from the strip to the charge storage structure. The bias configuration of Figure 5B is similar to Figure 5A.

Figure 6A is a schematic illustration of the channel's hot electron injection into the charge storage structure in a non-volatile memory cell having a recessed channel. The gate region 602 has a 10V turn-off® λ, and the gentleman has another gate voltage vPn+ type source region 604 eight has a source voltage of -5V Vse n+ type bungee region _ has a Q voltage V6P type body region _ Has a body voltage % of QV. / Figure 6B is a schematic diagram of a channel thermoelectric man-to-charge storage structure in a non-volatile memory cell having a raised source region and a non-polar region. The bias configuration of Figure 6B is similar to Figure 6A. Heart Figure 7A is a non-volatile memory unit with a recessed channel 12 1360201 -- ·

In the TW3191PA, the schematic diagram of the substrate hot electron injection into the charge storage structure. The idle region 702 has a closed-voltage voltage of 10 V. The source region 7 〇 4 ' has a source voltage VS of 0 V. The traitless zone 706 has a 0V immersion - voltage Vd. The N-type body region has a body voltage Vb. The p-type well region 710 has a well voltage Vw of -5V. The source region 7〇4 and the immersion region are located in the well region 710, and the well region 71() is located in the body region. Figure 7B is a schematic illustration of the thermal electron injection into the charge storage structure of the substrate in a non-volatile memory cell having raised source and drain regions. The bias configuration of Figure 7B is similar to Figure 7A. Figure 8A is a schematic illustration of a non-volatile memory cell 'hole from a dopant to a charge storage structure with a recessed human channel. The gate region 802 has an extreme voltage Vg between 10V. The source region is 8〇4 • 10V or the source voltage Vs of the ocean. The bungee zone 8〇6 has _ι〇ν or floating secret Vd. Benlong 8G8 has a torn body and multiple vb.帛8B is a schematic diagram of a hole injected into a charge storage structure from a gate in a non-volatile memory cell having a raised source region and a nonpolar region. The bias configuration of Figure 8B is similar to Figure 8A. Figure 9A is a schematic illustration of the injection of a hole from a substrate into a charge storage structure in a non-volatile memory cell having a recessed channel. The gate region 9〇2 has a gate voltage Vg of -10V. The source region 904 has a source voltage Vs of 1 〇V or floating. The drain region 906 has a voltage of 1 〇v or & The body region _ has a body voltage vb of 1 GV. Figure 9B is an illustration of the injection of a hole from a substrate into a charge storage structure in a non-volatile memory cell having a lifted source region and a drain region 13 1360201

Three ^ 1 §: TW3191PA v map. The 9B winter bias configuration is similar to Figure 9A. Figure 10A is a schematic illustration of the injection of inter-band thermoelectric holes into a charge storage structure in a non-volatile memory cell having recessed channels. The pole region 1002 has a idle pole region Vg of -10V". The n+ type source region 1004 has a source voltage Vs of 5V. The n+ type drain region 1006 has a 0V or floating drain voltage Vd. The P-type body region 1008 has a body voltage Vb of 0V. φ Figure 10B is an illustration of the injection of inter-band thermoelectric holes into a charge storage structure in a non-volatile memory cell having lifted source and drain regions. The bias configuration of Figure 10B is similar to Figure 10A. Figure 11A is a schematic illustration of the injection of channel thermowells into a charge storage structure in a non-volatile memory cell having recessed channels. The gate region 1102 has a gate voltage Vg of -10V. The p+ type source region 1104 has a source voltage Vs of 0V. The p+ type drain region 1106 has a 5V drain voltage Vd. The N type body region 1108 has a body voltage Vb of 0V. • Figure 11B is an illustration of the injection of a channel thermowell into a charge storage structure in a non-volatile memory cell with lifted source and drain regions. The bias configuration of Figure 11B is similar to Figure 11A. Fig. 12A is a schematic view showing the injection of a substrate thermowell into a charge storage structure in a non-volatile memory cell having a recessed channel. The interpole region 1202 has a -10V" between the extreme electric "Vg. The p+ type source region 1204 has a source voltage Vs of 0V. The p+ type drain region 1206 has a drain voltage of 0 V. The P type body region 1208 has a body voltage Vb of 6V. The N-type well region 1210 has a well voltage Vw of 5V. Source region 1204 and bungee 14 1360201

i: TW3191PA ^ is located in the well area 12, and the foot is in the body area Li Di map is the source of the lifted source and the substrate thermoelectric hole injected into the charge storage junction = Figure 12B bias The configuration is similar to Figure 12A. In the meta-input, the one-way read operation of the non-volatile memory of the concave channel is shown as one of the data on the right side of the electrical storage structure, 1304 d. 02 has a gate voltage % of 3V. η+ source region - has a source voltage of 1.5V Vsen+

The no-polar voltage.!>-type body right °° 3〇6-with 0V The (10) picture is the non-volatile data in the source and bungee regions with body voltage and sensitization The right side of the charge storage structure is similar to Figure 13A. "The bias configuration of the 13B diagram uses 1 2::: in the non-volatile memory single-fetch operation with the concave channel ^ = the reverse reading of the data on the left side of the storage structure 1404 has ^ = Pressure: The gate of the V"+ source region has no enthalpy of money/姊 has a ^ _ body £1408 has a body voltage Vb of ον. Transmitting memory single [: for the source region of the rise and the > and the non-swept data of the polar region, the reverse reading operation of the left side of the storage structure, the bias configuration type of Figure 14B] 5 1360201

Word: TW3191PA is similar to Figure 14A. Figure 15 is a schematic diagram of the capture operation between the non-volatile memory having a recessed channel and the data stored on the right side of the charge storage structure. ΐ ΐ 5〇 / 1 ΪΪ 1502 has a tearing gate voltage Vg ° n + type source region π π:, the source voltage Vs of the pollution. The n+ plastic germanium region 1506 has a voltage of 2V. The Vd°P-type body region 15〇8 has a body voltage of 〇v = the source of the lift (4) the non-volatile value of the disparity region is read and stored on the right side of the charge storage structure. Transmission _ ^ between the belt (9) take the operation of the schematic. The configuration of the WB chart is similar to the 〗5Α diagram. The unit A ® is read between the strips of the data stored on the left side of the charge storage structure in a non-volatile memory with a concave channel. The 1604 2 region 1602 has a gate voltage of 犹. The source voltage of the sprite source region and the source voltage of the r r2 V V S . The n+ type non-polar region 16 〇 6 has a floating 1 voltage (four) type body region, which is a body electric house Vb having 0V. The characterization, / Γ ΓΓ ΓΓ ( ( ( ( 举 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 。 The bias configuration of Fig. 16B is the one-way electric field of the memory, and flows through the specific part of the non-volatile memory to accurately store the storage structure. Large vertical and transverse electric fields lead to 1360201

Sanda number: TW3191PA ' Larger current between the strips. A biasing configuration is applied to a variety of different terminals to bend the bands sufficiently to cause current between the strips in the non-volatile memory cell structure while maintaining the potential difference between the non-volatile memory cell nodes Be low enough so that stylization or erasure does not occur. ^ In the bias configuration example, the non-volatile memory cell structure is reverse biased relative to the active source region or the drain region and the body region to create a junction of the reverse bias. In addition, the voltage of the gate structure causes these bands to bend to φ sufficient to cause interband tunneling through the non-volatile memory cell structure. The high doping concentration in one of the non-volatile memory cell structure nodes (in the majority of the embodiments, the source or drain regions). The structural node has a high charge density in the space charge region generated, and the voltage change of the space charge region in a short distance is helpful for generating an acute band bend. The electrons of the valence band on one side of the junction of the reverse bias are punctured to the conduction band on the other side of the junction of the reverse bias via the forbidden gap and drift down to the potential energy hill (potential) Hill), deeper to the N-type node of the junction of the reverse bias φ pressure. Similarly, the hole drifts over the potential energy hill away from the N-junction of the junction of the reverse bias and faces the P-type junction of the junction of the reverse bias. The voltage in the gate region controls the voltage at the junction of the reverse bias voltages near the charge storage structure. When the voltage of the gate structure becomes more negative, the voltage at the portion of the junction of the reverse bias located near the charge storage structure becomes more negative, resulting in a deeper band bend in the diode structure. As a result of at least some of the following combinations of (1) and (2), more current between the bands will flow: (1) occupied electron energy levels and bending energy bands on one side of the bending energy band 17 1360201

Sanda number: the incremental overlap between the unoccupied electron energy levels on the other side of TW3191PA; and (2) the narrower barrier between the occupied electron energy level and the unoccupied electron energy level Width (Sze, Physics of Semiconductor Devices, 1981). The net negative or net positive charge stored on the charge storage structure further affects the band curvature. According to Gauss's law, when the junction of the negative voltage and the reverse bias is applied to the gate region, the stronger electric field is connected by the reverse bias of the portion of the charge storage structure having a relatively high net negative charge. Partial experience. Similarly, when a positive voltage is applied to the gate region with respect to the reverse bias, the stronger electric field is the portion of the junction of the reverse bias that is close to the portion of the charge storage structure having a relatively high net positive charge. Experienced. The different bias configurations for reading and the biasing configuration for stylization and erasing show a careful balance. With respect to reading, the potential difference between the junction nodes of the reverse bias should not cause a substantial number of charge carriers to pass through a dielectric material to the charge storage structure and affect the charge storage state (ie, the programmed logic level). . In contrast, with respect to stylization and erasing, the potential difference between the junction nodes of the reverse bias is sufficient to cause a substantial number of carriers to pass through a dielectric material and affect the charge by inter-band hot carrier injection. Storage status. Figure 17 is a manufacturing flow diagram of a non-volatile memory cell array having a recessed channel showing various possible combinations of process steps of Figures 19-23. Figure 17 discloses the following combinations of process flows: Figures 19 and 22; Figures 19 and 23; Figures 20 and 22; Figures 20 and 23;

Three-face number: TW3191PA Figures 21 and 22; and Figures 21 and 23. These combinations are accompanied by backend processing. 18A and 18B are manufacturing flow diagrams of a non-volatile memory cell array having lifted source and drain regions. Fig. 18A is a manufacturing flow diagram of a NOR non-volatile memory cell array having one of the lifted source and drain regions. It shows various possible combinations of the process steps of Figs. The 18th figure discloses the following combination of process flows: Figures 24, 25 and 27; and Figures 24, 26 and 27. These combinations are accompanied by backend processing. Figure 18B is a manufacturing flow diagram of a NAND non-volatile memory cell array having one of the raised source and drain regions. It shows various possible combinations of the process steps of Figures 28-30. Figure 18B discloses the following combination of process flows: Figures 28 and 29; and Figures 28 and 30. These combinations are accompanied by backend processing. 19A to 19C are process steps for forming a trench in a non-volatile memory cell having a recessed channel before the 22nd or 23rd. In Figure 19A, oxide 1910 is deposited on substrate 1900. A photoresist is deposited and patterned, and the patterned photoresist is used to remove portions of the oxide in accordance with the photoresist pattern. In Figure 19B, the remaining photoresist 1922 protects the residual oxide 1912. The residual photoresist is removed' and the substrate not covered by the oxide is left in place. In Figure 19C, trench 1930 is etched into substrate 19A that is not covered by oxide 1912. Figures 20A to 20E are before the 22nd or 23rd, in the non-wing 19 1360201

Three-face number: The process step of reducing the length of a gate before forming a trench in the TW3191PA. The 20A to 20C drawings are similar to the 19A straight 19C chart. In Fig. 20D, a spacer 2040 is deposited into the trench leaving the next smaller trench 1932. In Fig. 20E, the portion of the gap wall beside the bottom of the trench is etched, leaving the spacer 2042. This gate length scaling can leave a smaller gate length than in Figure 19. 21A to 21E are process steps for expanding the gate length before forming a trench in the non-volatile memory cell before the 22nd or 23rd. Figures 21A through 21B are similar to the 19A straight 19B map. In Figure 21C, the remaining patterned photoresist is removed to expose the patterned oxide 1912. In Figure 21D, the patterned oxide is etched to leave a smaller patterned oxide 2112. In Fig. 21E, the trench 2132 is etched into the substrate 1900 which is not covered by the oxide 2112. This reduction in gate length will result in a longer gate length than in Figure 19. _ 22A to 22K are process steps after the 19th, 20th or 21th stage to form an N〇R non-volatile memory cell array, each NOR non-volatile memory cell is located in a trench In order to have each of the non-volatile memory cells have a concave channel. In Fig. 22A, an example - a dielectric material such as a 〇N 〇 layer and a charge storage structure 2250 are formed in the trench, thereby leaving a smaller trench 2232. In Fig. 22B, a gate material 2260 such as polysilicon is deposited. In Fig. 22C, the gate material is etched' so that the lower gate material 2262 remains inside the trench. In the figure, a dielectric material 2270 such as SlN is deposited on the gate material 2262 20

Claims (1)

13 Following 01 _ 101 January 13, revised replacement page 2012 Chuan 13_Re-examination 2|^申复&4*Correction 10. Patent scope: 1. A method for manufacturing a non-volatile memory cell integrated circuit, The method includes the following steps: _ forming a charge storage structure, one or more dielectric structures and a gate for each of the non-volatile memory cells in a non-volatile memory cell array, and the one or more dielectrics a structure: 1) at least partially between the charge storage structure and a channel region; and 2) at least partially between the charge storage structure and the gate; forming the charge storage structure and the one or more dielectrics Forming a drain region and a source region of each of the non-volatile memory cells in the non-volatile memory cell array, and the non-volatile memory cells in the non-volatile memory cell array a channel region extending between the drain region and the source region of the non-volatile memory cell in the non-volatile memory cell array, and forming the drain region of each of the non-volatile memory cells The step of the source region includes: adding a material layer to the non-volatile memory cell product before a portion of the drain region and the source region are formed on a substrate of the non-volatile memory cell integrated circuit On the substrate of the bulk circuit; and implanting ions from the material layer such that the ion is distributed to the material layer and a portion of the substrate, and the material layer and the portion of the substrate are formed. And the source region and the source region, the < and the polar region and the source region are lifted off the substrate; wherein, regarding each of the non-volatile memory cells of the non-volatile memory cell array, the interface is separated by the interface Or one of the plurality of dielectric structures 096125136 1013015752-0 35 -5OU201 101 January 13th 2012/1/13_Re-examination 2 Asahi & 4»' repair 1 £ Knife with the passage area, the interface a first end ends in the middle portion of the source region and a second end of the interface ends in a middle portion of the drain region. The step of forming the gate includes: forming a photolithography structure on the substrate The lithographic structure includes the charge storage junction The one or more dielectric structures, a gate material and a arsenium compound material are disposed on the gate material; a spacer is formed to cover the lithography structure; The spacer wall is such that the remaining spacer wall is formed on a side of the lithographic structure to form a spacer sidewall; and the galvanic material is used to: the sidewall and the yttrium compound material; a portion of the interface material of the material causes the nitrogen-cut compound material to be exposed and the remaining dielectric material is located around the sidewall of the spacer. The Nitrogen compound material is removed to expose the gate material. And forming another gate material on the gate material to form the gate. The method described in the patent item, wherein the (four) m feed _ county plate - worm 曰曰曰 夕 曰 添加 is added to make the secret zone and the simple electrode _ in the μ (four) layer. 3. The method of claim 1, wherein the step of adding the layer comprises: adding a lift away from the substrate - the polycrystalline stone 曰 曰 to make the money source _ Formed in the polycrystalline germanium layer. 4. As claimed in the first section of the patent, ten, + seven, soil ^ storage structure - charge trapping structure. The method described in the item, wherein Qianhe 096125136 1013015752-0 36 13^0201 _ 101 January 13, revised replacement page 2012/1/13_retrial 2 plus application & 4* amendment 5. If the scope of patent application The method of claim 1, wherein the charge storage structure is a nanocrystalline structure. 6. The method of claim 1, wherein the forming step of the dielectric structure between at least the portion of the charge trapping structure and the channel region comprises: forming a layer of ruthenium oxide; forming a An inter-zinc nitride layer is formed on the lower hafnium oxide layer; and an upper hafnium oxide layer is formed on the intermediate tantalum nitride layer. 7. The method of claim 6, wherein the lower ruthenium oxide layer has a thickness of about 5 to 20 angstroms. 8. The method of claim 6, wherein the intermediate tantalum nitride layer has a thickness of about 10 to 20 angstroms. 9. The method of claim 6 wherein the upper ruthenium oxide layer has a thickness of between about 15 and 20 angstroms. 10. The method of claim 6, wherein the dielectric tunneling tunneling barrier is less than or equal to 1.9 eV. 11. The method of claim 1, wherein the work function of the gate is greater than 4.1 eV. 096125136 101301575.2-0 37