TWI336941B - Nonvolatile memory array having modified channel region interface - Google Patents

Description

1336941

f* 三达编号: TW3137PA ί 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九(Recess-Channel Non-Volatile Memory Cell Structure, Manufacturing Methods and Operating Methods) ° φ [Technical Field of the Invention] The present invention has With respect to non-volatile memory, and particularly non-volatile memory having a varying channel region interface, the varying channel region interface is, for example, a lifted source and drain or a recessed channel region. [Prior Art] The electrically programmable and erasable volatile memory technology, known as EEPROM and flash memory storage structures, is used in a variety of modern applications. A plurality of memory cell structures are used for EEPR〇M and flash memory. When the size of the integrated circuit is reduced, the importance of the memory cell structure based on the charge trapping dielectric layer is gradually increasing because of the ability to adjust the size and the simplification of the process. The structure of the CMOS structure based on the charge trapping dielectric layer includes structures such as the industrial name PHines, SONOS or NROM. These memory cell structures store data by trapping charge in a charge trapping dielectric layer such as tantalum nitride. When the negative charge is captured, the threshold voltage of the memory cell increases. Record 5 5336941

> Sanda number: TW3137PA V The threshold voltage of the V body unit is reduced by removing the negative charge from the charge trapping layer. The conventional non-volatile nitride cell structure is planar to oxidize the oxide and nitride. A material (ΟΝΟ) structure is formed on the surface of the substrate. However, this planar structure has the ability to have a small size, a poorly programmed __. and a high erase operation power, and a high sheet resistance value. This structure is described in ΥΕΗ, CC et al., "PHINES: A new low-power stylized/erased, small-interval, single-cell dual-bit flash memory (PHINES: φ A Novel Low Power Program/ Erase, Small Pitch, 2-Bit per Cell Flash Memory), Electronic Device Conference, 2002, IEDM 丨 02. Digest. International, 8-11, December 2002, Pages: 931 - 934. Therefore, need to be modified The planar structure of the conventional non-volatile nitride cell structure to address one or more of the above disadvantages. SUMMARY OF THE INVENTION The present invention is directed to a non-volatile memory array having a varying channel region interface. In a first aspect, a non-volatile memory cell integrated circuit is provided, comprising a non-volatile memory array. The non-volatile memory array comprises a plurality of rows, each row comprising a plurality of non-volatile columns arranged in a series Memory unit. A subset of such non-volatile memory cells in the series is electrically connected to a bit line via other non-volatile block elements in the string One example of this situation is a NAND configuration. 6

Sanda number: TW3137PA non-volatile memory unit package human f-polar region and one or more dielectric shuttle charge storage structure, source region to control 甴 non-volatile memory single _ charge storage structure storage shape%. In various embodiments, the circuit library stores one logical element or multiple bits. In a variety of different _: What is the storage structure misplaced - the one-bit material is - electric capture structure or ~ ^, the polar storage of the charge storage structure is separated by 1 zone, the source zone and the immersion zone and 汲The circuit of the polar region is one of the eight parts in the case where the circuit is reversed to electrically connect the source structure. In the absence of an electric field to overcome the dielectric junction, the circuit is at least partially located in the electrically isolated portion of the Ray 4 °. The dielectric structure is between the charge storage "domain structure" and the channel region, and is at least partially located between the 'Q structure and a gate voltage source. Each bite/car column of each non-volatile memory cell One interface separates one part of the mountain eclipse's electrical structure from the channel region. One of the interfaces is the first = the middle part of the two H-pole regions, and one of the second ends of the interface ends at 〉 and the φ pq of the polar region To implement this interface, in this embodiment, the region is incorporated into one of the non-volatile memory cell integrated circuits. Some embodiments include a gate length adjustment dielectric. The material layer is at least partially located between the t-plate and the dielectric structure. According to a second aspect of the present invention, a method for manufacturing a non-volatile memory early-arc array integrated circuit is provided, comprising the following steps : The medium I first 'forms a plurality of non-volatile memory cells in this array. Each row contains a plurality of non-volatile memory cells arranged in a series. The example is a NAND configuration. This step contains the following substeps: 1336941

Sanda number: TW3137PA

V

From then, each of the non-volatile ... charge storage structures in the array forms a charge with one or more of the dielectric layers to control the state of storage by the non-volatile memory. In a variety of different implementations; early =; circuit storage - logic bits or multiple bits. In various implementations:: storage, = two materials are - charge trapping structure τ: the storage structure system is at least under the charge storage structure to:: points in the charge storage structure and - closed pole electrical cladding, To provide the interpole voltage. Then, a plurality of bit lines are formed to provide a subset of the non-volatile memory cells of each row in the current row to the rate column, via the == non-volatile memory The cells are electrically connected to a single bit line; the other then forms a portion and channel region in which each non-volatile (four) cell of the array is ... separated from one or more dielectric structures. The first end of the interface 2 ends in the middle portion of the first vertical line, and one end of the interface ends in the middle portion of the H-th line. To implement this interface, an embodiment forms a trench in a substrate to form a charge trapping structure and structure in the trench. ' ~

Some embodiments adjust the gate length by forming a fill that is at least partially between the dielectric structure and a substrate. Prior to forming the charge reservoir structure and the dielectric structure, certain embodiments include: adjusting the gate length S 1336941 by forming a dielectric layer and removing a plurality of portions of the dielectric material layer

^ 三达编号: TW3137PA V According to a third aspect of the present invention, a method of manufacturing a non-volatile memory cell array integrated circuit is provided, comprising: first, forming a non-volatile memory cell for each array of the array A charge storage structure and one or more dielectric structures. The charge storage structure stores electrical charge to control the logic t state stored by the non-volatile memory cell integrated circuit. In various embodiments, the charge storage structure stores one bit or multiple bits. In various embodiments, the material of the charge storage structure is a charge trapping structure or a nanocrystalline structure. One or more of the dielectric structures 1) are at least partially located between the charge storage structure and a channel region and 2) at least partially between the charge storage structure and a gate voltage source. Next, a first portion of one of the conductive layers for providing a gate voltage is formed. After forming a first portion of the conductive layer for providing a gate voltage, a plurality of bit lines are formed, for example, by adding dopants to provide a drain voltage and a source voltage to each of the non-volatile memories in the array. Body unit. The channel region of each non-volatile memory cell in the array is in the first bit line of the bit line providing the gate voltage and the bit line providing the source voltage A second bit line extends between. An example of this is a NOR configuration. After forming these bit lines, a second portion of one of the conductive layers for providing a gate voltage is formed. The first portion of the conductive layer is physically coupled to the second portion. Some embodiments include forming a layer of dielectric material to separate the bit lines from the second portion of the conductive layer. For each non-volatile memory cell of this array, an interface is separated 9 1336941

*' Sanda number: TW3137PA * One or more dielectric structures are part of the channel area. One of the first ends of the interface ends in a middle portion of the first bit line, and one of the second ends of the interface ends in a middle portion of the second bit line. To implement this interface, an embodiment forms a trench in a substrate to form a charge trapping structure and a dielectric structure in the trench. Some embodiments adjust the gate length by forming a fill that is at least partially between one or more dielectric structures and a substrate. Prior to forming the charge storage structure and the dielectric structure, certain embodiments include reducing the gate length by forming a layer of dielectric material and removing a portion of the dielectric material layer. In other embodiments of the invention, the dielectric structure at least partially between the charge trapping structure and the channel region comprises a germanium structure as disclosed herein. In order to make the above description of the present invention more comprehensible, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. FIG. 1 is a non-volatile memory unit. In schematic, the non-volatile memory cell has a recessed channel between the source and drain regions. Gate 102, in most embodiments a partial word line, has a gate voltage Vg. In some embodiments, the gate structure comprises a material having a work function greater than an intrinsic work function of the N-type, or greater than about 4.1 eV, and preferably greater than about 4.25 eV, including, for example, greater than about 5 eV. Representative gate materials include P-type polysilicon, titanium oxide, platinum, and other high work function metals and materials. 1336941 having a relatively high work function suitable for embodiments of the present invention

Sanda number: TW3137PA = material contains: metal, including but not limited to nails (metal alloys, including but not limited to 钌-titanium =: genus; and metal oxides, including but not limited to oxidized needle U 2) . The π work function gate material produces an implant barrier that is better than the code of the electron. The injection barrier of the bismuth-type polycrystalline slab gate with two gasifications is at 3 i5eV left 曰 = the embodiment of the thyristor (4) and the external dielectric layer is about 4 ev. Regarding the etched barrier with dioxo, the injection barrier is approximately 4 ^. The threshold of the unit containing the dioxide dielectric N-type multi (10)_ single m converging is reduced. 2 volts. °, the dielectric structure 104 is located at the gate 1〇2 and the electric 锉 ::::: interface 108 is located between the charge storage structure 1:1:: 4. Representative dielectric materials include dioxodere and oxynitrides having a large degree, or a non-existent amount thereof, including, for example, oxidation although l2〇3). (10) The dielectric constant material The charge storage structure 106 stores the logic state stored by the spheroid unit. First: = by non-volatile memory, such as polycrystalline, eve, =: = storage structure, storage structure. (4) Time ^, exhibition and charge storage of this electricity. One deposit = 1336941

♦, Sanda number: TW3137PA, the catching structure contains a thickness of about 3 to 9 nm. The source region 110 has a source electric house Vs, and the non-polar region 112 has a pole voltage vd. In the embodiment where the source region 110 and the polar region 112 are mostly, the 4-pole line 7L line ' is characterized by a junction depth. The body area .122 is implemented in a majority of substrates - wells or wells - and has a body voltage 'Vb. A channel 1H is electrically connected to the source 110 and the drain 112 in response to a suitable biasing configuration applied to the gate 102, the source 110, and the pole 112 and the body 122. • The upper edge of the practice and 〆 and pole regions 116 is higher than the interface 118 between the channel 114 and the dielectric structure 〇8. However, the | face 118 between the channel 114 and the dielectric junction 108 is maintained above the lower edge of the source and the non-polar region. Thus, the interface 118 between the channel 114 and the dielectric structure 〇8 ends in the intermediate region between the source region 110 and the drain region 112. The upper edge region of the source region 110 and the drain region 112 is aligned with the upper portion of the body region 122 < Thus, the non-volatile memory cell of the first diagram is an embodiment of a recessed channel. • Figure 2 is a schematic diagram of a non-volatile memory cell with a source region and a germanium region lifted off the semiconductor substrate. The non-volatile memory cells of Figures 1 and 2 are substantially similar. However, the source region 210 and the upper edge of the drain region 212 are located above the upper edge of the present region 122. Therefore, the non-volatile memory unit of Fig. 2 is an example of the source and the immersion of the lift. The interface 218 between the channel 214 and the dielectric structure 208 still ends in the middle region of the source region 210 and the drain region 212. The source region 210 and the drain region 212 are characterized by a connection 12 1336941

*" Sanda number: TW3I37PA it

The depth of the surface is 220. The first Μ @ is a schematic diagram of electrons from the gate to the charge storage structure in a non-volatile memory unit having a channel. The gate region 3〇2 has a gate voltage Vg of -10 ν. The source region has a source voltage Vs of 10V or floating. The immersion zone 3〇6 has purchased or floated; and the pole voltage Vd. The body region 3G8 has a body voltage of 1 〇v. Figure 3B is a diagram showing the bias configuration of electrons from the gate gap to the charge storage structure in a non-volatile unit having a source region of the lifted source region, similar to the third diagram. . Figure 4 is a schematic illustration of the electrons being injected from the substrate to the charge storage structure in a non-volatile memory cell having a recessed channel. The polarity region 402 has a gate voltage % of 1 〇ν. The source region has a source voltage Vs of -10V or >pre-action. The drain region 4 (10) has a -Μ or floating drain voltage Vd. The body region 408 has a body voltage vb of _1 〇v. Fig. 4B is a schematic diagram of the electrons from the base m to the charge storage structure in the non-volatile memory unit having the lifted and the non-polar regions. The bias configuration of Figure 4B is similar to Figure 4A. Figure SA is a band-to-band thermoelectric in a non-volatile memory cell with a concave human channel. The illustrated dummy region 502 implanted into the charge storage structure has a gate voltage vg of 丨0V. The metering source region 5〇4 has a source voltage Vs of -5V. The time-type drain region 5〇6 has or floats the drain voltage V6N-type body region 5〇8 has a body voltage vb of 〇v. Figure 5B shows the non-volatile content in the source and bungee regions with lift 13 1336941

Sanda number: TW3137PA A schematic diagram of the inter-band hot electron injection to charge storage structure in the 记忆3 memory. The bias configuration of Figure 5B is similar to Figure 5A. Figure 6A is a schematic illustration of the channel hot electron injection into the charge storage structure in a non-volatile memory cell having a recessed channel. The interpole region 602 has a pole voltage Vg between 1 〇V. ; ^ source (four) _ has a source voltage of -5V Vp n + drain region _ has ^ no pole voltage W. ? Type body region _ body voltage with GV Fig. 6B is a schematic view of a non-volatile body unit having a lifted source region and a non-polar region, which relies on an electron injection to a charge storage structure. The bias configuration of Figure 6B is similar to Figure 6A. The figure is a schematic diagram of the substrate hot electron injection into the charge storage structure in a non-volatile memory cell having a recessed channel. The gate region 702 has a source voltage Vs of a pole (4) ν "+ source region 7 〇 4 2 〇V between 10V. The n+ type secret area is written with the utmost p vd. The body region 708 has a body voltage vb of _6V. ^ ^ Zone 7H) has a well voltage Vw of -5V. The source area is said to be only in the 71没 of the well area, and the well area is located in the body area. Fig. 7B is a schematic view showing the injection of hot electrons into the charge storage structure of the substrate in the non-volatile J-body unit having the lifted source region and the non-polar region. The bias configuration of Figure 7B is similar to Figure 7A. Figure 8A is a schematic diagram of a non-volatile memory cell having a recessed channel into which a hole is injected from a gate to a charge storage structure. The gate region 802 has a closed-pole voltage Vg of 10V. The source region has a -mόν or floating source voltage Vs. Bungee area 8〇6 has ·(10) or float 1336941

’ Sanda number: TW3137PA, moving bungee voltage Vd. The body region 808 has a body voltage Vb of -10V. Figure 8B is a schematic illustration of the injection of a hole from a gate into a charge storage structure in a non-volatile memory cell having a lifted source region and a drain region. The bias configuration of Figure 8B is similar to Figure 8A. ‘9A is a schematic diagram of a hole injected into a charge storage structure from a substrate in a non-volatile memory cell t having a recessed channel. The gate region 902 has a gate voltage Vg of -10V. Source region 904 has a 10V or floating source voltage Vs. The drain region 906 has a 10V or floating drain voltage Vd. The body region 908 has a body voltage Vb of 10V. Figure 9B is a schematic illustration of the injection of a hole from a substrate into a charge storage structure in a non-volatile memory cell having a lifted source region and a drain region. The bias configuration of Figure 9B is similar to Figure 9A. Figure 10A is a schematic illustration of the injection of inter-band thermoelectric holes into a charge storage structure in a non-volatile memory cell having recessed channels.

The gate region 1002 has a gate voltage Vg of -10V. The n+ type source region 1004 has a source voltage Vs of 5V. The n+ type drain region 1006 has a 0V • or floating drain voltage Vd. The P-type body region 1008 has a body voltage Vb of 0V. Fig. 10B is an illustration of the injection of inter-band thermoelectric holes into a charge storage structure in a non-volatile memory cell having a raised source region and a drain region. The bias configuration of Figure 10B is similar to Figure 10A. Figure 11A is a schematic illustration of the injection of channel thermowells into a charge storage structure in a non-volatile memory cell having recessed channels. The gate region 1102 has a gate voltage Vg of -10V. p+ source region 15 1336941

The i-number: TW3137PA 1104 has a source voltage of ον Vsap + type drain region 11〇6 has a gate voltage type body region 11〇8 having a body voltage % of 〇v. Section 11B® is intended to inject a channel thermowell into a charge storage structure in a non-volatile memory cell with lifted source and drain regions. The bias configuration of Figure 11B is similar to the UA diagram. Figure 12A is a sound map of a substrate thermowell injected into a charge storage structure in a non-volatile memory cell having a recessed channel. ^Polar area·There is a source of the source voltage with a source voltage Vs of 0V. The p+ type has no polarity region 12〇6 and has 〇v = voltage tree body region 1208 has a body voltage Vb of 6V. It has a well voltage Vw of 5V. The source region deputy and the immersion = the system is located in the yucca, and the wire 121G is located in the body region, the Li 12B diagram is in the source of the lifting = memory unit, the substrate thermoelectric hole is injected into the charge element, with 1 2. A non-volatile memory cell with a recessed channel for reading a picture stored in a charge dry direction read operation. ΤSave, ,,. On the right side of the structure - anti-13. The gate of the second pole is "electrical" (4). ===_ Have the first (10) stomach system is in | there is t 0V body power repeatedly Vb. In the memory unit, the non-volatile source of the two-two U source region and the non-polar region is stored on the right side of the charge storage structure. 1336941

Every number: TW3137PA, the data: schematic diagram of the reverse read operation. The first is similar to Figure 13A.阋 偈 偈 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第Reverse reading of the data on the left side of the memory

The gate region 1402 and the ancient B 1404 have a source of 0V and a gate electric house Vg. The no-polar voltage of the η+-type source region is purchased. The ^^^+-type non-polar region should have a 1·~•* 14Β graph system with a body voltage of 0V at 丄4〇8. The reverse reading operation of the source region and the non-polar region of the priming memory is similar to that on the left side of the storage structure. Do not think about it. The first SA diagram of the bias configuration type in Fig. 14B is in the case of a recessed channel:: take: charge storage structure • data: band • 15〇4 ^ ΪΓ02 has ^ 〇V closed-pole voltage %... type source Polar zone

1506 2V Body & 1508 has a body voltage vb of 〇v. The 恃 恃 在 在 在 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 _ _ _ _ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四The figure is for reading between the strips of non-volatile memory with concave channels for storing data located on the left side of the electrical dump structure 17 1336941

^ Sanda number: TW3137PA Take a sketch of the work. The gate region 1602 has a gate of -1〇v 1604 9V ^ 莹Vg. The n+ type source region has a source voltage Vs of 2V. The n+ type non-polar region (10) has a bungee voltage V&P-type body region 16〇8/, and there is a spear-moving _(four) for the body of the Ίον I ν I I I I 之 之 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I A schematic representation of the storage on the left side of the charge storage structure. The bias configuration of Figure 16 is similar to the 16th diagram.

Because of,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The transverse electric field causes a large inter-τ current. The bias configuration is applied to a variety of different terminals to bend these bands sufficiently to produce inter-band currents in the non-volatile memory cell structure, while at the same time The potential difference between the volatile memory cell nodes is kept low enough that stylization or erasing does not occur. In the bias configuration example, the non-volatile memory cell structure is relative to the active source region or not. The polar region and the body region are reverse biased to create a junction of reverse bias. Furthermore, the voltage of the gate structure causes the energy bands to bend sufficiently to cause interband tunneling through the non-volatile memory cell structure. a highly doped concentration in a non-volatile memory cell structure node (in most embodiments, a source region or a drain region), wherein the structural node has a high charge of the generated space charge region Density, and the space charge region changes in voltage within a short distance, help produce sharply curved band crossbow ° junction of the reverse biased located - this electron valence band of the upper side via the 1336941-- __________ _ _

y Sanda number: TW3137PA v Prohibited gap traversing to the other side of the junction on the reverse bias

Belt, and drift down to the potential hill, deeper into the N-node of the junction of the reverse bias. Similarly, the hole drifts over the potential energy hill, away from the N-junction of the junction of the reverse bias, and faces the P. node of the junction of the reverse bias. The voltage in the gate region controls the voltage at the junction of the reverse bias voltages near the charge storage structure. When the voltage of the gate structure becomes more negative, the voltage of the portion of the junction of the reverse bias located near the charge storage structure becomes more negative, resulting in a deeper band bend in the diode structure. As a result of at least some of the following combinations of (1) and (2), more current between the bands will flow: (1) the occupied electron energy level on one side of the bending energy band and the other side of the bending energy band The increasing overlap between the unoccupied electron energy levels; and (2) the narrower barrier width between the occupied electron energy level and the unoccupied electron energy level (Sze, Physics of Semiconductor Devices, 1981). The net negative or net positive charge stored on the charge storage structure goes further • Affects the band curvature. According to Gauss's law, when the junction of the negative voltage and the reverse bias is applied to the gate region, the stronger electric field is connected by the reverse bias of the portion of the charge storage structure having a relatively high net negative charge. Partial experience. Similarly, when a positive voltage is applied to the gate region with respect to the reverse bias, the stronger electric field is the portion of the junction of the reverse bias that is close to the portion of the charge storage structure having a relatively high net positive charge. Experienced. Different bias configurations for reading and about stylization and erasure 19 1336941

''Sanda's number: TW3137PA^'s bias configuration shows a careful balance. With respect to reading, the potential difference between the junction nodes of the reverse bias should not cause a substantial number of charge carriers to pass through a dielectric material to the charge storage structure and affect the charge storage state (ie, the programmed logic level). . In contrast, with regard to stylization and erasing, the potential difference between the junction nodes of the reverse bias is sufficient to cause the substantial number of carriers to pass through a dielectric material and be affected by inter-band thermal carrier injection. v Charge storage status. Figure 17 is a manufacturing flow diagram of a non-volatile memory cell φ array having a recessed channel showing various possible combinations of process steps of Figures 19-23. The figure illustrates the combination of process flows as follows: Figures 19 and 22; 19 and 23; 20 and 22; 20 and 23; 21 and 22; and 21 and 23. These combinations are accompanied by backend processing. 18A and 18B are manufacturing flow diagrams of a non-volatile memory cell array having lifted source and drain regions. Figure 18A is a manufacturing flow diagram of a NOR non-volatile memory cell array with one of the source and drain regions of the lift, showing various possible combinations of the process steps of Figures 24-27. Figure 18A discloses the following combination of process flows: Figures 24, 25 and 27; and Figures 24, 26 and 27. These combinations are accompanied by backend processing. Figure 18B is a manufacturing flow diagram of a NAND non-volatile memory cell array having one of the source and drain regions of the lift, showing various possible combinations of the process steps of Figures 28-30. Figure 18B discloses the following combination of process flows: Figures 28 and 29; and Figures 28 and 30. These 20 1336941 two-numbered: TW3137PA v combination is accompanied by back-end processing. 19A to 19C are process steps for forming a trench in a non-volatile memory cell having a recessed channel before the 22nd or 23rd. In Figure 19A, a telluride 1910 is deposited on substrate 1900. The photoresist is deposited and patterned' and the patterned photoresist is used to remove portions of the oxide in accordance with the photoresist pattern. In Figure 19B, the remaining photoresist 1922 protects the residual oxide 1912. The residual photoresist is removed and the substrate not covered by the oxide is etched. In Fig. 19C, the trench 1930 is etched into the substrate 1900 that is not covered by the oxide 1912. 20A to 20E are process steps for reducing the length of a gate before forming a trench in the non-volatile memory cell before the 22nd or 23rd. Figures 20A through 20C are similar to Figures 19A through 19C. In the 20th DD, a spacer 2040 is deposited into the trench, leaving a smaller trench 1932 in the 20E, the spacer portion beside the bottom of the trench is etched, leaving the spacer 2042 . This gate length ratio can be adjusted to leave a smaller gate length than in Figure 19. 21A to 21E are process steps for expanding a gate length before forming a trench in the non-volatile memory cell before the 22nd or 23rd. Figures 21A through 21B are similar to Figures 19A through 19B. In Figure 21C, the remaining patterned photoresist is removed to expose the patterned oxide 1912. In Figure 21D, the patterned oxide is etched leaving a smaller patterned oxide 2112. In FIG. 21E, the trench 2132 is etched and recessed to be covered by the oxide 2112. 21 1336941

Order Sanda number: TW3137PA V substrate 1900. This gate length scaling will result in a longer gate length than in Figure 19. , 22A to 22, the figure is the end of the process of the 19th, 2nd or 21th process, to form an N〇R non-volatile memory cell array, 'each calendar non-volatile memory cell is located - Ditching so that each 'non-volatile memory cell has a - recessed channel. In Fig. 22A, a dielectric material such as a germanium layer and a charge storage structure 225 are formed in the trench, thereby leaving a smaller trench 2232. In the first coffee, for example, a polycrystalline stone gate material 226 沉积 is deposited. In the first figure, the gate material is annealed so that the lower gate material 2262 remains inside the trench. In the second figure, for example, a dielectric material 227 of SiN is deposited on the material. In Figure 22E, the dielectric material is engraved and the remaining dielectric material 2272 is inside the trench. In Figure 22F, the residual patterned oxide is removed. At this point, the stack of gate material 2262 and oxide 2272 rises above the surface of the substrate. At 22g, ion implantation forms source region 2280 and drain region 2282. In Fig. 22H, #deposited oxide 2290 such as oxidized oxide. In Fig. 221, the excess oxide covering the oxide 2272 is removed, for example, by CMP, dip_back or etch back. In Figure 22J, the oxide η" is removed. In Figure 22K, an additional gate material is deposited to form the gate region 2264. Figures 23A through 23E are the end of the process after the 19th, 20th or 21th a step of forming a NAND non-volatile memory cell array, each NAND non-volatile memory cell being located in a trench such that each non-volatile memory cell has a recessed channel. 22 1336941

^ Sanyan: TW3137PA V ', for example, a dielectric material of 0N0 layer and a charge storage structure 2250 are formed in the trench, thereby leaving a smaller trench 2232. In Fig. 23], a gate material 2260 such as polysilicon is deposited. In Fig. 23C, the excess gate material is removed, for example by CMP, to expose the 〇N 〇 layer. In 'FIG. 23D', the residual patterned oxide is removed. At this point, the gate material 2262 rises above the surface of the substrate. In Fig. 23E, ion implantation forms source region 2380 and drain region 2382. Figures 24A through 24D are process steps beginning at the beginning of Figure 25 or 26 to form the lifted source and drain regions of a non-volatile memory cell in a NOR array. In Fig. 24A, a dielectric material such as a 〇N 层 layer and a charge storage structure 2410 are deposited on the substrate 2400. In Fig. 24B, a gate material such as polysilicon is deposited, for example, an oxide material of SiN is deposited on the gate material to form a photolithographic structure 'residual SiN 243 〇, poly 矽 242 〇 and 0N0 2412 Stacking. In Fig. 24C, a spacer 2440 is formed. In Fig. 24D, the spacer is etched while the lower spacer sidewall 2442 remains. ^ 25th to 25th is a process step after the 24th and before the 27th, which uses epitaxy to form a non-volatile § memory unit in an N〇R array. The source area and the bungee area. In Fig. 25A, an epitaxial 矽 255 沉积 is deposited. In Fig. 25B, ion implantation forms source region 2560 and non-polar region 2562. 26A to 26C are process steps after Fig. 24 and before Fig. 27, which use polysilicon to form a source of lift for a nonvolatile § memory element in an N〇R array District and Wuji District. In the 23rd 1336941

~ Sanda number: TW3137PA v 26A, deposited polycrystalline germanium 2650. In Figure 26B, the polysilicon is etched back to leave polysilicon 2652. In Figure 26C, ion implantation forms source region 2660 and drain region 2662. The 27A to 27D diagram ends the process 'step' before the 25th or 26th figure to form a NOR non-volatile memory cell array, and each of the N0R non-volatile memory cells has a source region for lifting. With the bungee area. In Fig. 27A, a dielectric material such as HDP oxide is deposited to cover the structure including the spacer sidewalls and oxide 2430. In the 27B φ diagram, the excess oxide covering the oxide 2430 is removed, for example, by CMP, dip-back or back-to-back, while the remaining oxide 2772 surrounds the sidewall of the spacer. In Figure 27C, oxide 2430 is removed. In Figure 27D, additional gate material is deposited to form gate region 2722. 28A to 28D are process steps starting before the 29th or 30th drawing to form a NAND non-volatile memory cell array, each NAND non-volatile memory cell having a source region and a lift Polar zone. In Fig. 28A, a dielectric material such as a germanium layer and a charge storage structure 281 are deposited on the substrate 2800. In Fig. 28, a gate material such as polysilicon is deposited to form a photolithographic structure, and a stack of polycrystalline germanium 2820 and germanium 2812 remains. In Fig. 28C, a spacer 2840 is formed. In Fig. 28D, the spacer is etched while the spacer sidewall 2842 remains. The 29th to 29th drawings are the steps of the finishing process after the 28th drawing, which uses the epitaxial germanium to form a NAND non-volatile memory cell array, and each NAND non-volatile memory cell has a source of lifting. Polar zone 24 丄336941

Sanda number: TW3137PA and bungee area. In Figure 29A, epitaxial germanium 2950 is deposited. In the FIG. 29B diagram, the ion implantation method forms the source region 2960 and the drain region 2962.

30A to 30C are process steps ending after FIG. 28, which use polysilicon to form a NAND non-volatile memory cell array, each NAND non-volatile memory cell having a source region of lift Bungee area. 30A to 30C are process steps after FIG. 24 and before the 27th drawing, which use polysilicon to form a lift source region of one of the non-volatile memory cells in an n〇r array. With the bungee area. In Fig. 30A, polycrystalline germanium 3〇5〇 is deposited. In the third panel, the polysilicon is etched back to leave the polysilicon 3052. In Fig. 30C, the ion implantation method forms source region 3060 and drain region 3062. Figure 31 is a block diagram of a non-volatile memory volume circuit having an exemplary channel region as disclosed herein. The integrated circuit 315G includes a memory channel, a memory channel, a memory channel, a memory channel, a memory channel, a memory channel, a memory channel, a memory channel, a memory channel, a memory channel, a channel region, such as a recessed channel region, or a lifting device: The coffee department is connected to a plurality of character lines. Line decoder 31: line 3HM, which is provided along the memory array by a number of bits, and the address is provided to the line solution as (10) and column 2 to line solution (4) gamma system _# dragon row 3107 Connect 仃 Decrypt 3103. The data is entered via data entry ^(1) from 25 1336941

^ Erda number: TW3137PA The input/output port on the integrated circuit 3150, or from other sources inside or outside the product, to the data input and output in the box 3106. Structure. - The material is supplied from the 2 amplifiers on the block side to the wheel/wheel exit on the integrated circuit 315 via the data output 'line 3115, or other information inside or outside the integrated circuit 315G. aims. — = Configuration State Machine Controls the configuration of the bias supply supply voltage 3(10) (eg 'Yes, acknowledgment and stylized acknowledgment voltage'), and the configuration used to program, erase and read the memory cells.

Figure 32 is a schematic illustration of a recessed-to-non-volatile memory cell between the source and drain regions, whereby the lower dielectric has three thin layers. This structure is similar to the non-volatile = memory cell of the figure, but the dielectric structure 1 〇 8 (between the charge storage structure 1 and the channel region Π 4) is replaced by a three-layer thin structure 3208. The structure 3208 has a small hole with a barrier to the barrier, for example less than 戋 equals about 4.5 eV, or preferably less than or equal to about 1.9 eV. The approximate thickness range of the gentleman structure 3208 is as follows. Regarding the lower oxide: < 2 Å, 5-20 angstroms, or < 15 angstroms. About the intermediate nitride: < 2 〇 咬 10-20 angstroms. Regarding the upper oxide: < 20 angstroms or 15-20 angstroms. Some embodiments of the memory cell of Figure 32 are represented by SONONOS or band gap ^^ (BE)-SONOS. Additional details of various embodiments of the three-layered thin crucible structure 3208 are disclosed in U.S. Patent Application Serial No. 11/324,540, the disclosure of which is incorporated herein by reference. ~ Figure 33 is a schematic diagram of a non-volatile memory cell having a source region and a polar region lifted off the semiconductor substrate, thereby enabling the lower dielectric structure to have a 26 1336941

^ Sanda number: TW3137PA * There are three layers of thin tantalum structure 3208. In the above, the present invention has been disclosed in the above preferred embodiments, but it is not intended to limit the present invention. Those skilled in the art having the knowledge of the present invention can make various changes and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

27 1336941 --

^ Sanda Number: TW3137PA « [Simplified Schematic] Figure 1 is a schematic diagram of a non-volatile memory cell with a recessed channel between the source and drain regions. Figure 2 is a schematic diagram of a non-volatile memory cell having a source region and a drain region lifted off the semiconductor substrate. ^ Figure 3A is a schematic diagram of electrons injected from a gate to a charge storage structure in a non-volatile memory cell having a recessed channel. Figure 3B is a schematic illustration of the injection of electrons from the gate into the charge storage structure in a non-volatile memory cell having a lifted source region and a drain region. Figure 4A is a schematic illustration of the injection of electrons from a substrate into a charge storage structure in a non-volatile memory cell having a recessed channel. Figure 4B is a schematic illustration of the injection of electrons from a substrate into a charge storage structure in a non-volatile memory cell having lifted source and drain regions. Figure 5A is a schematic diagram of the injection of hot electrons between the strips into the charge storage structure in a non-volatile memory cell having a recessed channel. Fig. 5B is a schematic view showing the injection of hot electrons between the bands into the charge storage structure in the nonvolatile memory unit having the lifted source region and the drain region. Figure 6A is a schematic illustration of the channel hot electron injection into the charge storage structure in a non-volatile memory cell having a recessed channel. Figure 6B is an illustration of the channel hot electron injection into the charge storage structure in a non-volatile memory cell having lifted source and drain regions. 28 1336941

^ Sanda number · TW3137PA ^ Figure. Figure 7A is a schematic diagram of the substrate's hot electron injection into the charge storage structure in a non-volatile memory cell having a recessed channel. Figure 7B is a schematic diagram of the substrate's hot electron injection into the charge storage structure in a non-volatile memory cell having a raised source region and a drain region (Fig. 8A is a recessed channel) In the non-volatile memory cell, a schematic diagram of a hole injected from the gate to the charge storage structure. • Figure 8B shows the non-volatile memory cell in the source and drain regions with lift. A schematic diagram of a hole injected from a gate to a charge storage structure. Figure 9A is a schematic diagram of a hole injected into a charge storage structure from a substrate in a non-volatile memory cell having a recessed channel. Schematic diagram of the injection of holes from the substrate into the charge storage structure in the non-volatile memory cells of the source and drain regions of the lift. • Figure 10A shows the non-volatile memory cells with recessed channels. Schematic diagram of injection of a thermal hole between the strips into the charge storage structure. Fig. 10B is a schematic diagram of the injection of a thermoelectric hole between the strips into the charge storage structure in a non-volatile memory cell having a raised source region and a drain region. . Figure 11A is a schematic diagram of a channel thermowell injected into a charge storage structure in a non-volatile memory cell having a recessed channel. Figure 11B is a non-swing in the source region and the drain region with lift 29

Sanda number: TW3137PA In the memory unit, the channel is hot. ^ / / into the charge storage structure shown in Figure 12A is in the _ yuan, the substrate thermoelectric hole injected into the electricity: k non-volatile memory single Figure 12B is a schematic diagram with === 冓. The origin of the memory unit Yin, the base ♦ / the original pole and the bungee area are not intended. The /5 diagram of the primary storage to the charge storage structure is a schematic diagram of the non-volatile memory unidirectional read operation in the recessed element for reading the memory. One of the data on the right side of the ''sigma's UB map is the reverse reading of the data in the source and the bungee area of the source of the sensible memory unit. It is stored in the right side of the charge storage structure. The i4A figure is a schematic diagram of the non-volatile memory single-fetch operation for storing the one-way in the right side. The reverse-reading memory unit 〇1 of the data on the left side of the structure has the reverse reading operation of the non-swept data of the source region and the non-polar region of the lift = stored on the left side of the charge storage structure After that, the schematic diagram. Figure 15 is the data on the right side of the charge storage structure for reading and storing: a non-volatile memory single-single read operation with a recessed channel; Figure 15B is a memory cell The source and lift regions of the lift are used to read and store on the right side of the charge storage structure.

** Three-way number: TW3137PA < One of the data is a schematic diagram of the inter-band read operation. Figure 16A is a schematic illustration of an inter-band read operation for storing data located to the left of the charge storage structure in a non-volatile memory cell having a recessed channel. Fig. 16B is a schematic diagram of an inter-band reading operation for storing data located on the left side of the charge storage structure in a non-swing memory cell having a lifted source region and a drain region. The second diagram is a manufacturing flow diagram of a non-volatile memory cell φ array having a recessed channel showing various possible combinations of the process steps of Figures 19-23. Figure 18A is a manufacturing flow diagram of a NOR non-volatile memory cell array having one of the source and drain regions of the lift, showing various possible combinations of the process steps of Figures 24-27. Figure 18B is a manufacturing flow diagram of one of the source and drain regions of the lift: a NAND non-volatile memory cell array showing various possible combinations of process steps of Figures 28-30. • Figures 19A through 19C are process steps for forming a trench in a non-volatile memory cell having a recessed channel prior to the 22nd or 23rd. 20A to 20E are process steps for reducing the length of a gate before forming a trench in the non-volatile memory cell before the 22nd or 23rd. 21A to 21E are diagrams for expanding a gate length before forming a trench in a non-volatile memory cell before the 22nd or 23rd graph 31 1336941

Process steps with Sanda number: TW3137PA ^. 22A to 22K are the process steps after the 19th, 20th or 21th step to form an N〇R non-volatile memory cell array, each NOR non-volatile memory cell is located in a trench _ So that each non-volatile memory cell has a recessed channel. '23A to 23E are the process steps after the 帛19, 20 or 21, to form a NAND non-volatile memory cell array. Each NAND non-volatile memory cell is located in a trench. So that each non-volatile memory unit has a recessed channel. Figures 24A through 24D are process steps beginning before g 25 or 26 mesh to form a source and a non-polar region of a non-volatile memory cell in a NOR array. 25A to 25B are process steps after the 24th and before the 27th, which form the (four) crystal phase in the source of the non-volatile memory cell in the __ n〇r array District and Wuji District.帛26A to 26C are the process steps after the 24th and before the 27th, which use polycrystalline stone to form a non-volatile memory fresh element in an n〇r array. Source _ and bungee area. Figures 27A through 27D are the steps of the process of forming the front-end beam of the 25th or 26th figure to form - NOR non-volatile memory cell arrays, each NOR non-volatile memory cell having a source region for lifting No pole area. The 28A to 28D diagram is a process stepping before the 29th or 3rd drawing to form a NAND non-volatile memory cell array, each NAND non-volatile memory cell having a source region for lifting Plate no pole 32 1336941

1 Sanda number: TW3137PA < District. 29A to 29B are process steps after the 28th drawing, which use epitaxial germanium to form a NAND non-volatile memory cell array, each NAND non-volatile memory cell having a source of lift District. With the Wuji District. 30A to 30C are process steps after the 28th drawing, which use polysilicon to form a NAND non-volatile memory cell array, and each NAND non-volatile memory cell has a source region for lifting. With > and polar regions. Figure 31 is a block diagram of a non-volatile memory volume circuit having an exemplary interface of the varying channel region as disclosed herein. Figure 32 is a schematic illustration of a non-volatile memory cell having a recessed channel between the source region and the drain region, whereby the lower dielectric structure has a three-layered germanium structure. Figure 33 is a schematic diagram of a non-volatile memory cell having a source region and a drain region lifted off the semiconductor substrate, whereby the lower dielectric structure has three thin 0 Ν 0 structures. 33 1336941 ...

11 Sanda number: TW3137PA ^ [main component symbol; description] 102, 302, 402, 502, 602, 702, 802, 902, 1002, 1102, 1202, 1302, 1402, 1502, 1602, 2264, 2722: gate / Gate region. 104: Dielectric structure. 106: Charge storage structure 108: Charge storage structure / dielectric structure 110, 210, 304, 404, 804, 904, 1204, 2280, 2380, 2560, 2660, 2960, 3060: source/source regions 112, 212, 306, 406, 806, 906, 1206, 2282, 2382, 2562, 2662, 2962, 3062: drain region/drain 114, 214: channel region/channel 116: Source and drain regions 118: interface 120: junction depth 122: body/body regions • 208: dielectric structure 218: interface 220: junction depths 308, 408, 808, 908, 1208: body regions 504, 1104: p+ type source regions 506, 1106: p+ type drain regions 508, 708, 1108: N type body regions 604, 704, 1004, 1304, 1404, 1504, 1604: n+ type source 34 1336941

H Sanda number: TW3137PA < Polar regions 606, 706, 1006, 1306, 1406, 1506, 1606: η+ type drain regions 608, 1008, 1308, 1408, 1508, 1608: Ρ type body region. 710, 1210 : Well area 1900, 2400, 2800: substrate 1910, 1912, 2112, 2290, 2772: oxide 1922: photoresist φ 1930, 1932, 2232 · · trench 2040, 2042, 2440, 2840: spacer 2250: dielectric Materials and Charge Storing Structures 2260, 2262: Gate Materials 2270, 2272: Dielectric Material 2410: Dielectric Material and Charge Storing Structure 2412: ΟΝΟ 2420, 2650, 2652, 2820, 3050, 3052: Polycrystalline 24 2430: SiN/Oxidation 2442, 2842. Gap sidewalls 2550, 2950: epitaxial germanium 2810: charge storage structure 2812: ΟΝΟ 3100: memory array 3101: column decoder 3102: word line 35 1336941

Sanda number: TW3137PA 3103: row decoder 3104: bit line 3105: bus bar 3106: sense amplifier and data input structure 3107: data bus 3108: bias configuration supply voltage 3109: bias configuration state machine 3111: data Input line 3115: data output line 3150: integrated circuit 3208: ΟΝΟ structure 36

Claims (1)

1336941, Sanda number: TW3137PA ^ X. Patent application scope: 1. A non-volatile memory cell integrated circuit comprising: a non-volatile memory array comprising a plurality of rows, each row comprising arranged in a series a plurality of non-volatile memory cells such that a subset of the non-volatile memory cells in the string is electrically coupled to other non-volatile memory cells in the string of t columns a bit line, each of the non-volatile memory cells comprising: a charge storage structure for storing charge to control a logic state stored by the non-volatile memory cell integrated circuit; a source and a drain a region separated by a channel region; one or more dielectric structures at least partially between the charge storage structure and the channel region, and at least partially between the charge storage structure and a gate voltage source, wherein Wherein, for each of the non-volatile memory cells of each of the non-volatile 1S body cell arrays, an interface separates one of the one or more dielectric structures from the pass Region, and the ends at one end of the first interface • the source region of the intermediate portion and the second end of the one end of the interface to the intermediate portion of the drain region division. 2. The circuit of claim 1, wherein the first end of the interface ends in the source region because the channel region is recessed into a substrate of the non-volatile memory cell integrated circuit. a middle portion, and the second end of the interface ends in a middle portion of the drain region. 3. The circuit of claim 1, further comprising: a gate length adjusting dielectric material layer at least partially located on a substrate and 37 1336941 ^ Sanda number: TW3137PA « one or more dielectric structures . 4. The circuit of claim 1, wherein the charge storage structure stores one bit. 5. The circuit of claim 1, wherein the charge storage structure stores multiple bits. 6. The circuit of claim 1, wherein the charge storage structure is a charge trapping structure. 7. The circuit of claim 1, wherein the charge φ storage structure is a nano crystal structure. 8. The circuit of claim 1, wherein the dielectric structure at least partially between the charge storage structure and the channel region comprises: a lower yttrium oxide layer; an intermediate tantalum nitride layer located at the On the lower hafnium oxide layer; and an upper hafnium oxide layer on the intermediate tantalum nitride layer. 9. The circuit of claim 8 wherein the lower oxygen philipid layer has a thickness of less than about 20 angstroms. 10. The circuit of claim 8 wherein the intermediate tantalum nitride layer has a thickness of less than about 20 angstroms. 11. The circuit of claim 8 wherein the upper ruthenium oxide layer has a thickness of less than about 20 angstroms. 12. The circuit of claim 8 wherein the lower ruthenium oxide layer has a thickness of between about 5 and 20 angstroms. 38. The circuit of claim 8, wherein the intermediate tantalum nitride layer has a thickness of about 10 to 20 angstroms. 14. The circuit of claim 8 wherein the upper ruthenium oxide layer has a thickness of between about 15 and 20 angstroms. 15. The circuit of claim 8 wherein the lower ruthenium oxide layer has a thickness of less than about 15 angstroms. 16. A method of fabricating a non-volatile memory cell array integrated circuit, comprising the steps of: φ forming a plurality of rows of non-volatile memory cells in the non-volatile memory array, each row comprising arranged in a series a plurality of non-volatile memory cells, the step comprising the substeps of: forming a charge storage structure and one or more dielectric structures for each of the non-volatile memory cells of the non-volatile memory array, wherein the charge storage structure Storing a charge to control a logic state stored by the non-volatile memory cell array integrated circuit, and the one or more dielectric structures are: 1) at least partially located between the charge storage structure and a channel region; And 2) at least partially between the charge storage structure and a source of a gate voltage; and forming a conductive layer to provide the gate voltage; and forming a plurality of bit lines to provide a drain voltage and a source voltage Non-volatile memory cells of each row in the non-volatile memory array such that the non-volatile memory of each row One subset of the cells is electrically connected to one of the bit lines via other non-volatile memory cells in the string; 39 1336941 Jadada number: TW3137PA 'where the non-volatile memory of the array a body unit, an interface separating a portion of the one or more dielectric structures from the channel region, a first end of the interface ending in a middle portion of a first bit line, and a second end of the interface ends The middle part of a second bit line. * 17. The method of claim 16, further comprising the steps of: forming a trench in a substrate, wherein the step of forming the charge storage structure and the one or more dielectric structures Occurs in the trench. 18. The method of claim 16, further comprising the step of: adjusting a length of a gate by forming a filler, the filler being at least partially located in the one or more dielectric structures and a substrate between. 19. The method of claim 16, further comprising the steps of: forming a layer of dielectric material and removing the charge storage structure and the one or more dielectric structures prior to the forming step A portion of the dielectric material layer is used to reduce the length of a gate. 20. The method of claim 16, wherein the charge storage structure stores one bit. 21. The method of claim 16, wherein the charge storage structure stores multiple bits. 22. The method of claim 16, wherein the charge storage structure is a charge trapping structure. The method of claim 16, wherein the charge storage structure is a nano crystal structure. 24. The method of claim 16, wherein the forming step of the dielectric structure* at least partially between the charge storage structure and the channel region comprises: forming a ruthenium oxide layer; forming a An intermediate tantalum nitride layer is on the lower tantalum oxide layer; and an upper tantalum oxide layer is formed on the intermediate tantalum nitride layer. The method of claim 24, wherein the lower ruthenium oxide layer has a thickness of less than about 20 angstroms. 26. The method of claim 24, wherein the intermediate tantalum nitride layer has a thickness of less than about 20 angstroms. 27. The method of claim 24, wherein the upper ruthenium oxide layer has a thickness of less than about 20 angstroms. 28. The method of claim 24, wherein the lower ruthenium oxide layer has a thickness of between about 5 and 20 angstroms. The method of claim 24, wherein the intermediate tantalum nitride layer has a thickness of about 10 to 20 angstroms. The method of claim 24, wherein the upper ruthenium oxide layer has a thickness of about 15 to 20 angstroms. The method of claim 24, wherein the lower ruthenium oxide layer has a thickness of less than about 15 angstroms. 32. A method of manufacturing a non-volatile memory cell array integrated circuit, comprising the following steps: 41 1336941 *> Sanda number: TW3137PA ^ Each of the non-volatile memory in the non-volatile memory cell array The cell forms a charge storage structure and one or more dielectric structures, wherein the charge storage structure stores charge to control a logic state stored by the non-volatile memory cell array integrated circuit, and the one or more dielectrics The structure 1) is at least partially located between the charge storage structure and a channel region: and 2) at least partially between the charge storage structure and a gate voltage source; forming a conductive layer for providing the gate voltage a first portion; φ forming a plurality of bit lines after forming the first portion of the conductive layer providing the gate voltage, the plurality of bit lines for providing a drain voltage and a source voltage to the non-volatile Each of the non-volatile memory cells in the array of memory cells, each of the non-volatile memory cells in the array of non-volatile memory cells The channel region extends between a first bit line of one of the bit lines providing the drain voltage and a second bit line of the bit lines providing the source voltage; After the bit line, a second portion of the conductive layer is formed to provide the gate voltage, and the first portion is physically connected to the second portion, wherein each of the non-volatile memory cell arrays is non-volatile a volatile memory cell, an interface separating a portion of the one or more dielectric structures from the channel region, a first end of the interface ending in a middle portion of the first bit line, and one of the interfaces The two ends end in the middle portion of the second bit line. 42. The method of claim 32, further comprising the steps of: forming a trench in a substrate, wherein the charge storage structure and the one or more dielectric structures This forming step occurs in the trench. 34. The method of claim 32, further comprising the steps of: adjusting a length of a gate by forming a filler, the filler being at least partially located in the one or more dielectric structures and a substrate between. Φ 35. The method of claim 32, further comprising the steps of: forming a layer of dielectric material and moving before the step of forming the charge storage structure and the one or more dielectric structures In addition to a portion of the dielectric material layer to reduce the length of a gate. 36. The method of claim 32, further comprising: forming a layer of dielectric material separating the bit lines from the second portion of the conductive layer. 37. The method of claim 32, further comprising: the step of forming the bit lines comprises adding dopants. 38. The method of claim 32, wherein the charge storage structure stores one bit. 39. The method of claim 32, wherein the charge storage structure stores a plurality of bits. 40. The method of claim 32, wherein the charge storage structure is a charge trapping structure. 43. The method of claim 32, wherein the charge storage structure is a nano crystal structure. 42. The method of claim 32, wherein the dielectric structure is at least partially located between the charge trapping structure and the channel region. The forming step comprises: forming a lower cerium oxide layer; forming an intermediate nitrogen A ruthenium layer is formed on the lower ruthenium oxide layer; and an upper ruthenium oxide layer is formed on the intermediate tantalum nitride layer. The method of claim 42, wherein the lower ruthenium oxide layer has a thickness of less than about 20 angstroms. 44. The method of claim 42, wherein the intermediate tantalum nitride layer has a thickness of less than about 20 angstroms. 45. The method of claim 42, wherein the upper ruthenium oxide layer has a thickness of less than about 20 angstroms. The method of claim 42, wherein the lower ruthenium oxide layer has a thickness of about 5 to 20 angstroms. 47. The method of claim 42, wherein the intermediate tantalum nitride layer has a thickness of about 10 to 20 angstroms. 48. The method of claim 42, wherein the upper bismuth telluride layer has a thickness of about 15 to 20 angstroms. 49. The method of claim 42, wherein the lower ruthenium oxide layer has a thickness of less than about 15 angstroms. 44