JP4370749B2 - Nonvolatile semiconductor memory device and operation method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a non-volatile semiconductor memory device including a control gate electrode (second gate electrode) for controlling source side injection in addition to a memory gate electrode (first gate electrode), and an operation (charge injection and reading) method thereof. About.
[0002]
[Prior art]
In the flash EEPROM, the charge storage means is an FG (Floating Gate) type in which a single conductive layer is formed, and the MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) type, MNOS (type in which the charge storage means is planarly discretized). Metal-Nitride-Oxide-Nitride-Oxide) type is known.
[0003]
For example, in the FG type memory element, a conductive film (floating gate FG) and a gate which are electrically floating by being surrounded by an insulating film on a semiconductor substrate surface region (channel forming region) where a transistor channel is formed. Electrodes are stacked, and source / drain impurity regions having a conductivity type opposite to that of the channel forming region are formed in the substrate surface region on both sides of the stacked pattern.
On the other hand, in the MONOS memory element, the dielectric film structure between the channel formation region and the gate electrode has a so-called ONO (Oxide-Nitride-Oxide) structure. In the ONO film, bulk traps in the nitride film or interface trap charges near the interface with the oxide film of the nitride film are accumulated.
[0004]
Writing is performed by injecting charges from the substrate side into the dielectric film (ONO film) or the floating gate FG having the charge holding capability. In erasing, the retained charge is extracted to the substrate side, or a reverse polarity charge that cancels the retained charge is injected into the dielectric film.
As a charge injection method, in addition to utilizing a charge tunneling phenomenon in a dielectric film, a so-called CHE (Channel-Hot-Electron) injection or the like, an oxide film at the lowest layer of the ONO film or an oxide film immediately below the floating gate FG is used. There is a method of energetically exciting the charge to such an extent that it can overcome the insulating barrier.
[0005]
As a kind of CHE injection method, a source side injection method is known.
In order to realize the source side injection method, it is necessary to separately provide an electrode for controlling the drain side channel (memory gate electrode) and an electrode for controlling the source side channel (control gate electrode). This is because the drain-side channel is in a strong inversion state and the source-side channel is in a weak inversion state during charge injection. At this time, a high electric field is generated near the boundary between the two, and the charge supplied from the source side is excited by this high electric field and injected from the source side into the charge storage means under the memory gate electrode. The injection efficiency is improved by an order of magnitude compared with the normal CHE injection.
In this charge injection, a pulse is usually raised in the order of the control gate electrode and the memory gate electrode with a voltage applied between the source and drain. Therefore, the write time is defined by the generation time of the pulse applied to the memory gate electrode.
[0006]
In reading from the source-side injection memory element, first, a voltage between the source and the drain is applied. Next, a voltage necessary for channel formation is applied to the control gate electrode, and then a voltage capable of controlling ON / OFF of the channel according to the amount of charge stored in the charge storage means is applied to the memory gate electrode. As a result, the amount of channel current changes according to the amount of stored charge in the charge storage means, and this is detected by fluctuations in the drain potential and the like.
[0007]
[Problems to be solved by the invention]
In the conventional source side type memory device, when writing is performed by injecting charges into charge storage means such as a floating gate FG, as described above, first, after opening the channel directly under the control gate electrode, the memory gate electrode A write pulse having a predetermined time width is applied to the. This memory gate electrode is often shared, for example, between memory cells in the row direction in the memory cell array to form a word line. In this case, the load capacity is considerably high. In addition, since the write pulse voltage applied to the control gate electrode is higher than the pulse voltage applied to the control gate electrode, a drive circuit having a considerably high capacity is required to charge and discharge the memory gate electrode (word line) in a short time.
Therefore, there is a disadvantage that the power consumption of the drive circuit for the conventional source side type memory element is high. In addition, since the wiring capacitance from the signal source to the memory element differs depending on the location of the word line, there is a problem of delay of the write pulse between elements, and inconvenience such as variation in write time occurs.
[0008]
By the way, the present inventor makes charge injection efficiency in the source side injection type memory device by making the channel formation region below the memory gate electrode an impurity region having a conductivity type opposite to that of the channel formation region below the control gate electrode. Proposed an element structure capable of further enhancing the above (Japanese Patent Application No. 2001-351417). Here, the channel formation region below the control gate electrode where the channel is formed by the minority carrier inversion layer is referred to as the inversion layer formation region, whereas the channel formation region below the memory gate electrode forms a channel due to the accumulation of majority carriers. Therefore, this region is called a storage layer formation region. In addition, such a storage layer formation region is formed on both the source and drain sides so that 2-bit information can be stored per cell.
[0009]
However, when reading is performed by the above-described conventional pulse application procedure in the source side injection type memory device capable of storing 2 bits with such a configuration, the storage layer formation region is present, so that even a region below the accumulated charge on the drain side accumulates. Since the layer channel is formed, the conductivity of the channel is easily affected by the amount of charge accumulated on the drain side. Therefore, the read drain potential change is greatly influenced by the magnitude of the accumulated charge amount on the drain side in addition to the magnitude of the accumulated charge amount on the source side to be originally read, and “1” and “0” of the binary data. There has been a problem that the determination margin of “is narrowed.
[0010]
Even if the element structure proposed by the present inventor is not described, that is, the writing speed cannot be improved, the channel formation region below the memory gate electrode is made to have the same conductivity as the channel formation region below the control gate electrode. Even when it is formed by a type impurity region, the total channel conductivity under the memory gate electrode and under the control gate electrode shows the accumulated charge amount and drain on the source side when reading is performed by the conventional pulse application procedure. There is a problem in that 2-bit information cannot be read independently because of the influence of both the stored charge amount on the side.
This is because, in charge injection from the source side, the charge storage region is separated from the drain side and limited to the source side charge storage film portion below the memory gate electrode due to the principle of the device structure and charge injection operation. . That is, the lower part of this portion is an inner channel region that is out of the pinch-off region, so that the conductivity of the channel is easily affected by the accumulated charge on the drain side. The discrimination margin between “1” and “0” of the value data is narrowed.
[0011]
A first object of the present invention is to suppress power consumption and write pulse delay during writing in a so-called source-side injection type memory device.
A second object of the present invention is to reduce the influence of a bit different from a read bit as much as possible in, for example, a source side type memory element capable of storing 2 bits.
[0012]
[Means for Solving the Problems]
An operation method (charge injection method) of a nonvolatile semiconductor memory device according to a first aspect of the present invention is for achieving the first object described above, and includes a channel formation region made of a first conductivity type semiconductor, , Each made of a second conductivity type semiconductor and arranged with a channel formation region in between First source / drain region and second Interposing the source / drain region and the laminated film with charge storage capability On the first source / drain region side The first gate electrode formed on the channel formation region and a single-layer dielectric film having no charge storage capability are interposed. Between the first gate electrode and the second source / drain region Formed on the channel formation region the above Second gate electrode insulated from first gate electrode And A non-volatile semiconductor memory device having an operation method comprising:
When writing or erasing
Second source / drain region Based on The first source / drain region Applying a predetermined drain voltage to
the above Charges energetically excited in the channel formation region the above In the laminated film under the first gate electrode Second source / drain region side As injected from the above A first gate voltage is applied to the first gate electrode, the above Apply a second gate voltage to the second gate electrode Step and Have
In the gate voltage application step, the above Application of the first gate voltage is started, and during the application of the first gate voltage the above Application of the second gate voltage is started.
[0013]
A nonvolatile semiconductor memory device according to a second aspect of the present invention is for achieving the first object described above, and includes a memory cell,
A drive circuit for applying a bias to the memory cell; , Have
The memory cell includes a channel forming region made of a first conductivity type semiconductor, two source / drain regions each made of a second conductivity type semiconductor and sandwiching the channel formation region, and a stacked film having charge storage capability And a first gate electrode formed on the channel formation region with a single layer dielectric film having no charge storage capability interposed therebetween and insulated from the first gate electrode. 2 gate electrodes And Have
When the driving circuit applies predetermined voltages to the first gate electrode and the second gate electrode at the time of writing, erasing or reading, the above In the middle of voltage application to the first gate electrode, voltage application to the first gate electrode is started. the above Means for controlling the timing of voltage application for starting voltage application to the second gate electrode is included.
[0014]
In the nonvolatile semiconductor memory device and the operating method according to the first and second aspects, the memory gate electrode is first written at the time of writing or reading. To (first gate electrode) Rise the applied pulse, then control gate electrode (Second gate electrode) For example, both pulses are terminated at the same time. In this control, the generation time of the pulse applied to the control gate electrode having a relatively small voltage value is the writing time. Therefore, the charge / discharge time of the large total gate load capacity (or word line capacity) in the entire memory cell array during writing is shorter than before, and the phase difference of the write pulse in the memory cell array is smaller than before. Also, the point that a pulse having a relatively large voltage value is applied to the memory gate electrode is the same as in the past, but the pulse application of the memory gate electrode does not directly define the write time, and this voltage is applied to the memory gate at the time of writing. It may be applied. Therefore, for example, when one word line sector is written a plurality of times, the memory gate electrode may be kept raised. In this case, the number of times of charging / discharging the word line is reduced as compared with the prior art.
Such an action is the same even when a charge having the opposite polarity to the accumulated charge is injected from the source side during erasing.
[0015]
A non-volatile semiconductor memory device operating method (reading method) according to a third aspect of the present invention is for achieving the above-described second object, and is composed of a second-conductivity-type semiconductor and has a majority carrier accumulation layer. A channel formation region comprising: a storage layer formation region in which a channel is formed by the step; and an inversion layer formation region formed of a first conductivity type semiconductor adjacent to one side of the storage layer formation region and in which a channel is formed by the inversion layer; A first source / drain region made of a second conductivity type semiconductor adjacent to the channel formation region on the storage layer formation region side, and a first source / drain region adjacent to the channel formation region on the side opposite to the storage layer formation region. A second source / drain region made of a two-conductivity type semiconductor; a first gate electrode formed on the storage layer formation region with a stacked film having charge storage capability interposed; A non-volatile semiconductor memory device having a second gate electrode formed on the inversion layer formation region with a single-layer dielectric film having no capability interposed therebetween. Applying a predetermined read voltage to the first source / drain region with reference to the two source / drain regions; Laminated film Applying a first gate voltage capable of controlling the formation of a channel according to the amount of charge in the first gate electrode to the first gate electrode, and applying a second gate voltage necessary for the channel formation to the second gate electrode. In the application step of the gate voltage, the application of the first gate voltage is started, and the application of the second gate voltage is started during the application of the first gate voltage.
[0016]
The operation method (reading method) of the nonvolatile semiconductor memory device according to the fourth aspect of the present invention is for achieving the second object described above, and the channel is formed by the inversion layer made of the first conductivity type semiconductor. A channel forming region to be formed; Each consisting of a second conductivity type semiconductor Channel formation region A first source / drain region and a second A source / drain region and a laminated film with charge storage capability Formed on the channel forming region on the first source / drain region side The first gate electrode and a single-layer dielectric film having no charge storage capability are interposed. Channel forming region on the second source / drain region side Second gate electrode formed on And A method for operating a nonvolatile semiconductor memory device, comprising: The first source / drain region is based on the second source / drain region. Applying a predetermined read voltage to Above lamination Channel formation can be controlled according to the amount of charge in the film First gate voltage Is applied to the first gate electrode and is necessary for channel formation. Second gate voltage A second gate electrode, , And applying the gate voltage Then, above Application of the first gate voltage is started, and during the application of the first gate voltage the above Application of the second gate voltage is started.
[0017]
In these read methods, for example, when charge (for example, electrons) is sufficiently accumulated on the read target bit side and the stored data is written to “0”, the amount of accumulated electrons on the other bit side (“1”) “,“ 0 ”), the read current hardly flows. In the case of 2-bit storage, if the left and right data are expressed as “11”, “01”, “10”, “00”, for example, when the read target is the right bit, the read current is “10”, “00”. Hardly flows. On the other hand, a large current flows in “11” where there is no electron in both bits, but in “01” that is not a read target, the current value is slightly smaller than in “11”, but there is a problem when setting an appropriate read voltage. In addition, by using this reading method, 2-bit information can be read with almost no influence of non-reading bits.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
The present embodiment relates to a memory cell structure according to the present invention and a writing or erasing method thereof.
1 and 2 are equivalent circuit diagrams of a nonvolatile memory cell according to an embodiment of the present invention.
[0019]
These memory cells have a three-transistor configuration in which a memory transistor, a MOS transistor, and a memory transistor are connected in series between two bit lines BLa and BLb.
In the memory cell M shown in FIG. 1, the gates of the two memory transistors are controlled by the word line WL, and the gate of the central MOS transistor is controlled by the control line CL parallel to the bit lines BLa and BLb.
In the memory cell M shown in FIG. 2, the gate of the central MOS transistor is controlled by the word line WL, the gate of the right memory transistor is controlled by the control line CLa, and the gate of the left memory transistor is controlled by the control line CLb. Be controlled. The control lines CLa and CLb are arranged in parallel between the two bit lines BLa and BLb.
[0020]
Although not particularly illustrated, a large number of memory cells M having any one of these configurations are arranged in a matrix to form a memory cell array. In this memory cell array, word lines WL are arranged in the row direction and are shared by hundreds to thousands of memory cells constituting the memory cell row, and control lines CL or control lines CLa and CLb are arranged in the column direction. Are shared by hundreds to thousands of memory cells. Therefore, the load capacity of the word line and the control line is considerably large.
In addition, a read circuit including a sense amplifier, a write circuit that drives a common line in the column direction, a word line drive circuit that drives a word line, and the like are arranged around the memory cell, although not particularly illustrated. These are included in the “drive circuit” in the present invention. The drive circuit is provided with control means as required. In the drive circuit, the applied voltage and timing of driving each common line (word line, control line, bit line, etc.) at the time of writing, erasing or reading are controlled by a clock synchronization or control circuit.
[0021]
3A is a schematic cross-sectional view in the row direction along the word line of the memory cell shown in FIG. 1, and FIG. 3B is a plan view thereof.
In the memory cell shown in FIG. 3A, reference numeral SUB denotes a base (for example, a P-type semiconductor substrate, a P-well, a P-type SOI layer, etc., hereinafter referred to as a substrate) formed of a semiconductor material such as silicon. Indicates. Two source / drain regions S / D formed by introducing N-type impurities at a high concentration are formed in a surface region in the substrate SUB so as to be separated from each other. The source / drain regions S / D are long and parallel to each other in the column direction as shown in FIG. The substrate surface region between the two source / drain regions S / D becomes a channel formation region in which the channel of the memory transistor is formed during operation. The channel forming region is composed of an inner channel region CH1 formed substantially at the center thereof, and two outer channel regions CH2a and CH2b between the inner channel region CH1 and the source / drain regions S / D.
The inner channel region CH1 is a surface region of the substrate SUB and has a P-type conductivity type. The inner channel region CH1 is hereinafter referred to as an inversion layer forming region because a channel is formed by the inversion layer.
On the other hand, the outer channel regions CH2a and CH2b are composed of N-type impurity regions ACLa and ACLb having a lower concentration than the source / drain regions S / D. In these N-type impurity regions ACLa and ACLb, since channels are formed by accumulating majority carriers on the surfaces thereof, they are hereinafter referred to as storage layer forming regions. The storage layer formation regions ACLa and ACLb are arranged in parallel with each other along the source / drain S / D.
[0022]
A single-layer gate dielectric film GD0 made of silicon dioxide having a thickness of about 1 nm to 10 nm, for example, is formed on the inversion layer forming region CH1. The gate dielectric film GD0 is a single layer and has relatively few carrier traps in the film, and does not have a charge holding capability.
On the gate dielectric film GD0, a control gate CL made of, for example, polycrystalline silicon doped with impurities or amorphous silicon is formed. The control gate CL corresponds to the “second gate electrode” in the present invention. As shown in FIG. 3B, the control gate CL is wired long in the column direction in parallel with the source / drain region S / D within the space between the source / drain regions S / D. Although there is no limitation on the width (gate length) of the control gate CL, for example, it is preferable that the control gate CL be ultrafine, for example, 50 nm or less, because the carriers in the channel travel semi-ballistically. In other words, although depending on the electric field conditions, if the gate length is made extremely fine in this way, when the carriers supplied from the source move in the channel, they receive fine small-angle scattering due to impurities but bend the trajectory greatly. The carrier travels ballistically without receiving large-angle scattering.
[0023]
Charge accumulation by stacking a plurality of dielectric films covering the surface of the stacked pattern of the gate dielectric film GD0 and the control gate CL, the surfaces of the storage layer formation regions ACLa and ACLb, and the surfaces of the source / drain regions S / D A gate dielectric film GD having the capability is formed.
The gate dielectric film GD includes, in order from the lower layer, a bottom dielectric film BTM, a dielectric film (main charge storage film) CHS mainly responsible for charge accumulation, and a top dielectric film TOP.
[0024]
As the bottom dielectric film BTM, for example, a silicon dioxide film formed by a thermal oxidation method, a film obtained by nitriding silicon dioxide, or the like is used. The film thickness of the bottom dielectric film BTM is, for example, about 2.5 nm to 6.0 nm.
The main charge storage film CHS is made of a silicon nitride film of about 3.0 nm to 20 nm, for example. The main charge storage film CHS is produced, for example, by low pressure CVD (LP-CVD), and the film contains many charge traps.
The top dielectric film TOP needs to be formed with a high density of deep charge traps near the interface with the main charge storage film CHS. For this reason, for example, the main charge storage film after film formation is formed by thermal oxidation. . The top dielectric film TOP may be an HTO (High-Temperature-chemical-vapor-deposited-Oxide) film. When the top dielectric film TOP is formed by CVD, this trap is formed by heat treatment. The film thickness of the top dielectric film TOP is at least 3.0 nm, preferably 3 in order to effectively prevent hole injection from the gate electrode (word line WL) and prevent a decrease in the number of times data can be rewritten. .5 nm or more is required.
[0025]
On this gate dielectric film GD, a word line WL that intersects with the control gate CL and also serves as the gate electrode of the memory transistor is formed. The word line WL corresponds to the “first gate electrode” of the present invention, and is made of, for example, polycrystalline silicon or amorphous silicon doped with impurities.
[0026]
4A is a schematic cross-sectional view in the row direction along the word line of the memory cell shown in FIG. 2, and FIG. 4B is a plan view thereof.
In this memory cell, similarly to FIGS. 3A and 3B, the source / drain S / D and the storage layer formation regions ACLa and ACLb are formed in the surface region of the substrate SUB. The surface region of the substrate SUB between the accumulation layer formation regions ACLa and ACLb becomes the inversion layer formation region CH1.
[0027]
A word gate electrode WG is formed on the inversion layer forming region CH1 with a single-layer gate dielectric film GD0 interposed therebetween. The word gate electrode WG corresponds to the “second gate electrode” in the present invention, is divided by the same width as the word line WL, and is formed in an isolated pattern for each memory cell.
[0028]
A gate dielectric film GD having a three-layer structure having charge storage capability is formed on the side surface of the word gate electrode WG, the storage layer formation regions ACLa and ACLb, and the source / drain regions S / D. The thicknesses, materials, and formation methods of the layers BTM, CHS, and TOP constituting the gate dielectric film GD are the same as those in FIGS. 3A and 3B.
[0029]
For example, sidewall-shaped control lines CLa and CLb are formed in regions located in contact with the gate dielectric film GD on the side surface side of the word gate electrode WL and above the storage layer formation regions ACLa and ACLb. The control lines CLa and CLb correspond to the “first gate electrode” in the present invention, and are made of polycrystalline silicon or amorphous silicon to which impurities are added. The control lines CLa and CLb are embedded in the interlayer insulating layer INT.
A word line WL electrically connected to the upper surface of the word gate electrode WG is formed on the interlayer insulating layer INT.
[0030]
In the two memory cells shown in FIGS. 1 to 4B, the central MOS transistor operates in an auxiliary manner to improve the characteristics when the memory transistor operates (write, read, erase). In addition, the region where the charge is injected is limited by the presence of the MOS transistor. That is, a region for injecting charges (hereinafter referred to as a memory portion) is limited to the gate dielectric film GD portion on the storage layer formation regions ACLa and ACLb, and the single-layer gate dielectric film GD0 between them has a charge storage capability. Can not contribute to data storage. Furthermore, the presence of the MOS transistor prevents charges injected on both sides from interfering with each other, so that 2-bit storage can be performed reliably.
[0031]
Next, the operation of the memory cell will be described.
FIG. 5A is an explanatory diagram of an operation when electrons are injected into the memory portion 1 using source-side injection.
[0032]
At the time of writing, a reference voltage Vs is applied to the source / drain region S / D on the left side of the drawing as a source, and a drain voltage Vd, for example, 5.0 V is applied to the source / drain region S / D on the right side of the drawing as a drain. A predetermined positive voltage Vmg, for example 7.0 V, is applied to the memory gates MGa and MGb, and a predetermined positive voltage Vcg, for example, 1.0 V is applied to the control gate CG. Note that the control line CL in FIG. 1 and the word line WL in FIG. 2 correspond to the control gate CG. Further, the word line WL in FIG. 1 and the control line CLa or CLb in FIG. 2 correspond to the memory gates MGa and MGb.
[0033]
This embodiment is characterized by the procedure of the voltage applied to both gates.
FIG. 6A and FIG. 6B illustrate waveform diagrams of pulses for applying this voltage. In the writing of the present embodiment, as shown in FIG. 6A, first, a pulse of a relatively high voltage Vmg (= 7 V) is raised on the memory gate MGa (and MGb), and as shown in FIG. In the middle of the application of the pulse voltage Vmg, another pulse to be applied to the control gate CG, that is, a pulse having a relatively low voltage Vcg (= 1V) is raised. Then, both pulses are terminated almost simultaneously. Alternatively, the former pulse having a relatively large voltage value is terminated slightly after the end of the latter pulse having a relatively small voltage value. These controls are performed by bias application timing control by the drive circuit described above.
[0034]
In this pulse application control, the generation time of the applied pulse to the control gate electrode CG having a relatively small voltage value is the writing time (program time T _PGM ) Therefore, the charge / discharge time of the large total gate load capacity (or word line capacity) in the entire memory cell array during writing is shorter than before, and the phase difference of the write pulse in the memory cell array is smaller than before. In addition, the point that a pulse having a relatively large voltage value is applied to the memory gate electrode is the same as in the prior art, but the pulse application of this memory gate electrode does not directly define the write time, and this voltage is applied to the memory gate electrode during writing It may be applied to MGa (and MGb). Therefore, for example, when one word line sector is written a plurality of times, the potential of the memory gate electrode MGa (and MGb) may be kept raised. In this case, the number of times of charging / discharging the word line WL is reduced as compared with the conventional case.
[0035]
This program time T _PGM Inside, an inversion layer is formed in the inversion layer formation region CH1, and accumulation layers are formed on the surfaces of the accumulation layer formation regions ACLa and ACLb on both sides thereof. Electrons supplied from the storage layer on the source side are accelerated in the inversion layer, a part of which is on the drain side, and the energy barrier ΦSiO of the silicon dioxide film constituting the bottom dielectric film BTM of the gate dielectric film GD ₂ High-energy electrons (hot electrons) exceeding A part of the hot electrons is injected into the storage unit 1 with a certain probability.
[0036]
FIG. 5B shows the relationship between the horizontal position Px in the channel direction at this time, the channel potential V, and the channel electric field Ex in the horizontal direction.
The potential difference between the drain voltage Vd and the source voltage (reference voltage) Vs is mainly applied to the channel region immediately below the space between the control line CL and the memory gate MGa on the drain side. As a result, a high electric field is generated in the channel region immediately below this space.
[0037]
The high electric field in the channel direction rapidly accelerates the electrons in the inversion layer channel and converts the electrons into high energy electrons, whereby electrons are injected into the storage unit 1. In order to improve the injection efficiency, the voltage applied to the control line CL and the memory gate MGa (word line WL) so that the electric field in the channel direction is concentrated in the same region as the region where the electric field in the channel vertical direction is concentrated. To control.
[0038]
In this embodiment, a storage layer is formed in the storage layer formation region ACLa, and its resistance is lowered. At this time, the resistance of the channel region immediately below the space between the control line CL and the memory gate MGa on the drain side becomes relatively high. Therefore, the potential difference between the drain voltage Vd and the source voltage Vs is applied locally and concentrated in the region immediately below this space. Utilizing this fact, the electric field in the channel direction is increased in the region near the source side end of the storage unit 1, and the vertical electric field in this region is increased by the potential difference between the memory gate MGa and the drain.
[0039]
In the source side injection method, the activation energy necessary for electrons to cross the potential barrier of the bottom dielectric film BTM is obtained from the electric field in the channel direction in the region near the source side end of the storage unit 1. In addition, an electric field perpendicular to the channel necessary for implantation can be obtained in the same region. For this reason, charge injection efficiency is improved as compared with normal CHE injection.
In particular, when the storage layer formation region is provided, the voltage applied to the control line CL and the memory gate MGa is optimized by optimizing the channel impurity concentration at which the inversion layer is formed and the concentration and depth of the storage layer formation region ACLa. There is an advantage that the flexibility of the range is increased and the charge injection efficiency can be easily improved.
[0040]
On the other hand, when writing to the other storage unit 2, electrons are efficiently injected into the storage unit 2 according to the same principle by switching the voltage relationship between the two source / drain regions S / D.
In this way, 2-bit information can be independently written in one memory cell.
[0041]
In erasing, the retained charge is extracted or a charge having a reverse polarity is injected.
When the retained charge is extracted, the charge may be extracted to the memory gate side through the top dielectric film TOP, or the charge may be extracted to the substrate side through the bottom dielectric film BTM. In any case, in order to generate a predetermined electric field in the pulling direction, a memory gate (word line WL in FIG. 1, control lines CLa and CLb in FIG. 2), source / drain regions S / D (and substrate SUB) A voltage is applied during As a result, the retained charge is extracted to the substrate side or the memory gate side by FN tunneling or the like. When the retained charge is extracted from the gate dielectric film GD, the memory transistor shifts to the erased state.
[0042]
FIG. 7 schematically shows an operation when erasing is performed by injecting a charge having a polarity opposite to that of the held charge.
A negative voltage is applied to the memory gate MGa, and a positive voltage is applied to the source / drain region S / D on the memory unit 1 side to be erased.
Under this condition, an inversion layer is formed in the storage layer formation region ACLa, and avalanche breakdown occurs due to sharp energy band bending. In the process leading to this breakdown, high energy electron-hole pairs are generated, and hot electrons are attracted to a positive voltage and absorbed in the storage layer formation region ACLa or the source / drain region S / D. On the other hand, most of the hot holes flow to the substrate SUB, but a part of them is attracted by the electric field generated by the memory gate MGa and injected into the gate dielectric film GD (storage unit 1).
Even in this erasing method, when it is desired to inject a hot hole into the storage unit 2 on the opposite side, a similar electric field is generated on the storage unit 2 side. The erasure of the storage unit 2 can be performed independently of the storage unit 1 and simultaneous 2-bit erasure is also possible.
[0043]
The above erasing method is not an embodiment of the erasing method of the present invention by source side injection. When writing is performed by hole injection using the avalanche breakdown described above, erasure may be performed by electron injection by source side injection. The erasing at this time is an embodiment of the erasing method according to the present invention. Since it is basically the same as the above-described writing method, including the voltage application procedure, description thereof is omitted here.
[0044]
[Second Embodiment]
The present embodiment relates to a reading method according to the present invention. Here, the cell configuration in FIG. 1 will be described as an example.
[0045]
In reading, so-called forward read is used. In forward read, first, for example, 1.0 V is applied between two source / drain impurity regions S / D so that the storage unit side where the storage data to be read is held is the drain and the other storage unit side is the source. A drain voltage of about a level is applied. Next, predetermined positive voltages are respectively applied to the control gate CG and the memory gate MGa or MGb on the drain side. As a result, the channel on / off or the current amount varies depending on the presence / absence of the charge in the drain side storage unit to be read or the difference in the charge amount, and as a result, the potential change in the impurity region S / D on the drain side Appears. By reading this potential change with a sense amplifier (not shown), it is possible to determine the logic of the stored data.
Reading data from other storage units is performed in the same manner by switching the source and drain. Thereby, the 2-bit stored data can be read independently.
Note that reading is often performed after writing, such as verification after writing, so the so-called forward read method, in which the voltage application direction between the source and drain is the same as that at the time of writing, is used for source lines and bits. This saves the time and power required to charge and discharge the wire, which is advantageous.
[0046]
In the reading method according to the present embodiment, in the application of the gate voltage described above, a pulse of a voltage of, for example, 1.0 V is first applied to the memory gate MGa or MGb on the drain side, and is applied to the control gate CG during the application. Raise the pulse. Then, for example, timing control is performed so as to end both pulses at the same time.
[0047]
FIG. 8 is a graph showing a drain current change with respect to the control gate voltage when the right storage unit 1 is read by forward reading. FIGS. 9A to 9D are graphs showing FIG. 8 divided into 2-bit storage states.
In this reading method, a large current flows when there is no data in the storage unit 1 and the storage unit 2 (□ in the figure), that is, in the state of “11”.
On the other hand, when there is no data in the storage unit 1 to be read and there is data in the storage unit 2 (Δ mark in the figure), that is, in the state of “01”, the resistance of the source viewed from the control gate is increased. Some current is reduced as compared with the state of 11 ″.
In the case where there is data in the storage unit 1 to be read and there is no data in the storage unit 2 (indicated by a circle in the figure), that is, in the state of “10”, the resistance of the drain as viewed from the control gate increases. The drain current is greatly reduced as compared with the above state.
In the case where both the storage unit 1 and the storage unit 2 have data (in the drawing, ◆), that is, in the state of “00”, the current is still extremely small.
[0048]
Thus, for example, when the drain voltage Vd is set to 1.0 V and the memory gate voltage Vmg is applied at 1.0 V, and the control gate voltage Vcg is applied at about 1.0 V, the storage unit 1 that is a read target has no electric charge. In some cases, a read current of about 0.1 mA flows whether or not the storage unit 2 is charged. In addition, when the storage unit 1 has a charge, the flowing current is 1 μA or less regardless of whether the storage unit 2 has a charge.
Therefore, by using this reading method, it is possible to read 2-bit information with almost no influence from the storage unit that is not to be read.
[0049]
Various modifications are possible in the embodiments of the present invention.
For example, as shown in FIG. 10, a memory cell structure in which a storage layer formation region ACL is provided only on one side of the control gate CG may be adopted. In this case, naturally, 1 bit / cell storage is performed, but the memory cell area is smaller than in the case of 2 bits / cell storage described above.
Further, the structure of the gate dielectric film GD is not limited to the so-called MONOS type but may be an MNOS type. Further, the present invention can be applied to a nanocrystal type in which small particle semiconductors, for example, fine particles of polycrystalline silicon are discretely embedded in a dielectric film, and also to a so-called FG type.
[0050]
In the charge injection of this embodiment, the variation in power consumption and writing is suppressed by controlling the voltage application timing of the gate electrode. When this voltage application timing control is performed during reading, the source and drain as viewed from the control gate are used. The storage layer forming region for improving the charge injection efficiency in the above-described embodiment is not indispensable.
[0051]
【The invention's effect】
According to the nonvolatile semiconductor memory device and the operation method (write / erase method) according to the present invention, in a so-called source side injection type memory element, it is possible to suppress power consumption and write pulse delay during writing.
In addition, according to the operation method (reading method) of the nonvolatile semiconductor memory device according to the present invention, for example, in a source side type memory element capable of storing 2 bits, reading that reduces the influence of a bit different from the reading bit as much as possible is possible. It becomes possible.
[Brief description of the drawings]
FIG. 1 is an equivalent circuit diagram showing a first configuration example of a nonvolatile memory cell according to an embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram showing a first configuration example of a nonvolatile memory cell according to an embodiment of the present invention.
3A is a schematic cross-sectional view in the row direction along the word line of the memory cell shown in FIG. 1, and FIG. 3B is a plan view thereof.
4A is a schematic cross-sectional view in the row direction along the word line of the memory cell shown in FIG. 2, and FIG. 4B is a plan view thereof.
FIG. 5A is an explanatory diagram of an operation when electrons are injected into the storage unit 1 using source-side injection. (B) is a diagram showing the relationship between the horizontal position Px in the channel direction at this time, the channel potential V, and the channel electric field Ex in the horizontal direction.
FIGS. 6A and 6B are waveform diagrams of pulses applied during writing to the memory gate and the control gate.
FIG. 7 is a diagram showing an operation when erasing is performed by injecting a charge having a polarity opposite to that of a held charge;
FIG. 8 is a graph showing a drain current change with respect to a control gate voltage when a right storage unit is read by forward read.
FIGS. 9A to 9D are graphs showing FIG. 8 separately for each 2-bit storage state.
FIG. 10 is a cross-sectional view of a memory cell according to a modification of the embodiment of the present invention in which a storage layer formation region is provided only on one side of a control gate.
[Explanation of symbols]
ACL, ACLa, ACLb ... accumulation layer forming region, BLa, BLb ... bit line, BTM ... bottom dielectric film, CG ... control gate (second gate electrode), CH1 ... inner channel region (inversion layer forming region), CH2a, CH2b ... outer channel region, CHS ... main charge storage film, CL, CLa, CLb ... control line, Ex ... channel electric field, GD, GD0 ... gate dielectric film, M ... memory cell, MG, MGa, MGb ... memory gate ( (First gate electrode), Px ... horizontal position, S / D ... source / drain impurity region, SUB ... substrate, TOP ... top dielectric film, T _PGM ... Program time, V ... Channel potential, Vcg ... Control gate voltage, Vd ... Drain voltage, Vmg ... Memory gate voltage, Vs ... Source voltage (reference voltage), WG ... Word gate electrode, WL ... Word line.

Claims (11)

A channel forming region made of the first conductive type semiconductor, and a first source / drain region and a second source / drain region each made of the second conductive type semiconductor and disposed with the channel forming region interposed therebetween, had charge storage capability. The first gate electrode formed on the channel forming region on the first source / drain region side with a laminated film interposed therebetween, and the single gate dielectric film having no charge storage capability interposed therebetween And a second gate electrode formed on a channel formation region between the second source / drain regions and insulated from the first gate electrode,
When writing or erasing
Applying a predetermined drain voltage to the first source / drain region with reference to the second source / drain region;
A first gate voltage is applied to the first gate electrode so that charges energized in the channel formation region are injected from the second source / drain region side into the stacked film under the first gate electrode. Applying a second gate voltage to the second gate electrode,
In the application step of the gate voltage, the application of the first gate voltage is started, and the application of the second gate voltage is started in the middle of the application of the first gate voltage. The method of operating a nonvolatile semiconductor memory device according to claim 1, wherein the second gate voltage is smaller than the first gate voltage. The pulse of the first gate voltage is activated, and the pulse of the second gate voltage having a shorter generation time is activated during the activation, and then the two pulses are simultaneously deactivated, or the second gate is activated. The method of operating a nonvolatile semiconductor memory device according to claim 1, wherein the pulse of the first gate voltage is returned to inactive after a voltage pulse. The nonvolatile semiconductor memory device includes another first gate electrode formed on a channel formation region between the second gate electrode and the second source / drain region with a stacked film having charge storage capability interposed therebetween. In addition,
Injection of high energy charges at the time of writing or erasing into the laminated film under the other first gate electrode is as follows.
Applying a predetermined drain voltage to the second source / drain region with reference to the first source / drain region;
Charges energized in the channel formation region are injected from the first source / drain region side into the stacked film under the other first gate electrode, so that the other first gate electrode is charged. Applying a second gate voltage to the second gate electrode, the first gate voltage,
The application of the first gate voltage to the other first gate electrode is started in the application step of the gate voltage, and the application of the second gate voltage is started during the application of the first gate voltage. Of operating the non-volatile semiconductor memory device. A memory cell;
A drive circuit for applying a bias to the memory cell,
The memory cell includes a channel forming region made of a first conductivity type semiconductor, two source / drain regions each made of a second conductivity type semiconductor and sandwiching the channel formation region, and a stacked film having charge storage capability And a first gate electrode formed on the channel formation region with a single layer dielectric film having no charge storage capability interposed therebetween and insulated from the first gate electrode. 2 gate electrodes,
When the driving circuit applies predetermined voltages to the first gate electrode and the second gate electrode at the time of writing, erasing or reading, the voltage application to the first gate electrode is started, A non-volatile semiconductor memory device comprising means for controlling a timing of voltage application for starting voltage application to the second gate electrode in the middle of voltage application to the electrode. The channel forming region is
An inversion layer forming region comprising a first conductivity type semiconductor and having a channel formed by an inversion layer below the second gate electrode;
The nonvolatile semiconductor memory device according to claim 5, further comprising: a storage layer forming region formed of a second conductivity type semiconductor and having a channel formed by a majority carrier storage layer below the first gate electrode. The storage layer formation region is provided between the inversion layer formation region and one source / drain region, and between the inversion layer formation region and the other source / drain region,
The non-volatile semiconductor memory device according to claim 6, wherein the first gate electrode is disposed above each storage layer forming region with the stacked film having the charge storage capability interposed therebetween. A storage layer forming region formed of a second-conductivity-type semiconductor and having a channel formed by a majority-carrier storage layer, and a channel formed of an inversion layer formed of a first-conductivity-type semiconductor adjacent to one side of the storage layer forming region. A channel forming region including an inversion layer forming region, a first source / drain region made of a second conductivity type semiconductor adjacent to the channel forming region on the storage layer forming region side, and the channel forming region A first source / drain region made of a second conductivity type semiconductor adjacent on the opposite side of the storage layer formation region and a first layer formed on the storage layer formation region with a stacked film having charge storage capability interposed therebetween. A non-volatile semiconductor memory device having a gate electrode and a second gate electrode formed on the inversion layer forming region with a single-layer dielectric film having no charge storage capability interposed A method of operation,
When reading
Applying a predetermined read voltage to the first source / drain region with reference to the second source / drain region;
Applying a first gate voltage capable of controlling the formation of a channel according to the amount of charge in the stacked film to the first gate electrode, and applying a second gate voltage necessary for the channel formation to the second gate electrode; Have
In the application step of the gate voltage, the application of the first gate voltage is started, and the application of the second gate voltage is started in the middle of the application of the first gate voltage. Another storage layer formation region formed in the channel formation region between the inversion layer formation region and the second source / drain region and made of a second conductivity type semiconductor;
Another first gate electrode formed on the other storage layer formation region with a laminated film having charge storage capability interposed therebetween,
Reading out the laminated film under the other first gate electrode
Applying a predetermined read voltage to the second source / drain region with reference to the first source / drain region;
A first gate voltage capable of controlling the formation of a channel according to the amount of charge in the stacked film under the other first gate electrode is applied to the other first gate electrode, and a second gate voltage necessary for the channel formation is applied. Applying to the second gate electrode,
The application of the first gate voltage to the other first gate electrode is started in the application step of the gate voltage, and the application of the second gate voltage is started during the application of the first gate voltage. Of operating the non-volatile semiconductor memory device. A channel forming region made of a first conductivity type semiconductor and having a channel formed by an inversion layer, and a first source / drain region and a second source / drain each made of a second conductivity type semiconductor and disposed across the channel formation region A first gate electrode formed on the channel forming region on the first source / drain region side through a region, a laminated film having charge storage capability, and a single-layer dielectric film having no charge storage capability A non-volatile semiconductor memory device having a second gate electrode formed on a channel forming region on the second source / drain region side through
When reading
Applying a predetermined read voltage to the first source / drain region with reference to the second source / drain region;
Applying a first gate voltage capable of controlling the formation of a channel according to the amount of charge in the stacked film to the first gate electrode, and setting the second gate voltage necessary for the channel formation to the second gate electrode; Have
In the application step of the gate voltage, the application of the first gate voltage is started, and the application of the second gate voltage is started in the middle of the application of the first gate voltage. And further comprising another first gate electrode formed on the channel formation region between the second gate electrode and the second source / drain region with a stacked film having charge storage capability interposed therebetween,
Reading out the laminated film under the other first gate electrode
Applying a predetermined read voltage to the second source / drain region with reference to the first source / drain region;
A first gate voltage capable of controlling the formation of a channel according to the amount of charge in the stacked film under the other first gate electrode is applied to the other first gate electrode, and a second gate voltage necessary for the channel formation is applied. Applying to the second gate electrode,
The application of the first gate voltage to the other first gate electrode is started in the application step of the gate voltage, and the application of the second gate voltage is started during the application of the first gate voltage. Of operating the non-volatile semiconductor memory device.

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