TWI364112B - Nonvolatile memory having modified channel region interface - Google Patents

Description

1364112

'三达编号: TW3135PA 九九, invention description: [References in the relevant application] • The present invention claims the priority of the inventor of the inventor, Liao Yijun, July 1, 2006 - US Patent Provisional Application No. 60/806,840 The name of the case is Recess-Channel Non-Volatile Memory Cell Structure, Manufacturing Methods and Operating Methods. BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to non-volatile memory, and more particularly to non-volatile memory having a varying channel region interface, such as a source and a threshold for varying channels. A pole or a recessed passage area. [Prior Art] The electrically programmable and erasable volatile memory technology, known as EEPROM and flash memory storage structures, is used in a variety of modern applications. A plurality of memory cell structures are used for EEPR0M and flash memory. When the size of the integrated circuit is reduced, the importance of the memory cell structure based on the charge trapping dielectric layer is gradually increasing because of the ability to adjust the size and the simplification of the process. The memory cell structure based on the charge trapping dielectric layer includes a structure called PmNES, SONOS or NR0M, for example, in the industry. These memory cell structures store data by trapping charge in a charge trapping dielectric layer such as tantalum nitride. When the negative charge is captured, the threshold voltage of the memory cell increases. Memory 1364112

-' Sanda number: TW3135PA gas. The power of the body unit is reduced by removing the negative charge from the charge trapping layer. The conventional non-volatile nitride unit structure is planar so that the oxidation··· A nitride-oxide structure is formed on the surface of the substrate. However, this planar structure has the ability to have a small size, stylized • and erase operating power, and the properties of the chip resistance. This structure is described in YEH'CC et al., "PHINES: A new low-power stylized/erased, small-interval, single-single-cell double-bit flash memory (PHines: • A Novel Low Power) Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory)”, Electronic Device Conference, 2 〇〇 2 years, IEDM, 〇 2

Digest. International’8-11, December 2002, Pages: 93i · 934. Accordingly, there is a need to modify the planar structure of this conventional non-volatile nitride cell structure to address one or more of the above disadvantages. [Summary of the Invention]

The present invention relates to a non-volatile memory having a varying channel region interface. X In accordance with a first aspect of the present invention, a non-volatile memory cell integrated circuit is provided that includes a charge trapping structure, a source and a drain, and a dielectric structure. The charge trapping structure stores charge to control the logic state stored by the non-volatile memory cell integrated circuit. In various embodiments, the charge trapping structure stores one bit or multiple bits. The source region and the immersion region are separated by a channel region, which is a part of a circuit that undergoes inversion to 'electrically connect the source and the drain region. ^ The dielectric structure lacks a power 1364112

,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The dielectric structure is at least partially located between the charge trapping structure and the channel region and at least partially between the charge trapping structure and a gate voltage source. An interface separates a portion of the one or more dielectric structures from the channel region. One of the first ends of the interface ends in an intermediate portion of one of the source regions, and one of the second ends of the interface ends in an intermediate portion of one of the drain regions. To implement this interface, an embodiment lifts the source and drain regions away from one of the substrates of the I non-volatile memory cell integrated circuit. In another embodiment, the channel region is recessed into one of the substrates of the non-volatile memory cell integrated circuit. According to a second aspect of the present invention, a method of fabricating a non-volatile memory cell integrated circuit includes the steps of: forming a charge trapping structure to store charge to control storage by a non-volatile memory cell integrated circuit a logic state, wherein in various embodiments, the charge trapping structure stores one bit or multiple bits; I forms a source region and a drain region separated by a channel region; and forms a dielectric structure, at least A portion is located between the charge trapping structure and the channel region and at least partially between the charge trapping structure and a gate voltage source. An interface separates one of the one or more dielectric structures from the channel region, and one of the first ends of the interface ends in an intermediate portion of the source region, and the second end of the interface ends in a middle portion of the drain region . In order to implement this interface, an embodiment adds a layer of material to the integrated body.

* TW3135PA board, lifting the source region Wei pole area away from the non-volatile symmetry body sheet, one of the substrates is formed by another embodiment - the groove is formed on a substrate to form the charge trapping structure and the dielectric structure In the slot. Body junction charge nanocrystals ^ How to capture the structure. The structure and other implementations are at least partially located in the charge trapping structure. The above-mentioned "electrical structure" includes, for example, the above-mentioned embodiments, which can be more clearly understood. The following detailed description is in accordance with the accompanying drawings, and the detailed description is as follows: [Embodiment] Schematic diagram of the volatile memory cell, the non-volatile gate 102, the channel of the Taixi slave virtual A recess. The gate voltage Vg has a work function greater than that of Τ^, 不艺贝%, the gate structure contains a best material. It is greater than about the eigenfunction function of the type 4 guard, or greater than about Me eV, and the material contains p-type eve 2 5 eV, for example, greater than about 5 eV ° representative gate material. Suitable for people, silicon nitride, titanium nitride , platinum and other high work function metals and materials include other cobalt (Co). gold having a relatively high work function in the examples, including but not limited to ruthenium (Ru), ruthenium ((7), nickel (Ni) Is a nitride · r alloy, including but not limited to 钌 _ titanium and nickel - titanium; gold (Ru 〇 2h ancient, and metal oxide, including but not limited to yttrium oxide 2 work function gate material production ratio The typical N-type polysilicon gate voltage W is the word line of the material, with 44112

Sanda number: TW3135PA The higher the electrons are worn by the person. The N-type multiple (four) gate with a dioxic barrier is used in the 3 15 / as the outer dielectric layer. The embodiment of the present invention uses the gate for the gate and the outside for the donor. Therefore, there is a -injection barrier, which is higher than about 3.15 eV. For example, the material used for the layer is that the rTM has a day-to-day gate, and the implantation barrier is about 4.25 eV, and the P type contains a dioxide dioxide dielectric. The N-type polycrystalline layer of the layer is closed and the threshold value of the unit with the convergence of the life is reduced by about 2 volts. The dielectric structure 104 produced by the 5' is located at the gate 102 and the electrical material. It contains other similar high dielectric constant materials. The charge storage structure should store charge to control the non-volatile (four) is; = stored: logic state. The charge storage structure of the prior embodiment is stored! 槿 = polycrystalline ♦ to spread the charge throughout the disk. The charge storage structure of the new embodiment is a charge trapping circuit. This newer embodiment is not like a conductive material, it will be used to store the position of the structure, so as to start different positions to capture the structure, and save (4) logic (4). Pure charge trapping, '. Structure. 4 has a thickness of about 3 to 9 nm of tantalum nitride. The partial/primary region 11G and the drain region 112 are in the majority of the embodiment 70 lines' and are characterized by a junction depth 120. Body Area 1364112 Sanda Number: TW3135PA 122 is a substrate or well in most embodiments and is pressure vb. In order to be applied to the gate 1〇2' source 11 and the appropriate biasing configuration of the body 122, a "channel ι4", 110 and a drain 112^ are electrically connected to the source core.

The top edge of the source and the dipole d 116 is higher than the interface 118 between the channel 114 and the structure 108. However, the interface 118 between the channel ιΐ4 and the dielectric=m is maintained at the edge of the source and the sub-region = 冓 Therefore, the interface between the channel 114 and the dielectric structure 〇8 is 妗^ source The intermediate region between the region 110 and the bungee region 112. Q; the source region 110 and the upper edge of the drain region 112 are lined with the upper edge of the body region 122. So 'the first! The non-volatile memory of the figure is an embodiment of a recessed channel. Figure 2 is a schematic diagram of a non-volatile memory cell having a source region and a drain region lifted off the semiconductor substrate. The non-volatile memory cells of Figures 1 and 2 are substantially similar. However, the source region 210 and the upper edge of the drain region 212 are located above the upper edge of the body region 122. Therefore, the non-volatile memory cell of Figure 2 is the source of the Niu Sheng; and the polar embodiment. The interface 218 between the channel 214 and the dielectric structure 208 still ends in the inter-growth region of the source region 21A and the drain region 212. The source region 210 and the drain region 212 are characterized by a junction depth. Figure 3A is a schematic diagram of the 'electron from' injection to the charge storage structure in a non-volatile memory cell having a recessed channel. The gate region 302 has a gate voltage Vg of -10V. Source area 3〇4 with 1364112

'Sanda number: TW3135PA, with 10V or floating source voltage Vs. The drain region 306 has a 10V or floating drain voltage Vd. The body region 308 has a body voltage Vb of 10V. Figure 3B is an illustration of electron injection from a gate to a charge storage structure in a non-volatile memory cell with raised source and drain regions: The bias configuration of Figure 3B is similar to Figure 3A. 'Fig. 4A is a schematic diagram of electrons injected from a substrate into a charge storage structure in a non-volatile memory cell having a recessed channel. The gate region 402 has a gate voltage Vg of 10V. The source region 404 has a -1 OV or floating source voltage Vs. The non-polar region 406 has a -10V or floating drain voltage Vd. The body region 408 has a body voltage Vb of -10V. Figure 4B is a schematic illustration of the injection of electrons from a substrate into a charge storage structure in a non-volatile memory cell having lifted source and drain regions. The bias configuration of Figure 4B is similar to Figure 4A. Figure 5A is a schematic illustration of band-to-band hot electron injection into a charge storage structure in a non-volatile memory cell having a recessed channel. ^ Gate region 502 has a gate voltage of 10V Vg〇p+ type source region 504 has a source voltage Vs of -5V. The p+ type drain region 506 has a 0V or floating drain voltage Vd. The N type body region 508 has a body voltage Vb of 0V. Fig. 5B is a schematic view showing the injection of hot electrons between the bands into the charge storage structure in the nonvolatile memory unit having the lifted source region and the drain region. The bias configuration of Figure 5B is similar to Figure 5A. Figure 6A is a schematic illustration of the channel hot electron injection into the charge storage structure in a non-volatile memory cell having a recessed channel. 1364112

Sanda number: TW3135PA * Secret area 602 has a gate voltage Vg of 1 〇v. The n+ type source region 604 has a source voltage Vs of -5V. The n+ type non-polar region _ has a voltage Vd of 〇v. The P-type body region 608 has a body voltage vb of 0V. · · 6B is a schematic diagram of the channel's hot electron injection into the charge-storing structure in a non-volatile memory cell with lifted source and immersed regions. The bias configuration of the Figure is similar to Figure 6A. Figure 7A is a schematic diagram of the substrate's hot electron injection into the charge storage structure in a non-volatile memory cell having a recessed channel. • The closed-pole region 7〇2 has a gate voltage of 1〇V. The Vgf-type source region 7〇4 has a source electric dust Vs of 0V. The n+ type non-polar region 7〇6 has a voltage V of 〇v. The N-type body region 708 has a body voltage % of _6V. The p-type well area 7Π) has a well voltage of -5V, the Vwe source area 7〇4 and the non-polar area 7〇6 are located in the well area 710, and the well area 71〇 is located in the body area 7〇8. Fig. 7B is a diagram showing the hot electron injection into the charge storage structure of the substrate in the non-volatile memory cell having the source region and the polar region of the lift. The bias configuration of Figure 7B is similar to Figure 7A. Figure 8A is a schematic illustration of the injection of a hole from a gate to a charge-storing structure in a non-volatile memory cell having a recessed channel. The gate region 802 has a idle voltage Vg of 10V. The source region _ has -ιόν or a floating source voltage Vs. The bungee area 8〇6 has the guessing or floating of the non-polar electric M (4), which has the body voltage %. Figure 8B is a schematic illustration of the injection of a hole from a gate to a charge storage structure in a non-volatile memory cell having a lifted source region. The bias configuration of Figure 8B is similar to Figure 8A. 12 1364112

Sanda number: TW3135PA The 9th 'Α is a non-volatile memory cell with a recessed channel'. The hole is injected from the substrate into the charge storage structure. The gate region 902 has a gate voltage Vg of -10V. Source region 904 has a 10V or floating source voltage Vs. The sum region 906 has a 10V or floating drain voltage Vd. The body region 908 has a body voltage Vb of 10V. Fig. 9B is an unintentional view of the injection of holes from the substrate into the electrical storage structure in the non-volatile memory of the source region with the lifted source region and the drain region. The bias configuration of Figure 9B is similar to Figure 9A. Figure 10A is a schematic illustration of the injection of inter-band thermoelectric holes into a charge storage structure in a non-volatile memory cell having recessed channels. The gate region 1002 has a gate voltage Vg of -10V. The n+ type source region 1004 has a source voltage Vs of 5V. The n+ type drain region 1006 has a 0V or floating drain voltage Vd. The P-type body region 1008 has a body voltage Vb of 0V. Fig. 10B is an illustration of the injection of inter-band thermoelectric holes into a charge storage structure in a non-volatile memory cell having a raised source region and a drain region. The bias configuration of Figure 10B is similar to Figure 10A. Figure 11A is a schematic illustration of the injection of channel thermowells into a charge storage structure in a non-volatile memory cell having recessed channels. The gate region 1102 has a gate voltage Vg of -10V. The p+ type source region 1104 has a source voltage Vs of 0V. The p+ type drain region 1106 has a 5V drain voltage Vd〇N type body region 1108 having a body voltage Vb of 0V. Figure 11B is a diagram showing the injection of a channel thermoelectric hole into a charge storage structure in a non-volatile memory cell having a lifted source region and a drain region. 13 i'364112

Ida number: TW3135PA% Intent: The bias configuration of Figure 11B is similar to the UA diagram. Figure 12A is a schematic illustration of a substrate thermowell injected into a charge storage structure in a non-volatile memory cell having a recessed channel. The gate region 1202 has a gate voltage Vg of -ιόν. The pn+ source region 1204 has a source of 〇V, Vs. The p+ type non-polar region has a non-polarity type. The Vd°P-type body region 1 has a body electrical clock Vb of 6V. The N-type well area 1210 has a well VV of 5V. The source region cerebral plaque and polar region 1206 are located in the well region 1210, while the well region Π10 is located in the body region. Fig. 12B is a diagram showing the substrate thermoelectric hole injection to the charge retention structure in the non-volatile memory cell having the lifted source region and the nonpolar region. The partial editing & setting of Fig. 12B is similar to that of Fig. 12A. Fig. 13A is a diagram showing an inverse reading operation for reading one of the data stored on the right side of the charge storage structure in a non-volatile memory cell having a recessed channel. The gate region 1302 has a gate voltage of 3V. The Vgen+ source region has a source voltage VsL of uv and the pole region 13〇6 has a gate voltage of 〇v. The Vd«P body region has a body voltage of 〇v, Figure 13B is a schematic illustration of a reverse read operation for reading data stored on the right side of the charge storage structure in a non-volatile memory cell having raised source and drain regions. The bias configuration of Figure 13B is similar to Figure 13A. Figure 14A is a reverse reading of the data stored on the left side of the charge storage structure in a non-volatile memory cell having a recessed channel.

Ida number: TW3135PA take the operation diagram. The closed-pole area MO2 has a 3V gate electric house Vg. #型源巴 has just the electric ^η + Wei pole area μ has ^ the bungee voltage Vd. ? Type body area 14Λ0曰士^ The hair has lifted up to send f 4 body early 7G in the 'reverse reading operation for storing the bit data 咅R (four), the left side of the w structure is similar to the 14A Figure. ^H14B diagram of the bias configuration class - Φ field 15t diagram is a non-volatile memory with a concave channel for reading the body stored in the right side of the charge storage structure (four) = inter-read operation schematic diagram. With 1504 area Γ. 2 has a gate voltage Vg of _1 〇V. n+ type source region source voltage VS. The meter type immersed area has 2V> and the extreme electric VdeP type is too jin 1 ^ ^ / 歪 body £ 1508 has the body voltage Vb of 〇 v. The source and bungee area of the single-line lifting of the memory Non-volatile data - Inter-band read operation 2: Take::: Load storage junction (10) ^^^ Similar to Figure 15A / Figure. 15B® bias configuration system - by m16A system is concave The non-volatile memory of the human channel stores a schematic diagram of the inter-band read operation of the data located on the left side of the charge storage structure. The gate region 1602 has a gate voltage of ·10 V. The & source region has The source of 2 V is very likely to be %. The n+ type bungee zone has a floating immersed voltage (four) type body area with a body voltage of qv. 15 1364112

, 达三号: TW3135PA; Figure 16B is for the inter-band reading of the data stored on the left side of the charge storage structure in the non-volatile memory unit with the raised source and drain regions. Take a schematic diagram of the operation. The bias configuration of Figure 16B is similar to Figure 16A. Due to the combination of the vertical and transverse electric fields, the current between the strips flowing through the non-volatile memory cell structure determines the charge storage state of a particular portion of the charge storage structure with high accuracy. Larger vertical and transverse electric fields result in larger currents between the bands. A biasing configuration is applied to a variety of different terminals to bend the bands sufficiently to create inter-band currents in the non-volatile memory cell structure while being between non-volatile memory cell nodes The potential difference is kept low enough so that stylization or erasure does not occur. In the bias configuration example, the non-volatile memory cell structure is reverse biased relative to the active source region or the drain region to the body region, creating a junction of the reverse bias. In addition, the voltage of the gate structure causes these bands to bend enough to cause interband tunneling through the non-volatile memory cell structure. In one of the non-volatile memory cell structure nodes (in most embodiments)

• Medium is the high doping concentration in the source or drain region. The structure node has a high charge density in the space charge region generated, and the voltage change of the space charge region in a short distance helps to generate an acute band bend. The electrons of the valence band on one side of the junction of the reverse bias are punctured to the conduction band on the other side of the junction of the reverse bias via the forbidden gap and drift downward to the potential energy hill (potential) Hill), deeper into the N-type node of the junction of the reverse bias. Similarly, the hole drifts over the potential energy hill, away from the N-junction of the junction of the reverse bias, and faces the junction of the reverse bias P 16 1364112

Sanda number: TW3135PA. Type node. The voltage in the gate region controls the voltage at the junction of the reverse bias voltages near the charge storage structure. When the voltage of the gate structure becomes more negative, the voltage at the portion of the junction of the reverse bias adjacent the charge storage structure becomes more negative, resulting in a deeper band bend in the diode structure. As a result of at least some of the following combinations of (1) and (2), more current between the bands will flow: (1) the occupied electron energy level on one side of the bending energy band and the other side of the bending energy band The increasing overlap between the unoccupied electron energy levels; and (2) the narrower barrier width between the occupied electron energy level and the unoccupied electron energy level (Sze, Physics of Semiconductor Devices , 1981). The net negative or net positive charge stored on the charge storage structure further affects the band curvature. According to Gauss's law, when the junction of the negative voltage and the reverse bias is applied to the gate region, the stronger electric field is connected by the reverse bias of the portion of the charge storage structure having a relatively high net negative charge. Partial experience. Similarly, when the junction of the positive voltage with respect to the reverse bias is applied to the gate region, the stronger electric field is connected by the reverse bias of the portion of the charge storage structure having a relatively high net positive charge. Part of what is experienced. The different bias configurations for reading and the biasing configuration for stylization and erasing show a careful balance. With respect to reading, the potential difference between the junction nodes of the reverse bias should not cause a substantial number of charge carriers to pass through a dielectric material to the charge storage structure and affect the charge storage state (ie, the programmed logic level). . In contrast, about stylization and erasing, at 17 1364112

The three-week: TW3135PA potential difference between the junction nodes of the reverse bias is sufficient to cause the substantial number of carriers to pass through a dielectric material and affect the charge storage state by inter-band hot carrier injection. Figure 17 is a manufacturing flow diagram of a non-volatile memory cell array having a recessed channel showing various possible combinations of process steps of Figures 19-23. The figure illustrates the combination of process flows as follows: Figures 19 and 22; 19 and 23; 20 and 22; 20 and 23; 21 and 22; and 21 and 23. These combinations are accompanied by backend processing. 18A and 18B are manufacturing flow diagrams of a non-volatile memory cell array having lifted source and drain regions. Figure 18A is a manufacturing flow diagram of a NOR non-volatile memory cell array having one of the source and drain regions of the lift, showing various possible combinations of the process steps of Figures 24-27. Figure 18A discloses the following combination of process flows: Figures 24, 25 and 27; and Figures 24, 26 and 27. These combinations are accompanied by backend processing. Figure 18B is a manufacturing flow diagram of a NAND non-volatile memory cell array having one of the source and drain regions of the lift, showing various possible combinations of the process steps of Figures 28-30. Figure 18B discloses the following combination of process flows: Figures 28 and 29; and Figures 28 and 30. These combinations are accompanied by backend processing. 19A to 19C are process steps for forming a groove in a non-volatile memory cell having a grooved channel before the 22nd or 23rd. In Figure 19A, oxide 1910 is deposited on the base 18 1364112

'Sanda number: TW3135PA ^ board 1900. The photoresist is deposited and patterned in m, and the patterned photoresist is used to remove portions of the oxide in accordance with the photoresist pattern. In Figure 19B, the residual photoresist helps protect the residual oxide i9i2. The residual photoresist is removed and the substrate not covered by the oxide is etched. • In Figure 19C, trench 丨 930 is etched into substrate 1900 that is not covered by oxide 1912. 20A to 20E are process steps for reducing the length of one pole before forming a groove in the non-volatile § memory unit before the 22nd or 23rd. 20A to 20E are process steps for reducing the length of a gate before forming a trench in a non-volatile memory cell before the 22nd or 23rd. Figures 20A through 20C are similar to Figures 19A through 19C. In Fig. 20D, a spacer 2040 is deposited into the trench leaving the next smaller trench 1932. In Fig. 20E, the portion of the spacer next to the bottom of the groove is engraved by the surname, leaving the spacer 2042. This reduction in gate length can result in a smaller gate length than in Figure 19. 21A to 21E are process steps for expanding a gate length before forming a trench in the non-volatile memory cell unit before the 22nd or 23rd. Figures 21A through 21B are similar to Figures 19A through 19B. In Figure 21C, the remaining patterned photoresist is removed to expose the patterned oxide 1912. In Figure 21D, the patterned oxide is surnamed, leaving a smaller patterned oxide 2112. In Fig. 21E, the trench 2132 is etched into the substrate 1900 which is not covered by the oxide 2112. This gate length scaling will result in a longer gate length than in Figure 19. 19 1364112

Sanda number: TW3135PA Figures 22A to 22K are the end of the 19th, 2nd or 21st drawing process step 'to form - NC) R _ hairline counting cell array, each NOR non-volatile memory The cells are located in a trench such that each non-volatile memory cell has a channel of one person. In Fig. 22A, a dielectric material such as a 0N0 layer is formed in the charge storage structure 225, thereby leaving a smaller trench 2232. In 帛22]311, the gate material 2260 of the deposition example is deposited in Fig. 22C, and the gate material is patterned, thereby leaving the lower gate material 2262 inside the trench. In the 22β-graph, a dielectric material 227 such as SiN is deposited on the gate material 2262. In Fig. 22E, the dielectric material is etched while the remaining dielectric material 2272 remains inside the trench. In Figure 22F, the residual patterned oxide is removed. At this point, the stack of gate material 2262 and oxide 2272 rises above the surface of the substrate. In the 22nd (Fig.), the ion implantation method forms the source region 2280 and the nonpolar region 2282. In the 22H image, for example, an oxide 229 HD of HDP oxide is deposited. In Fig. 221, for example, by CMP , dip-back or etch back to remove excess oxide overlying oxide 2272. In Figure 22J, oxide 2272 is removed. In Figure 22K, additional gate material is deposited to form a gate Polar regions 2264 〇 23A to 23E are process steps after the 19th, 2nd, or 21th drawing to form a NAND non-volatile memory cell array, each NAND non-volatile memory cell is located at In the trench, so that each non-volatile memory cell has a recessed channel. In FIG. 23A, for example, a dielectric material of a germanium layer and a charge storage structure 225 are formed in the trench, thereby remaining Small groove 2232 » In the 23rd picture, sink 1364112

: Sanda number: TW3135PA 'Production such as polysilicon gate material 2260. In Fig. 23C, the excess gate-pole material is removed, for example by CMP, to expose the germanium layer. In Figure 23D, the residual patterned oxide is removed. At this point, the point ' gate material 2262 rises above the surface of the substrate. In the 23rd, ion implantation forms source region 2380 and drain region 2382. · 24th to 24D is the process step before the 25th or 26th figure to form the source and bungee regions of a non-volatile memory cell in an N〇R array. . In Fig. 24A, a dielectric material such as a 〇N〇 ® layer and a charge storage structure 2410 are deposited on the substrate 2400. In Fig. 24B, a gate material such as polysilicon is deposited, for example, an oxide material of SiN is deposited on the gate material to form a photolithographic structure, and a stack of SiN 2430, polysilicon 2420 and germanium 2412 remains. In Fig. 24C, a spacer 2440 is formed. In Fig. 24D, the spacer is etched while the lower spacer sidewall 2442 remains. The 25th to 25th drawings are the ones of the non-volatile memory cells in the NOR array after the 24th and 27th processes. Source area and bungee area. In Figure 25A, 'deposited blasting stone eve 2550. In Fig. 25B, ion implantation forms source region 2560 and drain region 2562. The 26th to 26thth drawings are the process steps after the 24th and before the 27th, which use polysilicon to form the lift source region of one of the non-volatile memory cells in an N〇R array and No pole area. In Figure 26A, polycrystalline germanium 2650 is deposited. In Figure 26B, the polysilicon is returned to leave polycrystalline germanium 2652. In Figure 26C, ion implantation forms the source 21 1364112

· 'Sanda number: TW3135PA» Polar zone 2660 and polar zone 2662. 27A through 27D are process steps before the 25th or 26th drawing to form a nor non-volatile memory cell array, each _ NOR non-volatile memory cell having a source region for lifting Bungee area. In Fig. 27A, a dielectric material such as HDP oxide is deposited to cover the structure including the spacer sidewalls and oxide 2430. In Figure 27B, the excess oxide covering the oxide 2430 is removed, for example by CMP, dip-back or return money, while the remaining oxide 2772 surrounds the sidewalls of the spacer. In Figure 27C, oxide 2430 is removed. Additional gate material is deposited in Figure 27D to form gate region 2722. 28A to 28D are process steps starting before the 29th or 30th drawing to form a NAND non-volatile memory cell array, each NAND non-volatile memory cell having a source region and a lift Polar zone. In Fig. 28A, a dielectric material such as a germanium layer and a charge storage structure 2810 are deposited on the substrate 2800. In Fig. 28, a deposition example, such as a gate material of polysilicon, forms a lithographic structure, leaving a stack of polycrystalline germanium 2820 and germanium 2812 remaining. In Fig. 28C, a spacer 2840 is formed. In FIG. 28D, the spacer is etched, and the remaining spacer sidewalls 2842 〇 29th to 29th are the processing steps after the 28th drawing. The epitaxial enthalpy is used to form a NAND non-volatile memory unit. The array, each NAND non-volatile memory cell has a raised source region and a drain region. In Figure 29A, epitaxial germanium 2950 is deposited. In Figure 29B, ion implantation forms source region 2960 and drain region 2962. 22 1364112

- Canda No.: TW3135PA: Figures 3A to 30C are the process steps after the 28th drawing, which uses polysilicon to form a NAND non-volatile memory cell array, each NAND non-volatile memory cell. They all have the source area of lifting • and the bungee area. The 30th to 30thth drawings are the process steps after the 24th and the 27th, which use polysilicon to form the lift source region of one of the non-volatile memory cells in a NOR array. Bungee area. In Fig. 30A, polycrystalline germanium 3〇5〇〇 is deposited in Fig. 30B, and polycrystalline germanium is etched back to leave polycrystalline germanium 3052. In Fig. 30C, the ion implantation method forms a source region 3〇60 and a nonpolar region 3062. Figure 31 is a block diagram of a non-volatile memory volume circuit having an exemplary interface of the varying channel region as disclosed herein. The snubber body 3150 includes a memory array 31 非 of a non-volatile memory unit located on a semiconductor substrate. Each of the memory cells of array 31 has a varying channel region interface, such as a recessed channel region, or a lifted, pole and drain region. The memory cells of the array 31 may be individual ones that are connected to each other in an array or interconnected into multiple arrays. The column decoder 31〇1 is connected to a plurality of word lines 31〇2 which are arranged along the rank of the memory array 3100. The row decoder 31〇3 is connected to a plurality of bit lines 31〇4, which are arranged along the row of the memory array 31〇〇 on the bus bar 3 〇5 to provide the row decoder 3103 and the column. The decoder 31〇1. Sensing The rose and data input structures 31〇6 are connected to the 仃 decoder 3103 via the data bus 31〇7. The data is supplied to the data input in the block 31〇6 via the data input line 3111, from the input/output port on the integrated circuit 315, or from other sources inside or outside the integrated circuit 3(9). 〇4ΐΐ2

Ξ达号: TW3135PA into the structure. The data is supplied from the sense amplifier on the block (10) to the wheel input/output port on the integrated circuit 315 via the data output line 3115, or supplied to the inside or outside of the integrated circuit 3! Other information. 1. (4) Configuring the state machine to control the bias configuration supply voltage (for example, smearing and stylizing confirmation voltage), and for stylizing, and reading the configuration of the memory unit. Figure 32 is a schematic illustration of a φ non-volatile memory cell having a recessed channel between the source and drain regions, whereby the lower dielectric structure has a three-layer thin germanium structure. This structure is similar to the non-volatile memory cell of the figure, but the dielectric structure 108 (between the charge storage structure 1 and 8 and the channel region 114) is replaced by a two-layer thin structure 3208. The germanium structure 3208 has a small hole tunneling stop barrier, such as less than or equal to about 4.5 eV, or preferably less than or equal to about 1 9e^^〇N〇 structure 32〇8 close to the illustrated thickness range as follows. Regarding the lower oxide: &lt; 2 angstrom, 5-20 angstroms, or &lt;15 angstroms&quot; about the intermediate nitride: <2 〇 or ι〇·2〇 鲁埃. Regarding the upper oxide ··&lt; 20 angstroms or 15-20 angstroms. Some embodiments of the memory cell of Figure 32 are represented by SON〇N〇s or bandgap engineered (BE)-SONOS. Additional details of various embodiments of the three-layer thin crucible structure 3208 are disclosed in U.S. Patent Application Serial No. 11/324,540, the disclosure of which is incorporated herein by reference. Figure 33 is a schematic diagram of a non-volatile memory cell having a source region and a non-polar region lifted off the semiconductor substrate, whereby the lower dielectric structure has a three-layered thin structure 3208. In summary, although the present invention has been disclosed above in a preferred embodiment,

24 1364112

Sanda number: TW3135PA - It is not intended to limit the invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention is defined by the appended claims &quot;, 'the scope of patents.

25 1364112

达达编号·· TW3135PA [Simple description of the diagram] Figure 1 is a schematic diagram of a non-volatile memory unit with a concave channel between the source and drain regions. Figure 2 is a schematic illustration of a non-volatile memory cell having a source region and a drain region lifted off the semiconductor substrate. Figure 3A is a schematic illustration of the injection of electrons from a gate into a charge storage structure in a non-volatile memory cell having a recessed channel. Figure 3B is a schematic illustration of the injection of electrons from a gate into a charge storage structure in a non-volatile memory cell having raised source and drain regions. Figure 4A is a schematic illustration of the injection of electrons from a substrate into an electrical storage structure in a non-volatile memory cell having recessed channels. Figure 4B is a schematic illustration of the injection of electrons from a substrate into a charge storage structure in a non-volatile memory cell having lifted source and drain regions. Figure 5A is a schematic illustration of the injection of hot electrons between the strips into the charge storage structure in a non-volatile memory cell having recessed channels. Fig. 5B is a schematic view showing the injection of hot electrons between the bands into the charge storage structure in the nonvolatile memory unit having the lifted source region and the drain region. Figure 6A is a schematic illustration of the channel hot electron injection into the charge storage structure in a non-volatile memory cell having a recessed channel. Figure 6B is an illustration of the channel hot electron injection into the charge storage structure in a non-volatile memory cell having a source region and a drain region of lift 26 1364112

: Sanda number: TW3135PA figure. Figure 7A is a schematic diagram of the substrate's hot electron injection into the charge storage structure in a non-volatile memory cell having a recessed channel. · Figure 7B is a schematic diagram of the substrate's hot electron injection into the charge storage structure in a non-volatile memory cell with lifted source and drain regions. Figure 8A is a schematic illustration of the injection of a hole from a gate to a charge storage structure in a non-volatile memory cell having a recessed channel. • Figure 8B is a schematic illustration of the injection of a hole from a gate into a charge storage structure in a non-volatile memory cell with lifted source and drain regions. Figure 9A is a schematic illustration of the injection of a hole from a substrate into a charge storage structure in a non-volatile memory cell having a recessed channel. Fig. 9B is an unintentional view of the injection of holes from the substrate into the electrical storage structure in the non-volatile memory of the non-volatile memory of the source region and the drain region. • Figure 10A is a schematic illustration of the injection of inter-band thermoelectric holes into an electrical storage structure in a non-volatile memory cell with recessed channels. Fig. 10B is an illustration of the injection of inter-band thermoelectric holes into a charge storage structure in a non-volatile memory cell having a raised source region and a drain region. Figure 11A is a schematic illustration of the injection of channel thermowells into a charge storage structure in a non-volatile memory cell having recessed channels. Figure 11B is a non-swing 27 1364112 three-numbered: TW3135PA hair memory unit with lift source and drain regions. • Intention:: Channel thermoelectric injection into the charge storage structure. It is a sound map of the storage structure of the substrate in the element, the substrate thermoelectric &amp;&amp; The first MM image of the source memory cell having the source region of the lift and the pole into the charge storage structure is a one-way read operation for reading the non-volatile memory stored in the charge channel. Schematic diagram. One of the data on the right side of the electric bribe storage structure is the storage of the charge storage in the reverse reading operation of the non-volatile data of the source region and the bungee region. The structure of the right Xie 篦 14 Δ can not bear the picture. The system is a schematic diagram of a non-volatile memory single operation for storing the electric storage household &amp; The reverse of the data on the left side of the electrical fault structure ^Fig. 14 is the right and η = ::,, the heart a::, the non-swept reverse reading operation in the electrical storage structure ^1 Λ on the left side ~ forbearance round. - Figure 15 is one of the data on the right side of the schematic I electric gift storage structure for reading the single-cell read operation of the non-volatile memory stored in the human channel 31. The source of the lift and the bungee area of the bungee area are stored on the right side of the charge-dissipating structure.

S 1364112

Sanda number: A schematic diagram of the inter-band read operation of one of the TW3135PA data. Figure 16A is a schematic illustration of an inter-band read operation for storing data located to the left of the charge storage structure in a non-volatile memory cell having a recessed channel. Figure 16B is a schematic illustration of inter-band read operations for storing data located on the left side of the charge storage structure in a non-volatile memory cell having raised source and drain regions. Figure 17 is a manufacturing flow diagram of a non-volatile memory cell array having a recessed channel showing various possible combinations of process steps of Figures 19-23. Figure 18A is a manufacturing flow diagram of a NOR non-volatile memory cell array having one of the source and drain regions of the lift, showing various possible combinations of the process steps of Figures 24-27. Figure 18B is a manufacturing flow diagram of a NAND non-volatile memory cell array having one of the source and drain regions of the lift, showing various possible combinations of the process steps of Figures 28-30. 19A to 19C are process steps for forming a trench in a non-volatile memory cell having a recessed channel before the 22nd or 23rd. 20A to 20E are process steps for reducing the length of a gate before forming a trench in the non-volatile memory cell before the 22nd or 23rd. 21A to 21E are diagrams for expanding a gate length before forming a trench in a non-volatile memory cell before the 22 or 23 figure. 29 1364112

Sanda number: TW3135PA process steps. 22A to 22K are the process steps after the 19th, 20th or 21th step to form an N〇R non-volatile memory cell array, and the parent NOR non-volatile memory cell is located in a trench. In the slot, so that each non-volatile memory cell has a recessed channel. 23A to 23E are the end of the 19th, 20th or 21th, and (4) '(4) into NAND non-volatile memory cell array, each NAND non-volatile memory cell is located in a trench, So that each non-volatile memory cell has a recessed channel. Figures 24A through 24D are process steps beginning before the 25th or 26th drawing to form the source and drain regions of the non-volatile (four) single turn in the -on array. 25A to 25B are the process steps after the 24th drawing and before the 27th drawing, which causes the county crystal (4) to form a non-volatile record of the -n〇r array, which is lifted by the unit. District and bungee area. The 26AS26C diagram ends the process step after FIG. 24 and before the 27th figure, which uses multiple (four) to form the lift source region of the non-volatile memory cell in the -n〇r array. . The 27th to 27th drawings are completed at the end of the 25th &lt; 26th drawing process step 'to form a -N〇R non-volatile memory cell array, and each Ν R non-volatile memory n unit has a source of material Polar zone and immersion zone. The 28A to 28D drawings are the process steps starting before the 29th or 3rd drawing to form a NAND non-volatile memory cell array, each NAND non-volatile (four) element has a transfer source (four) and a immersion 30 1364112 Sanda number: TW3135PA area. 29A to 29B are process steps after the 28th drawing, which use epitaxial germanium to form a NAND non-volatile memory cell array, each NAND non-volatile memory cell having a source of lift District and bungee area. The 30A to 30C are the process steps after the 28th drawing, which uses polysilicon to form a NAND non-volatile memory cell array.

Columns, each NAND non-volatile memory cell has a raised source region and a drain region. Figure 31 is a block diagram of a non-volatile memory volume circuit having an exemplary interface of the varying channel region as disclosed herein. Figure 32 is a schematic illustration of a non-volatile § memory cell having a recessed channel between the source region and the drain region, whereby the lower dielectric structure has a three-layered germanium structure. Figure 33 is a diagram of a non-volatile cell having a raised region of the source region of the semiconductor substrate. The lower dielectric structure has a two-layer thin 0Ν0 structure. Eight 31 1364112

Sanda number: TW3135PA [Description of main component symbols] 102, 302, 402, 502, 602, 702, 802, 902, 1002, 1102, 1202, 1302, 1402, 1502, 1602, 2264, 2722: gate/gate Region 104: Dielectric Structure 106: Charge Storing Structure 108: Charge Storing Structure/Dielectric Structure 110, 210, 304, 404, 804, 904, 1204, 2280, 2380, 2560, 2660, 2960, 3060: Source/Source Polar regions 112, 212, 306, 406, 806, 906, 1206, 2282, 2382, 2562, 2662, 2962, 3062: drain region/drain 114, 214: channel region/channel 116: source and drain regions 118: interface 120: junction depth 122: body/body region 208: dielectric structure 218: interface 220: junction depth 308, 408, 808, 908, 1208: body region 504, 1104: p+ source region 506, 1106: p+ type j: and polar regions 508, 708, 1108: N-type body regions 604, 704, 1004, 1304, 1404, 1504, 1604: n+ type source 32 1364112

: Sanda number: TW3135PA Polar zone 606, 706, 1006, 1306, 1406, 1506, 1606: n+ type bungee zone '608, 1008, 1308, 1408, 1508, 1608: P-type body zone '710, 1210: Well Zones 1900, 2400, 2800: Substrate 1910, 1912, 2112, 2290, 2772: Oxide 1922: Photoresist • 1930, 1932, 2232: Trench 2040, 2042, 2440, 2840: Clearance 2250. Dielectric material and charge Storage structure 2260, 2262: gate material 2270, 2272: dielectric material 2410: dielectric material and charge storage structure 2412: ΟΝΟ 2420, 2650, 2652, 2820, 3050, 3052: polysilicon 9 2430: SiN/oxide 2442 2842: spacer sidewalls 2550, 2950: epitaxial eve 2810: charge storage structure 2812: ΟΝΟ 3100: memory array 3101: column decoder 3102: word line 33 1364112

'Sanda Number·· TW3135PA ; 3103 : Row Decoder 3104 : Bit Line 3105 : Bus Bar ' 3106 : Sense Amplifier and Data Input Structure \ 3107 : Data Bus • 3108 : Bias Configuration Supply Voltage 3109 : Bias Configuration state machine 3111: data input line • 3115: data output line 3150: integrated circuit 3208: ΟΝΟ structure 34

Claims (1)

1364112 Page 10, the scope of patent application: 1. A non-volatile memory cell integrated circuit, comprising: a charge trapping structure for storing charge to control a logic state stored by the non-volatile memory cell integrated circuit; a source region and a gate region are separated by a channel region; and one or more dielectric structures are at least partially located between the charge trapping structure and the channel region, and at least partially located in the charge trapping structure and a gate Between extreme voltage sources, One of the interfaces separates a portion of the one or more dielectric structures and the channel region, a first end of the interface is located at an upper edge and a lower edge of the source region, and ends between the edges and ends in a middle portion of the source region And a second end of the interface is located between the upper edge and the lower edge of the drain region and ends in the middle portion of the &gt; and the polar region. 2. The circuit of claim 1, wherein the source region and the drain region are lifted off a substrate of the non-volatile memory cell integrated circuit, such that the interface is first The end ends in an intermediate portion of the source region, and the second end of the interface ends in a middle portion of the drain region. 3. The circuit of claim 1, wherein the first end of the interface ends in the source region because the channel region is recessed into a substrate of the non-volatile memory cell integrated circuit. The intermediate portion, and the second end of the interface ends in a middle portion of the drain region. 4. The circuit of claim 1, wherein the charge trapping structure stores one bit. 35 ^64112 5. The circuit described in claim 1 of the patent scope~; the charge capture structure stores multiple bits.硌*中电6. The circuit of claim 1, wherein the dielectric structure is between the charge trapping structure and the channel region, and the second layer of nitrogen The fossil layer is located on the lower oxidized layer; and an upper yttrium oxide layer is disposed on the intermediate tantalum nitride layer. 7. The oxidized stone layer has a thickness of less than about 20 angstroms as described in the scope of the patent application. The circuit, wherein the lower portion, has a thickness of less than about 20 angstroms, as in the sixth aspect of the patent application. A circuit, wherein the layer 9 has a thickness of less than about 20 angstroms as claimed in claim 6 of the patent application. /, 中中上10. As in the scope of the patent application, the oxidized stone layer has a circuit having a thickness of about 5 to 20 angstroms, wherein the lower nitrogen is two: and the circuit described in item 6, wherein The middle layer has a thickness of about 10 to 2 angstroms. The circuit of item 6, wherein the upper layer has a thickness of about 15 to 2 angstroms. I3. The Thunderbolt gasification layer as described in claim 6 has a circuit having a thickness of less than about 15 angstroms, wherein the lower idle electrode: ΐφ is the circuit described in claim 1 of the patent scope, Further including a source region and the immersion region, the channel region is separated from the charge trapping structure on the opposite side of the modified junction between August 25, 366. ^5.- A method for manufacturing a non-volatile memory cell integrated circuit' includes the following steps: Forming a charge trapping structure to store a charge, and reading the logic stored by the non-volatile memory unit circuit - logic a state separated from the channel region - a source region and a drain region; and forming one or more dielectric structures, the one or more dielectric junctions being located in the charge trapping structure and the channel Between the zones, and to the &gt;, the section between the charge her structure and the 1-pole source, the fish interface separates one or more of the dielectric structures from the two interfaces - the first end is located in the source region The upper edge of the flute-deuterium ends in the middle portion of the source region, and the interface-% is located at the upper edge of the drain region ^ ^ ^ ^ ^ ^ ^ ^ ^ in the middle portion of the non-polar region . And the method of claim 15 wherein the step of forming the source and the drain region comprises: a substrate to make the source Substrate. Lifting away from 1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The formation step of one or more dielectric structures is described in the following section: 37. August 25, pp. Amendment Replacement Page 8. As claimed in claim 15th J1, 1 charge trapping structure storage-bit. , 'U , , ' where 19 * as described in claim 15 of the scope of the patent, the charge trapping structure stores multiple bits. , /, 泫 20 · as described in claim 15 of the scope of the patent to form a ruthenium oxide layer; an intermediate tantalum nitride layer on the lower ruthenium oxide layer; and an upper ruthenium oxide layer formed in the middle nitridation On the 矽 layer. 21. The method according to claim 20, wherein the oxidized layer has a thickness of less than about 20 angstroms, wherein the 22. the intermediate gasification layer of the second aspect of the patent application has less than about 2 The thickness of the 〇 2 2 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到 到The layer/layer has a thickness of about 5 to 20 angstroms. The intermediate nitride layer has a thickness of about Π) to 2 〇 as described in claim 2 of the scope of the patent application. The method wherein the oxime is as described in claim 2, wherein the ruthenium oxide layer has a thickness of about 15 to 20 angstroms. , as described in the second paragraph of the patent scope of the application. The lower oxide layer has a thickness of less than about 15 angstroms, wherein the 38 ii04JL12 is revised on August 25, 2010. 28. If the patent application scope The following steps are described in the item 15: the method of the item further comprises: separating the source region from the secret region by the channel region and the charge trapping structure on the opposite side of the _ pole. 29. "A non-volatile memory cell integrated circuit, comprising: a nano crystal structure for storing the memory of the Ray 4 memory cell integrated circuit - logic state Ύ ° non-volatile ❿ a::: and a drain region 'which is separated by a channel region; and a 盥m-solid dielectric structure at least partially between the nanocrystal and a gate voltage source, ... the disc, the interface separates the one or a portion of the plurality of dielectric structures and the S-channel region, the interface of the first and lower edges of the interface is located at the upper edge of the source region, 'b1, and is bundled in the source region The middle portion, and the interface is in the middle portion of the bungee region. The circuit of claim 29, wherein the drain region is lifted away from the non-volatile substrate - such that the first end of the interface ends in a middle portion of the beam. a circuit as described in the "Patent Application No.", wherein the first end of the (four) interface of the non-volatile memory cell integrated circuit ends at the source end The middle portion of the zone 39 13,64112 is revised on August 25, 100, and the second end of the interface ends in the middle portion of the drain region. 32. The circuit of claim 29, wherein the nanocrystal structure stores one bit. 33. The circuit of claim 29, wherein the nanocrystal structure stores multiple bits. 34. The circuit of claim 29, further comprising a gate, wherein the source region and the non-polar region are the channel region and the nanocrystal on the opposite side of the gate Structural separation. 35. A method of fabricating a non-volatile memory cell integrated circuit, comprising the steps of: forming a nanocrystal structure to store a charge to control a logic state stored by the non-volatile memory cell integrated circuit; Separating a source region and a non-polar region from a channel region; and forming one or more dielectric structures at least partially between the nanocrystal structure and the channel region, and at least partially located in the nanocrystal Between the structure and a gate voltage source, one of the interfaces separates a portion of the one or more dielectric structures from the channel region, and the first end of the interface is located between the upper edge and the lower edge of the source region And ending at a middle portion of the source region, and a second end of the interface is located between the upper edge and the lower edge of the drain region and ends at a middle portion of the drain region. 36. The method of claim 35, wherein the forming step of the source region and the drain region comprises: adding a layer of material to a substrate of the integrated circuit to make the source region The substrate with the bungee area is lifted off _ ribs correction replacement page. Early t sheng. The method of the corpus callosum is as follows: the method described in claim 35 of the patent, further comprising: forming the step _:f slot 2 to make the nanocrystal structure In the groove. The method of forming a nano-structure of a ruthenium-electric structure, such as the method described in Item 35, wherein the nanocrystal, the method of claim 35, wherein The limb, 0耩 stores multiple bits. The following method: the method described in Item 35 of the patent 干 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' The crystal structure is separated. 1364.112 li:^P -1 1 1 ^ 1900 2270 2250 1912 Figure 22F 1364112 /r&gt; 22G 22H picture Figure 221