TWI506769B - Silicon on insulator and thin film transistor bandgap engineered split gate memory - Google Patents

Description

Insulation layer coating and thin film transistor energy gap engineering separation gate memory [Reference documents for related applications]

The present invention is a continuation of U.S. Patent No. 11/ 324, 594, filed on Jan. 31, 2007, which is incorporated herein by reference. U.S. Patent Application Serial No. 60/640, 229, filed on Jan. 3, 2005, and U.S. Patent Application Serial No. 60/689,237, filed Jan. U.S. Patent Application Serial No. 60/689,231, filed on June 10, 2005, and U.S. Patent Application Serial No. 60/689,314, filed on Jun. As a reference for cooperation.

The present invention is a continuation-in-part of U.S. Patent No. 11/425,959, the priority of which is hereby incorporated by reference in its entire entire entire entire entire entire entire entire entire entire entire content As a reference.

The present invention is a continuation-in-part of U.S. Patent No. 11/549,520, the priority of which is hereby incorporated by reference in its entire entire entire entire entire entire entire entire entire entire entire content As a reference.

The priority of the present application is based on U.S. Patent No. 60/980,788 filed on Oct. 18, 2007, and U.S. Patent Application Serial No. 61/018,589, filed on Jan. As a reference.

The present invention relates to an integrated circuit technology including an integrated circuit memory device having a novel structure.

Non-volatile memory (NVM) refers to a semiconductor memory that can still store data continuously if the power supply to the component containing the NVM cell is removed. NVM includes Mask Read Only Memory (Mask ROM), Programmable Read Only Memory (PROM), Erasable Programmable Read Only Memory (EPROM), and Electrically Erasable Programmable Read Only Memory (EEPROM) ) and flash memory. Non-volatile memory systems are widely used in the semiconductor industry and are a type of memory that prevents program data from being lost. Typically, non-volatile memory can be programmed, read, and/or erased according to the end-use requirements of the component, and the stylized data can be stored for long periods of time.

In general, non-volatile memory elements may have a variety of different designs. An example of an NVM cell design is generally referred to as a germanium-oxide-nitride-oxide-germanium (SONOS) component that can use a thin tunnel oxide layer to allow for hole tunneling erase operations. Although this design may have a good erase rate, this data is poorly preserved, in part because direct tunneling can be induced under a low-intensity electric field, which may be in a memory. The component exists during the save state.

Another NVM design is a nitride charge storage memory that utilizes a thick tunneling oxide layer to prevent loss of charge during storage. However, a thick tunnel oxide layer may reduce the channel erase speed. Therefore, the tunneling thermoelectric hole (BTBTHH) erasing method between the tape and the tape can be Used to inject holes to offset electrons. However, this BTBTHH erasure method may induce certain reliability issues. For example, the characteristics of nitride charge storage memory elements using the BTBTHH erase method may degrade after many sub-programs/erasing of the ring.

In addition, techniques for stacking array memory arrays on a single integrated circuit have been developed to meet the demand for high density non-volatile memory. Therefore, for non-volatile memory designs and arrays that can be operated multiple times (program/erase/read) and have improved data retention performance and faster operation speed, and are also applicable to and implemented in thin film structures and stacked arrays, There is considerable demand in this area.

The present invention relates to a matte-free thin film memory cell formed on an insulating layer-covered substrate and a similar insulating structure, and with respect to the stacked free-standing memory cells. An integrated circuit memory device is described which comprises a semiconductor body formed on an insulating layer, such as on an insulating layer, and a plurality of gates, which are serially serially formed in the semiconductor body Above, the plurality of gates comprise a first gate between the series sequence and a last gate between the series series, and have an insulating member, the insulating member separating the gates in the series sequence and the series sequence An adjacent gate; and a charge storage structure on the semiconductor body, the charge storage structure comprising a dielectric charge trap located under at least two gates of the plurality of gates in the series sequence, the charge storage The structure includes a tunneling dielectric structure disposed on the semiconductor body, a charge storage layer disposed on the tunnel dielectric structure, and an insulating layer disposed on the charge storage layer. Where the semiconductor main system is included in the string A continuous, multi-gate channel region below the plurality of gates within the sequence. This multi-gate channel region may be of the n-type or p-type conductivity type.

An embodiment of the present invention includes a plurality of memory cells including: a semiconductor substrate having a source region and a drain region disposed under the substrate and separated by a channel region; a tunneling dielectric structure, It is placed on the channel region, the tunneling dielectric structure has a hole tunneling barrier height at the interface with the semiconductor body, and a hole tunneling barrier height at a distance away from the interface is less than The hole tunneling barrier height at the interface. A tunneling dielectric layer comprising a multilayer structure comprising a layer in contact with the semiconductor body and at least one layer having a hole tunneling barrier height less than a hole tunneling barrier of the layer in contact with the semiconductor body height. a charge storage layer disposed on the tunnel dielectric structure; an insulating layer disposed on the charge storage layer; and a gate electrode disposed on the insulating layer.

Another embodiment of the invention includes a memory cell as an alignment with a junctionless embodiment comprising a semiconductor substrate having a source disposed beneath the surface of the substrate and separated by a channel region a polar region and a drain region; a dielectric multilayer tunneling structure disposed on the channel region, the dielectric multilayer tunneling structure comprising at least one layer having a hole tunneling barrier height less than the semiconductor substrate The height of the hole of the contact layer; a charge storage layer disposed on the dielectric multilayer tunneling structure; an insulating layer disposed on the charge storage layer; and a gate electrode Place on this insulation layer.

In some preferred embodiments, the layer providing a small hole tunneling barrier height may contain certain materials such as tantalum nitride (Si ₃ N ₄ ) or hafnium oxide (HfO ₂ ). In some preferred embodiments of the invention, the memory cell comprises a tunneling dielectric structure having a plurality of layers, such as a stacked three-layer structure of dielectric yttrium-niobium nitride and yttrium oxide (ONO). Such tunneling dielectric structures provide a SONONOS (矽-oxide-nitride-oxide-nitride-oxide-germanium) or a superlattice SONONOS design.

In some preferred embodiments of the invention, the tunneling dielectric structure can comprise at least two dielectric layers each having a thickness of about 4 nanometers. Additionally, in some preferred embodiments of the invention, the gate electrode comprises a material having a work function value that is greater than a work function value of the N+ polysilicon.

In some preferred embodiments of the present invention, the tunneling dielectric structure may comprise a layer comprising a material having a small hole tunneling barrier height, wherein the material is present in the layer with a concentration gradient, and The concentration of this material is a maximum in this layer.

In accordance with one or more embodiments described above, the present invention also encompasses a non-volatile memory element comprising a plurality of memory cells (i.e., an array). As used herein, a "plural" means two or more. In accordance with the present invention, the operational characteristics of the memory element are considerably improved, including increased erase speed, improved charge retention, and greater operating space.

The invention also encompasses methods of operating a non-volatile memory cell and array. The method of operation according to the present invention includes resizing the memory element by using a self-convergence method to limit the Vt distribution of the memory element; injecting +EN to program at least one memory element; and applying a voltage To read at least one memory component, wherein the voltage is between one of the erased state values and a stylized state value. As used herein, the term "restriction" refers to the reduction of the distribution of this threshold voltage in a number of memory cells within an array. In general, the threshold voltage distribution is "shrinked" by a threshold voltage of many memory cells within a narrow range, so the operation of the array is improved and superior to conventional designs. For example, in some preferred embodiments, such as a NAND array, an embodiment according to one or more of the present invention includes a memory cell, a "limited" The boundary voltage distribution represents that the threshold voltage of the various different memory cells is in the range of 0.5V. In other array architectures employing memory cells, in accordance with the present invention, the threshold voltage distribution of this "restriction" may have a range from an upper limit to a lower limit of about 1.0V.

An operation method according to an embodiment of the present invention includes operating an array by applying a self-convergent reset/erase voltage to a substrate to be reset/erased and a gate electrode of each memory cell, according to the present invention Invented; staging at least a plurality of memory cells; and reading at least one memory cell by applying a voltage between the erased state value and a stylized state value of the memory component to the memory component.

The invention also includes a method of forming a memory cell, comprising: providing a semiconductor substrate having a source and a drain region formed under the surface of the substrate and separated by a channel region; forming a tunneling The dielectric structure is formed on the channel region, wherein the tunneling dielectric structure comprises forming at least two dielectric layers, wherein one of the at least two dielectric layers has a small hole tunneling barrier height, which is smaller than other dielectric layers The hole of the electrical layer penetrates the energy barrier height; a charge storage layer is formed on the tunnel dielectric structure; an insulating layer is formed on the charge storage layer; and a gate electrode is formed on the insulating layer.

According to an embodiment of the junctionless technique, a semiconductor structure includes a plurality of first semiconductor body regions on an insulating layer overlying substrate, and the plurality of first semiconductor body regions are characterized by having a first doped state A concentration. A first select line and a second select line are overlaid and substantially perpendicular to the first semiconductor body region. The plurality of first word lines are between the first selection line and the second selection line, and each of the plurality of first word lines covers a channel region on each of the first semiconductor body regions and is substantially perpendicular to the first semiconductor body region . a first pass energy barrier, a first charge storage layer, and a first dielectric layer located at each A first word line is between a corresponding channel region in each of the first semiconductor body regions. At least one first region is located within each of the first semiconductor body regions. The at least one first region is adjacent to the first selection line or the second selection line. The at least one first region is characterized by a second doped state. One or more second regions are located in each of the first semiconductor body regions, and each of the second regions is located between two adjacent channel regions, and the one or more second regions are characterized by having a first doping A second concentration of the state, wherein the second region is a junction.

According to an embodiment of the SOI technique, the semiconductor structure further includes a plurality of trench structures adjacent to and parallel to the first semiconductor body region, each trench structure separating two adjacent first semiconductor body regions.

According to an embodiment of the SOI technology, the first tunneling barrier comprises a first oxide layer, a nitride layer and a second oxide layer.

According to an embodiment of the SOI technology, the first tunneling barrier, the first charge storage layer, and the first dielectric layer are an ONONO structure.

According to one embodiment of the SOI technique, the SOI structure includes an oxide layer on the substrate and below the first semiconductor body region.

According to an embodiment of the SOI technique, the first region extends below the at least one first selection line and the second selection line.

According to an embodiment of the SOI technology, the semiconductor structure is stacked and provides a plurality of layers of the junctionless memory cells, and further comprising: a second insulating layer on the first word line. A plurality of second semiconductor body regions having a third concentration of the first doped state overlying the second dielectric layer. The plurality of second word lines are located between a third select line and a fourth select line, and the second word line, the third select line and the fourth select line are substantially perpendicular to the second semiconductor body region. a second tunneling barrier, a second charge storage layer and a second dielectric layer Located between the second word line and the second semiconductor body region. The second semiconductor body region includes at least one third region adjacent to the third select line and the fourth select line. The at least one third region is characterized by a second doped state. The second semiconductor body region also includes at least one fourth region between two adjacent second word lines. The fourth region is characterized by a fourth concentration of the first doped state. The size of the first region is greater than the size of the third region.

In the case of the junctionless embodiment of the stack, in particular, the bottom layer can be implemented on an SOI substrate or directly in a semiconductor substrate region without an overlapping insulating layer.

In accordance with another embodiment of the technology disclosed herein, a method for forming a semiconductor structure includes forming a plurality of first semiconductor body regions having a first concentration of a first doped state implanted on a substrate . A first selection line, a second selection line, and a plurality of first word lines are formed and substantially perpendicular to the first semiconductor body region, and the plurality of first word lines are arranged on the first selection line and the second selection Between the lines. A first tunneling energy barrier, a first charge storage layer and a first dielectric layer are formed between the first semiconductor body region and the plurality of first word lines. The first dielectric sidewall is formed on one sidewall of the first select line and one sidewall of the second select line to form a first dielectric material between the two adjacent first word lines. The first source/drain junction has a second doped state, and is formed adjacent to the first selection line and the second selection line by using the first dielectric sidewall as an implantation mask. A region is formed between two adjacent first word lines. The region between the adjacent first word lines has a second concentration of the first doped state, wherein the region between the two adjacent first word lines is substantially free of junctions.

According to one embodiment of some applications, a method is provided herein, It is used to operate a semiconductor structure. The semiconductor structure includes: a plurality of semiconductor body regions on a substrate; a plurality of word lines between a first selection line and a second selection line, the word line including a selected word line and a plurality of unselected a word line, a word line, a first selection line, and a second selection line, which are substantially perpendicular to the semiconductor body region; and a tunneling barrier, a charge storage layer, and a dielectric layer are located at the word line and the semiconductor Between the body regions, wherein the semiconductor body region includes at least one first region adjacent to the first selection line and the second selection line, and a second region between the two adjacent word lines, wherein the first region There is a doping concentration that is higher than the doping concentration in the second region, and wherein at least one of the second regions is a dead junction. The method includes applying a first voltage to a first select line and a second select line; applying a second voltage to the word line, the first voltage is higher than the second voltage; and applying a third voltage to the semiconductor body region Resetting the semiconductor structure, the third voltage system is higher than the second voltage

As used herein, the term "small hole tunneling barrier height" generally refers to the value of the hole tunneling barrier height less than a ceria/矽 interface. In addition, in a preferred case, a small hole tunneling barrier height is less than about 4.5 eV. In a better case, a small hole tunneling energy barrier is less than or equal to 1.9 eV.

One of the junctionless TFT NAND elements for stackable multi-layered three-dimensional flash memory is proposed. The TFT NAND does not have a diffusion junction (eg, an N+ doped junction) within the memory array. The diffusion junction is fabricated only outside of the array selection transistors BLT and SLT.

When the space between the word lines is small (for example, a space of 75 nanometers), an inversion layer will be induced by the word line edge electric field. This junctionless TFT NAND structure avoids this junction being broken down after a repeated thermal budget. Short channel effects can also be suppressed. Therefore, this technology allows TFT The NAND structure has a multi-layer stack that achieves a very high density.

Three-dimensional flash memory has recently attracted widespread attention. The three-dimensional multilayer stack of memory allows for higher densities than conventional single-layer memory components.

Conventional doped junctions (e.g., N+ doped junctions) have considerable lateral diffusion after heat treatment. This lateral diffusion is very severe for very short channel elements. For a three-dimensional flash TFT NAND device with multiple layers of stacking, this short channel effect will become more severe. Because the bottom layer is subject to a larger thermal budget, lateral diffusion of the junction causes severe breakdown, which will severely degrade the performance of the short channel effect.

This jointless NAND described herein allows multilayer stacks and junctions to diffuse only at this array boundary, which provides a larger thermal budget processing range to avoid breakdown.

The difference from the conventional component is that the junction is formed before the sidewall, and a method for manufacturing the junctionless TFT NAND includes forming the junction after the sidewall between the word lines is formed. . The sidewall sub-systems between the individual word lines are completely filled and unnotched, which is therefore a small spacing of the TFT NAND array. Thus, the junction IMP is blocked by the sidewalls within the memory array and the junctions are formed outside the array.

In another method, an additional mask is employed that covers the word lines and BLTs and SLTs, and the interface IMP is executed.

The simulation results show that an inversion layer can be induced under the sidewalls due to the electric field at the edge of the high electric field on the word line, so there is no need to fabricate n+ doped regions.

The components described above also include p-channel TFT NAND, where n-well and P+ junctions are used.

The invention and its presently preferred embodiments are described in detail herein by reference to the accompanying drawings. Reference numerals, which may be the same or similar, are used in this illustration and this description is intended to indicate the same or similar parts. It should be noted that the non-curve portion is a rather simplified illustration and does not have an accurate ruler. Reference is made to the convenience and conciseness of the words, for example, to indicate the top, bottom, left, right, top, bottom, top, bottom, bottom, and thereafter of the additional illustrations. Front section. The wording of the directional term is used to describe the following description of the invention, and should not be construed as limiting the scope of the invention in any way, which may not be explicitly set within the scope of the appended claims. Although the present invention has been described with reference to certain embodiments, it is understood that these embodiments are disclosed by way of example and not limitation. It should be understood and appreciated that the process steps and structures described herein do not cover a complete process for making a complete integrated circuit. The present invention can be applied to a variety of integrated circuit process technologies that have been known or developed for use in the art.

In accordance with the present invention, memory cells can overcome some of the issues of reliability of SONOS and nitride charge storage memory elements. For example, the memory cell structure, in accordance with the present invention, allows for a fast FN channel erase method while still having a good charge retention structure. In accordance with the present invention, various embodiments of the memory cell can also ease the reliance on the BTBTHH erasing method, thereby avoiding degradation of the component after multiple stylization/erasing of the ankle ring.

In an embodiment where the tunneling dielectric structure is a multilayer structure, an example may employ an ultra-thin tunneling dielectric layer or an ultra-thin oxide layer to match the small hole tunneling barrier height, which provides better stress relief. . According to the present invention, the non-volatile memory cells may have only a slight deterioration after being repeatedly programmed/erased.

Memory cells in accordance with the present invention may employ an n-channel or a p-channel design, such as shown in Figures 1a and 1b. 1a depicts a cross-sectional illustration of an n-channel memory cell 100, in accordance with an embodiment of the present invention. The memory cell comprises a p-type substrate 101 comprising at least two n-doped regions 102 & 104, wherein each doped region 102 & 104 can function as a source or a drain, depending on the applied voltage. As shown in FIG. 1a, for reference purposes, doped region 102 can serve as the source and doped region 104 can serve as the drain. The substrate 101 further includes a channel region 106 between the two n-doped regions. Above the channel region 106, the surface of the substrate 101 is a tunneling dielectric structure 120. In some preferred embodiments, the tunneling dielectric structure 120 can comprise a three-layer thin film ONO structure in which a small hole tunneling barrier high nitride layer 124 is sandwiched between a thin low oxide layer 122. And a thin high oxide layer 126. The memory cell 100 further includes a charge trapping (or charge storage) layer 130, preferably tantalum nitride, over the tunnel dielectric structure 120, and an insulating layer placed over the charge trapping layer 130. Layer 140, which preferably comprises a barrier oxide. A gate 150 is placed over the insulating layer 140.

Figure 1b depicts a cross-sectional view of a p-channel memory cell 200 in accordance with an embodiment of the present invention. The memory cell comprises an n-type substrate 201 comprising at least two p-doped regions 202 & 204, wherein each doped region 202 & 204 may function as a source or drain. The substrate 201 further includes a channel region 206 between the two p-doped regions. The p-channel memory cell 200 also includes a tunneling dielectric structure 220 comprising a three-layer thin ONO structure, wherein a small hole tunneling barrier is formed by a highly nitrided layer 224 sandwiched between a thin low oxide layer 222. And a thin high oxide layer 226, a charge trapping (or charge storage) layer 230, an insulating layer 240, and a gate 250.

Therefore, for example, as described in FIGS. 1a and 1b, the memory cell according to the present invention may comprise: a multilayer thin film tunneling dielectric structure comprising a first tantalum oxide layer O1 and a first tantalum nitride layer N1 And a second hafnium oxide layer O2; a charge storage layer, such as a second tantalum nitride layer N2; and an insulating layer, such as a third hafnium oxide layer O3, on a substrate, such as a semiconductor substrate (eg, a base). The tunneling dielectric structure allows the hole to tunnel from the substrate to the charge storage layer when one of the memory elements is erased/reset. Preferably, the tunneling dielectric structure of a non-volatile memory cell of the present invention has a negligible charge trapping efficiency and, more preferably, does not capture charge at all during memory operation.

Materials of the charge storage layer, such as a tantalum nitride layer, HfO ₂ and Al ₂ O _{3 ,} can also be used as a material for the small hole tunneling barrier level in a tunneling dielectric structure. In certain preferred embodiments of the invention, an effective charge storage material, such as tantalum nitride, can be used as one of the charge storage layers of the memory element. A barrier oxide that prevents charge loss and acts as an insulating layer, such as a third layer of yttria O3. The memory cell also includes a gate or gate electrode, such as a polysilicon gate, over the insulating layer in accordance with the present invention. The tunneling dielectric structure, the charge storage layer, the insulating layer and the gate may be formed on a portion of the at least one channel region of the substrate, the channel region being defined by a source region and a drain region Somewhere in between.

A memory cell in accordance with various embodiments of the present invention includes a tunneling dielectric structure that provides approximately at a negative gate bias (Vg), such as a Vg of about -10 to -20V. Fast FN erase speed of 10msec. On the other hand, this charge retention capability is still maintained and, in some instances, is superior to many conventional SONOS components. Memory cells can also be used in accordance with the present invention to avoid band-to-band thermal hole erase operations, which are commonly used for nitride charge storage memory elements. Avoid bringing a hot hole wipe In addition to the operation, the damage caused by the thermoelectric holes can be largely eliminated, and the avoidance of this damage is what I want.

Referring to FIG. 2, an experimental measurement of a threshold voltage of a tunneling dielectric structure according to an embodiment of the present invention shows that an ultra-thin O1/N1/O2 structure can have a negligible capture efficiency, which can be Verification by the unchanging threshold voltage value under successive program pulses. In the example tested in Figure 2, the O1/N1/O2 layers have a thickness of 30/30/35 angstroms, respectively. As shown in Figure 2, this threshold voltage Vt is stably maintained when multiple programming is performed using many different program methods, namely -FN stylization, +FN stylization, and channel hot electron (CHE) stylization. At about 1.9 volts. Therefore, this ultrathin O1/N1/O2 film may be used as a tunneling dielectric structure for energy gap engineering, which is negligible because of charge trapping in a structure having a nitride layer of 30 Å or less. of. The results of various charge injection methods, including CHE, +FN, and -FN, all indicate negligible hole capture. The fabrication process or component structure can be designed to minimize interface capture, so the O1/N1 and N1/O2 interfaces are not activated.

Figure 3 depicts a memory cell erase characteristic wherein the memory cell has a SONONOS design in accordance with one embodiment of the present invention. The memory cell of this embodiment in FIG. 3 includes an n-MOSFET design having an ONO tunneling dielectric structure having a thickness of 15/20/18 angstroms, respectively. The memory cell of the present invention comprises a tantalum nitride charge storage layer having a thickness of about 70 angstroms, an insulating ruthenium oxide having a thickness of about 90 angstroms, and a gate comprising any suitable conductive material, for example , n-doped polysilicon. Referring to Figure 3, a fast FN erasure may be achieved, for example, within 10 milliseconds, and an excellent self-converging erase characteristic may be obtained.

Figure 4 depicts an embodiment in accordance with one embodiment of a memory cell The charge retention characteristics of the SONONOS element, wherein the memory cell is described in Figure 3 in accordance with the present invention. As shown, this preservation feature is superior to conventional SONOS components and may be superior to multiple orders of magnitude if compared by intensity.

Figures 5a and 5b are energy band diagrams depicting the possible effects of tunneling a dielectric structure using at least one of the high level tunneling barrier layers. The tunneling dielectric structure, in this example, is an O1/N1/O2 three-layer, and the energy band diagram is shown in Figure 5a. Direct tunneling, as indicated by the dotted arrow, can be eliminated under low electric fields, thus providing good charge retention in the stored state. On the other hand, the energy band diagram under a high electric field, as shown in Fig. 5b, can reduce the energy barrier effect of N1 and O2, so direct tunneling through O1 may occur. A tunneling dielectric structure having at least one small hole tunneling barrier layer allows for efficient FN erasing operations.

Figures 5c and 5d depict another set of energy band diagrams in an example. In one example, for a preferred band compensation condition, the thickness of this N1 may be greater than O1. The energy band diagram of this valence band is depicted on the same electric field E ₀₁ = 14 MV/cm. This tunneling probability is related to this shaded area according to the WKB approximation. For some examples, for band thickness N1 = O1, this band compensation does not completely obscure the O2 barrier. On the other hand, for the case of the thickness N1>O1, this band compensation can more easily mask O1. Therefore, for the case of the thickness N1>O1, the tunnel tunneling current may be larger at the same voltage of O1.

An experiment of measuring and simulating hole tunneling currents, as shown in FIG. 6, further describes tunneling through a tunneling dielectric structure in accordance with certain embodiments of the present invention. For example, the tunneling current flowing through this O1/N1/O2 hole may fall between the tunneling current flowing through an ultra-thin oxide and a thick oxide. In an embodiment, a high electric field Under the hole, the tunneling current flowing through O1/N1/O2 may flow through a thin oxide layer. However, at a low electric field, this direct tunneling can be suppressed. As shown in Fig. 6, the tunneling current can be detected through a thin oxide layer even at a low electric field strength of only 1 mV/cm. Even at relatively high electric fields, such as 11-13 mV/cm, the tunneling current through a thick oxide layer can be ignored. However, this tunneling current through an ONO tunneling dielectric structure approaches a thin oxide layer at high electric field strengths. In Fig. 6, the large leakage current induced by tunneling through an ultra-thin oxide in a low electric field can be seen in the A region of the figure. In Fig. 6, the tunneling current flowing through the O1/N1/O2 tunneling dielectric structure under high electric field intensity can be seen in the B region in this figure. In Fig. 6, the tunneling current flowing through an O1/N1/O2 tunneling dielectric structure and a thick oxide under a low electric field can be seen in the C region in this figure.

The memory cell design in accordance with the present invention can be employed in a variety of different memory configurations including, but not limited to, NOR and/or NAND type flash memory.

As described above, a tunneling dielectric layer may comprise more than two layers and includes a layer that may provide a small hole tunneling barrier. In one example, the layer providing a small hole tunneling barrier height may contain tantalum nitride. This layer may be sandwiched between two layers of ruthenium oxide, so that if a tantalum nitride is used for this intermediate layer, an O/N/O tunneling dielectric structure is formed. In certain preferred embodiments, the bottom layer can have a thickness of about 2 nanometers or less. The middle and top layers of the tunneling dielectric structure may have a thickness of about 1 to 3 nanometers. In an exemplary component, a three-layer structure may have a bottom layer, such as a hafnium oxide layer, having a thickness of between about 10 and 20 angstroms. a middle layer, such as a tantalum nitride layer having a thickness of 10 to 30 angstroms, and a top layer, such as another layer of tantalum oxide, having 10 layers To a thickness of 35 angstroms. In a particular example, an O/N/O three-layer structure may be employed, wherein the structure has a 15 angstrom yttrium oxide underlayer, a 20 angstrom tantalum nitride layer, and a 18 angstrom yttrium oxide top layer. In a particular example, an O1/N1/O2 three-layer structure may be employed, wherein the structure has a 13 angstrom yttrium oxide layer, a 25 angstrom layer of tantalum nitride, and a 25 angstrom layer of yttrium oxide.

In another example, a thin O/N/O three-layer structure shows negligible charge trapping. Theoretical energy band diagrams and tunneling current analysis, such as those shown in Figures 5a, 5b, and 6 can be used to infer a tunneling dielectric structure, for example having a thickness of about 3 nm or less. One of the O1/N1/O2 structures can suppress the tunneling of the hole directly under low electric field in the state of preservation. At the same time, it can also allow sufficient hole tunneling under a high electric field. The reason may be that the band compensation can effectively shield the tunneling energy barriers of N1 and O2. Therefore, the proposed component may provide a fast hole tunneling erase without the preservation of conventional SONOS components. Experimental analysis shows excellent endurance and preservation characteristics of memory cells in accordance with various examples of the present invention.

In some preferred embodiments, the tunneling dielectric structure comprises at least one intermediate layer and two adjacent layers on both sides of the middle layer, wherein each middle layer and two adjacent layers comprise a first material and a second material The second material has a valence band energy level greater than the valence band energy level of the first material and the second material has a conduction band energy level that is less than the energy level of the conduction band of the first material. And wherein the concentration of the second material in the middle layer is greater than the concentration of the two adjacent layers, and the concentration of the first material in the middle layer is less than the concentration of the two adjacent layers. Preferably, in one embodiment of the invention, the dielectric structure is tunneled, the first material comprising oxygen and/or oxygenates and the second material comprising nitrogen and/or nitrogen containing compounds. For example, the first material may comprise an oxide such as hafnium oxide, and the second material may comprise a nitride such as Si ₃ N ₄ or Si _x O _y N _z .

A tunneling dielectric layer in accordance with the purposes of the present invention may comprise three or more layers, all of which may contain similar elements (e.g., helium, nitrogen, and oxygen), requiring only a small hole tunneling barrier material concentration, This middle layer is higher than the two adjacent layers.

According to some dielectric structures of the previous embodiments of the present invention, the second material may be present in the intermediate layer, wherein the material is present in a concentration gradient, and the concentration of the second material in the middle layer is from an adjacent layer/middle layer The interface increases and there is a maximum concentration at one of the depths in the middle layer, and decreases from a depth having a maximum concentration to a lower concentration at another adjacent/middle layer interface. The increase and decrease in this concentration is preferably progressive in the preferred case.

In still another embodiment of the present invention, the tunneling dielectric structure includes at least one middle layer and two adjacent layers on two sides of the middle layer, wherein the two adjacent layers comprise a first material and the middle layer comprises a second a material, wherein the second material has a valence band energy level greater than a valence band energy level of the first material, and the second material has a conduction band energy level that is less than a conduction band energy level of the first material; And wherein the second material is present in the middle layer and has a concentration gradient, wherein the concentration of the second material in the middle layer is increased from an adjacent layer/middle layer interface to a maximum concentration in the depth of one of the middle layers, and has The depth of the maximum concentration is reduced to a lower concentration at this other adjacent layer/intermediate layer interface. The increase and decrease of this concentration is, in the preferred case, a gradual occurrence. Preferably, in accordance with this embodiment of the invention, in a tunneling dielectric structure, the first material comprises oxygen and/or an oxide and the second material comprises nitrogen and/or a nitride. For example, the first material may comprise an oxide, such as hafnium oxide, and the second material may comprise a nitride, such as Si ₃ N ₄ or Si _x O _y N _z .

For example, in some embodiments of the invention, wherein the tunneling The electrical layer comprises a three-layer ONO structure, and the layer of the underlying oxide and the top oxide layer may comprise ruthenium oxide, and the intermediate nitride layer may comprise, for example, ruthenium oxynitride and tantalum nitride, wherein tantalum nitride The concentration (i.e., the material having a small hole tunneling barrier height in both) is not constant in this layer, but instead reaches a maximum at a certain depth between the nitride layers having the Sanmingye structure.

The material in the middle layer has a small hole tunneling barrier height, and the exact position of the depth to the maximum concentration has no decisive influence, and it only needs to be located within a concentration gradient and is tunneled into the dielectric layer. A certain depth in the middle layer reaches its maximum concentration.

The concentration gradient of this material with a small hole tunneling barrier height can help to enhance various characteristics of the non-volatile memory component, especially for components having a SONONOS or SOONOS-like structure. For example, charge drain in the saved state can be reduced, tunneling under high electric fields can be improved, and where possible, charge trapping of the tunneling dielectric layer can be avoided.

According to the purpose of the present invention, the energy band diagram of a tunneling dielectric layer can be adjusted (energy gap engineering), so that the valence band energy level and the conduction band energy level of the middle layer do not have a fixed value, but have The advantage of the material concentration of the small hole tunneling level is changed by the thickness of this layer. Referring to Figure 5e, in accordance with the purpose of the present invention, an ONO three-layer structure of a tunneling dielectric layer of a bandgap process is represented by a band diagram. This middle layer (layer 2) contains tantalum nitride. The additional layers (the first layer and the third layer) contain cerium oxide. The concentration of tantalum nitride in the second layer is floating, so that the valence band energy level and the conduction band energy level reach a maximum and a minimum at the depth at which the tantalum nitride concentration reaches the highest in the second layer. The three possible zirconium nitride concentration gradients are shown in Figure 5e, which is a broken line showing the variable valence band energy levels and conduction band energy levels caused by the concentration gradient. As shown in Figure 5e As shown, the circles on the dashed lines indicate the three maximum values of tantalum nitride concentration in the second layer, the minimum valence band energy level and the highest conduction band energy level occurring at the maximum concentration of tantalum nitride.

In accordance with embodiments of the present invention, a multilayer tunneling dielectric structure can be fabricated in a number of different ways. For example, a first layer (cerium oxide or hafnium oxynitride layer) can be formed by any conventional oxidation method including, but not limited to, thermal oxidation, free radical (ISSG) oxidation, and plasma oxidation/nitridation, and Chemical vapor deposition process. a middle layer having a concentration gradient of SiN which may then be formed, for example, by a chemical vapor deposition process, or alternatively by plasma nitridation to form an excess of oxide or nitrogen at the top of the first layer. The oxide is processed. A third layer, the upper oxide layer, can then be formed, for example, by oxidation or chemical vapor deposition.

A charge storage layer can then be formed over the tunnel dielectric structure. In one example, a charge storage layer, which is about 5 to 10 nanometers, can be formed over the tunnel dielectric structure. In another example, a tantalum nitride layer, which is about 7 nanometers or thicker, can be used. The insulating layer on the charge storage layer can be about 5 to 12 nm. For example, a ruthenium oxide layer, which is about 9 nm or more, can be used. And the ruthenium oxide layer can be formed by a heat treatment process for converting a portion of a nitride layer to form the ruthenium oxide layer. Any known or developed method for forming a plurality of layers of suitable materials as described herein can be used to deposit or form a tunneling dielectric layer, a charge storage layer, and/or an insulating layer. Suitable methods include, for example, a thermal growth method and a chemical vapor deposition method.

In one example, a thermal conversion process may form a high density or high concentration interface trap that enhances the capture effect of a memory component. For example, when the gate flow ratio is H ₂ :O ₂ =1000:4000 sccm, the thermal conversion of the nitride can be induced at 1000 degrees Celsius.

In addition, because tantalum nitride usually has very small (about 1.9eV) electricity The hole energy barrier, under high electric field, is directly tunnelable for the hole. At the same time, the total thickness of a tunneling dielectric structure, such as an ONO structure, may avoid direct electron tunneling under low electric fields. In one example, this asymmetric behavior can provide a memory component that not only provides fast hole tunneling erase, but also reduces or eliminates charge loss during storage. An example component can be fabricated by a 0.12 micron nitride charge storage memory technology. Table 1 shows the structure and parameters of the components in an example. The proposed tunneling dielectric structure with an ultra-thin O/N/O may change the tunnel tunneling current. In one example, a thicker (7 nm) N2 layer may act as a charge trapping layer and an O3 (9 nm) layer as a barrier layer. Both N2 and O3 may be fabricated using nitride charge storage memory technology.

In some embodiments of the invention, a gate may comprise a material having a work function greater than a work function of the N+ polysilicon. In certain preferred embodiments of the invention, such a high work function gate material may comprise a metal such as platinum, rhodium, tungsten, and other precious metals. In the preferred case, the gate material in this embodiment has a work function greater than or equal to about 4.5 eV. In a better case, the gate material comprises a high work function metal such as platinum or rhodium. Additionally, preferred high work function materials include, but are not limited to, P+ polysilicon, and metal nitrides such as titanium nitride and tantalum nitride. In a more preferred embodiment of the invention, the gate material comprises platinum.

In accordance with an embodiment of the present invention, an exemplary component having a high work function gate material may also be fabricated by a 0.12 micron nitride charge storage memory technology. Table 2 shows the structure and parameters of the components in an example. The proposed tunneling dielectric structure with an ultra-thin O/N/O may change the tunnel tunneling current. In one example, a thicker (7 nm) N2 layer may act as a charge trapping layer and an O3 (9 nm) layer as a barrier layer. Both N2 and O3 may be fabricated using nitride charge storage memory technology.

Memory cells of embodiments having high work function gate materials in accordance with the present invention exhibit better erase characteristics relative to other embodiments. The high work function gate material suppresses the gate electron injection trapping layer. In some embodiments of the invention, wherein the memory cell comprises an N+ polysilicon gate, the hole tunneling to the charge trapping layer occurs simultaneously with the gate electron injection during erasing. This self-convergence erase effect results in a higher threshold voltage class in the erased state, but is not good for NAND applications. The memory cells of the high work function gate material embodiment in accordance with the present invention can be used in a variety of different types of memory applications, including, for example, NOR- and NAND-type memories. However, the memory cell of the embodiment of the high work function gate material according to the present invention is particularly suitable for NAND applications because it is not good to raise the threshold voltage in the erase/reset state for NAND applications. The memory cell of the embodiment of the high work function gate material according to the present invention can be erased by a tunneling method, wherein the preferred method is performed by a -FN erase operation.

An exemplary device having an ONO tunneling dielectric structure and an N+ polysilicon gate can be programmed by conventional SONOS or nitride charge storage memory methods and can be erased by tunnel FN tunneling. Figure 7a shows the erase characteristic of an exemplary SONONOS component, which in one example has an ONO tunneling dielectric structure. Referring to Figure 7a, a higher gate voltage results in a faster erase speed. Since the gate implant also becomes stronger and the resulting dynamic equilibrium point (which determines Vt) is also higher, it also has a higher saturation Vt. Its representation In the right half of the figure, when the threshold voltage reaches a minimum of about 3 to 5 volts, the minimum value depends on the erase gate voltage. By a transient analysis method, the curve of the 7th graph is differentiated, and the tunnel tunneling current can be extracted. The current of the hole taken from the measurement of Fig. 7a is described in Fig. 6 above. For ease of comparison, the simulated hole tunneling current is approximated by WKB. This experimental structure is consistent with the predicted results. Through the tunneling current of this O1/N1/O2 stack, under high electric field, it is close to the ultra-thin O1 and is turned off under a low electric field.

A memory cell according to some embodiments of the present invention has a high work function gate material, wherein the high work function gate suppresses gate electron injection, and the threshold voltage of the element can be changed in an erased or reset state Smaller, and even negative, depending on the erase time. According to one embodiment of the present invention, the threshold voltage value of a memory device, wherein the gate electrode comprises platinum and the tunneling dielectric layer comprises a 15/20/18 angstrom ONO structure, which is shown in Figure 7b. As shown in Figure 7b, the flat band voltage (which is related to the threshold voltage) of the component can be set lower than a small gate voltage (-18V) during a-FN operation. -3V. The corresponding capacitance versus gate voltage values for this component are shown in Figure 7c.

Moreover, the storage characteristics of the memory elements of the embodiment having the high work function gate material in accordance with the present invention are improved. a storage element of a memory device, wherein the element has a platinum gate, which is shown in Figure 7d, wherein the capacitance is depicted as a function of gate voltage, wherein the image is erased and programmed, each Draw 30 minutes after the operation and 2 hours later. The smallest pass can be observed.

Memory cells in accordance with various embodiments of the present invention can be operated in at least two different modes. For example CHE stylization, which has a reverse read (mode 1), can be used to implement a 2-bit/cell operation. In addition, low power + FN stylization (mode 2) can also be used as a 1-bit/cell Work. Both holes can use the same hole tunneling erase method. Mode 1 can be preferably used as a virtual ground array architecture for NOR type flash memory. Mode 2 can be preferably used as a NAND type flash memory.

In one example, Figure 8 shows that a virtual grounded array architecture NOR flash memory has excellent endurance in accordance with an embodiment of the present invention operating in mode 1. Such memory elements having a tunneling dielectric structure are not found to have erase degradation, which is a uniform channel erase method due to tunnel tunneling (Vg = -15V). This corresponding IV curve is also shown in Figure 9, which shows that this element still has small degradation after multiple P/E turns. In one example, it may be because the ultra-thin oxide/nitride layer has good stress relief properties. In addition, this memory component does not suffer from damage induced by hot electrons. The endurance of the NAND type flash memory according to one embodiment of the present invention in mode 2 is shown in Fig. 10. For a faster convergence erase time, a larger bias voltage (Vg = -16V) can be used. Excellent endurance can also be obtained from this example.

A charge retention mechanism for a SONONOS device according to an example of an embodiment of the present invention is shown in Fig. 4, in which there is only a charge loss of 60 mV after 100 hours. This saving feature is improved in size over traditional SONOS components by multiple orders of magnitude. The accelerated VG save test also shows that direct tunneling can be suppressed at this low electric field. Figure 11 depicts an example of an accelerated VG save test for one of the 10K P/E loop elements. This charge loss is still small after applying a -VG stress of 1000 seconds, indicating that the tunnel can be suppressed by direct tunneling under a small electric field.

Accordingly, the SONONOS design in the above example provides a fast tunneling wiper with excellent endurance. As described above, this design can be implemented in NOR and NAND type nitride storage flash memories. In addition, a memory array according to the present invention may comprise a plurality of Memory components with similar or different configurations.

In various arrays in accordance with embodiments of the present invention, memory cells in accordance with the present invention can be used in conventional nitride charge storage memories or SONOS components within a virtual ground array architecture. This reliability issue and the elimination of degradation can be solved or relieved by using FN hole tunneling instead of hot hole injection. Without limiting the scope of the invention, in accordance with the specific structure described below, various operational methods are described below to describe an exemplary NOR virtual ground array structure in accordance with the memory array of the present invention.

CHE or channel hot electron induced secondary hot electron injection (CHISEL) stylization and reverse reading can be used for 2-bit/cell memory arrays. And this erasing method may be a tunneling erase of a uniform channel FN hole. In an example, the array architecture can be a virtual ground array or a JTOX array. Referring to FIG. 12a-20, an O1/N1/O2 three-layer structure can be used as the tunneling dielectric structure, having an O1 layer having a thickness of less than 2 nm and a N1 having a thickness of about 3 nm or less and The O2 layer provides direct tunneling of the holes. Referring to Figures 12a-20, the N2 layer can be thicker than 5 nm to provide a high capture efficiency. An insulating layer, O3, may be a hafnium oxide layer formed by wet oxidation, such as a wet conversion top oxide (yttria) to provide a large trap density at the interface between O3 and N2. O3 may be about 6 nm or more to prevent charge loss from escape of the ruthenium oxide layer.

Figures 12a and 12b depict an example of a virtual grounded array architecture that cooperates with the memory cells described above, such as a memory cell having a three-layer ONO tunneling dielectric structure. In particular, Figure 12a depicts an equivalent circuit of a portion of a memory array, and Figure 12b depicts an example layout of one of the portions of the memory array.

In addition, Figure 13 depicts a schematic cross-sectional view of a number of interacting memory cells within the array. In an example, a buried diffusion (BD) region pair The source or drain region of the memory cell may be an N+ doped junction. This substrate can be a p-type substrate. In order to avoid possible collapse of the BDOX (oxide on BD) region during -FN erasure, a thick BDOX (>50 nm) can be used in an example.

Figures 14a and 14b depict a schematic diagram of a possible electronic "reset" for an exemplary virtual ground array that incorporates a 2-bit/cell memory cell with a tunneling dielectric layer design as described above. All of this component can be "reset" electronically before any further stylization/erasing of the ring is implemented. A reset process may ensure the consistency of the Vt of the memory cells within the same array and boost the Vt of the component to a clear erased state. For example, applying 1 second of Vg = -15V, as shown in Figure 14a, may have the effect of injecting some charge into one of the charge trapping layers of tantalum nitride to achieve a state of dynamic equilibrium. With this reset, even a non-uniformly charged memory cell may converge its Vt due to, for example, the plasma charging effect produced during its processing. Another method of generating a self-converging bias state is to provide a bias voltage between the gate and the substrate. For example, referring to Figure 14b, either Vg = -8 and P-type well = +7V can be applied.

15a and 15b depict a stylized overview of an exemplary virtual ground array in which the array is mated with a 2-bit/cell memory cell having one of the tunneling dielectric layers described above. Channel hot electron (CHE) stylization can be used to program this component. Bit-1 is programmed in Figure 15a, which is locally implanted into the junction edge of bit line N (BLN). For the Bit-2 stylization shown in Figure 15b, this electron is stored at the junction edge of BLN-1. A typical stylized voltage for a word line (WL) is approximately 6V to 12V. A typical stylized voltage for a bit line (BL) is about 3 to 7 volts, and this p-type well can be kept grounded.

Figures 16a and 16b depict virtual grounding for an example A readout schematic of the array, wherein the array is coupled to a 2-bit/cell memory cell having one of the tunneling dielectric layers described above. Referring to Figure 16a, for reading Bit-1, the BLN-1 system is applied to a suitable read voltage, such as 1.6V. Referring to Figure 16b, for reading bit-2, the BLN is applied to an appropriate read voltage, such as 1.6V. In one example, the read voltage can be in the range of 1 to 2 volts. The word line and p-type well can be kept in a grounded condition. However, other adjusted reading methods, such as an elevated -Vs reverse reading method, can also be implemented. For example, a boosted -Vs reverse read method may use Vd/Vs = 1.8/0.2 to read Bit-2, and Vd/Vs = 0.2/1.8 to read Bit-1.

Figures 14a and 14b also depict block erase diagrams for an example virtual ground array in which the array is mated and has one of the above described 2-bit/cell memory cells of the dielectric layer design. In one example, the block is erased by channel hole tunneling or can be applied to erase the memory cell in real time. An ONO tunneling dielectric layer in a memory cell, wherein the memory cell has this SONONOS structure, provides a fast erase which can be achieved at about 10 to 50 msec and has a self-converging channel erasing speed. In one example, a block erase operation state can be similar to a "reset" process. For example, referring to Figure 14a, a VG of approximately -15V is applied synchronously to this WL's and all of this BL's are floated or a block erase can be achieved. And this p-well can be kept grounded.

In addition, referring to Figure 14b, applying about -8V to this WL's and about +7V to this p-type well can also achieve a block erase. In some examples, a full block erase operation can be achieved within 100 msec or less, without any memory cells that have been erased or cannot be erased. The above component design can be used to provide a channel erase with excellent self-convergence characteristics.

Figure 17 depicts an example of using a SONONOS component. Wipe off the feature. An example of a SONONOS component can have an O1/N1/O2/N2/O3 thickness of about 15/20/18/70/90 angstroms, respectively, having an N+ polysilicon gate and a thermally-converted top oxide as O3. This erasing speed for various gate voltages is shown here. An erase operation on a memory cell having an O1/N1/O2 tunneling dielectric layer, wherein the layers have a thickness of about 15/20/18 angstroms, respectively, resulting in less than 50 msec, for example, 10 msec. , reducing the threshold voltage of about 2 volts, showing that the -FN erase voltage is between -15 and -17 volts. A higher gate voltage results in a faster erase speed.

However, this convergent Vt is also higher because the gate implant system becomes more active at higher gate voltages. To reduce gate injection, a P+ polysilicon gate or other metal gate with a high work function can be used instead as a gate material to reduce gate injection electrons during erasing.

Figure 18 depicts the enhancement of the characteristics caused by the use of SONONOS components within a virtual grounded array architecture. In some cases there is excellent endurance performance. This stylized state is Vg/Vd = 8.5/4.4V, 0.1 microseconds for Bit-1 and Vg/Vs = 8.5/4.6V, and 0.1 microseconds for Bit-2. The FN erase can use Vg = -15V of about 50 msec to erase the two bits simultaneously. Because the FN erasure is a self-converging uniform channel erase, memory cells that cannot be erased or erased usually do not exist. In some instances, the above mentioned components exhibit excellent endurance even without the use of a stylized/erase detection or stage algorithm.

Figures 19a and 19b depict the I-V characteristics of the P/E偱 ring in an example. This corresponding I-V curve is represented here by a log scale (Fig. 19a) or a linear ruler (Fig. 19b). In one example, a SONONOS component has only a very small degradation performance after multiple P/E loops, so the subcritical swing and the transconductance are almost equal after multiple loops. with. Such SONONOS components have excellent durability and are superior to nitride charge storage memory components. One possible reason is that the hot hole injection is not used. Additionally, an ultrathin oxide such as one above may have better pressure relief characteristics than a thick tunneling oxide.

Figure 20 depicts a schematic representation of a CHISEL stylization in an example. Another method of stylizing this component is to use CHISEL stylization, which uses a negative substrate bias to enhance impact ionization to increase hot carrier efficiency. The stylized current can also be reduced due to the bulk effect. A typical condition is depicted in this figure where the substrate is applied with a negative voltage (-2V) and the junction voltage is reduced to 3.5V. For traditional nitride charge storage memory components and techniques, CHISEL is stylized because it may inject more electrons near the center of the channel and cannot be applied. And the thermoelectric erasing does not effectively remove electrons near the central region of the channel of the conventional nitride charge storage memory element.

Figures 21a and 21b depict the design of a JTOX virtual ground array in an example. This JTOX virtual ground array provides an implementation of the use of SONONOS memory cells within a memory array. In one example, the difference between the JTOX structure and a virtual ground connection is that the components of the JTOX structure are isolated by the shallow trench isolation process. A typical layout example is depicted in Figure 21a. Figure 21b depicts a corresponding equivalent circuit that is equivalent to a circuit of a virtual ground array.

As described above, the memory cell structure according to the present invention is applicable to NOR and NAND type flash memories. Additional examples of memory array design and methods of operation thereof will be described below. The scope of the present invention is not limited to the specific structures described below, and various methods of operation of the memory array in accordance with the present invention are examples of NAND architectures as described below.

As described above, an n-channel SONONOS memory device having an ONO tunneling dielectric layer can be used for a memory device. Figure 22a And Figure 22b depicts an example of a NAND array architecture. Figures 23a and 23b depict a cross-sectional view of a memory array design in two different directions. In some examples, a method of operating a memory array can include +FN stylization, -FN erasing, and reading methods. In addition, circuit operation methods may also be included to avoid program disturb that may occur in some examples.

In addition to the single-block gate structure design, a separate gate array, such as a NAND array, uses a SONONOS component between two transistor gates, where the gate is placed at the source/turn It can also be used next to the polar area. In some examples, a separate gate design may be downsized to F = 30 nm or less. Still further, the component can be designed to have good reliability to reduce or eliminate this interactive floating gate coupling effect, or to have the advantages of both. As mentioned above, a SONONOS memory component provides excellent self-convergence or high-speed erase, which can be used for block erase operations and Vt distribution control. Further, a compact erase state distribution may be advantageous for multi-level applications (MLC).

With some designs for a memory array structure, this effective channel length (Leff) can be increased to reduce or eliminate short channel effects. Some examples can be designed to use a non-diffused junction, thus avoiding the challenge of providing shallow junctions or pocket implants during the manufacturing process of memory components.

Figure 1 depicts an example of a memory component having a SONONOS design. In addition, Table 1 above describes examples of thicknesses and materials used in different layers. In some examples, a P+ polysilicon gate can be used to provide a low saturation reset/erase Vt that can be achieved by reducing gate implant.

Figures 22a and 22b depict an example of a memory array, For example, a SONONOS-NAND array having a memory cell according to the embodiment described in Table 1 and having a diffusion junction. In one example, separate components can be separated by various isolation methods, such as shallow trench isolation (STI) or insulating layer overlay (SOI) techniques. Referring to Figure 22a, a memory array can include a plurality of bit lines, such as BL1 and BL2, and a plurality of word lines, such as WL1, WLN-1, and WLN. Additionally, the array can include source line transistors (or source line select transistors or SLTs) and bit line transistors (or bit line select transistors or BLTs). As described above, the memory cells in this array can be designed using a SONONOS, and the SLTs and BLTs can include n-type gold oxide half field effect transistors (NMOSFETs).

Figure 22b depicts a layout of an example of a memory array, such as a NAND array. Referring to Figure 22b, Lg is the channel length of the memory cell and Ls is the distance between each separated line of the memory element. In addition, W is the channel width of the memory cell, and Ws is the width of the isolated bit line or the isolation region between the source/drain regions.

Referring to Figures 22a and 22b, the memory elements can be connected in series and form a NAND array. For example, a string of memory elements can contain 16 or 32 memory elements, providing a string number of 16 or 32. This BLTs and SLTs can be used as a selection transistor to control the NAND corresponding to this string. In the first column, the gate dielectric layer of the BLTs and the SLTs may be a hafnium oxide layer, wherein the hafnium oxide layer does not include a tantalum nitride trap layer. The configuration of this type, although not necessary for various situations, avoids the Vt shift that BLTs and SLTs may have in this memory array operation under certain examples. In addition, the BLTs and SLTs can use a combination of ONONO layers as their gate dielectric layers.

In some cases, the gate voltage applied to BLTs and SLTs can be less than 10 volts, where this voltage may induce a smaller gate dry Disturb. The gate dielectric layers of the BLTs and SLTs can be charged or trapped, and an additional -Vg erase can be applied to the gates of the BLT or SLT to discharge their gate dielectric layers.

Referring to Figure 22a, each BLT may be coupled to a bit line (BL). In a normal column, a single bit line can be a metal line having the same or substantially the same pitch as the STI. Also, each SLT is connected to a source line (SL). This source line is parallel to this WL and is connected to this sense amplifier for read sensing. The source line can be a metal such as tungsten, or a polysilicon line, or an N+ diffusion doped line.

Figure 23a is a cross-sectional view depicting an exemplary memory array, such as a SONONOS-NAND memory array, with this profile along the length of the channel. A typical Lg and Ls system is roughly equal to F, which generally represents the critical dimension of a component (or node). This critical dimension may vary with process technology. For example, F = 50 nm represents the use of a 50 nm node. Figure 23b depicts a cross-sectional view of an exemplary memory array, such as a SONONOS-NAND memory array, along the width of the channel. Referring to Fig. 23b, the distance between the channel width directions is approximately equal to or slightly larger than the channel length direction. Therefore, the size of a memory cell is slightly equal to 4F ² /memory cells.

For the fabrication of an array of memory arrays, such as the array described above, the process can include the use of only two main masks or development processes, such as one for polysilicon (character lines) and the other for STI (bit lines). . In contrast, the manufacturing method of the NAND type floating gate element may require at least two polycrystalline processes and another polycrystalline ONO process. Therefore, the structure and process of the proposed component can be made simpler than the NAND type floating gate memory.

Referring to FIG. 23a, in an example, a space (Ls) between word lines (WLs) may be formed as having a shallow junction, such as an N+ doped region. The shallow junction can be used as the source or drain region of this memory component. As described in Figure 23A, additional implant and/or diffusion processes, such as a beveled pocket implant, can be implemented to provide one or more "pocket" areas or junction pocket extensions adjacent to one Or multiple shallow junction areas. In some cases, this type of configuration provides better component characteristics.

In some examples of using STI to isolate discrete memory components, the trench depth in the STI region can be greater than the depletion width in the p-well, especially when the junction bias used is increased. For example, the junction bias can be as high as 7V to the stylized forbidden bit line (the bit line that was not selected during programming). In one example, the depth of the STI region can range from about 200 to 400 nanometers.

After fabricating a memory array, a reset operation can be performed first to tighten the distribution of Vt. Figure 24a depicts an example of such an operation. In one example, before other operations begin, VG can be used to equal -7V and VP-well is approximately equal to +8V to reset the array (the voltage drop of VG and VP-Well can be assigned to this gate voltage to each WL) And p-type well). At reset, BL's can be floating or boosted to the same voltage as this P-well. As described in Figure 24b, this reset operation provides excellent self-convergence characteristics. In one example, even the SONONOS component is first charged to various Vt values, and the reset operation can "tighten" it to the reset/erase state. In one example, this reset time is approximately 100 msec. In this example, the memory component can use an n-channel SONONOS component having ONONO=15/20/18/70/90 angstroms and having one of Lg/W=0.22/0.16 micron N+ polysilicon.

Conventional floating gate components are often unable to provide self-convergence erase. Conversely, SONONOS components can operate with a convergent reset/erase method. In some cases, this operation may become very important because the initial Vt distribution is due to certain process issues, such as non-uniform processing. The plasma charging effect is usually in a wide range. The self-convergence "reset" of this example may help to limit or narrow the initial Vt distribution of memory components.

In an example of a stylized operation, the selected WL can be applied with a high voltage, such as a voltage of approximately +16V to +20V, to induce channel + FN injection. Other pass gates (other unselected WL's) can be turned on to induce a string of inverted layers of NAND. In some examples, +FN stylization can be a low power method. In one example, parallel stylization methods, such as page programming with 4K Bytes of parallel memory cells, can produce a total stylized processing power of more than 10 MB/sec, while total current consumption can be controlled to within 1 mA. In some examples, to avoid stylized interference in other BLs, a high voltage, such as a voltage of about 7V, can be applied to other BLs, so the inversion potential can be boosted to suppress unselected BLs. The pressure drop (for example, memory cell B in Figure 25).

For the example of a read operation, the selected WL can be boosted to a voltage between an erased state class (EV) and a stylized state class (PV). Other WLs can be used as this "pass gate", so the gate voltage can be raised and higher than PV. In some examples, the erase operation can be a reset operation as described above, which can allow self-convergence to the same or similar reset Vt.

Figure 25 depicts an example of an operation-memory array. Stylization may involve channel +FN injection electrons into a SONONOS nitride capture layer. Some examples may include applying Vg approximately equal to +18V to the selected WLN-1, and applying VG approximately equal to +10V to other WLs, and this BLT. This SLT can be turned off to avoid hot electron injection into the memory cell B. In this example, since all of the electromorphic systems in this string of NANDs are turned on, this inversion layer passes through this string. Further, because The BL1 is grounded, and the inverted layer of BL1 has a level of zero. On the other hand, other BLs are boosted to a high level, such as a voltage of about +7V, so the inversion layers of other BLs become higher.

In particular, for memory cell A, which is a memory cell selected for stylization, this pressure drop is approximately +18V, which results in a +FN injection. And this Vt can be upgraded to PV. For memory cell B, this pressure drop is +11V, resulting in less +FN injection, while FN injection is quite sensitive to Vg. For memory cell C, only a voltage of +10 V was applied, resulting in no or negligible +FN injection. In some examples, a stylized operation is not limited to the described techniques. That is, other suitable stylization prohibition techniques can also be applied.

Figures 24a, 26 and 27 further illustrate some examples of array operation and describe the persistence and preservation characteristics of certain examples. As described, the degradation of this component after multiple cycles of operation can be very small. Figure 24A depicts an exemplary erase operation that can be similar to a reset operation. In an example, this erase operation is performed by a block or block. As noted above, this memory component may have good self-converging erase characteristics. In some examples, this erase saturation Vt may depend on Vg. For example, a higher Vg may result in a higher saturation Vt. As described in Fig. 26, this convergence time can be about 10 to 100 msec.

Figure 27 depicts an example read operation. In one example, the reading can be accomplished by applying a gate voltage that is between an erased state Vt (EV) and a stylized state Vt (PV). For example, the gate voltage can be approximately 5 volts. On the other hand, other WLs and BLTs and SLTs are applied with a higher gate voltage, such as a voltage of about +9V, to turn on all other memory cells. In one example, if the Vt of memory cell A is higher than 5V, the read current can be very small (<0.1uA). If the Vt of the memory cell A is less than 5V, the read current can be Higher (>0.1uA). Therefore, this memory state, that is, the stored information, can be confirmed.

In some examples, the pass gate voltage for other WLs should be higher than this high Vt state or this stylized state Vt, but not too high to induce gate interference. In one example, the PASS voltage is in the range of about 7 to 10V. The voltage applied to BL can be approximately 1V. Although a larger read voltage can induce a larger current, this read disturb can become apparent in some examples. In some examples, the sense amplifier can be placed on a source line (source sense) or on a bit line (drain sense).

Some examples of NAND strings may have 8, 16, or 32 memory elements per string. A larger NAND string can save unnecessary management and increase the efficiency of the array. However, in some examples, this read current may be smaller and the interference may become more significant. Therefore, the appropriate number of NAND strings should be selected based on various designs, processes, and operational factors.

Figure 28 depicts the periodic endurance of certain example components. Referring to Fig. 28, a P/E loop with +FN stylization and -FN erasing can be implemented, and this result has good endurance characteristics. In this example, the erased state is Vg about -16V in 100msec. In some examples, only a single erase action is required and no verification of the state is required. The range of the memory Vt is good and there is no deterioration.

Figures 29a and 29b illustrate the memory element IV features of this example using different rulers. In particular, Figure 29a depicts a small degradation swing of one of the components, and Figure 29b depicts a small gm degradation of one of the components. Figure 30 depicts the preservation features of an exemplary SONONOS component. Referring to Figure 30, a good preservation profile was provided and still had a charge loss of less than 100 mV after 10 K hems of ring operation and 200 hours at room temperature.

In some examples, a separate gate design, such as a split gate SONONOS-NAND design, can be used to achieve a smaller size of a memory array. Figure 31 depicts an example of using such a design. Referring to Fig. 31, this space (Ls) between individual word lines, or between two adjacent memory elements sharing the same bit line, can be reduced. In one example, Ls can be reduced to about 30 nanometers or less. As shown, the memory component, which uses a separate gate design along the same bit line, can share only one source region and one drain region. On the other hand, a split gate SONONOS-NAND array can use no diffusion regions or junctions, such as N+ doped regions, for certain memory components. In one example, this design can also reduce or eliminate the need for shallow joints and adjacent "pockets", which in some instances may involve a more complex process. Moreover, in some examples, this design is less affected by the short channel effect, so the channel length has been increased, for example in one example to Lg = 2F-Ls.

Figure 32 depicts an exemplary process for a memory array using a separate gate design. This summary diagram is merely an illustrative example, and this memory array can be designed and fabricated using a variety of different methods. Referring to Fig. 32, after a material for providing a plurality of layers of the memory element is formed, a tantalum oxide structure is used as a hard mask formed on the plurality of layers, and then the plurality of layers can be patterned. For example, the hafnium oxide region can be defined by development and etching steps. In one example, the pattern used to define the initial yttrium oxide region may have a width of about F and a space between the yttrium oxide regions of about F, resulting in a distance of about 2F. After the initial yttria region is patterned, the yttria sidewalls can then be formed around the patterned regions to increase the individual yttria regions and reduce their space.

Continuing to refer to Fig. 32, after the yttrium oxide region is formed, it can be used as a hard mask to define or pattern its covered layer to provide At least one memory component, such as a plurality of NAND strings. Alternatively, an insulating material, such as hafnium oxide, can be used to fill the space, such as the Ls space shown in Figure 32, between adjacent memory elements.

In one example, the space Ls along the same bit line and between adjacent memory elements can range from about 15 nanometers to about 30 nanometers. As noted above, this effective channel length can be extended to 2F-Ls in this example. In one example, if the F system is about 30 nm and the Ls system is about 25 nm, the Leff is about 45 nm. For the operation of these example memory components, the gate voltage can be reduced to less than 15V. In addition, the voltage drop of the internal polysilicon between the word lines can be designed to be no more than 7V to avoid sidewall collapse in the Ls space. In an example, this can be achieved by having an electric field of less than 5 MV/cm between adjacent word lines.

For a conventional NAND floating gate device, the Leff with a diffusion junction is about half the length of its gate. In contrast, if the F system is about 50 nm and the Leff is about 30 nm, in one example of the proposed design (this split gate NAND), the Leff is about 80 nm. This longer Leff provides better component characteristics as it reduces or eliminates the effects of short channel effects.

As described above, a split gate NAND design can further reduce the spacing between adjacent memory cells on the same bit line. In contrast, conventional NAND type floating gate elements may not provide a small gap because the coupling effect between floating gates may result in loss of memory tolerance. The internal floating gate coupling is at an interface between adjacent memory cells when the capacitance of the adjacent floating gate is relatively high (the space of the floating gate is small and adjacent to the floating gate) The coupling capacitance between the poles becomes high and causes read disturb). As mentioned above, this design eliminates the need to make certain diffusion junctions, and if all When the word line system is activated, the inversion layer can be directly connected, so this design can simplify the process of the memory element.

A multilayer SONOS component using an ultra-thin ONO tunneling dielectric layer is described. Since there is an n+ polysilicon gate, in one example, a self-convergence forward erase threshold voltage of about +3V is achieved for a NOR architecture. The channel thermal electronic stylization can be used to store two bits per memory, can be read by using the standard reverse reading method, and is erased by tunneling, which uses an electric field to assist FN. The tunneling is performed at a gate voltage, for example -15 volts. Using a p+ polysilicon (or other high work function material) gate, a depletion mode component can be obtained which has a threshold voltage of less than zero and a stylized threshold voltage of more than about 6 volts, which can be achieved very large The memory usable range is applicable to the NAND architecture, where the architecture uses field-assisted FN electron tunneling for stylization and uses electric field-assisted FN hole tunneling for erase operation, which is erased It has a gate voltage, such as -18 volts.

Figure 33 is a graph of a MOSFET-threshold voltage change for a plurality of stylized interference bias pulses or erased interference bias pulses, wherein the MOSFET has an ultra-thin multilayer tunneling dielectric layer (O1/ N1/O2 = 15/20/18 angstroms). This figure shows negligible charge trapping in this ONO tunneling dielectric layer, whether the CHE, +FN, or -FN implant mode is used in the example component with a multilayer tunneling dielectric layer.

Figure 34 is a graph of the gate voltage of an ultra-thin ONO dielectric capacitor versus time at a fixed current stress, which highlights a small charge trapping under negative gate current stress and indicates excellent Stress tolerance. This small capture efficiency may be due to the fact that this capacitance represents a free channel longer than about 20 angstroms of nitride thickness. It also shows that a N1 layer of less than 20 angstroms is a preferred embodiment. Additionally, in a preferred embodiment, No gap capture was induced at O1/N1 and N1/O2 during processing.

Figure 35 is a self-convergence threshold voltage Vt as a function of the erase gate voltage V _G during the erasing process of a component, wherein the component has an ultra-thin multilayer tunneling dielectric layer (O1/N1/ O2 = 15/20/18 angstroms) and has an N+ poly gate. A greater intensity of the gate voltage V _G causes a higher saturation value of one of the V _T due to the gate implant becoming stronger. A high self-convergence erase is beneficial for the NOR architecture because it avoids the problem of over-erasing.

Figure 36 is a plot of threshold voltage vs. bake time. For an example component, it has an N+ polymorph gate at various P/E loop numbers for memory cells in erased and stylized states. It shows excellent electronic preservation ability for this multilayer tunneling dielectric layer BE-SONOS device.

For NAND applications, a depletion mode component (V _T <0) is beneficial for the erase state. By using a P+ poly gate, the gate implant system can be reduced and the components can be erased to a depletion mode, as shown in Figure 37. Figure 37 is a graph of flat band voltage vs. time for a multilayer tunnel dielectric layer memory cell (ONONO = 15/20/18/70/90 angstroms) showing erase time with higher intensity Negative gate voltage is reduced. Figure 37 also depicts that at a larger V _G (e.g., about -20 volts), the gate implant becomes significant, causing the erase saturation to be about -1 volt.

Figure 38 is a +FN for a sample element with a P+ poly gate and an ONONO=15/20/18/70/90 angstrom when V _G is equal to +19, +20, and +21 volts. Stylized feature, its flat band voltage vs. time graph. As shown in Fig. 38, a large usable range (up to about 7 volts in this figure) is available in 10 msec, and a usable range of 3 volts can be obtained in less than 200 microseconds. .

Figure 39 is for a stylized pulse of 20 volts for each The curve of the flat band versus the programmed/erased loop number for a chirped ring of 500 microseconds and an erase pulse of -20 volts per cycle of 10 msec or -18 volts per cycle of 100 msec Figure, which depicts the P/E loop endurance. In Figure 39, a single stylization and one erasing is used in each P/E loop.

Figure 40 is a graph of flat band voltage vs. stress time, which depicts a V _G accelerated storage test that applies -V _G in the programmed state and +V _G in the erased state to have a P+ Example components of the thyristor. As described in Fig. 40, small charge loss and small charge gain indicate that direct charge tunneling has been suppressed under a typical electric field (<4 MV/cm).

Figure 41 is a graph of flat band voltage vs. time, which is described in charge storage at room temperature and elevated temperature for charge trapping nitride N2 of an element having a P+ poly gate in accordance with the present invention. As shown in Figure 41, charge loss and charge gain are negligible at room temperature. In addition, the usable range of more than 6 volts can be preserved even after baking for 500 hours at 150 degrees Celsius. This range of more than 6 volts, and excellent preservation is a very good result for SONOS-type components.

Figure 42 is a graph of the flat band voltage vs. time for ONONO components with N2 and O3 layers of 70 and 90 angstroms, respectively, and the O1, N1, and O2 layers are 15/20. /18, 15/20/25 and 18/20/18 angstroms, describing the erasing speed of the BE-SONOS component, having a thickness of less than 20 angstroms with this O1 layer, especially 18 angstroms or 15 angstroms in this example, There have been significant improvements. Indeed, with an O1 of 15 angstroms, this erasing speed is significantly improved, resulting in a speed at which the erasing speed is less than 100 milliseconds and less than 10 milliseconds. For a 15 angstrom O1 layer, the flat band voltage is less than 10 milliseconds (its close It is based on the change in the threshold voltage) that has a reduction of more than 3 volts. As shown in Fig. 42, this erasing speed is very sensitive to changes in O1. As shown in Fig. 42, the thickness of O1 is reduced from 18 angstroms to 15 angstroms, which results in a reduction in the erase time. For changes in O2 thickness, there is usually only a small effect on the erase time. It is therefore the ONO tunneling system that is dominated by the O1 layer, and the effect of this O2 layer is masked almost (as in Figure 5c) or completely (as in Figure 5d) during a erase bias operation.

Figure 43 is a plot of a flat strip voltage versus time for a wiper bias of -18 volts, with the component having a BE-SONOS structure with ONONO = 15/20/18/70/90 angstroms. Figure 43 is a comparison of the erase characteristics of the elements of the second example, with one example element having a P+ polysilicon gate and the other example having a gate containing platinum. Platinum has a higher work function relative to P+ polysilicon, which can result in an unsaturated erase, as shown in Figure 43. This high work function gate material can be patterned using, for example, a photoresist stripping method.

As mentioned, some of the above examples, including structural design, array design, and operation of memory components, can provide the desired array size, good reliability, good performance, or any combination of the above advantages. Some of the above examples can be used to scale small non-volatile flash memory, such as NAND flash memory and flash memory for data applications. Some examples provide a SONONOS component that has a uniform and high speed channel hole tunneling erase. Some examples can also provide good endurance of memory components and reduce some of the issues that are difficult to erase or erase. At the same time, good component characteristics can be provided, such as still only small degradation after P/E ring and good charge retention. The uniformity of the components in a memory array can be provided without the unstable bits or memory cells. Further, some examples can be borrowed Designed by a split gate NAND, it provides good short channel component characteristics, which provides better sensing boundaries when operating the memory components.

Figure 44 is a schematic top view showing a portion of an exemplary array utilizing a thin film transistor structure on an insulating substrate. Referring to FIG. 44, a portion of the memory array 400 is formed on an insulating substrate 401. A portion of the memory array 400 includes a plurality of parallel semiconductor body regions 410 on an insulating layer within the substrate 401, and a plurality of parallel word lines 420c between the select lines 420a and the select lines 420b. The select line 420a and the select line 420b and the word line 420c are substantially perpendicular to and cover the semiconductor body region 410. The number of the character lines 420c is not limited to the number shown in Fig. 44. The number of word lines 420c may be 8, 16, 32, 64, and 128 or other numbers suitable for use in a memory array.

The substrate 401 may be, for example, a semiconductor substrate, a tri-five-family composite substrate, a germanium substrate, an epitaxial substrate, an insulating layer overlay (SOI) substrate, a display substrate such as a liquid crystal display, a plasma Display, an electronically illuminated (EL) lamp display, or a light emitting diode (LED) substrate. For an embodiment of an insulating layer coating (SOI), the substrate 401 includes at least one insulating dielectric layer, such as a spacer material substrate 401, such as a semiconductor wafer, and a dielectric layer 405 (shown at 46A). Figure).

Referring to the embodiment shown in FIG. 44, each semiconductor body region 410 includes at least one junction region, such as the junction region 412 adjacent to the selection line 420a and the selection line 420b, wherein the selection line 420a and the selection line 420b are Located between the two ends of a continuous junctionless channel region. Select line 420a can be referenced as a block select line and select line 420b can be referenced as a source select line. The junction area 412 is connected to the whole by contact vias or other (not shown) Body bit line or source line. The selection line 420a and the selection line 420b are configured to connect a selection block or a memory cell to the bit line and the source line when the voltage is applied to the selection line 420a and the selection line 420b.

In the depicted embodiment, a portion of the memory array 400 includes a plurality of parallel insulated trench structures 430 adjacent the semiconductor body region 410 and interposed between two adjacent semiconductor body regions 410.

Referring to FIG. 44, a rectangle 402 represents a size of a memory cell which is substantially the width of the double word line 420c multiplied by the width of a trench 430 and a semiconductor body region 410.

Figure 45 is a schematic cross-sectional illustration showing a portion of an exemplary array and drawing a line of characters 420c along the section line 2-2 in Figure 44, indicating a crossing A perspective view of a memory cell array. In FIG. 45, the trench structure 430 is formed between two adjacent semiconductor body regions 410. A tunneling barrier layer 310, a charge storage layer 320, a dielectric layer 330, and a conductive layer 335 are stacked and substantially conformable to the structure of the semiconductor body region 410 and the trench structure 430. A detailed description of the tunneling barrier layer 310, the charge storage layer 320, the dielectric layer 330, and the conductive layer 335 is illustrated in Figure 46A.

46A and 46B are schematic illustrations of cross-sections showing the steps taken along line 3-3 of Figure 44 in a step in an exemplary method of forming an exemplary semiconductor structure.

Figure 46A is a cross-sectional view taken along line 3-3 of Figure 44, which shows a single memory cell line in a junctionless NAND configuration. The dielectric layer 305 covers the substrate 401 as described in FIG. 46A. The semiconductor body region 410 is formed over the dielectric layer 305. Dielectric layer 305 can be, for example, an oxide layer, a nitride layer, an oxynitride layer, other dielectric layers, or a combination of the various combinations described above. In some embodiments, the dielectric layer 305 can be referred to as a buried oxide layer, as if covered by an insulating layer. (SOI) structure. The semiconductor body region 410 can be a germanium layer, a polysilicon layer, an amorphous germanium layer, a germanium layer, an oriented epitaxial layer, layers of other semiconductor materials, or a combination of any of the above. For some embodiments for generating a p-type semiconductor region, the semiconductor body region 410 can have dopants such as germanium, gallium, aluminum, and/or other tri-family elements. In some embodiments, the semiconductor body region 410 and the dielectric layer 305 can be formed by an SOI process. In other embodiments, the dielectric layer 305 can be formed by a chemical vapor deposition (CVD) process, an ultra-high vacuum chemical vapor deposition (UHVCVD) process, and an atomic layer chemical vapor deposition (ALCVD) process. , a metal organic chemical vapor deposition (MOCVD) process or a CVD process thereof. The semiconductor body region 410 can be formed by, for example, an orientation epitaxy process, a CVD process, an epitaxial process, or a combination of various combinations. In one embodiment, the TFT element has a 60 nm thick polysilicon channel over the buried oxide. The polycrystalline germanium is an amorphous germanium (a-Si) layer which is deposited by a low pressure chemical vapor deposition (LPCVD) process followed by a low temperature thermal annealing (600 degrees Celsius) to complete the crystallization. A multilayer O1/N1/O2 tunneling dielectric layer has an easy hole tunneling during erasing and eliminates charge loss in the tunneling dielectric layer during storage. Next, a SiN trap layer (N2) and a top barrier oxide (O3) are formed. A heavily doped P+ poly gate is used to suppress this gate implant during -FN erasing. This component has a three-gate structure, as shown in Fig. 45, having equivalent three channel surfaces, one on each side and one on top of the semiconductor body region 410.

The top oxide process has the largest thermal budget. The process of forming the two top oxides (O3) is representative, including a LPCVD oxide (HTO) with rapid thermal annealing, and an undisturbed vapor generation (ISSG) oxidation to convert a portion of the capture nitride (N2). To oxide. Lower thermal budgeting process is more suitable for reducing doping by selective gate junctions The spread of matter. However, the ISSG process can result in a better endurance feature, as published in the International Electron Devices Meeting, IEDM Journal, December 2006, "A Multi-Layer Stackable Thin-Flim Transistor (TFT) NAND-TYPE Flash Memory. The inventor is Lai et al., which is hereby incorporated by reference. The planarization system is then implemented, for example, by HDP oxidative implantation and chemical mechanical polishing. After forming the bottom TFT element. Contact etching for multiple layers can be independently implemented to avoid excessive etching.

Referring to Figure 46A, semiconductor body region 410 includes a continuous contactless channel region 414 between select line 420a, select line 420b, and below word line 420c and between word line 420c. The semiconductor body region 410 includes at least one continuous contactless channel region, such as region 415, below select line 420a, select line 420b, and word line 420c.

Each of the selection lines 420a and 420b includes a gate insulator 331 and a conductive layer 336. The gate insulator 331 can be an oxide layer, a nitride layer, an oxynitride layer, a high-k dielectric layer, other layers of dielectric material, or various combinations thereof. The conductive layer 336 can be, for example, a polysilicon layer, an amorphous germanium layer, a metal containing layer, a tungsten germanium layer, a copper layer, an aluminum layer, or other layers of conductive material. The conductive layer 336 can be formed by, for example, a CVD process, a physical vapor deposition (PVD) process, an electroplating process, and/or an electroless plating process.

Each word line 420c may include a tunneling barrier layer 310, a charge storage layer 320, a dielectric layer 330, and a conductive layer 335. In some embodiments, the tunneling barrier layer 310, the charge storage layer 320, the dielectric layer 330, and the conductive layer 335 can be formed over the semiconductor body region 410.

The tunneling barrier layer 310 may allow charge, such as holes or electrons, to tunnel from the semiconductor body region 410 to the charge storage layer 320 during an erase operation and/or a reset operation. The tunneling barrier layer 310 can be an oxide layer, a nitride layer, an oxynitride layer, other layers of dielectric material, or a combination of any of the above. In some embodiments, the tunneling barrier layer 310 can include a first oxide layer (not labeled), a nitride layer (not labeled), and a second oxide layer (not labeled). ONO structure. In some embodiments, the first oxide layer can be an ultra-thin oxide layer having a thickness of about 2 nanometers or less. In another embodiment, the first oxide layer can have a thickness of about 1.5 nanometers or less. In other embodiments, the first oxide layer can have a thickness of between about 0.5 nanometers and about 2 nanometers. An ultra-thin oxide layer can be formed, for example, by an undisturbed vapor generation (ISSG) oxidation process. The process for forming the nitride layer can be, for example, the use of DCS and NH ₃ as a precursor at a temperature of about 680 degrees Celsius. In certain embodiments, the nitride layer can have a thickness of about 3 nanometers or less. In other embodiments, the nitride layer can have a thickness of between about 1 and 2 nanometers. The formation of the second oxide layer can be performed, for example, by an LPCVD process. In certain embodiments, the second oxide layer can have a thickness of about 3.5 nanometers or less. In another embodiment, the second oxide layer can have a thickness of about 2.5 nanometers or less. In another embodiment, the second oxide layer can have a thickness of between about 2.0 and 3.5 nanometers.

The charge storage layer 320 can store charge, such as electrons or holes, as previously described. The charge storage layer 320 can be, for example, a nitride layer, an oxynitride layer, a polysilicon layer, or other layer of material suitable for storing charge. In some embodiments, to form a nitride layer of the charge storage, this process can be used, e.g., silane-dichloro DCS and NH ₃ were used as front material and process a temperature of about 680 degrees celsius. In another embodiment for forming a charge storage layer of an oxynitride, such a process can be used, for example, DCS, NH ₃ , N ₂ O as a precursor. In some embodiments, the charge storage layer 320 can have a thickness of about 5 nanometers or more, for example, about 7 nanometers.

The dielectric layer 330 can insulate the conductive layer 335 to inject charge into the charge storage layer 320. The dielectric layer 330 can be, for example, an oxide layer, a nitride layer, an oxynitride layer, an aluminum oxide layer, other dielectric materials, or a combination of any of the above. In some embodiments, the process for forming the dielectric layer 330 converts portions of the charge storage layer 320, such as a nitride layer, to form the dielectric layer 330. The process can be a wet shift process that utilizes O ₂ and H ₂ O gas in the furnace at temperatures between about 950 and 1000 degrees Celsius. For example, a nitride layer having a thickness of about 13 nanometers can be converted to dielectric layer 330, which has a thickness of about 9 nanometers, and a remaining nitride layer, such as a charge. A storage layer 320 having a thickness of about 7 nanometers. The wet conversion process is applied to a small portion of the initial layer and then deposited to balance the layer by a small thermal budgeting process for depositing cerium oxide, such as a high temperature oxidizing HTO process or a The original steam generation (ISSG) oxidation process. In other embodiments, dielectric layer 330 is formed over charge storage layer 320 and a wet conversion process is not used. The various thicknesses of the tunneling barrier layer 310, the charge storage layer 320, and the dielectric layer 330 can be used to form a desired structure.

The conductive layer 335 can be, for example, a polysilicon layer, an amorphous germanium layer, a metal-containing, tungsten-phosphide layer, a copper layer, an aluminum layer or other layer of conductive material, or a combination of the above materials. The conductive layer 335 can be formed by, for example, a CVD process, a physical vapor deposition (PVD) process, an electroplating process, and/or an electroless plating process. In some embodiments, conductive layers 335 and 336 can be formed by the same process. In some embodiments, the tunneling barrier layer 310 and the charge storage layer 320 are included. The structure of the dielectric layer 330 can be referred to as an engineering energy gap SONOS (BE-SONOS) structure.

Referring to FIG. 46A, dielectric material 339 is formed between select line 420a, select line 420b, and word line 420c, and between word line 420c. Dielectric material 339 can comprise, for example, oxides, nitrides, oxynitrides, and/or other dielectric materials. Dielectric material 339 can be formed by, for example, a CVD process. At least one dielectric sidewall, such as dielectric sidewall 337, may be formed over sidewalls of select line 420a and select line 420b. Dielectric sidewall 337 can comprise, for example, oxides, nitrides, oxynitrides, and/or other dielectric materials. In some examples, dielectric sidewall 337 and dielectric material 339 are fabricated from the same material and fabricated from the same process.

Referring to FIG. 46B, a implant process 340 implants dopants into the semiconductor body region 410 by using dielectric sidewalls 337 and/or dielectric material 339 as an implant mask to form at least one doped layer. A region, for example, region 412, forms a junction within the semiconductor body region 410. Region 412 can be referenced as a source/drain (S/D) region of select line 420a and select line 420b. In some embodiments, the implant process 340 can be a tilt implant process such that the region 412 can be properly formed within the semiconductor body region 410. In other embodiments, the implant process 340 can have a direction of implantation that is substantially perpendicular to the surface of the substrate 401, wherein an electro-crystalline system is formed over the substrate 401. In some embodiments for forming an n-channel transistor, the implant process 340 can use n-type dopants such as germanium, arsenic, and/or other five-element elements.

Referring to FIG. 46B, the implant process 340 does not implant, for example, an n-type dopant into the semiconductor body region 410, such as a p-type semiconductor body region, which is blocked by the dielectric sidewall 337 and the dielectric material 339. Process 340. Therefore, the implant process 340 does not form a source/drain region. The field is in a region 414 between the select line 420a and the select line 420b and the word line 420c. It is noted that no implant process is implemented to form a common source/drain region within region 414 of semiconductor body region 410 in Figure 46A. Thus, the region 414 of the semiconductor body region 410 is a junctionless design. The doping concentration of region 414 and region 415 are thus substantially identical, providing a junction free region over select line 420a, select line 420b, and word line 420c.

Figure 46C is a schematic illustration of a cross-section showing an exemplary process for implanting dopants in the semiconductor body region. In Fig. 46C, a patterned mask layer 350 is formed over select line 420a, select line 420b, and word line 420c. The patterned mask layer 350 covers at least a portion of the select line 420a, the select line 420b, and the word line 420c. The patterned mask layer 350 protects regions 414 of the semiconductor body region 410 from being implanted in the implant process 355. The patterned mask layer 350 can be, for example, a patterned photoresist layer, a patterned dielectric layer, a patterned material layer suitable for use in an etch mask, and various combinations of the foregoing. After the implant process 355, the patterned mask layer 350 can be removed. The implant process 355 can be a tilt implant process or an implant process having a direction generally perpendicular to the substrate 401.

Figure 47 is a schematic illustration of a cross-section showing a portion of an exemplary stacked array structure. In Figure 47, another array structure layer 357 can be formed over the structure of Figure 46B. Array structure layer 357 can include, for example, a dielectric layer 360 formed over select line 420a, select line 420b, and word line 420c. Dielectric layer 360 can be an oxide layer, a nitride layer, an oxynitride layer, or various combinations of the foregoing. Dielectric layer 360 can be formed by, for example, a CVD process, a glass spin coating process, and/or other processes suitable for forming a dielectric layer.

Referring to FIG. 47, the array structure layer 357 may further include at least one semiconductor body region, such as a semiconductor body region 365, including a region 367, a region 368, a region 369, a select line 370a, a select line 370b, a word line 370c, and a gate. Insulator 371, tunneling barrier layer 372, charge storage layer 374, dielectric layer 376, conductive layer 380, conductive layer 381, dielectric sidewall 382, and dielectric material 384 are similar to semiconductor body region 410, wherein The semiconductor body region 410 includes a region 412, a region 414, a region 415, a select line 420a, a select line 420b, a word line 420c, a gate insulator 331, a tunnel barrier layer 310, a charge storage layer 320, a dielectric layer 330, and a conductive layer. Layer 335, conductive layer 336, dielectric sidewall 337, and dielectric material 339 are as described in connection with FIG. 46B. It should be noted that the array structure layer 357 is formed on the structure of Fig. 46B. Region 412 (shown in FIG. 44) belongs to the same enthalpy ring when fabricated, for example, dielectric layer 360, semiconductor body region 365, select line 370a, select line 370b, word line 370c, tunneling barrier Layer 372, charge storage layer 374, dielectric layer 376, conductive layer 380, dielectric sidewall 382, and/or dielectric material 384 are as described in connection with FIG. Region 412 can extend toward select line 420a, select line 420b, thus forming region 412a. The extended region 412a can have a dimension "a" that is greater than the dimension "b" of the region 367.

It should be noted that the example structure of Figure 47 does not have the same source/drain regions, wherein regions are formed between select line 420a, select line 420b, word line 420c and between word line 420c. Region 412a may not extend or be adjacent to other junctions and doped source/drain regions even after a plurality of turns. Therefore, the issue of short channel effects and leakage currents in the memory array can be properly avoided.

Figure 47 shows only an exemplary embodiment comprising two stacked array structures. The number of this array structure, for example, this array structure layer 357, not limited to two. Two or more array structures can be formed over the structure in Figure 47 to achieve a suitable memory capacity.

Figure 48 is a schematic illustration of a cross-sectional view showing a process for creating an example of an inversion layer in a semiconductor body region. Referring to Figure 48, a voltage "V" can be coupled to word line 420c. In some embodiments, there is a space "S" between two adjacent word lines, wherein the word lines can be, for example, word lines 420c, 420d or word lines 420c, 420e, which can be about 75. Nano or smaller. In an exemplary embodiment, the space S is 30 nanometers or less. Because of this small space, the voltage "V" applied to word line 420c can be coupled to and create an inversion layer 411 in semiconductor body region 410, where the 411 is between two adjacent word lines. For example, word lines 420c, 420d or word lines 420c, 420e, and 411. 411, 411a below word line 420c can serve as the source/drain terminal and channel of the array transistor. In some embodiments using a NAND type structure, a voltage system is applied to each of the word lines 420c-420e, and may invert and/or generate an inversion layer to two adjacent word lines 420c-420e and select line 420a. , select line 420b. Thus, the array transistor can function properly without the need to heavily dope the S/D junction within the semiconductor body region 410.

reset

In some embodiments, a reset operation can be implemented to limit the distribution of Vt prior to operation of the memory array. For example, a voltage can be applied to and on select line 420a and select line 420b. Prior to operation, a voltage of approximately -7V can be applied to word lines 420c-420e and a voltage of approximately +8V can be applied to semiconductor body region 410 as shown in FIG. The voltage applied to select line 420a and select line 420b is higher than the voltage applied to word lines 420c-420e. The voltages of the word lines 420c-420e and the semiconductor body region 410 are appropriately distributed and applied to each Word line and semiconductor body area. In some embodiments, the memory array can be charged at various voltages. The reset operation can properly reset the memory cells of the memory array. In some embodiments, the reset time is approximately 100 milliseconds. In some embodiments for resetting the memory array, the memory array can include an n-channel BE-SONOS component having an ONONO of about 15/20/18/70/90 angstroms, and the component has an N+ polysilicon. The gate has an Lg/W of about 0.22/0.16 microns.

Stylized

In some embodiments for memory cells for staging memory arrays, a high voltage, for example, a voltage between about +16V and +20V, can be applied to word line 420c to induce channel + FN injection. In some embodiments, the high voltage system is approximately +18V. A voltage, such as a voltage of approximately +10 volts, can be applied to the other pass gates, i.e., unselected 420d and 420e, to induce an inversion layer to the NAND string. The semiconductor body region 410 is substantially grounded. A charge, such as an electron, can be implanted into the charge storage layer of word line 420c. In some embodiments, the +FN stylization can be a low power stylized. In some embodiments, a parallel stylization method, such as a page stylization method, having a 4K byte of memory cells can appropriately increase the total programmed output to more than 10 MB/sec. The total current consumption can be about 1 milliamperes or less. In some embodiments, a voltage, such as a voltage of about 7 volts, can be applied to other bit lines to avoid stylized interference. The voltage applied to the bit line may increase the level of the inversion layer to suppress the voltage drop across the unselected bit line.

Erase

In some embodiments, the erase operation can be similar to a reset operation. A voltage of about -7V can be applied to word line 420c and a voltage of about +8V can be applied to semiconductor body region 410 as shown in FIG. The voltage of the word line 420c and the semiconductor body region 410 is The local distribution is applied to individual word lines and semiconductor body regions.

Read

In some embodiments for reading a memory array, the selected word line can be boosted to a voltage, such as about +5V, which is a state class (EV) and a program that is erased by one of the memory cells. Between state classes (PV). Other unselected word lines can be used as "pass gates", so their gate voltage can be boosted to a voltage higher than PV. In some embodiments, the voltage applied across the gate is about +9V. In some embodiments, a voltage of approximately +1 V is applied to the semiconductor body region 410.

The structure and method for forming the structures of the above-mentioned 44th, 45th, 46A-46C and 47 can be applied to any NAND type flash memory, which can have various memory cell structures, such as a polysilicon floating. The flash memory of the gate.

Example embodiment

The following is an example of a jointless BE-SONOS component. In certain embodiments, the component has a polycrystalline pitch of about 0.15 microns. After patterning the polycrystalline hard mask, an oxidized liner layer can be formed to fill the polycrystalline space, for example, about 70 nm or more, and then etch the polycrystal to define the final polycrystalline space. This component avoids abnormal polysilicon shorts or line crashes. The narrow space (S) between the sidewalls of the oxide liner is properly controlled by the thickness of the oxide of the liner.

Conventional junction implants can be formed after polycrystalline etching. In the embodiment of the jointless element, the shallow joints and the side walls can be retained. The oxidized sidewalls can be filled in a narrow space between the word lines. A beveled implant can be implemented to form a junction outside of the array and adjacent the array. Because the thick polycrystalline gate blocks the implant, the center of the array is not obscured and is junctionless. The process is beneficial for compatibility with traditional NAND processes. And no An extra mask is required.

The following is a description of the electronic characteristics of the junctionless components. The component is a 16-WL NAND array. The ONONO structure, for example, O1/N1/O2/N2/O3, has dimensions of about 13/20/25/60/60 angstroms, respectively.

Figure 49A depicts the effect of various p-type well dopings. A lightly doped well provides greater electron density and causes more current. Figure 49B depicts the effect of this space (S). As S increases, the electron density decreases slightly in space, resulting in less current.

Figure 50 is a graph showing the initial IV of a measured example n-channel component. The junctionless elements can have subcritical behavior similar to conventional junction elements. It was found that the drain current of the junctionless component is slightly lower than the gate current of the conventional junction component. It was also found that a larger space (S) showed a slightly smaller current. Figure 51 shows that a higher doping concentration well can increase the Vt value of the junctionless component, which is also consistent with the simulation shown in Figure 49A.

Figures 52A-52B show +FN ISPP stylization and -FN erasure, respectively. The junctionless elements can have similar electronic features as conventional junction elements. The reason may be that the +/- FN injection system is dominated by the ONONO characteristics of the body and is independent of the junction.

Figure 53 shows the electronic features of an exemplary P-channel BE-SONOS NAND having a structure similar to one of the N-channel BE-SONOS NAND stacks described in Figure 50 above. In Fig. 53, it was found that the junctionless elements have a large Vt difference and a small current compared to conventional junction elements. The reason may be that the conventional junction elements are undesirably optimized and have a large Vt comparison effect.

For p-channel NAND, stylize/erase voltage polarity for n Channel NAND is the opposite. Figures 54A-54B show -FN ISSP stylization and +FN erasure for an example p-channel BE-SONOS NAND. From Figure 54A-54B, it can be seen that an exemplary p-channel BE-SONOS NAND-FN ISPP stylization and +FN stylized erasure can be implemented.

Figure 55 shows the endurance of an exemplary n-channel component. In Fig. 55, the junctionless component does not have a large amount of reliability degradation, and the conventional junction component has this problem.

Figure 56 shows an IV curve of an exemplary TFT BE-SONOS component. To understand the impact of the thermal budget, simulate the effect of this thermal budget on the thermal annealing in 20% after one of 850 degrees Celsius in a three-dimensional product. In Fig. 56, the TFT element also exhibits similar electronic characteristics after thermal annealing. This result is good for a three-dimensional product process because the junctionless components are quite insensitive to the thermal budgeting system.

Figure 57 shows a simulation of an example junctionless component in which the components have various different technology nodes (F is one and a half of the polycrystalline pitch) and have the same space (S is 20 nm). In Fig. 57, it can be found that the junctionless element Vt comparison effect can be properly controlled. It can be attributed that the effective channel length in the junctionless element is relatively larger than conventional junction elements. In Figure 57, the effect of the stylized state is also simulated. For components with smaller F, the stylized Vt drift is reduced. The reason for this is that the length of the element channel is very short and the boundary electric field causes deterioration of the gate control ability. It has also been found that junctionless components are suitable for charge trapping components. For embodiments of floating gate components, the small space (S) can induce more FG-FG interference.

The foregoing preferred embodiments of the invention are used to describe and illustrate the invention. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. It can be used in this field The above-described embodiments can be changed or adjusted without departing from the spirit and scope of the invention. It is understood that the invention is not to be construed as limited to the details of the embodiments disclosed herein. definition.

100‧‧‧n channel memory cell

101‧‧‧p-type substrate

102‧‧‧n doped area

104‧‧‧n doped region

106‧‧‧Channel area

120‧‧‧Tunnel dielectric structure

122‧‧‧low oxide layer

124‧‧‧ nitride layer

126‧‧‧High oxide layer

130‧‧‧Charge trapping layer

140‧‧‧Insulation

150‧‧‧ gate

200‧‧‧p channel memory cell

201‧‧‧n type substrate

202‧‧‧p-doped area

204‧‧‧p-doped area

206‧‧‧Channel area

214‧‧‧Area

220‧‧‧Tunnel dielectric structure

222‧‧‧low oxide layer

224‧‧‧ nitride layer

226‧‧‧High Oxide

230‧‧‧ Charge trapping layer

240‧‧‧Insulation

250‧‧‧ gate

305‧‧‧ dielectric layer

310‧‧‧ Tunneling barrier

320‧‧‧Charge storage layer

330‧‧‧ dielectric layer

331‧‧‧gate insulator

335‧‧‧ Conductive layer

336‧‧‧ Conductive layer

337‧‧‧ dielectric sidewall

339‧‧‧ dielectric materials

340‧‧‧planting process

350‧‧‧ patterned mask layer

355‧‧‧planting process

357‧‧‧Array structure layer

360‧‧‧ dielectric layer

365‧‧‧Semiconductor main area

367‧‧‧Area

368‧‧‧Area

369‧‧‧Area

370a‧‧‧Selection line

370b‧‧‧Selection line

370c‧‧‧ character line

371‧‧‧gate insulator

372‧‧‧ Tunneling barrier

374‧‧‧Charge storage layer

376‧‧‧ dielectric layer

380‧‧‧ Conductive layer

381‧‧‧ Conductive layer

382‧‧‧ dielectric sidewall

384‧‧‧ dielectric materials

400‧‧‧ memory array

401‧‧‧Base

402‧‧‧Rectangle

410‧‧‧Semiconductor main area

411‧‧‧Area

411a‧‧‧Area

412‧‧‧Area

414‧‧‧Area

415‧‧‧ area

420a‧‧‧Selection line

420b‧‧‧Selection line

420c‧‧‧ character line

420d‧‧‧ character line

420e‧‧‧ character line

430‧‧‧Insulated trench structure

The above description, as well as the following detailed description of the invention, may be further understood by the accompanying drawings. As a description of the use of the present invention, the presently preferred illustrated embodiments are shown herein. However, it should be understood that the present invention should not be limited to the precise arrangement and arrangement of the disclosure.

1a and 1b are cross-sectional schematic views showing an N-channel memory cell according to an embodiment of the present invention and a P-channel memory cell according to an embodiment of the present invention; The various program methods in accordance with one embodiment of the present invention are a graphical representation of a threshold voltage (charge trapping capability) of a tunneling dielectric structure.

Figure 3 is a graphical representation of one of the threshold voltages of a SONONOS memory cell in accordance with one embodiment of the present invention at erase time.

Figure 4 is an illustration of the threshold voltage of a SONONOS memory cell in accordance with one embodiment of the present invention at the time of storage.

5a-5e is an energy band diagram of an ONO tunneling dielectric structure in accordance with various embodiments of the present invention.

Figure 6 is a graphical representation of the tunneling current versus electric field strength for three different tunneling dielectric structures.

Figure 7a is an illustration of an embodiment of the present invention in which a memory cell is erased after various classes of programs.

Figure 7b is a graphical representation of a threshold voltage of a memory cell with a platinum gate at the time of erasing in accordance with one embodiment of the present invention.

Figures 7c and 7d are graphical representations of the capacitance versus voltage for the memory cells mentioned in Figure 7b.

Figure 8 is a graphical representation of a threshold voltage of a memory cell after a majority of programs/erasing of the annulus in various operating situations in accordance with one embodiment of the present invention.

Figure 9 is a graphical representation of the relationship of current-voltage (IV) for a memory cell in one cycle and 1000 cycles in accordance with one embodiment of the present invention.

Figure 10 is an illustration of a threshold voltage for a program/erase loop in a program and erase condition in accordance with one embodiment of the present invention.

Figure 11 is a diagram showing the variation of the threshold voltage of a memory cell in VG accelerated storage in accordance with one embodiment of the present invention.

Sections 12a and 12b are equivalent circuit diagrams and layout diagrams, respectively, for an embodiment of a virtual memory cell array in accordance with the present invention.

Figure 13 is a diagram of a virtual ground cell array taken along line 12B-12B which is identical to the 12b representation in accordance with one embodiment of the present invention.

14a and 14b are memory array equivalent circuit diagrams including memory cells in accordance with one embodiment of the present invention and describing suitable reset/erase voltages in accordance with two operational embodiments of the present invention.

15a and 15b are circuit diagrams equivalent to a memory array. The memory cell comprises a memory cell in accordance with an embodiment of the present invention.

Figures 16a and 16b are diagrams of a memory array that includes a memory cell for reading a bit in accordance with one embodiment of the present invention.

Figure 17 is a threshold voltage of a memory cell in accordance with one embodiment of the present invention in a variety of different program/erasing loops.

Figure 18 is a graphical representation of the threshold voltage of a memory cell in accordance with one embodiment of the present invention for multiple program/erase rings.

Figures 19a and 19b are diagrams of currents flowing from a drain of a memory cell in accordance with one embodiment of the present invention at various gate voltages, respectively, to a pair of scale gauges and a linear ruler.

Figure 20 is a diagram of a program bit element including an equivalent circuit diagram of an array of memory cells in accordance with one embodiment of the present invention.

21a and 21b are a layout diagram and an equivalent circuit diagram of a virtual ground array according to an embodiment of the present invention.

Figures 22a and 22b are respectively an equivalent circuit diagram and layout diagram for an NAND memory cell array in accordance with one embodiment of the present invention.

Figures 23a and 23b are cross-sectional views showing a NAND memory cell array taken from lines 22A-22A and 22B-22B, respectively, as shown in Figure 22b, in accordance with one embodiment of the present invention.

Figure 24a is an equivalent circuit diagram of a NAND array. An operational method in accordance with the present invention is described in accordance with one embodiment of the present invention.

Figure 24b is a diagram showing the threshold voltage for resetting the operating time. According to one embodiment of the present invention, it has different initial threshold voltages for two memory cells.

Figure 25 is an equivalent circuit diagram depicting an operational method in accordance with an embodiment of the present invention.

Figure 26 is a graphical representation of the threshold voltage of a memory cell. One embodiment of the invention follows a variety of different erase states.

Figure 27 is an equivalent circuit diagram depicting an operational method in accordance with an embodiment of the present invention.

Figure 28 is a graphical representation of the threshold voltage of a memory cell in accordance with an embodiment of the present invention after various erase states.

Figures 29a and 29b are diagrams showing the drain current of a memory cell. According to one embodiment of the present invention, the various gate voltages are described in a plurality of different turns and are respectively described in a pair of scale gauges and a line. Sex ruler.

Figure 30 is a graphical representation of the threshold voltage of a memory cell in accordance with one embodiment of the present invention after being stored in three different temperature and helium ring states.

Figure 31 is a cross-sectional view showing a NAND array word line in accordance with one embodiment of the present invention; and Figure 32 is a cross-sectional view showing a NAND array word line forming technique in accordance with one embodiment of the present invention.

Figure 33 is the threshold voltage versus the number of peaks of an nMOSFET program. This nMOSFET has an ONO tunneling dielectric layer for several program bias arrangements.

Figure 34 is a graph showing the change in voltage versus negative current for a capacitor having an ONO tunnel dielectric insulator.

Figure 35 is a plot of self-convergence threshold voltage versus erase gate voltage.

Figure 36 is a graph showing the endurance of a memory cell described herein which utilizes high temperature baking of an element in accordance with an embodiment of the present invention.

Figure 37 is a diagram showing the change in the flat band voltage versus the erase time which is biased to the -FN program in an element in accordance with an embodiment of the present invention.

Figure 38 shows the change in the flat band voltage versus the program time. For the +FN program, the biasing class is in an element in accordance with an embodiment of the present invention.

Figure 39 shows the P/E loop endurance of a component in accordance with one embodiment.

Figure 40 illustrates an accelerated storage test of an element in accordance with an embodiment.

Figure 41 shows the charge retention of a charge trapping nitride N2 at one of room temperature and high temperature.

Figure 42 depicts the erase characteristics of the different sized components in accordance with an embodiment.

Figure 43 depicts the erase characteristics of the various gate material components in accordance with an embodiment.

Figure 44 is a schematic top view showing a portion of an exemplary memory array for a thin film charge trapping memory array.

Figure 45 is a schematic cross-sectional view showing a portion of an exemplary array for a thin film transistor charge trapping memory taken along a line from Figure 44.

46A and 46B are schematic cross-sectional views showing an exemplary semiconductor structure for a thin film transistor charge trapping memory taken along line 3-3 of Fig. 44.

Section 46C is a schematic cross-sectional view showing an exemplary process for a thin film transistor charge trapping memory for implanting dopants in a semiconductor body region.

Figure 47 is a schematic cross-sectional view showing a portion of a stacked structure for an example of a thin film transistor charge trapping memory.

Figure 48 is a schematic cross-sectional view showing an exemplary process for a thin film transistor charge trapping memory for creating an inversion layer in a semiconductor body region.

Figures 49A-49B are diagrams showing the electron concentration of the junctionless BE-SONOS NAND implemented as an example of a thin film transistor charge trapping memory.

Figure 50 is a graph showing the measured initial IV curve for an n-channel component of an example of a thin film transistor charge trapping memory.

Figure 51 shows that a heavier well doping concentration can increase the Vt of the junctionless component.

Figures 52A-52B depict the +FN ISPP program and the -FN ISPP erase for a thin film transistor charge trapping memory, respectively.

Figure 53 shows an example p-channel BE-SONOS NAND having a stack structure similar to this N-channel BE-SONOS NAND, which is described in Figure 50 above.

Figure 54A is a plot of threshold voltage vs. program voltage for a -FN ISSPP program.

Figure 54B shows a plot of erase time versus threshold voltage for +FN erase.

Figure 55 is a graph showing the persistence of an exemplary n-channel component of a thin film transistor charge trapping memory.

Figure 56 shows the IV curve of an exemplary TFT BE-SONOS component for a thin film transistor charge trapping memory.

Figure 57 is a simulation diagram showing an example of a junctionless component having a different technology node (F is the half pitch of the polymorph) and having the same space (S = 20 nm) for a thin film transistor charge trapping memory.

305‧‧‧ dielectric layer

310‧‧‧ Tunneling barrier

320‧‧‧Charge storage layer

330‧‧‧ dielectric layer

331‧‧‧ gate insulation

335‧‧‧ gate layer

336‧‧ ‧ gate layer

337‧‧‧ dielectric sidewall

339‧‧‧ dielectric materials

357‧‧‧Array structure

360‧‧‧ dielectric layer

365‧‧‧Semiconductor main area

367‧‧‧Area

368‧‧‧Area

369‧‧‧Area

370a‧‧‧Selection line

370b‧‧‧Selection line

370c‧‧‧ character line

371‧‧‧ gate insulation

372‧‧‧ Tunneling barrier

374‧‧‧Charge storage layer

376‧‧‧ dielectric layer

380‧‧ ‧ gate layer

381‧‧‧ gate layer

382‧‧‧ dielectric sidewall

384‧‧‧ dielectric materials

401‧‧‧Base

410‧‧‧Semiconductor main area

412a‧‧‧Area

414‧‧‧Area

415‧‧‧ area

420a‧‧‧Selection line

420b‧‧‧Selection line

420c‧‧‧ character line

Claims (22)

A semiconductor structure comprising: a plurality of first semiconductor body regions in a substrate, the plurality of first semiconductor body regions having a first doped state; a first select line and a second select line, substantially vertical In the first semiconductor body region; a plurality of first word lines are located between the first selection line and the second selection line, and each of the plurality of first word lines covers the first semiconductor body regions a channel region and substantially perpendicular to the first semiconductor body regions, a space between each first word line is no more than 75 nm; a first tunneling energy barrier structure, a first charge storage layer, and a first a dielectric layer is located between each of the first word lines and the corresponding first semiconductor body region, and a corresponding channel region is located within the first semiconductor body region; at least one of the junctions Within the first semiconductor body region, wherein the at least one junction is adjacent to the first selection line, the at least one mask has a second doped state; and wherein the junction and the second selection line Corresponding None of the semiconductor body surface area-based. The semiconductor structure of claim 1, further comprising a plurality of trench structures adjacent to and substantially parallel to the first semiconductor body regions, each of the trench structures separating two adjacent first semiconductors Body area. The semiconductor structure of claim 1, wherein the first tunneling energy barrier structure comprises a tunneling dielectric structure having a tunneling tunnel at an interface with the corresponding semiconductor body region can The height of the barrier, and the height of the tunneling barrier at a distance away from the interface is less than the height of the tunneling barrier at the interface. The semiconductor structure of claim 1, wherein the first tunneling barrier structure, the first charge storage layer, and the first dielectric layer are an ONONO structure. The semiconductor structure of claim 1, wherein the substrate comprises an oxide layer, wherein the oxide layer is on the substrate and under the first semiconductor body region. The semiconductor structure of claim 1, further comprising: a second insulating layer on the first word lines; a plurality of second semiconductor body regions having the first doped state and covering The second insulating layer; the plurality of second word lines are between a third select line and a fourth select line, the third select line and the fourth select line being substantially perpendicular to the second semiconductor body region And a second tunneling barrier structure, a second charge storage layer, and a second dielectric layer between the second word line and the second semiconductor body region; at least one The second junction is adjacent to the second semiconductor body region, the at least one second junction is adjacent to the third selection line, and the at least one second mask has a second doped state; and wherein The second semiconductor body region corresponding between the second junction and the fourth selection line is a junctionless surface. A method of forming a semiconductor structure, comprising: forming a plurality of first semiconductor body regions implanted on a substrate using a first doped state; forming a plurality of first word lines on a first select line and a Between the second selection lines, the first word line, the first selection line, and the second selection line cover the first semiconductor body regions; forming a first tunneling energy barrier structure, a first a charge storage layer and a first dielectric layer between the first semiconductor body regions and the first word lines; forming a first dielectric sidewall on a sidewall of the first selection line and the second selection a sidewall of one of the lines; forming a first source/drain junction adjacent to the first select line and the second select line, and having a second doped state; and wherein the two adjacent The plurality of regions in the first semiconductor body regions between the word lines are no junctions, and the space between two adjacent word lines is no more than 75 nm. The method of claim 7, wherein forming the first dielectric sidewall comprises forming a first dielectric material between two adjacent first word lines. The method of claim 7, wherein forming the first source/drain region comprises using the first dielectric sidewall as an implant mask. The method of claim 7, further comprising forming a plurality of trench structures substantially parallel to the first semiconductor body region. The method of claim 7, wherein the forming the first source/drain junction comprises: forming a patterned mask layer covering at least a portion of the first and second select lines and The first word line; and implanting the first doped dopant to the first semiconductor body regions, wherein the patterned mask layer is used as an implant mask. The method of claim 7, wherein forming the first tunneling barrier structure comprises forming a tunneling dielectric structure having a multilayer or composite composition and being between the first semiconductor body region and the first semiconductor body region One of the interfaces has a hole tunneling barrier height, and a hole tunneling barrier height at a distance away from the interface is smaller than the hole tunneling barrier height of the interface. The method of claim 7, further comprising forming an oxide layer between the substrate and the first semiconductor body regions. The method of claim 7, further comprising: forming a second insulating layer on the first word line; forming a plurality of second semiconductor body regions having the first doped state and located a plurality of second word lines are formed between a third selection line and a fourth selection line, and the second word line, the third selection line, and the fourth selection line are substantially Vertically surrounding and over the second semiconductor body regions; forming a second tunneling barrier structure, a second charge storage layer and a second dielectric layer on the second semiconductor regions and the second words Yuan line Forming a second dielectric sidewall on one of the sidewalls of the third select line and a sidewall of the fourth select line; and forming a second source/drain region having the second doping And adjacent to the third selection line and the fourth selection line. The method of claim 14, wherein forming the second dielectric sidewall comprises forming a second dielectric material between two adjacent second word lines. The method of claim 14, wherein forming the second source/drain (S/D) region comprises using the second dielectric sidewall as an implant mask. The method of claim 7, wherein the forming the first source/drain region comprises using the first dielectric layer as a implant barrier layer to implant a dopant in the second doped state to The first semiconductor body regions prevent implanting the dopants in the first semiconductor body regions of the two adjacent first word lines. The method of claim 7, wherein the method does not include a first semiconductor for forming a common source/drain region between two adjacent first word lines Embedding program in the main area. A method of operating a semiconductor structure, the semiconductor structure comprising a plurality of parallel semiconductor body regions on a substrate; a plurality of word lines between a first select line and a second select line, the word lines comprising a selected word line and a plurality of unselected word lines, the word lines, the first selection line and the second selection line are substantially perpendicular to the semiconductor body regions; and a tunneling energy a barrier structure, a charge storage layer and a dielectric layer between the word lines and the semiconductor body regions, wherein the semiconductor body regions comprise at least a first region adjacent to the first selection line and the a second selection line, and a second region between the two adjacent word lines, wherein the first region has a doping concentration that is higher than a doping concentration in the second region, and wherein at least One of the second regions is a junctionless surface, the method comprising: applying a first voltage to the first selection line and the second selection line; applying a second voltage to the word lines, the first voltage system Higher than the second voltage; and applying a third voltage to the semiconductor body regions to reset the semiconductor structure, the third voltage being higher than the second voltage. The method of claim 19, further comprising: applying a fourth voltage to the selected word line; applying a fifth voltage to at least one of the unselected word lines to induce At least one inversion layer between the word lines, the fourth voltage is higher than the fifth voltage to inject a charge into the charge storage layer; and one of the semiconductor body regions is grounded, and is coupled to The second region adjacent to the selected character line. The method of claim 20, further comprising: applying a sixth voltage to the selected word line, the sixth voltage is less than the fifth voltage; applying a seventh voltage to the unselected Character line, the seventh power The voltage system is higher than the sixth voltage; and an eighth voltage is applied to the grounded semiconductor body region to read a state stored in one of the charge storage layers, the eighth voltage being lower than the sixth voltage. The method of claim 19, further comprising: applying a sixth voltage to the first selection line and the second selection line; applying a seventh voltage to the word lines, the sixth The voltage system is higher than the seventh voltage; and the semiconductor body region is floated to erase the charge stored in the charge storage layer.