CN109216362A - Flash memories and preparation method thereof - Google Patents

Flash memories and preparation method thereof Download PDF

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Publication number
CN109216362A
CN109216362A CN201710525672.8A CN201710525672A CN109216362A CN 109216362 A CN109216362 A CN 109216362A CN 201710525672 A CN201710525672 A CN 201710525672A CN 109216362 A CN109216362 A CN 109216362A
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floating gate
window
polycrystal layer
layer
flash memories
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CN109216362B (en
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梁志彬
张松
刘涛
金炎
王德进
王成
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CSMC Technologies Corp
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CSMC Technologies Corp
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Priority to PCT/CN2018/093701 priority patent/WO2019001570A1/en
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

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  • Semiconductor Memories (AREA)

Abstract

The present invention relates to a kind of flash memories and preparation method thereof.Preparation method includes: to sequentially form floating gate oxide layers, floating gate polycrystal layer and barrier layer on a semiconductor substrate;It is sequentially etched barrier layer, floating gate polycrystal layer formation window, window extends in floating gate polycrystal layer;The floating gate polycrystal layer for being exposed to window area is pre-processed, the depth for making floating gate polycrystal layer be recessed to along the direction of floating gate oxide layers, and being recessed is tapered off trend from the center of the window area to both sides of the edge;The first field oxide is formed, and fills up the window in floating gate polycrystal layer;Etching forms the floating gate for having discharging sharp-angle.The above method is by pre-processing the floating gate polycrystal layer for being exposed to window area, set low the thickness for being exposed to outer floating gate polycrystal layer in interposition, and the trend that both sides of the edge position is high, subsequent floating gate polycrystal layer is oxidized to form field oxide, and the discharging sharp-angle for etching formation is more sharp keen compared with the discharging sharp-angle that conventional method is prepared.

Description

Flash memories and preparation method thereof
Technical field
The present invention relates to technical field of semiconductors, more particularly to flash memories and preparation method thereof.
Background technique
Flash memories fever erasing mechanism be by adding high pressure in selection grid, with tunnelling (Fowler Nordheim, FN) mode is realized, when floating gate tip is sharper, electric field is bigger, and barrier width is smaller, the easier tunnelling of electronics, flash memories It is better to wipe performance.
In the traditional handicraft of production floating gate, oxidation window is etched to floating gate mask layer, the depth for aoxidizing window is bigger In the thickness of floating gate mask layer.At oxidation window, oxidation processes are done to floating gate polycrystal layer, form silicon dioxide layer.Due to oxygen The floating gate polycrystal layer changed at window is plane, in oxidation process, region that floating gate polycrystal layer is oxidized and floating gate polycrystal layer not by The interface of oxidation is arc surface.When removing the floating gate polycrystal layer formation floating gate except window, the ratio of the discharging sharp-angle of floating gate It is more blunt, it is easy to be caused memory erasing performance unstable by the fluctuation of other techniques.
Summary of the invention
Based on this, it is necessary to for the problem that the discharging sharp-angle of floating gate is more blunt, it is sharp keen and wipe to provide a kind of discharging sharp-angle The good flash memories and preparation method thereof of performance.
A kind of preparation method of flash memories, comprising:
Floating gate oxide layers, floating gate polycrystal layer and barrier layer are sequentially formed on a semiconductor substrate;
It is sequentially etched the barrier layer, floating gate polycrystal layer formation window, the window extends in the floating gate polycrystal layer;
The floating gate polycrystal layer for being exposed to the window area is pre-processed, makes the floating gate polycrystal layer to along institute The direction recess of floating gate oxide layers is stated, and the depth of the recess is presented from the center of the window area to both sides of the edge Subtract trend;
Form the first field oxide, and the window being located in the floating gate polycrystal layer;
Etching forms the floating gate for having discharging sharp-angle.
The preparation method of above-mentioned flash memories pre-processes the floating gate polycrystal layer for being exposed to window area, makes sudden and violent The floating gate polycrystal layer to expose outside is recessed to along the direction of the floating gate oxide layers, and makes the depth of recess from center to two sides Edge tapers off trend, sets low the thickness for being exposed to outer floating gate polycrystal layer in interposition, and both sides of the edge position is high becomes Gesture, subsequent floating gate polycrystal layer are oxidized to form field oxide, and the discharging sharp-angle for etching formation is put compared with what conventional method was prepared Electric wedge angle is more sharp keen.
The described pair of floating gate polycrystal layer for being exposed to the window area is located in advance in one of the embodiments, Reason, comprising:
Using the barrier layer as mask plate, isotropic dry etch is carried out to the window.
The described pair of floating gate polycrystal layer for being exposed to the window area is located in advance in one of the embodiments, Reason, comprising:
The second field oxide is generated using boiler tube thermal oxide to the floating gate polycrystal layer for being exposed to the window area;
Wet etching is carried out to second field oxide.
The concave face for being exposed to the outer floating gate polycrystal layer in one of the embodiments, is arc surface.
The concave face for being exposed to the outer floating gate polycrystal layer in one of the embodiments, has gradual change trend by multiple Plane or curved surface constitute.
The angular range of the concave face and the window both sides of the edge is 75~80 degree in one of the embodiments,.
The range of the discharging sharp-angle is 40~50 degree in one of the embodiments,.
Etching forms the floating gate for having discharging sharp-angle in one of the embodiments, comprising:
Removal is located at the barrier layer above the floating gate polycrystal layer;
The floating gate polycrystal layer outside the window area, floating gate oxide layers are performed etching and to be formed with discharge tip The floating gate at angle.
In one of the embodiments, further include:
Tunnel oxide is formed in the semiconductor substrate, floating gate polycrystal layer two sides and field oxide;
Selection grid is formed on the tunnel oxide.
In addition, also providing a kind of flash memories, flash memories flash memory as described in any of the above-described embodiment is deposited The production method of reservoir is made.
Detailed description of the invention
Fig. 1 is the flow chart of the preparation method of flash memories in an example;
Fig. 2-Figure 12 is the structural schematic diagram in an example in flash memories manufacturing process.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and It is not used in the restriction present invention.
Fig. 1 is the flow chart of the preparation method of flash memories in an example.In embodiments of the present invention, flash memory storage The preparation method of device, includes the next steps:
Step S110: floating gate oxide layers, floating gate polycrystal layer and barrier layer are sequentially formed on a semiconductor substrate.
With reference to Fig. 2, provide semiconductor substrate 210, semiconductor substrate 210 can be silicon substrate, or germanium, germanium silicon, SiGe or gallium arsenide substrate can also be silicon-on-insulator (Silicon-on-insulator, SOI) substrate etc..It is real one It applies in example, semiconductor substrate 210 is to prepare the substrate of floating gate, and floating gate is the component units of flash memories, due to its flash memory Memory as carrier, is formed with p-type doping well region in semiconductor substrate 210, after semiconductor substrate 210 is used as using electronics The continuous platform for forming flush memory device.
Floating gate oxide layers 220 are formed in semiconductor substrate 210.Wherein, the material of floating gate oxide layers 220 can be oxidation Silicon, silicon nitride, silicon oxynitride or other high-g values.In the present embodiment, floating gate oxide layers 220 are silicon oxide layer.Floating gate oxidation The forming method of layer 220 can be boiler tube thermal oxide, atomic layer deposition (Atomic Layer Deposition, ALD), chemistry Vapor deposition (Chemical Vapor Deposition, CVD), plasma-enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) etc., in the present embodiment, select boiler tube thermal oxide to generate floating Gate oxide 220.
The depositing polysilicon in floating gate oxide layers 220, as the floating gate polycrystal layer 230 for preparing floating gate.
In 230 layers of floating gate polycrystal layer upper deposit silicon nitride, silicon nitride layer is formed, as barrier layer 240.
Step S120: being sequentially etched barrier layer, floating gate polycrystal layer formation window, and window extends in floating gate polycrystal layer.
With reference to Fig. 3, it is more that barrier layer 240, floating gate be sequentially etched using etching technics in the band of position for needing to make floating gate Crystal layer 230 forms window 231.Wherein, window 231 runs through barrier layer 240, and extends in floating gate polycrystal layer 230.
Wherein, dry etching can be used by forming 231 etching technics of window.Dry etching is to carry out film with plasma Not only there is equal sides' property of chemical reaction but also the different side there are physical reactions when being dry-etched in etching surface material in the technology of etching Property.Just because of the unique way that this physical reactions of dry etching and chemical reaction combine, in anisotropy and isotropic phase Under interaction, the size and shape of figure can be accurately controlled.
Step S130: the floating gate polycrystal layer for being exposed to window area is pre-processed, makes floating gate polycrystal layer to along floating gate The direction of oxide layer is recessed, and the depth being recessed is tapered off trend from the center of the window area to both sides of the edge.
With reference to Fig. 4, the floating gate oxide layers 230 for being exposed to 231 region of window are pre-processed, make to be exposed to outer floating gate Polycrystal layer 230 is recessed to along the direction of floating gate oxide layers 220, and makes the depth of recess by the center O of the window area To both sides of the edge (A, A '), taper off trend.That is, keep the thickness for being exposed to outer floating gate polycrystal layer 230 low in middle position O, And both sides of the edge position (A, A ') high trend.So in the subsequent process, so that it may be formed than relatively sharp floating gate discharging point Angle.
In one embodiment, the concave face for being exposed to outer floating gate polycrystal layer 230 is arc surface.
In one embodiment, the concave face for being exposed to outer floating gate polycrystal layer 230 has multiple putting down with gradual change trend Face is constituted, with reference to Fig. 5.Wherein, the tilt angle relative to 210 place plane of semiconductor substrate of each plane becomes in gradual change Gesture.
Optionally, the concave face for being exposed to outer floating gate polycrystal layer 230 has multiple curved surfaces with gradual change trend to constitute, respectively The radius of curvature of a curved surface is in gradual change trend.
In one embodiment, the concave face of outer floating gate polycrystal layer 230 and the angle of 231 both sides of the edge of window are exposed to Range Theta is 75~80 degree.With reference to Fig. 6, in sectional view, concave face is a camber line, and camber line is handed over in 231 both sides of the edge of window The tangent line at point place and the angle theta range at 231 edge of window are 75~80 degree, that is, camber line and in 231 both sides of the edge intersection point of window The tangent line at place is 10~15 degree with the angular range φ of horizontal line (parallel with substrate).Specifically, camber line in 231 two sides of window The tangent line of edge point of intersection is 12 degree with the angular range of horizontal line (parallel with substrate).
Step S140: the first field oxide, and the window 231 being located in floating gate polycrystal layer 230 are formed.
With reference to Fig. 7, oxidation processes are carried out to the floating gate polycrystal layer 230 being exposed at window 231, make its oxide full of position In the window 231 in floating gate polycrystal layer 230.Since floating gate polycrystal layer 230 is formed by polycrystalline silicon deposit, the oxidation of polysilicon is produced Object forms the first field oxide 250 in window 231.
It is plane since traditional floating gate polycrystal layer 230 is exposed to 231 region of window, and in embodiments of the present invention, Be exposed to 231 region of window floating gate polycrystal layer 230 be concave face, oxidizing condition under the same conditions, the polycrystalline of consumption Identical silicon is A degree, such as Fig. 8 a (conventional preparation techniques) and 8b (preparation process of the embodiment of the present invention).Traditional floating gate polycrystalline Layer 230 is oxidized to form the range of field oxide as indicated at a, i.e., it is a that subsequent etching, which is formed by the angular dimension of discharging sharp-angle,. And in the embodiment of the present invention, being exposed to the floating gate polycrystal layer 230 in 231 region of window is concave face, is oxidized to form field oxidation Also as indicated at a, i.e., it is b that subsequent etching is formed by the angular dimension of discharging sharp-angle to the range of layer.Obviously, in the embodiment of the present invention The angle b for being formed by discharging sharp-angle is less than the angle a of discharging sharp-angle made of prepared by traditional handicraft, the embodiment of the present invention Formed in discharging sharp-angle angle b it is more sharp keen, when flash memories carry out erasing operation when, will form bigger electricity , electronics is more advantageous to carry out tunnelling, to obtain a preferably erasing performance.
Step S150: etching forms the floating gate for having discharging sharp-angle.
In one embodiment, etching forms the floating gate for having discharging sharp-angle, including removal is located on floating gate polycrystal layer 230 The barrier layer 240 of side;Floating gate polycrystal layer 230 outside 231 region of window, floating gate oxide layers 220 are performed etching and to form band There is the step of floating gate of discharging sharp-angle.
With reference to Fig. 9, wet chemistry removing removal barrier layer 240 is carried out using hot phosphoric acid.It is then floating to aoxidize with reference to Figure 10 The field oxide that grid polycrystal layer 230 is formed is exposure mask, and dry etching removes floating gate polycrystalline made of deposit outside field oxide region Layer 230 and floating gate oxide layers 220, to form the floating gate for having discharging sharp-angle.
In one embodiment, field oxide is symmetrical structure, left side discharging sharp-angle θ 1 and right 2 side discharge tip of θ The angle at angle is also identical.
In one embodiment, the angular range of left side discharging sharp-angle θ 1 and right 2 side discharging sharp-angle of θ is at 40 degree~50 degree.Tool Body, the angle of left side discharging sharp-angle θ 1 and right 2 side discharging sharp-angle of θ is 45 degree.
By the above method, the window 231 for being located at floating gate polycrystal layer 230 is pre-processed, makes to be exposed to outer floating gate polycrystalline Layer 230 is recessed to along the direction of floating gate oxide layers 220, and the depth of recess is made to taper off from center to both sides of the edge Gesture can make 40 degree~50 degree of angular range of discharging sharp-angle (θ 1, θ 2), be stablized with increasing erasable and writing speed and efficiency and enhancing Property.
In one embodiment, the floating gate polycrystal layer 230 for being exposed to 231 region of window is pre-processed, is specifically included Using barrier layer 240 as mask plate, to window 231 carry out isotropic dry etch the step of.
Using barrier layer 240 as mask plate, using plasma dry etching is more to the floating gate for being exposed to 231 region of window Crystal layer 230 performs etching.Not only there is equal sides' property of chemical reaction when being dry-etched in etching surface material but also there are physical reactions Anisotropy.Just because of the unique way that this physical reactions of dry etching and chemical reaction combine, in anisotropy and grade side Property interaction under, can the accurate removal of being etched figure size and shape.
In one embodiment, the floating gate polycrystal layer 230 for being exposed to 231 region of window is pre-processed and can also be wrapped It includes: the second field oxide is generated using boiler tube thermal oxide to the floating gate polycrystal layer 230 for being exposed to window 231;To the second field oxidation Layer carries out the step of wet etching.
Floating gate polycrystal layer is aoxidized by the way of boiler tube thermal oxide to the floating gate polycrystal layer 230 for being exposed to 231 region of window 230, so that it is generated the second field oxide, then etch areas is located at 231st area of window in such a way that hydrofluoric acid carries out wet etching Second field oxide in domain, and then form required graphics shape and size.
In one embodiment, preparation method further includes the steps that carrying out n-type doping to floating gate.
In the present embodiment, floating gate polycrystal layer 230 is polysilicon layer, and the forming method of floating gate can be chemical vapor deposition (CVD).After forming multi-crystal silicon floating bar, it can be doped.Due to tunnelling carrier be electronics, to floating gate into Row n-type doping, Doped ions can be the pentads such as phosphorus, antimony and arsenic.
In one embodiment, preparation method further include: in semiconductor substrate 210,230 two sides of floating gate polycrystal layer and field Tunnel oxide is formed in oxide layer;In the step of forming selection grid on tunnel oxide.
With reference to Figure 11, tunnel oxide is formed in semiconductor substrate 210,230 two sides of floating gate polycrystal layer and field oxide Layer 260.Tunnel oxide 260 can also be silicon nitride, silicon oxynitride or other high-g values.The forming method of tunnel oxide It can be boiler tube thermal oxide, atomic layer deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition etc., in this reality It applies in example, boiler tube thermal oxide is selected to generate tunnel oxide 260.
With reference to Figure 12, depositing polysilicon forms selection grid on the tunnel oxide 260 outside floating gate and the floating gate band of position Polysilicon chemical wet etching removal part selection gate polysilicon, forms control gate 270.
In addition, also providing a kind of flash memories, flash memories are by such as the flash memories of above-mentioned any embodiment Production method is made.The discharging sharp-angle of floating gate is sharp keen, when flash memories carry out erasing operation, will form bigger electric field, Electronics is more advantageous to carry out tunnelling, to obtain a preferably erasing performance.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention Range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.

Claims (10)

1. a kind of preparation method of flash memories characterized by comprising
Floating gate oxide layers, floating gate polycrystal layer and barrier layer are sequentially formed on a semiconductor substrate;
It is sequentially etched the barrier layer, floating gate polycrystal layer formation window, the window extends in the floating gate polycrystal layer;
The floating gate polycrystal layer for being exposed to the window area is pre-processed, makes the floating gate polycrystal layer to along described floating The direction of gate oxide is recessed, and the depth of the recess tapers off from the center of the window area to both sides of the edge Gesture;
The first field oxide is formed, the window in the floating gate polycrystal layer;
Etching forms the floating gate for having discharging sharp-angle.
2. the preparation method of flash memories according to claim 1, which is characterized in that described pair is exposed to the window The floating gate polycrystal layer in region is pre-processed, comprising:
Using the barrier layer as mask plate, isotropic dry etch is carried out to the window.
3. the preparation method of flash memories according to claim 1, which is characterized in that described pair is exposed to the window The floating gate polycrystal layer in region is pre-processed, comprising:
The second field oxide is generated using boiler tube thermal oxide to the floating gate polycrystal layer for being exposed to the window area;
Wet etching is carried out to second field oxide.
4. the preparation method of flash memories according to claim 1, which is characterized in that it is more to be exposed to the outer floating gate The concave face of crystal layer is arc surface.
5. the preparation method of flash memories according to claim 1, which is characterized in that it is more to be exposed to the outer floating gate The concave face of crystal layer is made of multiple planes with gradual change trend or curved surface.
6. the preparation method of flash memories according to claim 4 or 5, which is characterized in that the concave face with it is described The angular range of window both sides of the edge is 75~80 degree.
7. the preparation method of flash memories according to claim 1, which is characterized in that the range of the discharging sharp-angle is 40~50 degree.
8. the preparation method of flash memories according to claim 1, which is characterized in that etching, which is formed, has discharging sharp-angle Floating gate, comprising:
Removal is located at the barrier layer above the floating gate polycrystal layer;
The floating gate polycrystal layer outside the window area, floating gate oxide layers are performed etching and to be formed with discharging sharp-angle Floating gate.
9. the production method of flash memories according to claim 1, which is characterized in that further include:
Tunnel oxide is formed in the semiconductor substrate, floating gate polycrystal layer two sides and field oxide;
Selection grid is formed on the tunnel oxide.
10. a kind of flash memories, which is characterized in that the flash memories are by sudden strain of a muscle as described in any one of claims 1 to 9 The production method for depositing memory is made.
CN201710525672.8A 2017-06-30 2017-06-30 Flash memory and preparation method thereof Active CN109216362B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113257677A (en) * 2021-05-19 2021-08-13 上海华虹宏力半导体制造有限公司 Split-gate flash memory and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6667509B1 (en) * 1998-01-09 2003-12-23 Taiwan Semiconductor Manufacturing Company Method of forming sharp beak of poly by oxygen/fluorine implant to improve erase speed for split-gate flash
CN101170082A (en) * 2006-10-23 2008-04-30 上海华虹Nec电子有限公司 Making technology method for flash memory
CN105679713A (en) * 2016-04-26 2016-06-15 上海华虹宏力半导体制造有限公司 Method for manufacturing flash memories
CN106783866A (en) * 2017-01-05 2017-05-31 上海华虹宏力半导体制造有限公司 The manufacture method of flush memory device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6667509B1 (en) * 1998-01-09 2003-12-23 Taiwan Semiconductor Manufacturing Company Method of forming sharp beak of poly by oxygen/fluorine implant to improve erase speed for split-gate flash
CN101170082A (en) * 2006-10-23 2008-04-30 上海华虹Nec电子有限公司 Making technology method for flash memory
CN105679713A (en) * 2016-04-26 2016-06-15 上海华虹宏力半导体制造有限公司 Method for manufacturing flash memories
CN106783866A (en) * 2017-01-05 2017-05-31 上海华虹宏力半导体制造有限公司 The manufacture method of flush memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113257677A (en) * 2021-05-19 2021-08-13 上海华虹宏力半导体制造有限公司 Split-gate flash memory and manufacturing method thereof

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WO2019001570A1 (en) 2019-01-03

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