WO2019001570A1

WO2019001570A1 - Flash memory and preparation method therefor

Info

Publication number: WO2019001570A1
Application number: PCT/CN2018/093701
Authority: WO
Inventors: 梁志彬; 刘涛; 张松; 金炎; 王德进; 王成
Original assignee: 无锡华润上华科技有限公司
Priority date: 2017-06-30
Filing date: 2018-06-29
Publication date: 2019-01-03
Also published as: CN109216362B; CN109216362A

Abstract

A flash memory and a preparation method therefor. The preparation method comprises: sequentially forming a floating gate oxide layer, a floating gate polycrystalline layer and a barrier layer on a semiconductor substrate; sequentially etching the barrier layer and the floating gate polycrystalline layer to form a window, the window extending into the floating gate polycrystalline layer; pre-treating the floating gate polycrystalline layer exposed at a window region, so that the floating gate polycrystalline layer recesses in the direction of the floating gate oxide layer and the depth of the recess decreases from the middle position to the edges of the two sides of the window region; forming a first field oxide layer and filling a window in the floating gate polycrystalline layer; and carrying out etching to form a floating gate having a discharging sharp angle.

Description

Flash memory and preparation method thereof

Technical field

The present invention relates to the field of semiconductor technology, and in particular to a flash memory and a method of fabricating the same.

Background technique

The flash memory heat erasing mechanism is realized by tunneling (Fowler Nordheim, FN) by applying high voltage to the selection gate. When the tip of the floating gate is sharper, the electric field is larger, the smaller the barrier width is, the easier the electrons are tunneled. The better the erase performance of the flash memory.

In the conventional process of fabricating a floating gate, an oxidation window is etched to the floating gate mask layer, and the depth of the oxidation window is slightly larger than the thickness of the floating gate mask layer. At the oxidation window, the floating gate polycrystalline layer is oxidized to form a silicon dioxide layer. Since the floating gate polycrystalline layer at the oxidation window is planar, during the oxidation process, the interface where the floating gate polycrystalline layer is oxidized and the floating gate polycrystalline layer are not oxidized is a circular arc surface. When the floating gate polycrystalline layer outside the window is formed to form a floating gate, the discharge tip angle of the floating gate is relatively blunt, and the memory erasing performance is unstable due to fluctuations of other processes.

Summary of the invention

According to various embodiments of the present application, a flash memory and a method of fabricating the same are provided.

A method of preparing a flash memory, comprising:

Forming a floating gate oxide layer, a floating gate polycrystalline layer, and a barrier layer on the semiconductor substrate;

Etching the barrier layer, the floating gate polycrystalline layer to form a window, the window extending into the floating gate polycrystalline layer;

Pre-treating the floating gate poly layer exposed to the window region such that the floating gate poly layer is recessed in a direction along the floating gate oxide layer, and the depth of the recess is defined by the window region The center position is decreasing toward both sides;

Forming a first field oxide layer and the window located within the floating gate poly layer;

The etching forms a floating gate with a discharge sharp corner.

The above method for preparing a flash memory is to pretreat a floating gate poly layer exposed to a window region such that the exposed floating gate poly layer is recessed in a direction along the floating gate oxide layer, and the depth of the recess is centered The position is decreasing toward both sides, so that the thickness of the exposed floating gate polycrystalline layer is low in the middle position, and the edge positions on both sides are high, and the subsequent floating gate polycrystalline layer is oxidized to form a field oxide layer, and is formed by etching. The discharge sharp angle is sharper than the discharge sharp angle prepared by the conventional method.

A flash memory produced by the method of fabricating the flash memory of any of the above embodiments.

DRAWINGS

To better describe and illustrate the embodiments and/or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the figures are not to be construed as limiting the scope of any of the disclosed inventions, the presently described embodiments and/or examples, and the best mode of the invention.

1 is a flow chart showing a method of preparing a flash memory in an example;

2 to 12 are structural diagrams of a flash memory fabrication process in an example.

Detailed ways

In order to make the objects, technical solutions, and advantages of the present application more comprehensible, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the application and are not intended to be limiting.

1 is a flow chart of a method of fabricating a flash memory in an example. In the embodiment of the present application, a method for preparing a flash memory includes the following steps:

Step S110: sequentially forming a floating gate oxide layer, a floating gate polycrystalline layer, and a barrier layer on the semiconductor substrate.

Referring to FIG. 2, a semiconductor substrate 210 is provided. The semiconductor substrate 210 may be a silicon substrate, or may be a germanium, germanium silicon, silicon germanium or gallium arsenide substrate, or may be a silicon-on-insulator (Silicon-on-insulator). , SOI) substrate, etc. In one embodiment, the semiconductor substrate 210 is a substrate for preparing a floating gate, and the floating gate is a constituent unit of the flash memory. Since the flash memory uses electrons as carriers, a p-type doped well is formed in the semiconductor substrate 210. The semiconductor substrate 210 serves as a platform for subsequent formation of flash memory devices.

A floating gate oxide layer 220 is formed on the semiconductor substrate 210. The material of the floating gate oxide layer 220 may be silicon oxide, silicon nitride, silicon oxynitride or other high-k materials. In the present embodiment, the floating gate oxide layer 220 is a silicon oxide layer. The floating gate oxide layer 220 can be formed by thermal oxidation of the tube, Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical (Plasma Enhanced Chemical). Vapor Deposition, PECVD), etc., in this embodiment, the furnace oxide is thermally oxidized to form the floating gate oxide layer 220.

Polysilicon is deposited over the floating gate oxide layer 220 as a floating gate polycrystalline layer 230 for the fabrication of the floating gate.

Silicon nitride is deposited on the floating gate polycrystalline layer 230 layer to form a silicon nitride layer as the barrier layer 240.

Step S120: sequentially etching the barrier layer and the floating gate polycrystalline layer to form a window, and the window extends into the floating gate polycrystalline layer.

Referring to FIG. 3, the barrier layer 240 and the floating gate polycrystalline layer 230 are sequentially etched by an etching process in a region where the floating gate is required to form a window 231. The window 231 extends through the barrier layer 240 and extends into the floating gate poly layer 230.

The etching process for forming the window 231 can be performed by dry etching. Dry etching is a technique of plasma etching using plasma. Dry etching has both an isotropic chemical reaction and an anisotropy of physical reaction when etching a surface material. Because of the unique combination of physical and chemical reactions, dry etching can precisely control the size and shape of the pattern under the interaction of anisotropic and isotropic.

Step S130: pre-treating the floating gate poly layer exposed to the window region, causing the floating gate poly layer to be recessed in a direction along the floating gate oxide layer, and the depth of the recess is from the center position of the window region to both side edges The trend is decreasing.

Referring to FIG. 4, the floating gate oxide layer 230 exposed to the window 231 region is pretreated such that the exposed floating gate poly layer 230 is recessed in the direction along the floating gate oxide layer 220, and the depth of the recess is made by the window. The central position O of the area is decreasing toward both side edges (A, A'). That is, the thickness of the floating gate polycrystalline layer 230 exposed is low in the middle position O, and the edge position (A, A') is high. In this way, in the subsequent process, a relatively sharp floating gate discharge sharp angle can be formed.

In one embodiment, the recessed surface of the exposed floating gate polycrystalline layer 230 is a circular arc surface.

In one embodiment, the recessed face of the exposed floating gate polycrystalline layer 230 is comprised of a plurality of planes having a gradual tendency, with reference to FIG. Wherein, the inclination angle of each plane with respect to the plane of the semiconductor substrate 210 is gradually changing.

Optionally, the exposed surface of the exposed floating gate polycrystalline layer 230 is formed by a plurality of curved surfaces having a gradual tendency, and the radius of curvature of each curved surface is gradually changed.

In one embodiment, the angle of the angle θ between the recessed surface of the exposed floating gate polycrystalline layer 230 and the edges of the window 231 is 75 to 80 degrees. Referring to FIG. 6, in the cross-sectional view, the concave surface is an arc, and the angle θ between the tangent at the intersection of the edges of the window 231 and the edge of the window 231 ranges from 75 to 80 degrees, that is, the arc is in the window. The angle between the tangent at the intersection of the two side edges and the horizontal line (parallel to the substrate) is φ 10 to 15 degrees. In one embodiment, the angle between the tangent at the intersection of the edges of the edges of the window 231 and the horizontal line (parallel to the substrate) is in the range of 12 degrees.

Step S140: forming a first field oxide layer at the window 231 in the floating gate polycrystalline layer 230.

Referring to FIG. 7, the floating gate polycrystalline layer 230 exposed at the window 231 is oxidized to fill its window 231 in the floating gate polycrystalline layer 230. Since the floating gate polycrystalline layer 230 is deposited from polysilicon, its polysilicon oxidation product forms a first field oxide layer 250 within the window 231.

Since the conventional floating gate polycrystalline layer 230 is exposed to the plane of the window 231, in the embodiment of the present application, the floating gate polycrystalline layer 230 exposed in the window 231 region is a concave surface under the same oxidation conditions. The polysilicon consumed is the same as the A degree, as shown in FIG. 8a (conventional preparation process) and 8b (preparation process of the embodiment of the present application). The range in which the conventional floating gate polycrystalline layer 230 is oxidized to form a field oxide layer is as shown in A, that is, the angle of the discharge sharp angle formed by the subsequent etching is a. In the embodiment of the present application, the floating gate polycrystalline layer 230 exposed in the window 231 region is a concave surface, and the range of being oxidized to form the field oxide layer is also as shown in A, that is, the angle of the discharge sharp angle formed by the subsequent etching. The size is b. Obviously, the angle b of the discharge sharp angle formed in the embodiment of the present application is smaller than the angle a of the discharge sharp angle prepared by the conventional process, and the angle b of the discharge sharp angle formed in the embodiment of the present application is sharper. When the flash memory is erased, a larger electric field is formed, and the electrons are more favorable for tunneling, thereby obtaining a better erasing performance.

Step S150: etching forms a floating gate with a discharge sharp corner.

In one embodiment, etching forms a floating gate with a discharge sharp corner, including removing the barrier layer 240 over the floating gate poly layer 230; oxidizing the floating gate polycrystalline layer 230 outside the window 231 region, floating gate Layer 220 is etched to form a floating gate with a discharge sharp corner.

Referring to Figure 9, the barrier layer 240 is removed by wet chemical stripping using hot phosphoric acid. Referring to FIG. 10, the field oxide layer formed by the oxide floating gate polycrystalline layer 230 is used as a mask, and the floating gate polycrystalline layer 230 and the floating gate oxide layer 220 deposited outside the field oxide layer region are removed by dry etching. Thereby a floating gate with a discharge sharp corner is formed.

In one embodiment, the field oxide layer is a bilaterally symmetric structure, and the left discharge tip angle θ1 and the right discharge tip angle θ2 are also the same.

In one embodiment, the angle between the left discharge tip angle θ1 and the right discharge tip angle θ2 ranges from 40 degrees to 50 degrees. Specifically, the angles of the left discharge tip angle θ1 and the right discharge tip angle θ2 are both 45 degrees.

Through the above method, the window 231 located in the floating gate polycrystalline layer 230 is pretreated, so that the exposed floating gate polycrystalline layer 230 is recessed in the direction along the floating gate oxide layer 220, and the depth of the recess is from the center position to both sides. The edge is decremented, so that the angular angle of the discharge sharp angles (θ1, θ2) is 40 degrees to 50 degrees to increase the erasing speed and efficiency and enhance stability.

In one embodiment, the floating gate poly layer 230 exposed to the window 231 region is pretreated, specifically including the step of isotropic dry etching the window 231 with the barrier layer 240 as a masking layer.

With the barrier layer 240 as a masking layer, the floating gate polycrystalline layer 230 exposed to the window 231 region is etched by plasma dry etching. Dry etching has both the isotropic nature of the chemical reaction and the anisotropy of the physical reaction when etching the surface material. Because of the unique combination of physical and chemical reactions, dry etching can precisely control the size and shape of the pattern to be etched under the interaction of anisotropic and isotropic.

In one embodiment, pretreating the floating gate poly layer 230 exposed to the window 231 region may further include the step of thermally oxidizing the floating gate polycrystalline layer 230 exposed to the window 231 to form a second field oxide layer. The second oxide layer is wet etched.

The floating gate polycrystalline layer 230 is exposed to the floating gate polycrystalline layer 230 exposed in the window 231 region by means of thermal oxidation of the furnace tube to form a second field oxide layer, and then wet etching is performed by using hydrofluoric acid. The second field oxide layer located in the region of window 231 is etched to form the desired pattern shape and size.

In an embodiment, the preparation method further includes the step of performing N-type doping on the floating gate.

In this embodiment, the floating gate polycrystalline layer 230 is a polysilicon layer, and the floating gate may be formed by chemical vapor deposition (CVD). After the polysilicon floating gate is formed, it may be doped. Since the tunneling carriers are electrons, the floating gate is N-doped, and the doping ions may be pentavalent elements such as phosphorus, antimony and arsenic.

In one embodiment, the preparation method further includes the steps of: forming a tunneling oxide layer on the semiconductor substrate 210, on both sides of the floating gate polycrystalline layer 230 and on the field oxide layer; forming a selection gate on the tunneling oxide layer.

Referring to FIG. 11, a tunneling oxide layer 260 is formed on the semiconductor substrate 210, on both sides of the floating gate polycrystalline layer 230, and on the field oxide layer. Tunneling oxide layer 260 can also be silicon nitride, silicon oxynitride or other high k materials. The tunneling oxide layer may be formed by thermal oxidation of the furnace tube, atomic layer deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, etc. In this embodiment, the furnace tube is thermally oxidized to form a tunneling oxide layer 260. .

Referring to FIG. 12, polysilicon is deposited on the tunnel oxide layer 260 outside the floating gate and floating gate regions to form a select gate polysilicon, and then a portion of the select gate polysilicon is removed by photolithography to form a control gate 270.

Further, a flash memory is provided which is produced by a method of fabricating a flash memory as in any of the above embodiments. The discharge tip of the floating gate is sharp. When the flash memory is erased, a larger electric field is formed, and electrons are more favorable for tunneling, thereby obtaining a better erasing performance.

The technical features of the above-described embodiments may be arbitrarily combined. For the sake of brevity of description, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction between the combinations of these technical features, All should be considered as the scope of this manual.

The above-mentioned embodiments are merely illustrative of several embodiments of the present application, and the description thereof is more specific and detailed, but is not to be construed as limiting the scope of the invention. It should be noted that a number of variations and modifications may be made by those skilled in the art without departing from the spirit and scope of the present application. Therefore, the scope of the invention should be determined by the appended claims.

Claims

A method of preparing a flash memory, comprising:

Forming a floating gate oxide layer, a floating gate polycrystalline layer, and a barrier layer on the semiconductor substrate;

Etching the barrier layer, the floating gate polycrystalline layer to form a window, the window extending into the floating gate polycrystalline layer;

Pre-treating the floating gate poly layer exposed to the window region to recess the floating gate poly layer in a direction of the floating gate oxide layer, and the depth of the recess is determined by the window region The center position is decreasing toward both sides;

Forming a first field oxide layer at the window in the floating gate polycrystalline layer;

The etching forms a floating gate with a discharge sharp corner.
The method of claim 1 wherein said pretreating said floating gate poly layer exposed to said window region comprises:

The isotropic dry etching is performed on the floating gate poly layer exposed to the window region by using the barrier layer as a masking layer.
The method of fabricating a flash memory according to claim 1, wherein said pre-treating said floating gate poly layer exposed to said window region comprises:

Thermally oxidizing the floating gate polycrystalline layer exposed to the window region to form a second field oxide layer;

The second field oxide layer is wet etched.
The method of claim 1 wherein the recessed surface of the floating gate polycrystalline layer that is exposed is a circular arc surface.
The method of claim 1 wherein the recessed face of the floating gate polycrystalline layer that is exposed is comprised of a plurality of planes or curved surfaces having a gradual tendency.
The method according to claim 4 or 5, wherein the angle between the concave surface and the side edges of the window ranges from 75 to 80 degrees.
The method of claim 6 wherein said included angle is 78 degrees.
The method of claim 1 wherein said discharge sharp angles range from 40 to 50 degrees.
The method of claim 1 wherein said discharge sharp angle ranges from 45 degrees.
The method of claim 1 wherein etching forms a floating gate with a discharge spike comprises:

Removing the barrier layer above the floating gate poly layer;

The floating gate polycrystalline layer and the floating gate oxide layer located outside the window region are etched to form a floating gate with a discharge sharp corner.
The method of claim 10 wherein said step of removing said barrier layer over said floating gate polycrystalline layer is by wet chemical stripping to remove the barrier layer using hot phosphoric acid.
The method according to claim 1, wherein after the etching forms a floating gate with a discharge sharp corner, the method further comprises:

A tunneling oxide layer is formed on both sides of the floating gate polycrystalline layer and on the field oxide layer on the semiconductor substrate.
The method of claim 11 further comprising: forming a select gate on said tunneling oxide layer.
The method of claim 13 further comprising: photolithography and etching to remove portions of said select gates to form a control gate.
The method of claim 1 wherein the barrier layer is made of silicon nitride.
The method of claim 1 further comprising the step of N-doping said floating gate.
A flash memory produced by the method of fabricating the flash memory according to any one of claims 1 to 16.