CN106960786A - A kind of technique for the bottom and apical curvature radius for increasing groove - Google Patents
A kind of technique for the bottom and apical curvature radius for increasing groove Download PDFInfo
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- CN106960786A CN106960786A CN201610010198.0A CN201610010198A CN106960786A CN 106960786 A CN106960786 A CN 106960786A CN 201610010198 A CN201610010198 A CN 201610010198A CN 106960786 A CN106960786 A CN 106960786A
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- layer
- groove
- silicon nitride
- silica
- semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
Abstract
The invention discloses a kind of technique for the bottom and apical curvature radius for increasing groove, first layer silica and first layer silicon nitride are first formed on a semiconductor substrate；Then first layer silica and first layer silicon nitride are opened by photoetching by window；Using first layer silica and first layer silicon nitride as mask, by cutting technique, groove is formed in semiconductor substrate；Then, second layer silica and second layer silicon nitride are formed on a semiconductor substrate；Most of second layer silica and second layer silicon nitride are removed by anisotropic etch process, only retain second layer silica and second layer silicon nitride in the side wall of groove；Thermal oxide layer is formed in the bottom of groove and top by thermal oxidation technology, the bottom of groove and the radius of curvature at top is increased.
Description
Technical field
The invention belongs to semiconductor process technique field, it is related to semiconductor trench technique（trench process）, especially
It is related to the trench process of power device, relates in particular to a kind of technique for the bottom and apical curvature radius for increasing groove.
Background technology
In high power semiconductor device, including various MOS（Metal-oxide-semicondutor）Grid controlled transistor, particularly
IGBT（Igbt）, it is widely used trench gate structure.Compared with planar gate structure, the primitive unit cell of trench gate structure
Density is bigger, and saturation voltage drop is lower.But, trench gate structure has two problems：First, the electric field of channel bottom is concentrated, electric field
Strength ratio is larger, therefore the HTRB of device（High temperature reverse bias）Reliability is adversely affected.Secondly, the top edge of groove is very
It is not round and smooth, almost at right angles, electric leakage of the grid problem can be caused.It is therefore necessary to increase the bottom of groove and the curvature half at top
Footpath.
There is a kind of method for increasing channel bottom radius of curvature to be：The reactant produced using technique before protects channel side
Channel bottom, cunning is become more round by isotropic etching by wall（Referring to, such as, and United States Patent (USP) 6521538B2）.But, this
Kind of method it is inefficient because isotropic etching technics is relatively difficult to control.
Still an alternative is that increasing the radius of curvature of channel bottom using thermal oxidation technology（Referring to such as, the U.S. is special
Sharp 8659065B2）.Thermal oxidation technology is more prone to control, but this method still has two shortcomings：It needs twice first
Trench etch process, adds complexity and cost.Secondly the top of groove still has the shape at intimate right angle, not enough justifies
It is sliding.
In order to solve problem described above, the present invention proposes a kind of improved method, using thermal oxidation technology simultaneously
Increase the bottom of groove and the radius of curvature at top.
The content of the invention
The purpose of the present invention is to propose to a kind of simple controllable method, while increasing the bottom of groove and the curvature half at top
Footpath.Technical scheme is as follows：
A kind of technique for the bottom and apical curvature radius for increasing groove, comprises the following steps：Is formed on a semiconductor substrate
One layer of silica and first layer silicon nitride；Then first layer silica and first layer silicon nitride are opened by photoetching by window；With
First layer silica and first layer silicon nitride are mask, and by cutting technique, groove is formed in semiconductor substrate；Then, exist
Second layer silica and second layer silicon nitride are formed on semiconductor substrate；Most of second is removed by anisotropic etch process
Layer silica and second layer silicon nitride, only retain second layer silica and second layer silicon nitride in the side wall of groove；Pass through hot oxygen
Chemical industry skill forms thermal oxide layer in the bottom of groove and top, increases the bottom of groove and the radius of curvature at top.
Preferably, described semiconductor substrate is silicon materials or carbofrax material.
Beneficial effects of the present invention are as follows：
The present invention is a kind of simple controllable method：Its simplicity is that trench etch process only has a step, in one step
Increase the bottom of groove and the radius of curvature at top simultaneously；Its controllability, which is that, utilizes thermal oxidation technology increase curvature half
Footpath, only needs to just be accurately controlled etching result using thermal oxidation time under certain conditions.
Brief description of the drawings
Fig. 1 is that first layer silica and first layer nitridation are formd on the cross-sectional view of semiconductor substrate, semiconductor substrate
Silicon；
Fig. 2, which is shown in first layer silica and first layer silicon nitride, has outputed window；
Fig. 3 is shown using first layer silica and first layer silicon nitride as mask, and groove has been etched in semiconductor substrate；
Fig. 4, which is shown, forms second layer silica and second layer silicon nitride；
Fig. 5 shows that anisotropic etch process eliminates most of second layer silica and second layer silicon nitride, only in channel side
Wall retains second layer silica and second layer silicon nitride；
Fig. 6 is shown by thermal oxidation technology, and thermal oxide layer is produced in the bottom of groove and top；
Fig. 7 displays remove the semiconductor substrate after institute's silica and silicon nitride, the bottom of groove and the radius of curvature at top
Increase；
Fig. 8 is a kind of application example of Fig. 7 structures：Trench interiors form gate oxide and polysilicon layer.Polysilicon is only existed
In trench interiors；
Fig. 9 is another application example of Fig. 7 structures：Trench interiors form gate oxide and polysilicon layer, and polysilicon layer is stretched
Open up on groove.
Embodiment
The invention discloses a kind of technique for the bottom and apical curvature radius for increasing groove.First shape on a semiconductor substrate
Into first layer silica and first layer silicon nitride；Then first layer silica and first layer silicon nitride are opened by photoetching by window
Mouthful；Using first layer silica and first layer silicon nitride as mask, by cutting technique, groove is formed in semiconductor substrate；So
Afterwards, second layer silica and second layer silicon nitride are formed on a semiconductor substrate；Big portion is removed by anisotropic etch process
Divide second layer silica and second layer silicon nitride, only retain second layer silica and second layer silicon nitride in the side wall of groove；It is logical
Cross thermal oxidation technology and form thermal oxide layer in the bottom of groove and top, increase the bottom of groove and the radius of curvature at top.
It is an object of the invention to form a kind of groove on a semiconductor substrate, this kind of groove has the bottom and top of increase
Portion's radius of curvature.Specifically, the bottom of increase groove and the method for apical curvature radius comprise the following steps：a）First half
First layer silica and first layer silicon nitride are formed on conductor substrate；b）By photoetching and etching, in first layer silica and
One layer of silicon nitride uplifting window, that is, patterning step；c）By the use of first layer silica and first layer silicon nitride as mask, half
Groove is outputed in conductor substrate；d）Second layer silica guarantor type layer is deposited on the substrate for outputed groove；e）Then exist
Second layer silicon nitride guarantor type layer is deposited above；f）Anisotropic etching is carried out, to remove the second layer oxygen parallel with substrate surface
SiClx and second layer silicon nitride, only retain second layer silica and second layer silicon nitride on the sidewalls of the trench；g）Carry out hot oxygen
Change step, until corner forms thermal oxide layer at the top of the bottom of groove and groove；h）Remove all silicon nitride layers and oxygen
SiClx layer.
The present invention is described in further detail below in conjunction with the accompanying drawings：
The present invention includes below step.With reference to Fig. 1, the first step is that first layer silica 2 and the are formed on semiconductor substrate 1
One layer of silicon nitride 3.First layer silica 2 can be formed by thermal oxidation technology, can also pass through CVD（Chemical vapor deposition）Work
Skill is formed.First layer silicon nitride 3 can be formed by CVD techniques.These layers should be had respectively using that can be produced on substrate
Formed to the technique of the same sex or the film layer of shape-retaining ability, it would however also be possible to employ ALD（Ald）Technology is formed.
Then by photoetching and etching technics, window, such as Fig. 2 are opened on first layer silica 2 and first layer silicon nitride 3
It is shown.
Groove 101 is then etched in semiconductor substrate 1, as shown in Figure 3.Trench etch process is aoxidized using first layer
Silicon 2 and first layer silicon nitride 3 are used as mask.The top 11 of groove 101, with rectangular shaped.It is very not round and smooth.Groove 101
Width is 2r1.The radius of curvature of channel bottom 21 is r1。
After etching groove is completed, second layer silica 4 and second layer silicon nitride 5 are formd by CVD or ALD techniques,
As shown in Figure 4.CVD and ALD techniques have guarantor's type（conformal）The characteristics of, therefore second layer silica 4 and second layer nitridation
The upper surface that silicon 5 not only covers semiconductor substrate also cover the inner surface of groove.
Then most second layer silica 4 and second layer silicon nitride 5 are removed by anisotropic etching technics, only
Second layer silica 4 and second layer silicon nitride 5 are left in trenched side-wall, as shown in Figure 5.This anisotropic etch process step
It can be completed using Commercial semiconductors process equipment, such as etching devices of LAM 4300, and preferably with fluoroform gas
Body（CHF3）Etching condition under carry out.
It is exactly thermal oxidation technology below.The thermal oxide of silicon is carried out preferably at about 1050 DEG C, for the selection of oxidant, phase
Than in dry oxygen, being more preferably used as oxidant using vapor.Oxidant such as oxygen atoms can not by silicon nitride layer 3 and 5,
But it can be by oxide layer 2 and 4.The silicon substrate of channel bottom can not be by second layer silicon nitride layer 5 and second layer silica
The protection of layer 4.And the part second layer silicon nitride layer 5 and second layer silicon oxide layer 4 for removing substrate surface cause in groove
Drift angle at left behind very thin silica, form very short oxygen diffusion path.Therefore thermal oxide layer 6 is only formed
In the bottom and top of groove, the side wall of groove will not form thermal oxide layer.And thermal oxide layer 6 is formed most in channel bottom
Hurry up, and formed at groove drift angle it is slightly slow, as shown in fig. 6, at drift angle, oxygen can be diffused through in anisotropic etching
During there is no removed thin layer of silicon oxide 4.In silicon oxide layer 4 below second layer silicon nitride layer 5, oxidant is along side
Wall slowly spreads, and thus consumes the silicon substrate on the wall of side, slowly adds the thickness of the silicon oxide layer of side wall.Due to this heat
Oxidation technology consumes channel bottom and the silicon of groove drift angle or the speed ratio side wall of other semiconductive material substrates is fast, therefore changes
The shape of groove, makes original sufficiently oily corner become round and smooth, and also increases the radius of curvature of channel bottom, thus
So that the radius of curvature at bottom and top increases simultaneously.Control condition can be used as by such a situa-tion using oxidization time
Increase the size that controls bottom radius exactly, so that bottom radius is by r1Increase to r2.The silicon of groove corner is because forming
Silica and when consuming, thermal expansion ratio is about 2.4:1, this causes the upper surface silicon nitride layer 3 of groove corner（In original English text
For 5, if wrong）It is remote with silicon nitride layer 5 on the wall of side.The simulation carried out to groove disclosed herein formation and etching technics
Experiment shows, for the step, and the thermal oxidation time of 40 minutes makes channel radii increase to 0.6 micron by 0.4 micron,
The width of resulting groove is 0.8 micron（2×r1）And depth is about 5 microns.Suitable for other groove dimensions, aspect ratio
It can be readily determined with the condition of local curvature by changing original dimension and etch period by means of such simulation.
Finally by wet etching or CDE（Chemical dry etching, chemical drying method etching）Technique remove
All silica and silicon nitride layer, obtain result as shown in Figure 7.As can be seen that the shape and groove 101 of groove 102 are bright
Aobvious difference.The top 12 of groove 102 is substantially rounder and more smooth than the top 11 of groove 101.The width of groove 102 is still 2r1, But
The radius of curvature of the bottom of groove 102 is more than r1.So, the radius of curvature at channel bottom and top is all increased.By wearing
Cross when the mask open formed in silicon oxide layer 2 of starting silicon nitride layer 3 and first is performed etching, increase initial etching depth,
Gash depth can be easily set to increase above 5 microns.
Fig. 8 is one of application example of former trenches structure：Groove 102 has been internally formed gate oxide 6 and polysilicon layer
7.Polysilicon 7 exists only in the inside of groove 102.Specific device electrode and doped structure are not drawn.
Fig. 9 is the two of the application example of former trenches structure：Groove 102 has been internally formed gate oxide 6 and polysilicon layer
7.Polysilicon 7 is not only present in the inside of groove 102, and has been stretched over the surface of semiconductor substrate 1, forms polycrystalline silicon bridge
Structure.Specific device electrode and doped structure are not drawn.
During making devices, the material of semiconductor substrate 1 can be silicon either carborundum.
Presently preferred embodiments of the present invention is the foregoing is only, is not intended to limit the invention.All essences in the present invention
Any modification, equivalent and improvement made within refreshing and principle etc., should be included within the scope of the present invention.
Embodiments of the present invention are described in detail above in conjunction with the drawings and specific embodiments, but the present invention is not
It is limited to above-mentioned embodiment, in the knowledge that art those of ordinary skill possesses, can also departing from
Made a variety of changes on the premise of present inventive concept.
Claims (2)
1. a kind of technique for the bottom and apical curvature radius for increasing groove, it is characterised in that the technique comprises the following steps：
First layer silica and first layer silicon nitride are formed on a semiconductor substrate；Then by photoetching first layer silica and first
Layer silicon nitride opens window；Using first layer silica and first layer silicon nitride as mask, by cutting technique, in semiconductor substrate
Interior formation groove；Then, second layer silica and second layer silicon nitride are formed on a semiconductor substrate；Pass through anisotropic etching
Technique removes most of second layer silica and second layer silicon nitride, only retains second layer silica and second in the side wall of groove
Layer silicon nitride；Thermal oxide layer is formed in the bottom of groove and top by thermal oxidation technology, the bottom and top of groove is increased
Radius of curvature.
2. technique according to claim 1, it is characterised in that：Described semiconductor substrate is silicon materials or carborundum material
Material.
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| CN201610010198.0A CN106960786A (en) | 2016-01-08 | 2016-01-08 | A kind of technique for the bottom and apical curvature radius for increasing groove |
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| CN201610010198.0A CN106960786A (en) | 2016-01-08 | 2016-01-08 | A kind of technique for the bottom and apical curvature radius for increasing groove |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114864670A (en) * | 2022-05-13 | 2022-08-05 | 电子科技大学 | Uniform electric field device for relieving in-vivo curvature effect and manufacturing method |
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| CN102290343A (en) * | 2010-11-04 | 2011-12-21 | 天津环鑫科技发展有限公司 | Manufacturing method of trench gate for power device |
| CN103021870A (en) * | 2012-12-21 | 2013-04-03 | 上海宏力半导体制造有限公司 | Manufacturing method of MOS (metal oxide semiconductor) transistor and method for rounding top charge corners of channels |
| CN102456561B (en) * | 2010-11-02 | 2013-09-11 | 上海华虹Nec电子有限公司 | Forming method of thick gate oxide layer at bottom of groove in groove-type power device |
| CN104160512A (en) * | 2012-03-05 | 2014-11-19 | 株式会社电装 | Semiconductor device and manufacturing method therefor |
-
2016
- 2016-01-08 CN CN201610010198.0A patent/CN106960786A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102456561B (en) * | 2010-11-02 | 2013-09-11 | 上海华虹Nec电子有限公司 | Forming method of thick gate oxide layer at bottom of groove in groove-type power device |
| CN102290343A (en) * | 2010-11-04 | 2011-12-21 | 天津环鑫科技发展有限公司 | Manufacturing method of trench gate for power device |
| CN104160512A (en) * | 2012-03-05 | 2014-11-19 | 株式会社电装 | Semiconductor device and manufacturing method therefor |
| CN103021870A (en) * | 2012-12-21 | 2013-04-03 | 上海宏力半导体制造有限公司 | Manufacturing method of MOS (metal oxide semiconductor) transistor and method for rounding top charge corners of channels |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114864670A (en) * | 2022-05-13 | 2022-08-05 | 电子科技大学 | Uniform electric field device for relieving in-vivo curvature effect and manufacturing method |
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Application publication date: 20170718 |
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