CN103367262B - The forming method of flash memory cell - Google Patents
The forming method of flash memory cell Download PDFInfo
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- CN103367262B CN103367262B CN201310315247.8A CN201310315247A CN103367262B CN 103367262 B CN103367262 B CN 103367262B CN 201310315247 A CN201310315247 A CN 201310315247A CN 103367262 B CN103367262 B CN 103367262B
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Abstract
A kind of forming method of flash memory cell, including: some batch semiconductor structures include: substrate, substrate has some floating gate regions arranged in parallel and isolation area, the surface, floating gate region of substrate has tunnel oxide and floating gate layer, in the isolation area of substrate, there is isolation structure, the surface of isolation structure equals to or higher than floating gate layer surface, and isolation structure has adjacent first area and second area；It is sequentially etched the second area of the isolation structure of some batch semiconductor structures, make the second area surface of isolation structure less than surface, first area, wherein, the determination method of the etch period of each batch to be etched includes: a batch of isolation structure etch rate before testing batch to be etched, test the thickness of batch to be etched isolation structure before etching, preset thickness in conjunction with the isolation structure second area after lot etched to be etched, it is thus achieved that the etch period of batch to be etched.The thickness of the isolation structure formed is accurate, the stable performance of the flash memory cell formed.
Description
Technical field
The present invention relates to semiconductor storage unit field, particularly relate to the formation side of a kind of flash memory cell
Method.
Background technology
In current semiconductor industry, IC products can be divided mainly into three major types type: analog circuit,
Digital circuit and D/A hybrid circuit, a kind of important devices type during wherein memory device is digital circuit.
In recent years, the flash memory in memory device (flash memory) development is the rapidest.The main feature of flash memory
It is the information that can keep storage in the case of not powered for a long time；And flash memory has, and integrated level is high, access is fast
Degree is fast, be prone to the advantages such as erasing and rewriting, thus obtains in the multinomial field such as microcomputer, Automated condtrol
It is widely applied.
Fig. 1 is the cross-sectional view of a kind of flash memory cell of prior art, including: substrate 10；
It is positioned at the tunnel oxide 11 on described substrate 10 surface；It is positioned at the floating boom 12 on tunnel oxide 11 surface,
There is in described tunnel oxide 11 and floating boom 12 opening (mark) exposing substrate 10；It is positioned at
Described floating boom 12 top surface and cover the side wall 13 of described opening sidewalls；It is positioned at described open bottom lining
The source line layer 14 on surface, the end 10, described source line layer 14 covers the part surface of side wall 13, and described source line
The surface of layer 14 is not higher than the top of described side wall 13；It is positioned at side wall 13, source line layer 14 and floating boom 12
The word line layer 15 in outside, is electrically insulated by insulating barrier 16 between described word line layer 15 and floating boom 12.
The floating boom of the some flash memory cells being formed on same substrate need by isolation structure carry out electricity every
From, Fig. 2 is the schematic diagram of the isolation structure of isolation flash memory cell floating boom, including: substrate 20, institute
State substrate 20 and there is floating gate region 21 and isolation area 22；It is positioned at the tunnelling on substrate 20 surface of floating gate region 21
Oxide layer 25 and be positioned at the floating gate layer 23 on tunnel oxide 25 surface；It is positioned at the substrate of isolation area 22
Isolation structure 24 in 20, described isolation structure 24 has adjacent first area A and second area B,
The A surface, first area of isolation structure 24 equals to or higher than floating gate layer 23 surface, the of isolation structure 24
Two region B surface are less than floating gate layer 23 surface, and source line layer 14 as shown in Figure 1 is across isolation structure 24
First area A, and with corresponding for the second area B part floating gate layer 23 of isolation structure 24 rear
Be etched in continuous technique removal.
When etching removes the part floating gate layer 23 corresponding with second area B, due to described isolation structure
The surface of the second area B of 24 is less than floating gate layer 23 surface, it is possible to prevent the projection of isolation structure 24 from imitating
Answer (STI Shadowing Effect), it is to avoid remaining in the sidewall surfaces of isolation structure 24 second area B
The material of floating gate layer 23, thus ensure that the data of formed floating boom 12 (as shown in Figure 1) keep energy
Power.
But, when prior art forms the second area B of isolation structure 24, the thickness of second area B is difficult
Accurately to control, when the thickness of the second area B of isolation structure 24 is crossed thin, the isolation of second area B
Structure 24 is easier to breakdown, the threshold voltage decreasing of the second area B of isolation structure 24, can cause
Programming interference, or cause the turn-off capacity of word line layer 15 (as shown in Figure 1) to be deteriorated；When isolation structure 24
The thickness of second area B blocked up time, the data of formed floating boom 12 (as shown in Figure 1) can be caused
Holding capacity declines, the unstable properties of flash memory cell.
Summary of the invention
The problem that the present invention solves is to provide the forming method of a kind of flash memory cell, makes isolation flash memory deposit
The isolation structure thickness of storage unit can accurately control, and makes formed flash memory cell stable performance.
For solving the problems referred to above, the present invention provides the forming method of a kind of flash memory cell, including:
Thering is provided some batch semiconductor structures, described semiconductor structure includes: substrate, and described substrate has
Some floating gate regions arranged in parallel, have isolation area between adjacent floating grid region, the floating gate region table of described substrate
Mask has tunnel oxide and is positioned at the floating gate layer on tunnel oxide surface, the isolation area of described substrate
Inside having isolation structure, the surface of described isolation structure equals to or higher than floating gate layer surface, described isolation junction
Structure has adjacent first area and second area；
It is sequentially etched the second area of the isolation structure of some batch semiconductor structures, makes the of isolation structure
Two region surface are less than surface, first area, wherein, the determination side of the etch period of each batch to be etched
Method includes: a batch of isolation structure etch rate before testing batch to be etched, tests batch to be etched and exists
The thickness of the isolation structure before etching, by isolation structure etch rate a batch of before batch to be etched,
And the thickness of the isolation structure that batch to be etched is before etching obtains the etch period of batch to be etched；
Etch some batch semiconductor structures isolation structure second area after, floating gate layer and every
Forming sacrifice layer from body structure surface, described sacrifice layer has the first opening, and described first opening exposes portion
Divide floating gate layer and the isolation structure surface of first area.
Optionally, the determination method of the etch period of described each batch to be etched is: test to be etched batch
The thickness of secondary isolation structure second area before etching, obtains isolation structure the first thickness Tn；Test
A batch of isolation structure etch rate before batch to be etched, obtains isolation structure the first etch rate γn-1；
Use isolation structure the first thickness TnWith isolation structure the first etch rate γn-1Obtain the quarter of batch to be etched
Erosion time tn=(Tn-Ttarget)/γn-1, wherein, TtargetIsolation structure second area for batch to be etched
Preset thickness after etching.
Optionally, before testing described batch to be etched, the method for a batch of etch rate is: test to be etched
Thickness before a batch of isolation structure etches before erosion batch, obtains isolation structure the second thickness Tn-1；Survey
Thickness after a batch of isolation structure etches before trying batch to be etched, obtains isolation structure the 3rd thickness
Ttn-1；Use isolation structure the second thickness Tn-1With isolation structure the 3rd thickness Ttn-1Before obtaining batch to be etched
A batch of etch rate γn-1=(Tn-1-Ttn-1)/tn-1, wherein, described tn-1For a collection of before batch to be etched
The time of secondary etching isolation structure.
Optionally, also include: the sidewall surfaces at the first opening forms the first side wall；With the first side wall and
Sacrifice layer be mask etching floating gate layer and tunnel oxide till exposing substrate, form the second opening,
And form the second side wall in the sidewall surfaces of the second opening；After forming the second side wall, at the first opening
With formation source line layer in the second opening；After forming source line layer, remove sacrifice layer and with the first side wall and
Source line layer etching floating gate layer is until exposing tunnel oxide；Floating boom is being etched with the first side wall and source line layer
After Ceng, form word line layer, described word line layer and floating boom in the first side wall, source line layer and floating gate layer both sides
Electrically insulated by insulating barrier between Ceng.
Optionally, the formation process of described word line layer is: after etching described floating gate layer, use hot oxygen
Sidewall surfaces and Xian Ceng surface, source that metallization processes exposes at floating gate layer form insulating barrier；Forming insulating barrier
Afterwards, formation of deposits wordline thin film, described wordline thin film covers substrate, floating gate layer, the first side wall and source
Line layer surface；It is etched back to described wordline thin film, removes source line layer and the wordline thin film of substrate surface, formed
Word line layer.
Optionally, also include: before forming word line layer, etch floating gate layer with the first side wall and source line layer
With tunnel oxide till exposing substrate, described thermal oxidation technology also forms insulation at substrate surface
Layer.
Optionally, after forming word line layer, in the substrate of source line layer, word line layer and floating gate layer both sides
Form drain region.
Optionally, before the line layer of the source that formed, in the substrate of the second open bottom, form source region.
Optionally, the material of described first side wall, the second side wall and insulating barrier is silicon oxide, described wordline
The material of layer and source line layer is polysilicon.
Optionally, the forming method of described isolation structure is: forms tunnel oxide at substrate surface and floats
After gate layer, the etching floating gate layer of isolation area, tunnel oxide and section substrate are to form groove；Institute
State in groove and floating gate layer surface deposits dielectric materials；The dielectric material higher than floating gate layer surface is removed in polishing,
Form isolation structure.
Compared with prior art, technical scheme has the advantage that
When being sequentially etched the second area of isolation structure of some batch semiconductor structures, by test institute
A batch of isolation structure etch rate before stating batch to be etched, test batch to be etched before etching
The thickness of isolation structure, and combine the isolation structure preset thickness after lot etched to be etched, it is thus achieved that each
The etch period of batch to be etched；Wherein, owing to the etch rate variations of adjacent two batches is little, therefore,
With the speed of batch to be etched previous lot etched isolation structure, and combine batch to be etched before etching
Actual (real) thickness and etching after preset thickness, the etching of batch the most to be etched can either be obtained
Time；The isolation structure second area of each batch to be etched is etched with the etch period obtained, it is possible to
The thickness making the isolation structure second area after each lot etched is the most homogeneous, it is to avoid because of the of isolation structure
Two area thickness are crossed thin and are caused programming interference or wordline turn-off capacity to be deteriorated, or avoid therefore isolation structure
Second area thickness blocked up and cause the data holding ability of floating boom to decline, the flash memory storage list formed
The stable performance of unit.
Further, the determination method of the etch period of each batch to be etched is: test batch to be etched
Thickness, obtains isolation structure the first thickness Tn；A batch of isolation structure etching before testing batch to be etched
Speed, obtains isolation structure the first etch rate γn-1；Use isolation structure the first thickness TnAnd isolation junction
Structure the first etch rate γn-1Obtain the etch period t of batch to be etchedn=(Tn-Ttarget)/γn-1, wherein,
TtargetFor the preset thickness after the isolation structure etching of batch to be etched.Wherein, Tn-TtargetThe most to be etched batch
Secondary isolation structure second area is actually needed the degree of depth of etching；Quarter due to adjacent two lot etched techniques
Erosion speed change is less, therefore, is to be etched batch with actual etch rate a batch of before batch to be etched
Secondary etch rate, and combine the etching depth of the isolation structure second area reality of batch to be etched, institute
The etch period of the batch to be etched obtained is the most accurate；The etching of the batch each to be etched to be obtained
Time etches the isolation structure second area of this batch to be etched, it is possible to make each batch isolation junction after etching
The thickness of structure second area is homogeneous accurately, makes the stable performance of formed flash memory cell.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of a kind of flash memory cell of prior art；
Fig. 2 is the schematic diagram of the isolation structure of isolation flash memory cell floating boom；
Fig. 3 is the maintenance period of etching apparatus within T, etch rate schematic diagram over time；
Fig. 4 to Figure 13 is the schematic diagram of the forming process of the flash memory cell of the embodiment of the present invention.
Detailed description of the invention
As stated in the Background Art, the thickness of the second area of the isolation structure that prior art is formed is difficult to accurately
Control, make the unstable properties of flash memory cell.
In one embodiment, the isolation structure 24 isolating flash memory cell floating boom as shown in Figure 2 is formed
Method include: after substrate 20 surface forms tunnel oxide 25 and floating gate layer 23, etching isolation
The floating gate layer 23 in district 22, tunnel oxide 25 and section substrate 20 are to form groove；In described groove
With floating gate layer 23 surface deposits dielectric materials；The dielectric material higher than floating gate layer 23 surface is removed in polishing,
Form isolation structure 24；After glossing, use anisotropic dry etch process etching second
The isolation structure 24 of region B, makes isolation structure 24 surface table less than floating gate layer 23 of second area B
Face.
Find through research, in the actual production process of prior art, carve successively when using etching technics
During the second area B of the isolation structure 24 losing some batches, generally it is sequentially etched with fixing etch period
The isolation structure 24 of some batches.But, in actual production process, be sequentially etched some batches every
Etch rate when structure 24 is not consistent, after therefore etching isolation structure with fixing etch period, and meeting
The etching depth causing the isolation structure 24 second area B to some batches is inconsistent, if thus in etching
After the isolation structure 24 second area B of dry batch, the thickness of isolation structure 24 second area B is difficult to
Accurately control.Specifically refer to Fig. 3, in the maintenance period of an etching apparatus within T, etch rate is gradually
Decline, until etch rate is close to marginal value A, then etching apparatus is maintained.Therefore, in etching
The same maintenance period of equipment is in T, if be sequentially etched the isolation structure of some batches with a certain set time
24 second area B, are easily caused the thickness of the second area B of some batch isolation structures 24 through over etching
Spend inconsistent and be difficult to accurately determine, thus causing the unstable properties of flash memory cell.
The present invention proposes the forming method of a kind of flash memory cell, when being sequentially etched some batch quasiconductors
During the second area of the isolation structure of structure, by testing a batch of isolation junction before described batch to be etched
Structure etch rate, test the thickness of batch to be etched isolation structure before etching, and combine to be etched
Isolation structure preset thickness after lot etched, it is thus achieved that the etch period of each batch to be etched；Wherein,
Owing to the etch rate variations of adjacent two batches is little, therefore, isolate with the previous lot etched of batch to be etched
The speed of structure, and combine the preset thickness after batch to be etched actual (real) thickness before etching and etching,
The etch period of batch the most to be etched can either be obtained；Etch every with the etch period obtained
The isolation structure second area of one batch to be etched, it is possible to make isolation structure the secondth district after each lot etched
The thickness in territory is the most homogeneous, it is to avoid because of the second area thickness of isolation structure cross thin and cause programming interference or
Wordline turn-off capacity is deteriorated, or avoids the second area thickness of therefore isolation structure blocked up and cause floating boom
Data holding ability declines, the stable performance of the flash memory cell formed.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The specific embodiment of the present invention is described in detail.
Fig. 4 to Figure 13 is the schematic diagram of the forming process of the flash memory cell of the embodiment of the present invention.
Refer to Fig. 4, it is provided that some batch semiconductor structures, described semiconductor structure includes: substrate 200,
Described substrate 200 has some floating gate regions 210 arranged in parallel, has isolation between adjacent floating grid region 210
District 220, the surface, floating gate region 210 of described substrate 200 has tunnel oxide 201 and is positioned at tunnelling
The floating gate layer 202 on oxide layer 201 surface, has isolation structure in the isolation area 220 of described substrate 200
203, the surface of described isolation structure 203 equals to or higher than floating gate layer 202 surface, described isolation structure 203
There is adjacent first area I and second area II.
Described substrate 200 for providing work platforms for subsequent technique, described substrate 300 be silicon substrate,
Silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI) substrate, germanium on insulator (GOI) substrate,
Glass substrate or III-V substrate, such as gallium nitride or GaAs etc..Described substrate 200 has
Active area, floating gate layer is formed at surfaces of active regions, is subsequently formed flash memory cell in described active area
Source region and drain region.
The material of described tunnel oxide 201 is silicon oxide, and formation process is depositing operation, such as chemistry
Gas-phase deposition；When the material on described substrate 200 surface is silicon, described tunnel oxide 201
Formation process can also be thermal oxidation technology.Described tunnel oxide 201 is at the bottom of isolation liner 200 and floats
Gate layer 202, when the flash memory cell work formed, is positioned at the substrate 200 below floating gate layer 202
Interior formation channel region, and carrier can be through described tunnel oxide 201 at channel region and floating gate layer 202
Between move, to realize write, to wipe or the operation such as programming.
The material of described floating gate layer 202 is polysilicon, and the formation process of described floating gate layer 202 is deposition work
Skill, depending on the thickness of described floating gate layer 202 is according to concrete process requirements, should excessively not limit.
Described floating gate layer 202 obtains for the channel region in substrate 200 or conveying electronics, write with realization,
The operation such as erasing or programming.
The material of described isolation structure 203 is silicon oxide, silicon nitride, silicon oxynitride, described isolation structure
The thickness of 203 is 4500 angstroms～5300 angstroms, and described isolation structure 203 is used for isolating adjacent floating grid region 210
Active area in the floating gate layer 202 on surface and substrate 200；The forming method of described isolation structure 203
For: after substrate 200 surface forms tunnel oxide 201 and floating gate layer 202, etch isolation area 220
Floating gate layer 202, tunnel oxide 201 and section substrate 200 to form groove (not shown)；Institute
State in groove and floating gate layer 202 surface deposits dielectric materials；Polishing is removed higher than floating gate layer 202 surface
Dielectric material, forms isolation structure 203.The source line layer that subsequent technique is formed is across described isolation structure 203
First area I, the word line layer being subsequently formed is across the second area II of isolation structure 203.In this enforcement
In example, before forming dielectric material, in groove, form polishing stop layer (not with floating gate layer 202 surface
Illustrate), the material of described polishing stop layer is insulant, and the material of described polishing stop layer and isolation
The material of structure 203 is different, and described polishing stop layer can protect floating gate layer table when polishing medium material
Face is injury-free；Therefore, after glossing, need to remove the polishing stop layer on floating gate layer 202 surface,
The surface of the isolation structure 203 formed is higher than 600 angstroms～800 angstroms of floating gate layer 202 surface.Real at other
Executing in example, the isolation structure surface after described glossing can also flush with floating gate layer.
The floating gate layer 202 corresponding with the second area II of isolation structure 203 needs to pass through in subsequent technique
Anisotropic dry etch process is removed, in order to be developed across isolation structure 203 second area II's
Word line layer, therefore, is using anisotropic dry etch process to remove and isolation junction in order to avoid follow-up
During corresponding for the second area II floating gate layer 202 of structure 203, can be in the sidewall surfaces of isolation structure 203
The material of residual floating gate layer 202, needs after glossing, the secondth district of thinning isolation structure 203
The thickness of territory II, makes the second area II surface of isolation structure 203 be less than floating gate layer 202 surface, with this
Prevent from producing projection effect because isolation structure 203 surface to tunnel oxide 201 surface distance is excessive,
Avoid the problem of material at isolation structure 203 sidewall surfaces residual floating gate layer 202.
But, in the prior art, in the same etching period of etching apparatus, it is sequentially etched some batches
Semiconductor structure time, the etch rate for the semiconductor structure of some batches is inconsistent, is easily caused
The variable thickness of the isolation structure 203 second area II of the some batches after etching causes, and makes isolation structure 203
Second area II thickness and be difficult to accurately control, so that the unstable properties of flash memory cell；Especially
It constantly reduces along with the size of chip or semiconductor device, due to described isolation structure 203 second area
Thickness inaccuracy or inconsistent the caused performance issue of II are the most notable.
When the thickness of the second area II of isolation structure 203 is crossed thin, the isolation structure 203 of second area II
The most breakdown, the second area II threshold voltage decreasing of isolation structure 203, programming interference can be caused,
Or cause the turn-off capacity of word line layer to be deteriorated；When the thickness of the second area II of isolation structure 203 is blocked up,
Floating gate layer 202 data holding ability in follow-up formed flash memory cell can be made to decline, cause institute
The unstable properties of the flash memory cell formed.
Therefore, in the present embodiment, the secondth district of each lot etched isolation structure 203 to be etched is etched
During the II of territory, use a batch of etch rate before described batch to be etched, in conjunction with batch to be etched in etching
Isolation structure 203 thickness and the second area II of the isolation structure 203 of batch to be etched before carve
Preset thickness after erosion, it is thus achieved that the etch period of batch to be etched；Due to batch to be etched and previous batch
Etch rate closest to, therefore by a batch of isolation structure 203 second area II before etching
The etch period of the batch to be etched acquired in etch rate is accurate, with the etch period that obtained to be etched
The isolation structure 203 second area II of erosion batch performs etching, it is possible to make the isolation structure 203 of some batches
The thickness of second area II is the most homogeneous, advantageously ensures that the performance of formed flash memory cell.With
Lower the determination method of the etch period determining each batch to be etched will be specifically described.
Refer to Fig. 5, be sequentially etched the second area II of the isolation structure 203 of some batch semiconductor structures,
The second area II surface making isolation structure 203 is less than I surface, first area, wherein, each to be etched
The determination method of the etch period of batch includes: a batch of isolation structure etching before testing batch to be etched
Speed, tests the thickness of batch to be etched isolation structure before etching, previous by batch to be etched
The isolation structure etch rate of batch and the thickness of batch to be etched isolation structure before etching obtain
Obtain the etch period of batch to be etched.
Before etching technics, the I surface, first area of isolation structure 203 formed mask layer, described in cover
Film layer includes that photoresist layer, described etching technics are anisotropic dry etch process, to be perpendicular to lining
The direction on surface, the end 200 performs etching, and makes the surface of the second area II of the isolation structure after etching 203
The not higher than surface of floating gate layer 202, it is preferable that make the surface of the second area II of isolation structure 203
Surface less than floating gate layer 202.The degree of depth of the second area II of etching isolation structure 203 is 600 angstroms～800
Angstrom, etching gas includes CHF3。
Refer to Figure 12, the determination method of the etch period of described each batch to be etched is:
Perform step S11: test batch to be etched isolation structure 203 second area II before etching
Thickness, obtain isolation structure the first thickness Tn。
In the present embodiment, described batch to be etched is the n-th batch, shape in the n-th batch semiconductor structure
Become after isolation structure 203, the n-th batch is carried out, exist testing the isolation structure 203 of the n-th batch
Actual (real) thickness before etching second area II, it is thus achieved that isolation structure the first thickness Tn.In actual process mistake
Cheng Zhong, owing to there is error for the technique of each batch, the thickness of the isolation structure 203 of the most each batch
There are differences, need the most before etching the thickness of each batch isolation structure 203 to be tested.
Perform step S12: a batch of isolation structure etch rate before testing batch to be etched, acquisition is isolated
Structure the first etch rate γn-1。
Owing to described batch to be etched is the n-th batch, the previous batch of the most described batch to be etched is
N-1 batch, due to the (n-1)th batch and the etching of the second area II of the n-th lot etched isolation structure 203
Speed closest to, therefore, complete to etch the isolation structure 203 second area II of the (n-1)th batch
After technique, obtain the actual etch rate of the (n-1)th batch, and with the actual etch rate of the (n-1)th batch
The degree of depth in conjunction with the required etching of the n-th batch, it is possible to obtain the etch period of the n-th batch, with obtained
Etch period etches the second area II of the isolation structure 203 of the n-th batch, it is possible to make the isolation after etching
The second area II thickness of structure 203 is accurate.
Perform step S12: use isolation structure the first thickness TnWith isolation structure the first etch rate γn-1
Obtain the etch period t of batch to be etchedn=(Tn-Ttarget)/γn-1, wherein, TtargetFor batch to be etched every
Preset thickness after structure 203 second area II etches.
Wherein, Tn-TtargetThe actually required etching of second area II of the isolation structure 203 of the i.e. n-th batch
The degree of depth, and the first etch rate γ of the (n-1)th batchn-1With the etch rate of the n-th batch closest to, partially
Difference minimum, therefore with the actually required etching depth of the n-th batch and the first etch rate γn-1The quarter obtained
Erosion time tnAccurately；With described etch period tnEtch the second area of the isolation structure 203 of the n-th batch
II, it is possible to make the second area II thickness of isolation structure 203 after etching accurate.And, each to be etched batch
Secondary etch period is all obtained by front a batch of actual etch rate, it is possible to make each batch after etching
The second area II thickness of isolation structure 203 homogeneous, advantageously ensure that formed flash memory cell
Or the stable performance of semiconductor device.
A batch of etch rate before the described batch to be etched of above-mentioned test, i.e. tests the etching of the (n-1)th batch
The method of speed refer to Figure 13, including:
Perform step S21: before testing batch to be etched, a batch of isolation structure 203 second area II carves
Thickness before erosion, obtains isolation structure the second thickness Tn-1。
Execution step S22: the thickness after a batch of isolation structure 203 etches before testing batch to be etched
Degree, obtains isolation structure the 3rd thickness Ttn-1。
Perform step S23: use isolation structure the second thickness Tn-1With isolation structure the 3rd thickness Ttn-1Obtain
A batch of etch rate γ before batch to be etchedn-1=(Tn-1-Ttn-1)/tn-1, wherein, described tn-1For to be etched
The time of batch previous lot etched isolation structure.
Refer to Fig. 6 and Fig. 7, Fig. 7 is Fig. 6 cross-sectional view along AA ' direction, in etching
After the second area II (as shown in Figure 5) of the isolation structure 203 of some batch semiconductor structures,
Floating gate layer 202 and isolation structure 203 surface form sacrifice layer 204, and described sacrifice layer 204 has first and opens
Mouth 205, described first opening 205 exposes part floating gate layer 202 and the isolation structure of first area I
203 surfaces.
The material of described sacrifice layer 204 is silicon nitride, and the thickness of described sacrifice layer 204 is 3500 angstroms～4000
Angstrom, the thickness of described sacrifice layer 204 determines the source line layer and the height of word line layer being subsequently formed, therefore
Depending on described sacrifice layer 204 should be according to concrete technical need, this is not restricted.In the present embodiment,
The thickness of described sacrifice layer 204 is 3000 angstroms～4500 angstroms.Described sacrifice layer 204 and the first opening 205
Formation process be: use chemical vapor deposition method in floating gate layer 202 and isolation structure 203 surface shape
Become sacrificial film；Form mask on described sacrificial film surface, described mask exposes sacrificial film surface
The position corresponding with the first opening 205, in the present embodiment, described mask is photoresist layer；Cover with described
Film etching sacrificial layer, till exposing floating gate layer 202 and isolation structure 203 first area I, is formed sacrificial
Domestic animal layer 204 and the first opening 205.
The technique of described etches sacrificial thin film is anisotropic dry etch process, described anisotropic dry
Method etching technics can make the sidewall of the first formed opening 205 relative to substrate 200 surface vertically,
Damage the first opening 205 for forming source line layer, after the size of the most described first opening 205 determines
The size of continuous source line layer.In the present embodiment, the sidewall of described first opening 205 is relative to substrate 200
Surface is vertical, and owing to the material of sacrifice layer 204 is silicon nitride, therefore etching gas includes CF4。
Refer to Fig. 8, Fig. 8 is cross-sectional view based on Fig. 7, at the sidewall of the first opening 205
Surface forms the first side wall 206；With the first side wall 206 and sacrifice layer 204 for mask etching floating gate layer 202
With tunnel oxide 201 till exposing substrate 200, form the second opening 207, and open second
The sidewall surfaces of mouth 207 forms the second side wall 208.
The material of described first side wall 206 is different from sacrifice layer 204, when follow-up removal sacrifice layer 204 it
After, it is possible to retaining described first side wall 206, described first side wall 206 is used for electrically insulating source line layer 209 He
Word line layer；In the present embodiment, the material of described first side wall 206 is silicon oxide, described first side wall 206
Width be 2500 angstroms～3500 angstroms；The formation process of described first side wall 206 is: at sacrifice layer 204
Surface and the sidewall of the first opening 205 and lower surface deposit the first side wall layer；Employing is etched back to work
Skill removes sacrifice layer 204 surface and the first side wall layer of the first opening 205 lower surface, at the first opening
205 sidewalls form the first side wall.The width of described first side wall 206 is by the thickness of described first side wall layer certainly
Fixed, and described first side wall 206 is as the mask of subsequent etching floating gate layer 202, the most described first side
The width of wall 206 determines the size of floating gate layer 202, follow-up institute in formed flash memory cell
Floating gate layer 202 width dimensions formed is 2500 angstroms～3500 angstroms.
Floating gate layer 202 and the technique of tunnel oxide 201 bottom described etching the first opening 205 are each
Heterotropic dry etch process, the width of described second opening 207 is 1000 angstroms～1500 angstroms, institute's shape
The second opening 207 and the first opening 205 that become are used for being formed source line layer, follow-up formed flash memory storage
Unit lays respectively at Xian Ceng both sides, described source, and the flash memory cell being positioned at Xian Ceng both sides, source shares described
Source line layer.Owing to described first opening 205 exposes the first area I of isolation structure 203, therefore institute's shape
The second opening 207 become is positioned at the both sides of the first area I of isolation structure 203, is subsequently formed and opens in first
The source line layer of mouth 205 and the second opening 207 is across the first area I of described isolation structure 203, and covers
The sidewall of the first area I of described isolation structure 203 and top surface.
The material of described second side wall layer 208 is silicon oxide, is used for isolating described floating gate layer 202 with follow-up
The source line layer formed, the formation process of described second side wall 208 and the formation process phase of the first side wall 206
With, do not repeat at this.
Refer to Fig. 9, after forming the second side wall 208, at the first opening 205 (as shown in Figure 7)
With the second opening 207 (as shown in Figure 7) interior formation source line layer 209.
It should be noted that before the source that formed line layer 209, to the substrate 200 bottom the second opening 207
Carry out ion implanting, form the source region of flash memory cell.
Owing to described source line layer 209 is formed in the first opening 205 and the second opening 207, therefore described
Source line layer 209 is across the first area I (as shown in Figure 5) of isolation structure 203, and described source line layer 209
It is also located at substrate 200 surface corresponding with the first area I of isolation structure 203.Described source line layer 209
Material be polysilicon, described source line layer 209 is formed at substrate 200 surface bottom the second opening 207,
And contact with described source region.In the present embodiment, the formation process of described source line layer 209 is: sacrificing
Full first opening 205 is filled on layer 204 surface and the first opening 205 and the second interior deposition of opening 207
Polysilicon layer with the second opening 207；The polysilicon layer higher than sacrifice layer 204 surface is removed in polishing.?
In another embodiment, the formation process of described source line layer 208 can also be selective epitaxial depositing operation.
Refer to Figure 10, after the source that formed line layer 209, remove sacrifice layer 204 (as shown in Figure 9),
And etch floating gate layer 202 until exposing tunnel oxide 201 with the first side wall 206 and source line layer 209.
The technique of described removal sacrifice layer 204 is etching technics, including dry etching or wet etching,
After removing described sacrifice layer 204, expose part floating gate layer 202.In the present embodiment, described sacrifice
The material of layer 204 is silicon nitride, and the technique removing described sacrifice layer 204 is wet-etching technology, described
Wet-etching technology can remove sacrifice layer 204 the most up hill and dale, the etching liquid bag of described wet-etching technology
Include phosphoric acid.In the present embodiment, after removing described sacrifice layer 204, expose the of isolation structure 203
Two region II (as shown in Figure 5) surfaces and be positioned at the second area II both sides of isolation structure 203
The floating gate layer 202 on floating gate layer 202 surface, i.e. subsequent etching is positioned at the second area II of isolation structure 203
Both sides, after etching floating gate layer 202, expose the tunnelling of the second area II both sides of isolation structure 203
Oxide layer 201 surface.
The technique etching described floating gate layer 202 is anisotropic dry etch process, described anisotropic
Etching technics is with described first side wall 206 and source line layer 209 as mask.In the present embodiment, due to every
From structure 203 second area II surface equal to or less than floating gate layer 202 surface, thus in etching isolation junction
During the floating gate layer 202 of the second area II both sides of structure 203, it is difficult to the sidewall surfaces at isolation structure 203
The material of residual floating gate layer 202, thus ensure the stable performance of formed flash memory cell.
In other embodiments, floating gate layer 202 and tunnelling are etched with the first side wall 206 and source line layer 209
During oxide layer 201, moreover it is possible to etching is until exposing the substrate of the second area II both sides of isolation structure 203
Till 200 surfaces, when follow-up shape uses described thermal oxidation technology to form insulating barrier, described insulating barrier can also
Enough in the formation of substrate 200 surface.
Refer to Figure 11, after etching floating gate layer 202 with the first side wall 206 and source line layer 209,
First side wall 206, source line layer 209 and floating gate layer 202 both sides form word line layer 221, described word line layer 221
And electrically insulated by insulating barrier 222 between floating gate layer 202.
After with the first side wall 206 and source line layer 209 for mask etching floating gate layer 202, expose isolation
Second area II (as shown in Figure 5) surface of structure 203 and be positioned at the second of isolation structure 203
Tunnel oxide 201 surface of II both sides, region, the word line layer 221 formed is across described isolation structure
The second area II of 203, and cover sidewall and the top surface of the second area II of described isolation structure 203；
The isolation structure 203 second area II thickness being additionally, since some batches is the most homogeneous, some batches
The sidewall of isolation structure 203 second area II is difficult to remain the material of floating gate layer 202, makes formed word
Line layer 221 stable performance.
The formation process of described word line layer 221 is: after etching described floating gate layer 202, use hot oxygen
Sidewall surfaces and Xian Ceng surface, source that metallization processes exposes at floating gate layer 202 form insulating barrier 222；Formed
After insulating barrier 222, formation of deposits wordline thin film, described wordline thin film covers substrate 200, floating gate layer
202, the first side wall 206 and Xian Ceng209 surface, source；It is etched back to described wordline thin film, removes source line layer 209
With the wordline thin film on substrate 200 surface, form word line layer 221.
The material of described word line layer 221 is polysilicon, and formation process is: after forming insulating barrier 222,
On tunnel oxide 201, insulating barrier the 222, first side wall 206 and Xian Ceng209 surface, source, deposition wordline is thin
Film；It is etched back to described wordline thin film till exposing source line layer 209, forms word line layer.
It should be noted that after forming word line layer 209, at described source line layer 209, word line layer 221
Drain region is formed with carrying out ion implanting in the substrate 200 of the both sides of floating gate layer 202.
In sum, when being sequentially etched the second area of isolation structure of some batch semiconductor structures,
By testing a batch of isolation structure etch rate before described batch to be etched, testing batch to be etched and exist
The thickness of the isolation structure before etching, and combine the isolation structure preset thickness after lot etched to be etched,
Obtain the etch period of each batch to be etched；Wherein, owing to the etch rate variations of adjacent two batches is little,
Therefore, with the speed of batch to be etched previous lot etched isolation structure, and combine batch to be etched at quarter
Actual (real) thickness before erosion and the preset thickness after etching, can either obtain batch the most to be etched
Etch period；The isolation structure second area of each batch to be etched is etched with the etch period obtained,
The thickness that can make the isolation structure second area after each lot etched is the most homogeneous, it is to avoid because of isolation structure
Second area thickness cross thin and cause programming interference or wordline turn-off capacity to be deteriorated, or avoid therefore isolating
The second area thickness of structure is blocked up and causes the data holding ability of floating boom to decline, and the flash memory formed is deposited
The stable performance of storage unit.
Further, the determination method of the etch period of each batch to be etched is: test batch to be etched
Thickness, obtains isolation structure the first thickness Tn；A batch of isolation structure etching before testing batch to be etched
Speed, obtains isolation structure the first etch rate γn-1；Use isolation structure the first thickness TnAnd isolation junction
Structure the first etch rate γn-1Obtain the etch period t of batch to be etchedn=(Tn-Ttarget)/γn-1, wherein,
TtargetFor the preset thickness after the isolation structure etching of batch to be etched.Wherein, Tn-TtargetThe most to be etched batch
Secondary isolation structure second area is actually needed the degree of depth of etching；Quarter due to adjacent two lot etched techniques
Erosion speed change is less, therefore, is to be etched batch with actual etch rate a batch of before batch to be etched
Secondary etch rate, and combine the etching depth of the isolation structure second area reality of batch to be etched, institute
The etch period of the batch to be etched obtained is the most accurate；The etching of the batch each to be etched to be obtained
Time etches the isolation structure second area of this batch to be etched, it is possible to make each batch isolation junction after etching
The thickness of structure second area is homogeneous accurately, makes the stable performance of formed flash memory cell.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art, not
Depart from the spirit and scope of the present invention, all can make various changes or modifications, therefore the protection model of the present invention
Enclose and should be as the criterion with claim limited range.
Claims (9)
1. the forming method of a flash memory cell, it is characterised in that including:
Thering is provided some batch semiconductor structures, described semiconductor structure includes: substrate, and described substrate has
Some floating gate regions arranged in parallel, have isolation area between adjacent floating grid region, the floating gate region table of described substrate
Mask has tunnel oxide and is positioned at the floating gate layer on tunnel oxide surface, the isolation area of described substrate
Inside having isolation structure, the surface of described isolation structure equals to or higher than floating gate layer surface, described isolation junction
Structure has adjacent first area and second area；
It is sequentially etched the second area of the isolation structure of some batch semiconductor structures, makes the of isolation structure
Two region surface are less than surface, first area, wherein, the determination side of the etch period of each batch to be etched
Method includes:
Test the thickness of batch to be etched isolation structure second area before etching, obtain isolation structure
First thickness Tn；
A batch of isolation structure etch rate before testing batch to be etched, obtains isolation structure first and etches
Speed γn-1；
Use isolation structure the first thickness TnWith isolation structure the first etch rate γn-1Obtain batch to be etched
Etch period tn=(Tn-Ttarget)/γn-1, wherein, TtargetIsolation structure second area for batch to be etched
Preset thickness after etching；
Etch some batch semiconductor structures isolation structure second area after, floating gate layer and every
Forming sacrifice layer from body structure surface, described sacrifice layer has the first opening, and described first opening exposes portion
Divide floating gate layer and the isolation structure surface of first area.
2. the forming method of flash memory cell as claimed in claim 1, it is characterised in that treat described in test
Before etching batch, the method for a batch of etch rate is:
Thickness before a batch of isolation structure etching before testing batch to be etched, obtains isolation structure the
Two thickness Tn-1；
Thickness after a batch of isolation structure etching before testing batch to be etched, obtains isolation structure the
Three thickness Ttn-1；
Use isolation structure the second thickness Tn-1With isolation structure the 3rd thickness Ttn-1Before obtaining batch to be etched
A batch of etch rate γn-1=(Tn-1-Ttn-1)/tn-1, wherein, described tn-1For a collection of before batch to be etched
The time of secondary etching isolation structure.
3. the forming method of flash memory cell as claimed in claim 1, it is characterised in that also include:
Sidewall surfaces at the first opening forms the first side wall；
With the first side wall and sacrifice layer for mask etching floating gate layer and tunnel oxide until exposing substrate and being
Only, form the second opening, and form the second side wall in the sidewall surfaces of the second opening；
After forming the second side wall, in the first opening and the second opening, form source line layer；
After forming source line layer, remove sacrifice layer and etch floating gate layer with the first side wall and source line layer until
Expose tunnel oxide；
After etching floating gate layer with the first side wall and source line layer, at the first side wall, source line layer and floating gate layer
Both sides form word line layer, are electrically insulated by insulating barrier between described word line layer and floating gate layer.
4. the forming method of flash memory cell as claimed in claim 3, it is characterised in that described word line layer
Formation process be: etching after described floating gate layer, use thermal oxidation technology to expose at floating gate layer
Sidewall surfaces and Xian Ceng surface, source formed insulating barrier；After forming insulating barrier, formation of deposits wordline
Thin film, described wordline thin film covers substrate, floating gate layer, the first side wall and Xian Ceng surface, source；It is etched back to
Described wordline thin film, removes source line layer and the wordline thin film of substrate surface, forms word line layer.
5. the forming method of flash memory cell as claimed in claim 4, it is characterised in that also include:
Before forming word line layer, etch floating gate layer and tunnel oxide with the first side wall and source line layer until exposing
Till going out substrate, described thermal oxidation technology also forms insulating barrier at substrate surface.
6. the forming method of the flash memory cell stated such as claim 3, it is characterised in that forming word line layer
Afterwards, in the substrate of source line layer, word line layer and floating gate layer both sides, drain region is formed.
7. the forming method of flash memory cell as claimed in claim 3, it is characterised in that at the source that formed line
Before Ceng, in the substrate of the second open bottom, form source region.
8. the forming method of flash memory cell as claimed in claim 3, it is characterised in that described first side
The material of wall, the second side wall and insulating barrier is silicon oxide, and the material of described word line layer and source line layer is many
Crystal silicon.
9. the forming method of flash memory cell as claimed in claim 1, it is characterised in that described isolation junction
The forming method of structure is: after substrate surface forms tunnel oxide and floating gate layer, etches isolation area
Floating gate layer, tunnel oxide and section substrate to form groove；With floating gate layer table in described groove
Face deposits dielectric materials；The dielectric material higher than floating gate layer surface is removed in polishing, forms isolation structure.
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| CN105845593B (en) * | 2016-03-22 | 2018-08-10 | 上海华虹宏力半导体制造有限公司 | Monitoring methods of etching |
| CN106129008B (en) * | 2016-08-11 | 2018-11-16 | 上海华虹宏力半导体制造有限公司 | The forming method of flash memory |
| CN106206453B (en) * | 2016-08-30 | 2019-05-14 | 上海华虹宏力半导体制造有限公司 | The forming method of memory |
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| TW495930B (en) * | 2001-07-24 | 2002-07-21 | Vanguard Int Semiconduct Corp | Manufacturing method for flash memory |
| CN101777521A (en) * | 2010-01-28 | 2010-07-14 | 上海宏力半导体制造有限公司 | Manufacturing method of split-gate type flash memory of shared word line |
| CN102315252A (en) * | 2011-09-28 | 2012-01-11 | 上海宏力半导体制造有限公司 | Flash memory unit for shared source line and forming method thereof |
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| TW495930B (en) * | 2001-07-24 | 2002-07-21 | Vanguard Int Semiconduct Corp | Manufacturing method for flash memory |
| CN101777521A (en) * | 2010-01-28 | 2010-07-14 | 上海宏力半导体制造有限公司 | Manufacturing method of split-gate type flash memory of shared word line |
| CN102315252A (en) * | 2011-09-28 | 2012-01-11 | 上海宏力半导体制造有限公司 | Flash memory unit for shared source line and forming method thereof |
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