CN112750790B - Flash memory and method for manufacturing the same - Google Patents
Flash memory and method for manufacturing the same Download PDFInfo
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- CN112750790B CN112750790B CN202110093752.7A CN202110093752A CN112750790B CN 112750790 B CN112750790 B CN 112750790B CN 202110093752 A CN202110093752 A CN 202110093752A CN 112750790 B CN112750790 B CN 112750790B
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- 230000015654 memory Effects 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims description 44
- 238000002955 isolation Methods 0.000 claims abstract description 69
- 238000005530 etching Methods 0.000 claims abstract description 28
- 230000005684 electric field Effects 0.000 claims abstract description 3
- 239000010410 layer Substances 0.000 claims description 185
- 239000000463 material Substances 0.000 claims description 45
- 239000000758 substrate Substances 0.000 claims description 41
- 239000002346 layers by function Substances 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
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Abstract
The invention provides a flash memory and a manufacturing method thereof, wherein an isolation structure extending towards an initial floating gate layer and covering the upper surface of a part of the initial floating gate layer is formed in the initial floating gate layer, so that when the floating gate layer is formed by etching part of the initial floating gate layer, the part of the initial floating gate layer covered by the isolation structure is not etched, and at least the part of the floating gate layer covered by the isolation structure forms a floating gate tip. The floating gate tip formed by the manufacturing method of the flash memory can enhance the local electric field and improve the erasing efficiency when performing the electronic erasing operation.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a flash memory and a method for manufacturing the same.
Background
Flash memory is an important device in integrated circuit products. The main characteristic of flash memory is that it can keep the stored information for a long time without applying voltage. The flash memory has the advantages of high integration level, high access speed, easy erasing and the like, and is widely applied.
Current flash memories fall into two types: stacked gate (stack gate) flash memory and split gate (split gate) flash memory. The stacked gate flash memory has a floating gate and a control gate above the floating gate, and the control gates of the same column are connected to serve as word lines, while the current stacked gate flash memory has the over-erase problem. Unlike the stacked gate flash memory, the split gate flash memory forms a word line as an erase gate on one side of a floating gate and is programmed by hot electron injection at a source terminal, thereby having higher programming efficiency.
However, the self-aligned split gate flash memory formed in the prior art has poor erasing performance, a higher voltage needs to be applied to a word line in the erasing process, and a larger peripheral circuit area needs to be occupied in design, so that the power consumption of the device is higher in erasing.
Disclosure of Invention
The invention aims to provide a flash memory and a manufacturing method thereof, which are used for solving the problem of higher power consumption in the conventional split gate flash memory erasing process.
In order to solve the above problems, the present invention provides a method for manufacturing a flash memory,
providing a substrate;
forming an initial floating gate layer on the substrate, wherein a first groove extending to the substrate is formed in the initial floating gate layer;
forming an isolation structure, wherein the isolation structure fills the first trench and extends to cover part of the upper surface of the initial floating gate layer;
etching the initial floating gate layer to form a floating gate tip at least at a portion of the initial floating gate layer covered by the isolation structure to form a floating gate layer;
and etching the floating gate layer to form a second groove, and forming an erasing gate layer in the second groove.
Optionally, the method for forming the first trench and the isolation structure includes:
sequentially forming a floating gate material layer and a first mask layer with a first opening on the substrate;
etching the floating gate material layer and the substrate by taking the first mask layer as a mask, and stopping on the substrate to form the initial floating gate layer and the first groove;
etching the first mask layer to enlarge the first opening;
and forming the isolation structure in the increased first opening and the first groove, so that the isolation structure extends to cover part of the upper surface of the initial floating gate layer.
Optionally, the width of the first opening is increased to be 0.02 um-0.08 um.
Optionally, the method for forming the isolation structure and the initial floating gate layer includes:
forming a floating gate material layer on the substrate;
sequentially etching the floating gate material layer and the substrate and stopping on the substrate to form the initial floating gate layer and the first groove;
forming an isolation material layer on the upper surfaces of the first groove and the initial floating gate layer;
and etching the isolation material layer to enable the isolation structure to cover part of the upper surface of the initial floating gate layer, so as to form the isolation structure.
Optionally, the width of the isolation structure covering the upper surface of the initial floating gate layer is 0.01 um-0.04 um.
Optionally, the height difference between the top and the bottom of the floating gate tip is 10 nm-30 nm.
Optionally, the method for forming the erase gate layer includes:
forming a mask functional layer on the isolation structure and the floating gate layer, wherein a first slot is formed in the mask functional layer, and the first slot exposes part of the isolation structure and the floating gate layer;
etching the floating gate layer by taking the mask functional layer as a mask to form a second groove in the floating gate layer;
and forming the erasing gate layer in the second groove.
Optionally, the method for forming the mask functional layer includes:
forming a second mask layer on the floating gate layer and the isolation structure, wherein a third slot is formed in the second mask layer;
and forming a side wall on the side wall of the third slot so as to form the mask functional layer by using the side wall and the second mask layer, and defining the first slot by the side wall on the opposite side wall of the third slot.
Optionally, before forming the erase gate layer in the second trench, the method further includes: and forming an oxide layer on the side wall and the bottom of the second groove.
In order to solve the above problems, the present invention also provides a flash memory, which is manufactured according to the manufacturing method of the flash memory as described in any one of the above.
In the method for manufacturing the flash memory, the isolation structure which extends towards the initial floating gate layer and covers the upper surface of the part of the initial floating gate layer is formed in the initial floating gate layer, so that when the part of the initial floating gate layer is etched to form the floating gate layer, the part of the initial floating gate layer covered by the isolation structure is not etched, and at least the part of the formed floating gate layer covered by the isolation structure forms a floating gate tip. When the floating gate tip formed by the method is subjected to electronic erasing operation, the local electric field can be enhanced, and the erasing efficiency is improved.
Drawings
FIG. 1 is a flow chart of a method for manufacturing a flash memory according to an embodiment of the invention;
FIGS. 2 to 10 are schematic views illustrating a semiconductor manufacturing method according to an embodiment of the present invention during the manufacturing process;
wherein, the reference numerals are as follows:
10-a substrate;
20-a first dielectric layer; a 20' -first layer of dielectric material;
a 30' -initial floating gate layer;
30-a floating gate layer; 300-a layer of floating gate material;
40-a first mask layer;
50-isolation structures;
60-masking the functional layer; 61-a second mask layer;
62-a first side wall; 600-a layer of mask material;
71-a second side wall; 72-a third side wall;
73-fourth side walls;
80-an erase gate layer;
90-word lines;
101-a first opening; 102-a second opening;
100-a first trench;
201-first slotting; 202-second slotting;
200-second trenches.
Detailed Description
The following describes a flash memory and a method for manufacturing the same in detail with reference to the drawings and the embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments.
FIG. 1 is a flow chart of a method for manufacturing a flash memory according to an embodiment of the invention; fig. 2 to 10 are schematic views illustrating a semiconductor manufacturing method according to an embodiment of the present invention in a manufacturing process thereof. The following describes in detail the steps of the method for manufacturing the backside-illuminated sensor according to the present embodiment with reference to fig. 1 to 10.
In step S10, as shown in fig. 2, a substrate 10 is provided and an initial floating gate layer 30' is formed on said substrate 10. In this embodiment, the substrate 10 may include a semiconductor material, an insulating material, a conductor material, or any combination thereof, and may have a single-layer structure or a multi-layer structure. Thus, the substrate may be a semiconductor material such as Si, siGe, siGeC, siC, gaAs, inAs, inP and other III/V or II/VI compound semiconductors. Layered substrates such as, for example, si/SiGe, si/SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator may also be included.
In step S20, as shown in fig. 3, an initial floating gate layer 30 'is formed on the substrate 1, and a first trench 100 extending to the substrate is formed in the initial floating gate layer 30'.
In step S30, as shown in fig. 5, an isolation structure 50 is formed, the isolation structure 50 filling the first trench 100 and extending to cover a portion of the upper surface of the initial floating gate layer 30'. In this embodiment, the width of the isolation structure covering the upper surface of the initial floating gate layer 30' is 0.01um to 0.04um.
In this embodiment, the method of forming the first trench 100 and the isolation structure 50 includes the following steps one to four.
In step one, as shown in fig. 2 and 3, a floating gate material layer 300 and a first mask layer 40 having a first opening 101 are sequentially formed on the substrate 10.
The material of the first mask layer 40 may be silicon nitride, and the method for forming the first mask layer 40 may be to sequentially form a first mask material layer (not shown) and a photoresist layer (not shown) on the floating gate material layer 300, and etch the first mask material layer (not shown) by using the photoresist layer (not shown) as a mask to form the first mask layer 40. And, the material of the floating gate material layer 300 may be polysilicon.
Furthermore, in the present embodiment, before forming the floating gate material layer 300 on the substrate 10, the method further includes: a first dielectric material layer 20 'is formed on the substrate 10, wherein the material of the first dielectric material layer 20' may be silicon oxide.
In step two, as shown in fig. 3, the floating gate material layer 300 and the substrate 10 are sequentially etched with the first mask layer 40 as a mask to form an initial floating gate layer 30', and the first opening 101 is extended to the initial floating gate layer 30' and the substrate 10, and stopped in the substrate 10 to form the initial floating gate layer 30' and the first trench 100.
In this embodiment, the first opening 101 extends to the initial floating gate layer 30' and the substrate 10, and then a second opening 102 is formed, and the first opening 101 and the second opening 102 penetrate to form a first trench 100. In this embodiment, while sequentially etching the floating gate material layer 300 and the substrate 10 with the first mask layer 40 as a mask, the method further includes: the first dielectric material layer 20' is etched to form a first dielectric layer 20, and the second opening 102 extends through the first dielectric layer 20.
In this embodiment, the etching method for etching the floating gate material layer 300 and the substrate 10 may be wet etching or dry etching. The specific etching method is not particularly limited herein, and is based on actual conditions.
In step three, as shown in fig. 4, the first mask layer 40 is etched, to increase the width of the first opening 101,
in this embodiment, the width of the first opening 101 is increased to 0.02um to 0.08um. And the width of the first opening 101 after being increased is larger than the width of the second opening 102.
Further, in this embodiment, the etching method for etching the first mask layer 40 is wet etching, and in an alternative embodiment, the etching method for the second etching process may also be dry etching.
In step four, as shown in fig. 5, the isolation structure 50 is formed in the first trench 100 of the increased first opening 101, so that the isolation structure 50 extends to cover a portion of the upper surface of the initial floating gate layer 30'. In this embodiment, the method of forming the isolation structure 50 may include: an isolation material is deposited over the first trenches 100 and the upper surface of the first mask layer 40 to form an isolation material layer, and then the isolation material layer over the upper surface of the first mask layer 40 is removed by grinding to form isolation structures 50 within the first trenches 100. In this embodiment, the isolation material may be silicon oxide or silicon nitride, and the method for depositing the isolation material includes chemical vapor deposition.
Optionally, the method of forming the first trench 100 and the isolation structure 50 may further include the following first to fourth steps.
In a first step, as shown in fig. 2, a layer 300 of floating gate material is formed on the substrate 10.
In a second step, as shown in fig. 3, the floating gate material layer 300 and the substrate 10 are etched in sequence and stopped in the substrate 10 to form the initial floating gate layer 30' and the first trench 100.
In a third step, a layer of isolating material is formed on the upper surfaces of the first trench 100 and the initial floating gate layer 30'. In this step, the isolation material layer may be formed by depositing an isolation material by a chemical vapor deposition method.
In a fourth step, the isolation material layer is etched to form the isolation structure 50, and the isolation structure 50 is made to cover a portion of the upper surface of the initial floating gate layer 30'. In this embodiment, a photoresist layer may be formed on the isolation material layer, where the photoresist layer has a plurality of third openings, the third openings are located on the initial floating gate layer 30', and the width of the third openings is smaller than the width of the initial floating gate layer 30' between adjacent isolation structures 50. The isolation material layer is then etched using the photoresist layer as a mask to form the isolation structures 50.
In step S40, as shown in fig. 6, in the present embodiment, the initial floating gate layer 30 'is etched to form a floating gate layer 30, and a floating gate tip a is formed at least at a portion of the initial floating gate layer 30' covered with the isolation structure 50.
In this embodiment, as shown in fig. 6, the initial floating gate layer 30 'between the adjacent isolation structures 50 is etched in this embodiment to remove a portion of the initial floating gate layer 30' away from the substrate 10. This is done so that the initial floating gate layer 30' below the top of the isolation structure 50 is left to form the floating gate tip a. Wherein, the portion of the floating gate layer 30 between the adjacent isolation structures 50 is arc-shaped. In this embodiment, the etching method for etching the initial floating gate layer is dry etching.
And, in the present embodiment, the height difference between the top and bottom of the floating gate tip a is formed to be 10nm to 30nm. In this way, the discharge effect of the floating gate tip a is optimal. Wherein the top refers to the end of the floating gate tip furthest from the substrate 10, and the bottom refers to the end of the floating gate tip in contact with the substrate 10.
In step S50, as shown in fig. 10, the floating gate layer 30 is etched to form a second trench 200, and an erase gate layer 80 is formed in the second trench 200. Wherein, the extending direction of the erasing gate layer 80 is the same as the extending direction of the isolation structure 50.
In this embodiment, as shown in fig. 7, the method for forming the erase gate layer 80 includes the following steps one to three.
In the first step, referring to fig. 7 to 10, a mask functional layer 60 is formed on the isolation structure 50 and the floating gate layer 30, wherein a first trench 201 is formed in the mask functional layer 60, and the first trench 201 exposes a portion of the isolation structure 50 and the floating gate layer 30. In this embodiment, the extending direction of the first slot 201 is perpendicular to the extending direction of the isolation structure 50.
In the second step, as shown in fig. 9, the floating gate layer 30 is etched with the mask functional layer 60 as a mask to form a second trench 202 in the floating gate layer 30, and the first trench 201 and the second trench 202 penetrate to form a second trench 200. Furthermore, in this embodiment, the method further includes etching the first dielectric layer 20 at the same time as the floating gate layer 30 is etched, so that the second trench 202 extends into the first dielectric layer 20.
In this embodiment, the method of forming the mask functional layer 60 includes the following steps.
First, as shown in fig. 8, a second mask layer 61 is formed on the floating gate layer 30 and the isolation structure 50, and a third trench (not shown) is formed in the second mask layer 61.
Next, a sidewall 62 is formed on a sidewall of the third trench (not shown), so that the mask functional layer 60 is formed by using the sidewall 62 and the second mask layer 61, and the first trench 201 is defined by the sidewall 62 located on an opposite sidewall of the third trench (not shown). The second mask layer 61 and the side wall 62 may be made of silicon nitride or silicon oxide.
In step three, the erase gate layer 80 is formed within the second trench 200. In this embodiment, the material of the erase gate layer 80 may be polysilicon, where the method for forming the erase gate layer 80 may include: a polysilicon layer is formed on the second trenches 200 and the upper surface of the mask functional layer 60, and the polysilicon layer on the upper surface of the mask functional layer 60 is removed by grinding to form the erase gate layer 80 in the second trenches 200.
Furthermore, in the present embodiment, before forming the erase gate layer 80 in the trench 200, the method further includes: a first oxide layer 71 is formed on the sidewalls and bottom of the second trench 200. The material of the first oxide layer 71 may be silicon oxide, and the first oxide layer 71 is used for insulating the floating gate layer 30 and the erase gate layer 80.
Further, as shown in fig. 10, after forming the erase gate layer 80, the method further includes: and removing the second mask layer 61, and removing part of the first dielectric layer 20 and the floating gate layer 30 by using the first side wall 62 as a mask and performing self-aligned etching. And forming a third side wall 72 on the etched side wall of the floating gate layer 30, forming a word line 90 on the side wall of the third side wall 72, and forming a fourth side wall 73 on the side wall of the word line 90. The material of the third sidewall 72 and the fourth sidewall 73 may be silicon oxide. The third sidewall 72 is used for insulating the floating gate layer 30 and the word line 90 after etching.
Further, the embodiment also discloses a flash memory, which is prepared according to the manufacturing method of the flash memory.
In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, so that the same similar parts of each embodiment are referred to each other.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (10)
1. A method for manufacturing a flash memory is characterized in that,
providing a substrate;
forming an initial floating gate layer on the substrate, wherein a first groove extending to the substrate is formed in the initial floating gate layer;
forming an isolation structure, wherein the isolation structure fills the first trench and extends to cover part of the upper surface of the initial floating gate layer;
etching the initial floating gate layer to form a floating gate tip at least at a portion of the initial floating gate layer covered by the isolation structure to form a floating gate layer;
etching the floating gate layer to form a second groove, and forming an erasing gate layer in the second groove;
the floating gate tip can enhance a local electric field when performing an electronic erasing operation.
2. The method of manufacturing a flash memory device of claim 1, wherein the method of forming the first trench and the isolation structure comprises:
sequentially forming a floating gate material layer and a first mask layer with a first opening on the substrate;
etching the floating gate material layer and the substrate by taking the first mask layer as a mask, and stopping on the substrate to form the initial floating gate layer and the first groove;
etching the first mask layer to enlarge the first opening;
and forming the isolation structure in the increased first opening and the first groove, so that the isolation structure extends to cover part of the upper surface of the initial floating gate layer.
3. The method of manufacturing a flash memory device according to claim 2, wherein the first opening increases in width by 0.02um to 0.08um.
4. The method of manufacturing a flash memory device of claim 1, wherein the method of forming the isolation structure and the initial floating gate layer comprises:
forming a floating gate material layer on the substrate;
sequentially etching the floating gate material layer and the substrate and stopping on the substrate to form the initial floating gate layer and the first groove;
forming an isolation material layer on the upper surfaces of the first groove and the initial floating gate layer;
and etching the isolation material layer to form the isolation structure, and enabling the isolation structure to cover part of the upper surface of the initial floating gate layer.
5. The method of claim 1, wherein the isolation structure has a width of 0.01um to 0.04um covering the upper surface of the initial floating gate layer.
6. The method of manufacturing a flash memory device according to claim 1, wherein a height difference between a top and a bottom of the floating gate tip is 10nm to 30nm.
7. The method of manufacturing a flash memory device according to claim 1, wherein the method of forming the erase gate layer comprises:
forming a mask functional layer on the isolation structure and the floating gate layer, wherein a first slot is formed in the mask functional layer, and the first slot exposes part of the isolation structure and the floating gate layer;
etching the floating gate layer by taking the mask functional layer as a mask to form a second groove in the floating gate layer;
and forming the erasing gate layer in the second groove.
8. The method of manufacturing a flash memory device according to claim 7, wherein the method of forming the mask function layer comprises:
forming a second mask layer on the floating gate layer and the isolation structure, wherein a third slot is formed in the second mask layer;
and forming a side wall on the side wall of the third slot so as to form the mask functional layer by using the side wall and the second mask layer, and defining the first slot by the side wall on the opposite side wall of the third slot.
9. The method of manufacturing a flash memory device of claim 8, wherein prior to forming the erase gate layer in the second trench, the method further comprises: and forming an oxide layer on the side wall and the bottom of the second groove.
10. A flash memory device manufactured according to the method of manufacturing a flash memory device according to any one of claims 1 to 9.
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