CN109950247A - The manufacturing method of Split-gate flash memory - Google Patents
The manufacturing method of Split-gate flash memory Download PDFInfo
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- CN109950247A CN109950247A CN201910246202.7A CN201910246202A CN109950247A CN 109950247 A CN109950247 A CN 109950247A CN 201910246202 A CN201910246202 A CN 201910246202A CN 109950247 A CN109950247 A CN 109950247A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000010410 layer Substances 0.000 claims abstract description 203
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 95
- 229920005591 polysilicon Polymers 0.000 claims abstract description 60
- 239000000463 material Substances 0.000 claims abstract description 59
- 239000002346 layers by function Substances 0.000 claims abstract description 28
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 230000005641 tunneling Effects 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000011241 protective layer Substances 0.000 claims abstract description 12
- 239000002210 silicon-based material Substances 0.000 claims description 34
- 238000005530 etching Methods 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 26
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 11
- 230000000694 effects Effects 0.000 abstract description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 239000002784 hot electron Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- -1 silicon gallium compound Chemical class 0.000 description 1
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- Non-Volatile Memory (AREA)
Abstract
The present invention provides a kind of manufacturing method of Split-gate flash memory, comprising the following steps: provides semi-conductive substrate, sequentially forms matcoveredn, polysilicon material layer and dielectric layer in the semiconductor substrate；It etches the dielectric layer and forms first groove；The polysilicon material layer is etched in the first groove is arc-shaped its surface；Remove the remaining dielectric layer；Functional layer is formed on the polysilicon material layer；The functional layer is etched to form second groove in the functional layer；The polysilicon material layer is etched in the second groove to exposing the protective layer to form floating gate layer, wherein the vertex of the floating gate layer forms cutting-edge structure.The cutting-edge structure enhances floating gate layer to the electric field strength of wordline, so that the electronics in floating gate layer is easy to pass through tunnel oxide arrival wordline at the cutting-edge structure by tunneling effect under the big electric field of intensity, enhance tunneling effect, improves efficiency of erasing.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a split-gate flash memory.
Background
In the development of the existing memory, a split-gate flash memory has become an important non-volatile memory, the split-gate flash memory uses a floating gate layer as a storage unit, the floating gate layer performs programming and erasing through F-N electron tunneling and channel hot electron injection, the channel hot electron is injected into the floating gate layer during programming, a channel is in a blocking state, and the channel is in a state of '0'; when erased, the channel is in the open state, which is state "1", by F-N electron tunneling. Split gate flash memory is widely used for its high efficiency of programming and large area flash capability.
The erasing is to form a voltage difference between a word line and a floating gate layer of the split-gate flash memory (where the floating gate is in a low-voltage state and the word line is in a high-voltage state), the voltage difference enables the two to form a large electric field, and electrons in the floating gate layer pass through a tunneling oxide layer from the edge of the floating gate layer to reach the word line through a tunneling effect. However, in the existing split-gate flash memory, due to the defect that electrons of the floating gate layer cannot reach word lines quickly due to the appearance of the floating gate layer, the erasing performance of the split-gate flash memory is not ideal.
Disclosure of Invention
The invention aims to provide a manufacturing method of a split-gate flash memory, which aims to solve the problem that the erasing performance of the split-gate flash memory is not ideal.
In order to solve the above technical problem, the present invention provides a method for manufacturing a split gate flash memory, comprising the following steps:
providing a semiconductor substrate, wherein a protective layer, a polycrystalline silicon material layer and a dielectric layer are sequentially formed on the semiconductor substrate;
etching the dielectric layer until the polycrystalline silicon material layer is exposed so as to form a first groove in the dielectric layer;
etching the polycrystalline silicon material layer in the first groove to enable the surface of the polycrystalline silicon material layer in the first groove to be arc-shaped;
removing the residual dielectric layer and exposing the polycrystalline silicon material layer;
forming a functional layer, wherein the functional layer covers the polycrystalline silicon material layer;
etching the functional layer to form a second groove in the functional layer, wherein the second groove exposes the polycrystalline silicon material layer;
and etching the polysilicon material layer in the second groove until the protective layer is exposed to form a floating gate layer, wherein a tip structure is formed at the top corner of the floating gate layer.
Optionally, in the manufacturing method of the split-gate flash memory, after the forming of the tip structure, the method further includes:
and forming a side wall structure, wherein the side wall structure covers the side wall of the second groove.
Optionally, in the manufacturing method of the split-gate flash memory, after the forming of the sidewall structure, the method further includes:
and forming a tunneling oxide layer which covers the side wall structure and the bottom wall of the second groove.
Optionally, in the manufacturing method of the split-gate flash memory, after the forming of the tunneling oxide layer, the method further includes:
and forming a word line, wherein the word line fills the second groove.
Optionally, in the method for manufacturing a split-gate flash memory, the angle of the tip structure formed is between 10 ° and 80 °.
Optionally, in the manufacturing method of the split-gate flash memory, the thickness of the polysilicon material layer is between that of the polysilicon material layerIn the meantime.
Optionally, in the manufacturing method of the split-gate flash memory, the polysilicon material layer is etched in the first trench, so that the surface of the polysilicon material layer in the first trench is in an arc shape, and the maximum thickness of the polysilicon material layer is between that of the polysilicon material layer in the first trench and that of the polysilicon material layer in the first trenchTo (c) to (d); the polysilicon material layer has a minimum thickness betweenIn the meantime.
Optionally, in the manufacturing method of the split-gate flash memory, the dielectric layer is etched by using a dry etching process.
Optionally, in the manufacturing method of the split-gate flash memory, the polysilicon material layer is etched in the first trench by using an isotropic etching process, so that the surface of the polysilicon material layer in the first trench is arc-shaped.
Optionally, in the manufacturing method of the split-gate flash memory, hydrogen-containing gas is used to etch the polysilicon material layer in the first trench, so that the surface of the polysilicon material layer in the first trench is arc-shaped.
The split-gate flash memory has a tip at the edge of the floating gate at the junction of the floating gate layer and the word line, electrons in the floating gate layer can pass through the tunneling oxide layer from the tip to the word line through a tunneling effect, so that the floating gate is changed from a state of being rich in electrons to a state of being lack of electrons, and the split-gate flash memory is effectively erased. However, in the current split-gate flash memory, the edge of the floating gate layer close to the word line generally forms a 90 ° right-angled tip, and because of the manufacturing process, the tip is easily blunted and gradually becomes an obtuse angle greater than 90 °, so that the electric field intensity from the floating gate layer to the word line is reduced, and the erasing efficiency is reduced.
In summary, the present invention provides a method for manufacturing a split gate flash memory, which includes the following steps: providing a semiconductor substrate, wherein a protective layer, a polycrystalline silicon material layer and a dielectric layer are sequentially formed on the semiconductor substrate; etching the dielectric layer to form a first groove; etching the polycrystalline silicon material layer in the first groove to enable the surface of the polycrystalline silicon material layer in the first groove to be in an arc shape; removing the residual dielectric layer; forming a functional layer on the polycrystalline silicon material layer; etching the functional layer to form a second groove in the functional layer, wherein the second groove exposes the polycrystalline silicon material layer; and etching the polysilicon material layer in the second groove until the protective layer is exposed to form a floating gate layer, wherein a tip structure is formed at the top corner of the floating gate layer. The tip structure enables the electric field intensity from the floating gate layer to the word line to be enhanced, so that electrons in the floating gate layer easily penetrate through the tunneling oxide layer from the tip structure to the word line through the tunneling effect under the high-intensity electric field, the tunneling effect is enhanced, and the erasing efficiency is improved.
Drawings
FIGS. 1-10 are schematic views of semiconductor structures in various steps of a method for manufacturing a split-gate flash memory according to an embodiment of the present invention;
wherein,
100-a semiconductor substrate, 110-a protective layer, 120-a polycrystalline silicon material layer, 121-a polycrystalline silicon material layer, 122-a tip structure, 123-a floating gate layer, 130-a dielectric layer, 140-a functional layer, 141-an ONO film layer, 142-a control gate layer, 143-a first silicon nitride layer, 150-a side wall structure, 151-a first silicon oxide layer, 152-a second silicon nitride layer, 160-a tunneling oxide layer, 200-a word line, 300-a first trench and 310-a second trench, wherein the polycrystalline silicon material layer is positioned on the surface in the first trench.
Detailed Description
The following describes the manufacturing method of the split-gate flash memory according to the present invention with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
The invention provides a manufacturing method of a split-gate flash memory, which comprises the following steps:
providing a semiconductor substrate, wherein a protective layer, a polycrystalline silicon material layer and a dielectric layer are sequentially formed on the semiconductor substrate;
etching the dielectric layer until the polycrystalline silicon material layer is exposed so as to form a first groove in the dielectric layer;
etching the polycrystalline silicon material layer in the first groove to enable the surface of the polycrystalline silicon material layer in the first groove to be arc-shaped;
removing the residual dielectric layer and exposing the polycrystalline silicon material layer;
forming a functional layer, wherein the functional layer covers the polycrystalline silicon material layer;
etching the functional layer to form a second groove in the functional layer, wherein the second groove exposes the polycrystalline silicon material layer;
and etching the polysilicon material layer in the second groove until the protective layer is exposed to form a floating gate layer, wherein a tip structure is formed at the top corner of the floating gate layer.
Further, referring to fig. 1 to 10, fig. 1 to 10 are schematic views of a semiconductor structure in steps of a manufacturing method of a split-gate flash memory according to an embodiment of the present invention.
First, referring to fig. 1, a semiconductor substrate 100 is provided, and a passivation layer 110, a polysilicon material layer 120 and a dielectric layer 130 are sequentially formed on the semiconductor substrate 100. The semiconductor substrate 100 may be one of monocrystalline silicon, polycrystalline silicon, and amorphous silicon, the semiconductor substrate 100 may also be gallium arsenide, a silicon gallium compound, and the like, and the semiconductor substrate 100 may also have a silicon-on-insulator or silicon-on-silicon epitaxial layer structure; the semiconductor substrate 100 may also be made of other semiconductor materials, which are not listed here. The semiconductor substrate 100 may have an N well, a P well, or the like. Further, the polysilicon material layer 120 is formed by chemical vapor deposition, and the thickness of the polysilicon material layer 120 is between that of the polysilicon material layer In the meantime. The thickness of the polysilicon material layer deposited in the prior art is generally less thanThe thickness of the polysilicon material layer 120 in the present invention is larger than that of a polysilicon material layer deposited in the prior art, so as to form an arc shape on the surface of the polysilicon material layer for paving, and if the polysilicon material layer 120 is too thin, the polysilicon material layer may be etched through by a subsequent etching process performed on the polysilicon material layer 120, which may cause a storage failure.
Then, referring to fig. 2, the dielectric layer 130 is etched until the polysilicon material layer 120 is exposed, so as to form a first trench 300 in the dielectric layer 130. Before etching the dielectric layer 130, a layer of photoresist is firstly arranged on the dielectric layer 130, a corresponding photoresist pattern is formed on the photoresist by photolithography, the photoresist pattern is a plurality of repeating units, and the photoresist pattern is transferred into the dielectric layer 130 by etching to form a plurality of first trenches 300 at equal intervals in the dielectric layer 130.
Next, referring to fig. 3, the polysilicon material layer 120 is etched in the first trench 300, so that the surface 121 of the polysilicon material layer 120 in the first trench 300 is arc-shaped. Wherein the polysilicon material layer 120 with the arc-shaped surface in the first trench 300 is in a bowl shape with a thinner middle part and thicker two ends, and the maximum thickness of the polysilicon material layer 120 with the arc-shaped surface is between And the minimum thickness is betweenIn the meantime. In this embodiment, an isotropic etching process is used to etch the polysilicon material layer 120 in the first trench 300, and meanwhile, a hydrogen-containing gas is added to participate in the isotropic etching. Compared with the prior art, the invention adds the step of etching the polysilicon material layer 120 in the first trench 300 to enable the surface 121 of the polysilicon material layer 120 in the first trench 300 to be in the shape of an arc, and the step is carried out to prepare for forming a tip structure at the top corner of a floating gate layer when the polysilicon material layer is etched subsequently to form the floating gate layer.
Further, referring to fig. 4, the remaining dielectric layer 130 is removed, and the polysilicon material layer 120 is exposed. The remaining dielectric layer 130 is cleaned by using a solution to completely remove the dielectric layer 130, and the solution in this embodiment is hot phosphoric acid, and the hot phosphoric acid reacts only with the dielectric layer 130 and cannot react with the polysilicon material layer 120, so that the remaining dielectric layer 130 can be effectively removed by using the hot phosphoric acid and the polysilicon material layer 120 is not affected at all.
Then, referring to fig. 5, a functional layer 140 is formed, the functional layer 140 covering the polysilicon material layer 120. The functional layer 140 includes an ONO film 141, a control gate layer 142, and a first silicon nitride layer 143, which are sequentially deposited. The ONO film 141 is formed by sequentially depositing silicon oxide, silicon nitride, and silicon oxide. The control gate layer 142 is made of polysilicon.
Next, referring to fig. 6, the functional layer 140 is etched to form a second trench 310 in the functional layer 140, and the second trench 310 exposes the polysilicon material layer 120. The second trench 310 obtained by etching the functional layer 140 is located on the polysilicon material layer 120 with a planar surface.
Preferably, referring to fig. 7, the polysilicon material layer 120 is etched in the second trench 310 until the protection layer 110 is exposed to form a floating gate layer 123, wherein a tip structure 122 is formed at a top corner of the floating gate layer 123. The angle of the tip end structure 122 is formed between 10 ° and 80 °, that is, the tip end structure 122 is acute-angled. The tip structure 122 enhances the electric field intensity from the floating gate layer 123 to the word line, so that electrons in the floating gate layer 123 easily pass through the tunneling oxide layer from the tip structure to the word line through the tunneling effect under the high-intensity electric field, the tunneling effect is enhanced, and the erasing efficiency is improved.
Further, referring to fig. 8, after forming the tip structure 122, the method further includes: forming a sidewall structure 150, wherein the sidewall structure 150 covers the sidewall of the second trench 310. The sidewall structure 150 includes a first silicon oxide layer 151 and a second silicon nitride layer 152 deposited in sequence, and when the first silicon oxide layer 151 and the second silicon nitride layer 152 are deposited, the sidewall of the second trench 310 is covered, and the bottom wall of the second trench 310 is also covered. In order to finally obtain the structure of the split-gate flash memory, after the first silicon oxide layer 151 and the second silicon nitride layer 152 are deposited on the sidewall and the bottom wall of the second trench 310, an isotropic etching process is performed on the first silicon oxide layer 151 and the second silicon nitride layer 152 on the bottom wall surface of the second trench 310 to remove the first silicon oxide layer 151 and the second silicon nitride layer 152 on the bottom wall surface of the second trench 310.
In this embodiment, referring to fig. 9, after forming the sidewall structure 150, the method further includes: forming a tunnel oxide layer 160, wherein the tunnel oxide layer 160 covers the sidewall structure 150 and the bottom wall of the second trench 310.
Further, referring to fig. 10, after forming the tunnel oxide layer 160, the method further includes: a word line 200 is formed, and the second trench 310 is filled with the word line 200.
In this embodiment, since the tip structure 122 is relatively sharp, the electric field intensity from the floating gate layer to the word line is increased, and the tunneling voltage difference of electrons from the floating gate layer 123 to the word line 200 can be reduced, so that the split-gate flash memory may not need a negative voltage, and the deep N-well in the semiconductor substrate 100 can be selectively removed.
In summary, the present invention provides a method for manufacturing a split gate flash memory, which includes the following steps: providing a semiconductor substrate, wherein a protective layer, a polycrystalline silicon material layer and a dielectric layer are sequentially formed on the semiconductor substrate; etching the dielectric layer to form a first groove; etching the polycrystalline silicon material layer in the first groove to enable the surface of the polycrystalline silicon material layer in the first groove to be in an arc shape; removing the residual dielectric layer; forming a functional layer on the polycrystalline silicon material layer; etching the functional layer to form a second groove in the functional layer, wherein the second groove exposes the polycrystalline silicon material layer; and etching the polysilicon material layer in the second groove until the protective layer is exposed to form a floating gate layer, wherein a tip structure is formed at the top corner of the floating gate layer. The tip structure enables the electric field intensity from the floating gate layer to the word line to be enhanced, so that electrons in the floating gate layer easily penetrate through the tunneling oxide layer from the tip structure to the word line through the tunneling effect under the high-intensity electric field, the tunneling effect is enhanced, and the erasing efficiency is improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A manufacturing method of a split-gate flash memory is characterized by comprising the following steps:
providing a semiconductor substrate, wherein a protective layer, a polycrystalline silicon material layer and a dielectric layer are sequentially formed on the semiconductor substrate;
etching the dielectric layer until the polycrystalline silicon material layer is exposed so as to form a first groove in the dielectric layer;
etching the polycrystalline silicon material layer in the first groove to enable the surface of the polycrystalline silicon material layer in the first groove to be arc-shaped;
removing the residual dielectric layer and exposing the polycrystalline silicon material layer;
forming a functional layer, wherein the functional layer covers the polycrystalline silicon material layer;
etching the functional layer to form a second groove in the functional layer, wherein the second groove exposes the polycrystalline silicon material layer;
and etching the polysilicon material layer in the second groove until the protective layer is exposed to form a floating gate layer, wherein a tip structure is formed at the top corner of the floating gate layer.
2. The method of manufacturing a split-gate flash memory according to claim 1, further comprising, after forming the tip structure:
and forming a side wall structure, wherein the side wall structure covers the side wall of the second groove.
3. The method for manufacturing the split-gate flash memory according to claim 2, further comprising, after forming the sidewall structure:
and forming a tunneling oxide layer which covers the side wall structure and the bottom wall of the second groove.
4. The method for manufacturing the split-gate flash memory according to claim 3, further comprising, after forming the tunnel oxide layer:
and forming a word line, wherein the word line fills the second groove.
5. The method of claim 1, wherein the angle of the tip structure is between 10 ° and 80 °.
6. The method of claim 1, wherein the polysilicon layer has a thickness between two adjacent layersIn thatIn the meantime.
7. The method of claim 1, wherein the polysilicon material layer is etched in the first trench such that the surface of the polysilicon material layer in the first trench is in the shape of an arc, and the maximum thickness of the polysilicon material layer is between the maximum thickness of the polysilicon material layer in the first trench and the maximum thickness of the polysilicon material layer in the first trenchTo (c) to (d); the polysilicon material layer has a minimum thickness betweenIn the meantime.
8. The method of claim 1, wherein the dielectric layer is etched by a dry etching process.
9. The method for manufacturing the split-gate flash memory according to claim 1, wherein the polysilicon material layer is etched in the first trench by an isotropic etching process so that the surface of the polysilicon material layer in the first trench is in an arc shape.
10. The method of claim 9, wherein the polysilicon material layer is etched in the first trench using a hydrogen-containing gas, such that the surface of the polysilicon material layer in the first trench is in the shape of an arc.
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