CN112908857B - Method for manufacturing semiconductor device - Google Patents
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- CN112908857B CN112908857B CN202110258208.3A CN202110258208A CN112908857B CN 112908857 B CN112908857 B CN 112908857B CN 202110258208 A CN202110258208 A CN 202110258208A CN 112908857 B CN112908857 B CN 112908857B
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- 238000000034 method Methods 0.000 title claims abstract description 64
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims description 36
- 150000004767 nitrides Chemical class 0.000 claims abstract description 88
- 238000007667 floating Methods 0.000 claims abstract description 81
- 230000008569 process Effects 0.000 claims abstract description 34
- 238000005530 etching Methods 0.000 claims abstract description 17
- 230000005641 tunneling Effects 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims description 18
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 14
- 230000008878 coupling Effects 0.000 claims description 12
- 238000010168 coupling process Methods 0.000 claims description 12
- 238000005859 coupling reaction Methods 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 abstract description 6
- 238000001312 dry etching Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a preparation method of a semiconductor device, which comprises the following steps: first trenches are formed and then a second nitride layer is formed on sidewalls of the first trenches extending at least from sidewalls of the inter-gate dielectric layer to sidewalls of a portion of the first nitride layer. And removing the floating gate layer exposed from the bottom wall of the first trench to form a second trench in the floating gate layer. And laterally etching the second nitride layer to thin the second nitride layer so that the bottom of the second nitride layer can expose the top corners of part of the floating gate layer. And forming a tunneling dielectric layer which at least covers the exposed surface of the floating gate layer in the second trench. Finally, word lines are formed to fill the first trenches and the second trenches. Therefore, the invention can be realized by only thinning the second nitride layer without separately forming an oxide layer to form the corners of the floating gate. The device erasing performance can be improved by increasing the relative coverage area between the floating gate layer and the word line, the preparation flow is simplified, the process is simple, and the time cost and the economic cost are reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a preparation method of a semiconductor device.
Background
Currently, flash memory has been widely used as the best choice for non-volatile memory applications due to its high density, low cost, electrically programmable, etc. The erase capability of the flash memory is one of the important parameters for determining the quality of the flash memory. In general, in the erasing process, high and low voltages are applied to the word lines and the control gates in the flash memory, so that a higher potential difference and electric field strength are formed between the floating gates and the word lines, electrons stored in the floating gates tunnel through the tunnel oxide layer, and the potential on the floating gates is changed from negative to positive, thereby changing the storage state, i.e. realizing the transition between "0" and "1". Indeed, it is readily understood by those skilled in the art that the relative coverage area of the floating gate layer and the word line has a certain influence on the erase field strength. The larger the relative coverage area, the stronger the electric field strength generated upon erasure.
Therefore, in order to improve the erasing performance of the flash memory, an oxide layer is formed before etching the floating gate layer in the existing preparation process, and then a protective oxide layer side wall is formed by dry etching to cover part of the floating gate layer. And etching the floating gate layer, and removing the formed oxide layer side wall, so that the covered part of the floating gate layer is exposed, and a corner of the floating gate layer is formed. Therefore, the relative coverage area of the corner of the floating gate layer and the word line is far larger than that of the floating gate layer and the word line in a vertical mode, and the electric field strength can be enhanced and the erasing capability can be improved during erasing.
However, with the gradual shrinking of the critical dimensions of semiconductor devices and the increasing performance requirements of semiconductor devices, the improved method of further expanding the relative coverage area of the corners of the floating gate layer and the word lines by increasing the thickness of the oxide layer increases the process difficulty, reduces the yield, and increases the time cost and economic cost.
Therefore, a new method for manufacturing a semiconductor device is needed to increase the relative coverage area of the corner of the floating gate layer and the word line, improve the erasing performance of the flash memory, and reduce the time cost and the economic cost.
Disclosure of Invention
The invention aims to provide a preparation method of a semiconductor device, which aims to solve at least one problem of how to improve the erasure performance of a flash memory, how to reduce the complexity of the process and how to reduce the time cost and the economic cost.
In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, including:
providing a semiconductor substrate, wherein a floating gate layer, an inter-gate dielectric layer, a control gate layer and a first nitride layer are sequentially formed on the substrate;
Forming a first groove, wherein the first groove sequentially penetrates through the first nitride layer, the control gate layer and the inter-gate dielectric layer and exposes the top surface of the floating gate layer;
Forming a second nitride layer, wherein the second nitride layer is positioned on the side wall of the first groove and extends from at least the side wall of the inter-gate dielectric layer to part of the side wall of the first nitride layer;
removing the floating gate layer exposed from the bottom wall of the first trench to form a second trench in the floating gate layer, wherein the first trench and the second trench are communicated;
Laterally etching the second nitride layer to thin the second nitride layer, so that the bottom of the second nitride layer can expose part of the top corner of the floating gate layer;
Forming a tunneling dielectric layer, wherein the tunneling dielectric layer at least covers the exposed surface of the floating gate layer in the second groove;
Word lines are formed that fill the first and second trenches.
Optionally, in the method for manufacturing a semiconductor device, the thickness range of the second nitride layer formed is: 400 angstroms to 600 angstroms.
Optionally, in the method for manufacturing a semiconductor device, a wet etching process is used to laterally etch the second nitride layer; the etching liquid comprises phosphoric acid, and the temperature range of the phosphoric acid is 140-170 ℃.
Optionally, in the method for manufacturing a semiconductor device, after the second nitride layer is laterally etched, a thickness range of the remaining second nitride layer is: 200 angstroms to 400 angstroms.
Optionally, in the method for manufacturing a semiconductor device, after the second trench is formed and before the second nitride layer is laterally etched, the method for manufacturing a semiconductor device further includes: performing a rapid thermal oxidation process on inner walls of the first trench and the second trench; wherein, the process temperature is: 750-950 deg.c and 5-15 seconds.
Optionally, in the method for manufacturing a semiconductor device, before forming the first trench, the method for manufacturing a semiconductor device further includes:
Forming a third groove which penetrates through the first nitride layer and exposes the top surface of the control gate layer;
Forming an oxide layer, wherein the oxide layer covers the inner wall of the third groove and the upper surface of the first nitride layer;
And etching the oxide layer by adopting a dry method to form an oxide layer side wall, wherein the oxide layer side wall covers the side wall of the third groove.
Optionally, in the method for manufacturing a semiconductor device, after the oxide layer side wall is formed, the control gate layer exposed from the bottom wall of the third trench and the inter-gate dielectric layer below the control gate layer are removed to form the first trench.
Optionally, in the method for manufacturing a semiconductor device, the second nitride layer covers a sidewall of the oxide layer sidewall, an exposed sidewall of the control gate layer, and a sidewall of the inter-gate dielectric layer.
Optionally, in the method for manufacturing a semiconductor device, the tunneling dielectric layer is formed by a thermal oxidation process or a floating gate side wall process, and the process temperature for forming the tunneling dielectric layer is 900-1200 ℃.
Optionally, in the method for manufacturing a semiconductor device, the provided semiconductor substrate further includes a coupling oxide layer; the coupling oxide layer is formed between the floating gate layer and the substrate, and the inter-gate dielectric layer is an ONO film layer formed by stacking silicon oxide, silicon nitride and silicon oxide; and the second groove sequentially penetrates through the floating gate layer and the coupling oxide layer.
In summary, the present invention provides a method for manufacturing a semiconductor device, including: a semiconductor substrate is provided, and a floating gate layer, an inter-gate dielectric layer, a control gate layer and a first nitride layer are sequentially formed on the substrate. And forming a first groove, wherein the first groove sequentially penetrates through the first nitride layer, the control gate layer and the inter-gate dielectric layer and exposes the top surface of the floating gate layer. And forming a second nitride layer, wherein the second nitride layer is positioned on the side wall of the first groove and extends from at least the side wall of the inter-gate dielectric layer to part of the side wall of the first nitride layer. And removing the floating gate layer exposed from the bottom wall of the first trench to form a second trench in the floating gate layer, wherein the first trench and the second trench are communicated. And laterally etching the second nitride layer to thin the second nitride layer, so that the bottom of the second nitride layer can expose part of the top corner of the floating gate layer. And forming a tunneling dielectric layer, wherein the tunneling dielectric layer at least covers the exposed surface of the floating gate layer in the second groove. Word lines are formed that fill the first and second trenches. Therefore, the invention can be realized by only thinning the second nitride layer without separately forming an oxide layer to form the corners of the floating gate. The device erasing performance can be improved by increasing the relative coverage area between the floating gate layer and the word line, the preparation flow is simplified, the process is simple, and the time cost and the economic cost are reduced.
Drawings
Fig. 1 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
FIGS. 2-10 are schematic views of semiconductor structures at various steps of embodiments of the present invention;
Wherein, the reference numerals are as follows:
100-a substrate; 101-a coupling oxide layer; 102-a floating gate layer; 103-an inter-gate dielectric layer; 104-a control gate layer; 105-a first nitride layer; 106-oxide layer side walls; 107-a second nitride layer; 108-tunneling oxide layer; 109-word line; p1-a first trench; p2-a second trench; p3-a third trench; corner of M-floating gate layer; corner of N-tunnel oxide.
Detailed Description
The invention will be described in further detail with reference to the drawings and the specific embodiments thereof in order to make the objects, advantages and features of the invention more apparent. It should be noted that the drawings are in a very simplified form and are not drawn to scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments. It should be further understood that the terms "first," "second," "third," and the like in this specification are used merely for distinguishing between various components, elements, steps, etc. in the specification and not for indicating a logical or sequential relationship between the various components, elements, steps, etc., unless otherwise indicated.
To solve the above technical problem, this embodiment provides a method for manufacturing a semiconductor device, referring to fig. 1, the method for manufacturing a semiconductor device includes:
step one S10: a semiconductor substrate is provided, and a floating gate layer, an inter-gate dielectric layer, a control gate layer and a first nitride layer are sequentially formed on the substrate.
Step two S20: and forming a first groove, wherein the first groove sequentially penetrates through the first nitride layer, the control gate layer and the inter-gate dielectric layer and exposes the top surface of the floating gate layer.
Step three S30: and forming a second nitride layer, wherein the second nitride layer is positioned on the side wall of the first groove and extends from at least the side wall of the inter-gate dielectric layer to part of the side wall of the first nitride layer.
Step four, S40: and removing the floating gate layer exposed from the bottom wall of the first trench to form a second trench in the floating gate layer, wherein the first trench and the second trench are communicated.
Step five S50: and laterally etching the second nitride layer to thin the second nitride layer, so that the bottom of the second nitride layer can expose part of the top corner of the floating gate layer.
Step six S60: and forming a tunneling dielectric layer, wherein the tunneling dielectric layer at least covers the exposed surface of the floating gate layer in the second groove.
Step seven S70: word lines are formed that fill the first and second trenches.
The method for manufacturing the semiconductor device is described in detail below with reference to fig. 2 to 10.
Step one S10: referring to fig. 2-4, a semiconductor substrate 100 is provided, and a floating gate layer 102, an inter-gate dielectric layer 103, a control gate layer 104 and a first nitride layer 105 are sequentially formed on the substrate 100.
Referring to fig. 2, the semiconductor structure further includes: a coupling oxide layer 101, the coupling oxide layer 101 being formed between the floating gate layer 102 and the substrate 100. The inter-gate dielectric layer 103 is an ONO film layer formed by stacking silicon oxide, silicon nitride and silicon oxide. That is, the coupling oxide layer 101, the floating gate layer 102, the inter-gate dielectric layer 103, the control gate layer 104, and the first nitride layer 105 are sequentially formed on the substrate 100.
Referring to fig. 3-4, the first nitride layer 105 is etched by a dry etching process or a wet etching process to form a third trench P3, wherein the third trench P3 penetrates the first nitride layer 105. After forming the third trench P3, an oxide layer (not shown) is formed, which covers the inner wall of the third trench P3 and the upper surface of the first nitride layer 105. Then, the oxide layer is etched by adopting a dry method to form an oxide layer side wall 106, and the oxide layer side wall 106 covers the side wall of the third groove P3.
An oxide sidewall 106 is formed, and the oxide sidewall 106 covers the sidewall of the third trench P3. The material of the first nitride layer 105 includes silicon nitride, and the material of the oxide sidewall 106 includes silicon oxide.
Step two S20: referring to fig. 5, a first trench P1 is formed, and the first trench P1 sequentially penetrates through the first nitride layer 105, the control gate layer 104 and the inter-gate dielectric layer 103, and exposes the top surface of the floating gate layer 102.
The first trench P1 may be etched using a wet etching process or a dry etching process. After the oxide sidewall 106 is formed, the control gate layer 104 exposed from the bottom wall of the third trench P3 is removed, and then the inter-gate dielectric layer 103 is further etched by extension, and a portion of the floating gate layer 102 is exposed, so as to form the first trench P1. That is, the first trench P1 is formed by extension etching of the third trench P3.
Step three S30: referring to fig. 6, a second nitride layer 107 is formed, and the second nitride layer 107 is located on the sidewall of the first trench P1 and extends from at least the sidewall of the inter-gate dielectric layer 103 to a portion of the sidewall of the first nitride layer 105. That is, the second nitride layer 107 covers the sidewalls of the oxide sidewall 106, the exposed sidewalls of the control gate layer 104, and the sidewalls of the inter-gate dielectric layer 103.
Wherein, the thickness range of the second nitride layer 107 is: 400 angstroms to 600 angstroms. Alternatively 400 angstroms, 500 angstroms or 600 angstroms. The thickness of the second nitride layer 107 is thicker than the normal isolation thickness required by the semiconductor device in this embodiment, so that the corners of the floating gate layer 102 are exposed by thinning the second nitride layer 107, so that the relative coverage area between the floating gate layer 102 and the word line 109 (which is formed later as shown in fig. 10) is increased, and the electric field strength during erasing is further enhanced, so as to improve the erasing performance of the device. Compared with the prior art, the method saves the process links of growing the oxide layer, etching to form the oxide layer protection side wall and then removing the oxide layer protection side wall, and reduces the economic cost. And the time taken to grow the oxide layer using the furnace tube process far exceeds the time taken to form the thickened second nitride layer 107 in this example, thereby saving the time cost for device fabrication.
Step four, S40: referring to fig. 7, the floating gate layer 102 exposed from the bottom wall of the first trench P1 is removed to form a second trench P2 in the floating gate layer 102, where the first trench P1 and the second trench P2 are penetrated.
The second nitride layer 107 covers the sidewall of the first trench P1 in a sidewall manner, so that a bottom wall of the first trench P1 exposes a portion of the floating gate layer 102, and then the floating gate layer 102 and the coupling oxide layer 101 are sequentially etched by wet etching or dry etching. To form the second trenches P2. The second trench P2 penetrates the floating gate layer 102 and the coupling oxide layer 101 and exposes a portion of the substrate 100.
Step five S50: referring to fig. 8, the second nitride layer 107 is laterally etched to thin the second nitride layer 107, so that a portion of the top corner M of the floating gate layer 102 can be exposed at the bottom of the second nitride layer 107.
After the second trench P2 is formed and before the second nitride layer 107 is laterally etched, the method for manufacturing a semiconductor device according to this embodiment further includes: a rapid thermal oxidation process is performed on the inner walls of the first and second trenches P1 and P2 to form a thin oxide layer (not shown). The oxide layer covers the exposed top surface of the floating gate layer 102, so as to protect the appearance of the top surface of the floating gate layer 102, and avoid that the etching solution hot phosphoric acid affects the top surface of the floating gate layer 102 to a certain extent when the second nitride layer 107 is subsequently etched laterally. Thus, performing the rapid thermal oxidation process can form a preferred corner M topography (as shown in fig. 8). Further, the rapid thermal oxidation process temperature is: 750-950 deg.c and 5-15 seconds.
Further, a wet etching process is used to perform selective lateral etching on the second nitride layer 107. And the etching solution includes phosphoric acid, and the temperature of the phosphoric acid ranges from 140 degrees celsius to 170 degrees celsius, the etching speed of the second nitride layer 107 is about 50 angstroms per minute. Further, after removing a part of the thickness of the second nitride layer 107, the thickness range of the remaining second nitride layer 107 is: 200 a-400 a, optionally 200 a, 300 a or 400 a, to satisfy the function of isolating the word line from other layers. Within this range, the exposed area of the corner M of the floating gate layer 102 can be controlled by reserving more or less thickness of the second nitride layer 107, thereby satisfying various requirements of the device on the erasing performance. When the exposed area of the corner M of the floating gate layer 102 is large, that is, the remaining second nitride layer 107 is thin, the erasure performance is strong; when the exposed area of the corner M of the floating gate layer 102 is small, that is, the remaining second nitride layer 107 is thick, the erasing performance is weak.
Therefore, in this example, the corner M of the floating gate layer 102 may be exposed only by reducing the thickness of the second nitride layer 107, so as to enhance the erasing capability of the device, so that the process complexity is low, the product yield can be ensured, and the time cost and the economic cost are reduced.
Step six S60: referring to fig. 9, a tunneling dielectric layer 108 is formed, and the tunneling dielectric layer 108 covers at least the exposed surface of the floating gate layer 102 in the second trench P2.
The tunneling dielectric layer 108 is used to space the floating gate layer 102 and the word line (as shown in fig. 10). The tunnel oxide layer 108 is formed by a thermal oxidation process or a floating gate side wall process, and the process temperature for forming the tunnel dielectric layer 108 is 900-1200 ℃. The tunnel oxide layer 108 covers sidewalls of the first trench P1 and the second trench P2, and a bottom wall of the second trench P2. And a corner N of the tunnel oxide layer 108 is formed at a corner M of the floating gate layer 102. That is, the tunnel oxide layer 108 forms a corner N along the contour of the corner M of the floating gate layer 102 to ensure the relative coverage area of the floating gate layer 102 and the word line 109 required for a device.
Step seven S70: referring to fig. 10, a word line 109 is formed, and the word line 109 fills the first trench P1 and the second trench P2.
After forming the tunnel oxide layer 108, the word line 109 is formed on the tunnel oxide layer 108, and the word line 109 covers the corner N of the tunnel oxide layer 108. The material of the word line 109 includes polysilicon, and the formed word line 109 also covers the top surface of the first nitride layer 105, and the top surface of the word line 109 is level with the top surface of the first nitride layer 105 through a chemical mechanical polishing process. Further, a thermal oxidation process is subsequently used to form an oxide layer on the top surface of the word line 109 to protect the word line 109. The subsequent manufacturing process is a process step well known to those skilled in the art, and will not be described in detail herein.
In summary, in the method for manufacturing a semiconductor device according to the present embodiment, a sacrificial oxide sidewall is not required to be formed separately to form the corner of the floating gate 102, and the method can be implemented only by thinning the second nitride layer 107. Not only can the erasure performance of the device be improved by increasing the relative coverage area between the floating gate layer 102 and the word line 109, but also the manufacturing process is simplified, the process is simple, and the time cost and the economic cost are reduced.
It should also be appreciated that while the present invention has been disclosed in the context of a preferred embodiment, the above embodiments are not intended to limit the invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
Claims (10)
1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, wherein a floating gate layer, an inter-gate dielectric layer, a control gate layer and a first nitride layer are sequentially formed on the substrate;
Forming a first groove, wherein the first groove sequentially penetrates through the first nitride layer, the control gate layer and the inter-gate dielectric layer and exposes the top surface of the floating gate layer;
Forming a second nitride layer, wherein the second nitride layer is positioned on the side wall of the first groove and extends from at least the side wall of the inter-gate dielectric layer to part of the side wall of the first nitride layer;
removing the floating gate layer exposed from the bottom wall of the first trench to form a second trench in the floating gate layer, wherein the first trench and the second trench are communicated;
Performing a rapid thermal oxidation process on inner walls of the first trench and the second trench;
Laterally etching the second nitride layer to thin the second nitride layer, so that the bottom of the second nitride layer can expose part of the top corner of the floating gate layer;
Forming a tunneling dielectric layer, wherein the tunneling dielectric layer at least covers the exposed surface of the floating gate layer in the second groove;
Word lines are formed that fill the first and second trenches.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the second nitride layer is formed in a thickness range of: 400 angstroms to 600 angstroms.
3. The method of manufacturing a semiconductor device according to claim 1, wherein the second nitride layer is laterally etched by a wet etching process; the etching liquid comprises phosphoric acid, and the temperature range of the phosphoric acid is 140-170 ℃.
4. The method of manufacturing a semiconductor device according to claim 1, wherein after the second nitride layer is laterally etched, a thickness range of the remaining second nitride layer is: 200 angstroms to 400 angstroms.
5. The method of manufacturing a semiconductor device according to claim 1, wherein a process temperature in the rapid thermal oxidation process is: 750-950 deg.c and 5-15 seconds.
6. The method of manufacturing a semiconductor device according to claim 1, wherein before forming the first trench, the method further comprises:
Forming a third groove which penetrates through the first nitride layer and exposes the top surface of the control gate layer;
Forming an oxide layer, wherein the oxide layer covers the inner wall of the third groove and the upper surface of the first nitride layer;
And etching the oxide layer by adopting a dry method to form an oxide layer side wall, wherein the oxide layer side wall covers the side wall of the third groove.
7. The method of manufacturing a semiconductor device according to claim 6, wherein after the oxide sidewall is formed, the control gate layer exposed from the bottom wall of the third trench and the inter-gate dielectric layer under the control gate layer are removed to form the first trench.
8. The method of manufacturing a semiconductor device according to claim 6, wherein the second nitride layer covers sidewalls of the oxide layer sidewall, exposed sidewalls of the control gate layer, and exposed sidewalls of the inter-gate dielectric layer.
9. The method for manufacturing a semiconductor device according to claim 1, wherein the tunneling dielectric layer is formed through a thermal oxidation process or a floating gate side wall process, and the process temperature for forming the tunneling dielectric layer is 900-1200 ℃.
10. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate provided further comprises a coupling oxide layer; the coupling oxide layer is formed between the floating gate layer and the substrate, and the inter-gate dielectric layer is an ONO film layer formed by stacking silicon oxide, silicon nitride and silicon oxide; and the second groove sequentially penetrates through the floating gate layer and the coupling oxide layer.
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| CN110085592B (en) * | 2019-04-30 | 2021-10-08 | 上海华虹宏力半导体制造有限公司 | Flash memory manufacturing method |
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| CN109950247A (en) * | 2019-03-29 | 2019-06-28 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of Split-gate flash memory |
| CN111524810A (en) * | 2020-04-30 | 2020-08-11 | 华虹半导体(无锡)有限公司 | Flash memory device and method of manufacturing the same |
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