CN110085592B - Flash memory manufacturing method - Google Patents
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- CN110085592B CN110085592B CN201910363185.5A CN201910363185A CN110085592B CN 110085592 B CN110085592 B CN 110085592B CN 201910363185 A CN201910363185 A CN 201910363185A CN 110085592 B CN110085592 B CN 110085592B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 238000007667 floating Methods 0.000 claims abstract description 120
- 238000005530 etching Methods 0.000 claims abstract description 35
- 238000010168 coupling process Methods 0.000 claims abstract description 18
- 238000005859 coupling reaction Methods 0.000 claims abstract description 18
- 230000008878 coupling Effects 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a flash memory manufacturing method, which comprises the following steps: providing a substrate; sequentially forming a coupling oxide layer, a floating gate layer and a floating gate mask layer on a substrate; etching the floating gate mask layer to form a first opening; isotropically etching the floating gate layer in the first opening to form a groove and first side walls on two sides of the groove, wherein a floating gate tip is formed on the first side wall; depositing an oxide to cover the floating gate mask layer and the floating gate layer, and etching the oxide to form a second opening and second side walls positioned at two sides of the second opening; forming an ONO layer covering the floating gate layer and the floating gate mask layer in the second side wall and the second opening in sequence; sequentially etching the first dielectric layer, the control gate layer and the ONO layer to form a fourth opening; depositing a second dielectric layer to fill the fourth opening; and forming word line grids on two sides of the second medium layer. In the manufacturing method of the flash memory provided by the invention, the formed floating gate layer is provided with a floating gate tip, and the floating gate tip can enhance a local electric field and improve the erasing efficiency when carrying out electronic erasing operation.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a flash memory manufacturing method.
Background
Flash Memory (Flash Memory for short) is a long-life nonvolatile semiconductor Memory (capable of maintaining stored data information under power-off condition), and is widely applied to Flash Memory type digital storage products of various portable mobile devices such as Flash disks, Flash Memory cards, notebook computers, digital cameras and mobile phones.
The grid structure is a core structure of the flash memory, the grid structure is formed on a substrate and comprises a floating grid and a word line grid, and the floating grid of the split-grid flash memory formed by adopting the conventional common technology has no tip. When the electron erasing operation is carried out, the word line grid is added with high voltage to draw away electrons in the floating gate, and if a tip can be formed on the floating gate close to the word line grid, the local electric field is enhanced, and the erasing efficiency is greatly improved.
Disclosure of Invention
The invention aims to provide a flash memory manufacturing method, which enables a floating gate of a flash memory to form a tip, enhances a local electric field and improves the erasing efficiency.
In order to achieve the above object, a flash memory manufacturing method includes:
providing a substrate;
forming a coupling oxide layer, a floating gate layer and a floating gate mask layer on the substrate in sequence;
etching the floating gate mask layer to form a first opening and side walls positioned at two sides of the first opening;
isotropically etching the floating gate layer in the first opening to form a groove and first side walls on two sides of the groove, wherein a floating gate tip is formed on the first side walls;
depositing an oxide to cover the rest floating gate mask layer and the rest floating gate layer, and etching the oxide to form a second opening and second side walls positioned at two sides of the second opening, wherein the second side walls cover the rest floating gate mask layer;
sequentially forming an ONO layer covering the second side wall, the floating gate layer in the second opening and the floating gate mask layer, forming a control gate layer covering the ONO layer, and forming a first dielectric layer covering the control gate layer;
sequentially etching the floating gate mask layer and the first dielectric layer, the control gate layer and the ONO layer on the second side wall to expose the surfaces of the floating gate mask layer and the second side wall, forming a fourth opening between the second side wall, wherein the first dielectric layer, the control gate layer and the ONO layer after etching are also arranged in the fourth opening;
depositing a second dielectric layer to fill the fourth opening;
and forming word line grids on two sides of the second dielectric layer.
Optionally, in the flash memory manufacturing method, the material of the coupling oxide layer is silicon dioxide.
Optionally, in the flash memory manufacturing method, the material of the floating gate layer is polysilicon.
Optionally, in the flash memory manufacturing method, the method for forming word line grids on two sides of the second dielectric layer includes:
etching the floating gate mask layer and the floating gate layer on two sides of the dielectric layer to form a fifth opening;
and depositing polycrystalline silicon into the fifth opening, and grinding the polycrystalline silicon to enable the surface of the polycrystalline silicon to be flat to form the word line grid.
Optionally, in the flash memory manufacturing method, after the floating gate mask layer and the floating gate layer on both sides of the dielectric layer are etched to form a fifth opening, a dielectric film is formed to cover the surface of the second dielectric layer, the side of the second sidewall facing the fifth opening, and the side of the floating gate layer facing the fifth opening.
Optionally, in the flash memory manufacturing method, the thickness of the coupling oxide layer is 80 to 90 angstroms.
Optionally, in the flash memory manufacturing method, the thickness of the floating gate layer is 430 angstroms to 470 angstroms.
Optionally, in the flash memory manufacturing method, the thickness of the floating gate mask layer is 3100 angstroms to 3400 angstroms.
Optionally, in the flash memory manufacturing method, the first dielectric layer and the second dielectric layer are made of ethyl silicate layers.
Optionally, in the flash memory manufacturing method, the second dielectric layer and the control gate layer, the ONO layer, the floating gate layer and the coupling oxide layer under the second dielectric layer are etched to expose the surface of the substrate, and a plurality of independent flash memory structures are formed after etching.
In the manufacturing method of the flash memory provided by the invention, the formed floating gate layer is provided with a floating gate tip, and the floating gate tip can enhance a local electric field and improve the erasing efficiency when carrying out electronic erasing operation.
Drawings
FIG. 1 is a flow chart of a method for manufacturing a flash memory according to an embodiment of the present invention;
FIGS. 2 to 11 are schematic cross-sectional views illustrating a method for manufacturing a flash memory according to an embodiment of the invention;
wherein: 110-substrate, 120-coupling oxide layer, 130-floating gate layer, 140-floating gate mask layer, 151-first opening, 152-trench, 153-second opening, 154-third opening, 155-fourth opening, 156-fifth opening, 161-first side wall, 162-second side wall, 163-third side wall, 170-ONO layer, 180-control gate layer, 190-first dielectric layer, 200-second dielectric layer, 210-dielectric film, 220-word line grid, 230-floating gate tip.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. Advantages and features of the present invention will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 1, the present invention provides a method for manufacturing a flash memory, including:
s11: providing a substrate;
s12: forming a coupling oxide layer, a floating gate layer and a floating gate mask layer on the substrate in sequence;
s13: etching the floating gate mask layer to form a first opening and side walls positioned at two sides of the first opening;
s14: isotropically etching the floating gate layer in the first opening to form a groove and first side walls on two sides of the groove, wherein a floating gate tip is formed on the first side walls;
s15: depositing an oxide to cover the rest floating gate mask layer and the rest floating gate layer, and etching the oxide to form a second opening and second side walls positioned at two sides of the second opening, wherein the second side walls cover the rest floating gate mask layer;
s16: sequentially forming an ONO layer covering the second side wall, the floating gate layer in the second opening and the floating gate mask layer, forming a control gate layer covering the ONO layer, and forming a first dielectric layer covering the control gate layer;
s17: sequentially etching the floating gate mask layer and the first dielectric layer, the control gate layer and the ONO layer on the second side wall to expose the surfaces of the floating gate mask layer and the second side wall, forming a fourth opening between the second side wall, wherein the first dielectric layer, the control gate layer and the ONO layer after etching are also arranged in the fourth opening;
s18: depositing a second dielectric layer to fill the fourth opening;
s19: and forming word line grids on two sides of the second dielectric layer.
First, referring to fig. 2, a substrate 110 is provided, where the substrate 110 may be a silicon substrate, a coupling oxide layer 120 is formed on the substrate 110, the coupling oxide layer 120 may have a thickness of 90 angstroms, a floating gate layer 130 is formed on the coupling oxide layer 120, the floating gate layer 130 may have a thickness of 450 angstroms, the coupling oxide layer 120 may be silicon dioxide, the floating gate layer 130 may be polysilicon, a floating gate mask layer 140 is formed on the floating gate layer 130, the floating gate mask layer 140 may be silicon nitride, and the floating gate mask layer 140 may have a thickness of 3300 angstroms.
Referring to fig. 3, the floating gate mask layer 140 is etched to form a first opening 151, and the surface of the floating gate layer 130 is exposed in the first opening 151.
Referring to fig. 4, the floating gate mask layer 140 in the first opening 151 is partially etched to form the trench 152 and first sidewalls 161 at both sides of the trench 152, and since an isotropic etch is used, the first sidewalls 161 have a slope shape, and the floating gate layer 130 under the remaining floating gate mask layer 140 is also slightly etched.
Referring to fig. 4 and 5, an oxide is deposited into the trench 152 and the first opening 151, the trench 152 and the first opening 151 are filled with the oxide, the oxide in the trench 152 and the first opening 151 is etched to expose the surface of the floating gate layer 130, a second opening 153 and second sidewalls 162 at both sides of the second opening 153 are formed, the second sidewalls 162 cover the sidewalls of the floating gate mask layer 140, and one end of the second sidewalls 162 is connected to the floating gate mask layer 140 and the other end is connected to the bottom of the trench 152. In other embodiments of the present application, the deposition into the trench 152 and the first opening 151 may be a combination of oxide and silicon nitride, i.e., a layer of oxide is deposited followed by a layer of silicon nitride.
Referring to fig. 5 and 6, an ONO layer 170 is formed covering the second sidewall 162, the floating gate layer 130 within the second opening 153, and the floating gate mask layer 140, the ONO layer 170 being an oxide-nitride-oxide layer.
With continued reference to fig. 6, a control gate layer 180 is formed overlying the ONO layer 170 and a first dielectric layer 190 is formed overlying the control gate layer 180. The covered first dielectric layer 190 may form the third opening 154 and a third sidewall 163 at both sides of the third opening 154. The thickness of the first dielectric layer 190 in the third opening 154 is greater than the thickness of the first dielectric layer 190 on the floating gate mask layer 140.
Referring to fig. 6 and 7, the first dielectric layer 190 on the floating gate mask layer 140 is removed by etching to expose the surface of the control gate layer 180 on the floating gate mask layer 140, in this step, the first dielectric layer 190 on the third sidewall 163 is removed by etching and the first dielectric layer 190 in the third opening 154 is partially etched, and the remaining first dielectric layer 190 may be used as an etching barrier layer in the subsequent steps. In other embodiments of the present invention, if the third opening 154 is larger, the first dielectric layer 190 may be deposited to fill the third opening 154, and the first dielectric layer 190 may cover the surface of the control gate layer 180, such that the first dielectric layer 190 on the surface of the control gate layer 180 is polished to expose the control gate layer 180 on the floating gate mask layer 140, and then the first dielectric layer 190 in the third opening 154 is partially etched, and a portion of the first dielectric layer 190 is left as an etching stop layer.
With continued reference to fig. 6 and 7, the control gate layer 180 on the floating gate mask layer 140 is removed by etching, and in this step, the control gate layer 180 on the second sidewall 162 and the ONO layer 170 are removed by etching, respectively.
Referring to fig. 8, after the control gate 180 and the first dielectric layer 190 are etched, the second sidewalls 162 are exposed, fourth openings 155 are formed between the second sidewalls 162, a second dielectric layer 200 is deposited, the fourth openings 155 are filled, and the surface of the second dielectric layer 200 is ground to be flat; the floating gate mask layer 140 is removed by etching, the floating gate layer 130 on both sides of the second dielectric layer 200 is etched to expose the surface of the coupling oxide layer 120, the first sidewall 161, i.e., the floating gate layer 130 under the first sidewall 161, is remained, and the first sidewall 161 has a tip, i.e., the floating gate tip 230 in the subsequent step. The formation of the floating gate tip 230 can enhance the local electric field and the erase efficiency thereof can be greatly improved. The fifth opening 156 is formed on both sides of the etched second dielectric layer 200 (outside the second sidewall 162).
Referring to fig. 9, an oxide is deposited to form a dielectric film 210, wherein the dielectric film 210 covers the surface of the second dielectric layer 200, the side of the second sidewall 162 facing the fifth opening 156, and the side of the floating gate layer 130 facing the fifth opening 156.
Referring to fig. 10, polysilicon is deposited into the fifth opening 156, and the polysilicon surface is ground flat to form a word line gate 220.
Referring to fig. 11, the second dielectric layer 200 and the control gate layer 180, the ONO layer 170, the floating gate layer 130 and the coupling oxide layer 120 under the second dielectric layer 200 are etched to expose the surface of the substrate 110, and a plurality of independent split-gate symmetric flash memory structures are formed after etching, wherein the floating gate layer 130 of each independent flash memory structure is a floating gate, and the control gate layer 180 is a control gate.
In this embodiment, the first dielectric layer 190 and the second dielectric layer 200 are made of ethyl silicate, the floating gate layer 130 and the control gate layer 180 are made of polysilicon, and the tip 230 of the floating gate on the floating gate is close to the word line gate 220.
In summary, in the method for manufacturing a flash memory according to the embodiment of the present invention, the floating gate is formed to have a floating gate tip near the word line gate, when an electron erasing operation is performed, a high voltage is applied to the word line gate to extract electrons in the floating gate, and the formed floating gate tip can enhance a local electric field and improve erasing efficiency.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method of manufacturing a flash memory, comprising:
providing a substrate;
forming a coupling oxide layer, a floating gate layer and a floating gate mask layer on the substrate in sequence;
etching the floating gate mask layer to form a first opening and side walls positioned at two sides of the first opening;
isotropically etching the floating gate layer in the first opening to form a groove and first side walls on two sides of the groove, wherein the first side walls are in a slope shape, and floating gate tips are formed on the first side walls;
depositing an oxide to cover the rest floating gate mask layer and the rest floating gate layer, and etching the oxide to form a second opening and second side walls positioned at two sides of the second opening, wherein the second side walls cover the rest floating gate mask layer;
sequentially forming an ONO layer covering the second side wall, the floating gate layer in the second opening and the floating gate mask layer, forming a control gate layer covering the ONO layer, forming a first medium layer covering the control gate layer, wherein the covered first medium layer can form a third opening and a third side wall at two sides of the third opening, and the thickness of the first medium layer in the third opening is larger than that of the first medium layer on the floating gate mask layer;
sequentially etching the floating gate mask layer and the first dielectric layer, the control gate layer and the ONO layer on the second side wall to expose the surfaces of the floating gate mask layer and the second side wall, forming a fourth opening between the second side wall, wherein the first dielectric layer, the control gate layer and the ONO layer after etching are also arranged in the fourth opening;
depositing a second medium layer to fill the fourth opening, etching to remove the floating gate mask layer and etching the floating gate layers on the two sides of the second medium layer to expose the surface of the coupling oxide layer, and reserving the first side wall and the floating gate layer below the first side wall, wherein the first side wall is provided with a floating gate tip;
and forming word line grids on two sides of the second dielectric layer.
2. The method of claim 1, wherein the coupling oxide layer is formed of silicon dioxide.
3. The method of claim 1, wherein the material of the floating gate layer is polysilicon.
4. The method of claim 1, wherein forming word line gates on both sides of the second dielectric layer comprises:
etching the floating gate mask layer and the floating gate layer on two sides of the dielectric layer to form a fifth opening;
and depositing polycrystalline silicon into the fifth opening, and grinding the polycrystalline silicon to enable the surface of the polycrystalline silicon to be flat to form the word line grid.
5. The method of claim 4, wherein after the fifth opening is formed by etching the floating gate mask layer and the floating gate layer on both sides of the dielectric layer, a dielectric film is formed to cover the surface of the second dielectric layer, the side of the second sidewall facing the fifth opening, and the side of the floating gate layer facing the fifth opening.
6. The method of claim 1 wherein the coupling oxide layer has a thickness of 80-90 angstroms.
7. The method of claim 1, wherein the floating gate layer has a thickness of 430 a to 470 a.
8. The method of claim 1, wherein the floating gate mask layer has a thickness of 3100 angstroms to 3400 angstroms.
9. The method of claim 1, wherein the first dielectric layer and the second dielectric layer are made of ethyl silicate.
10. The method of claim 1, further comprising etching the second dielectric layer and the control gate layer, the ONO layer, the floating gate layer, and the coupling oxide layer beneath the second dielectric layer to expose the surface of the substrate, and forming a plurality of independent flash memory structures after etching.
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| CN201910363185.5A CN110085592B (en) | 2019-04-30 | 2019-04-30 | Flash memory manufacturing method |
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| CN201910363185.5A CN110085592B (en) | 2019-04-30 | 2019-04-30 | Flash memory manufacturing method |
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| CN110085592B true CN110085592B (en) | 2021-10-08 |
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| CN112234096B (en) * | 2020-10-27 | 2024-05-28 | 上海华虹宏力半导体制造有限公司 | Split gate flash memory and preparation method thereof |
| CN112750790B (en) * | 2021-01-22 | 2023-11-21 | 上海华虹宏力半导体制造有限公司 | Flash memory and method for manufacturing the same |
| CN112908857B (en) * | 2021-03-09 | 2024-06-18 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
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| CN102368479B (en) * | 2011-11-24 | 2015-01-21 | 上海华虹宏力半导体制造有限公司 | Flash memory and manufacturing method thereof |
| CN104465524B (en) * | 2014-12-30 | 2018-04-27 | 上海华虹宏力半导体制造有限公司 | Mirror image Split-gate flash memory and forming method thereof |
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