CN113903789B - Flash memory, manufacturing method and operating method thereof - Google Patents
Flash memory, manufacturing method and operating method thereof Download PDFInfo
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- CN113903789B CN113903789B CN202111150389.4A CN202111150389A CN113903789B CN 113903789 B CN113903789 B CN 113903789B CN 202111150389 A CN202111150389 A CN 202111150389A CN 113903789 B CN113903789 B CN 113903789B
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- 238000011017 operating method Methods 0.000 title abstract description 6
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- 238000000034 method Methods 0.000 claims abstract description 60
- 239000000463 material Substances 0.000 claims description 76
- 239000000758 substrate Substances 0.000 claims description 41
- 239000004065 semiconductor Substances 0.000 claims description 40
- 238000002955 isolation Methods 0.000 claims description 34
- 238000005468 ion implantation Methods 0.000 claims description 8
- 230000008878 coupling Effects 0.000 abstract description 15
- 238000010168 coupling process Methods 0.000 abstract description 15
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- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
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Abstract
The invention provides a flash memory, a manufacturing method and an operating method thereof, wherein in the flash memory, a word line is isolated from a first grid structure and a second grid structure by only adopting a first side wall layer, so that the size of the flash memory can be reduced, the coupling efficiency between a first floating gate layer and a first control grid layer and the coupling efficiency between a second floating gate layer and a second control grid layer are improved, and the programming efficiency is improved. In addition, in the operation method of the flash memory, electrons in the first floating gate layer can be tunneled into the well region by applying a first voltage to a first control gate, applying a second voltage to a well region and applying a zero voltage to a second control gate or making the second control gate layer empty, so that the electrons in the first floating gate layer are erased, namely, an erase operation is performed through FN tunneling effect between the first floating gate layer and the well.
Description
Technical Field
The present invention relates to the field of integrated circuit manufacturing technologies, and in particular, to a flash memory, and a manufacturing method and an operating method thereof.
Background
Flash memory (flash memory) is a nonvolatile memory that has a characteristic of being able to be stored for a long period of time without losing stored data even if power is turned off. In recent years, development of flash memory has been rapid, and flash memory having high integration, high storage speed and high reliability has been widely used in electronic products and devices including computers, mobile phones, servers, and the like. In improving and optimizing the performance of a flash memory, first, the structure or operation principle of each flash memory cell constituting the flash memory is aimed at. In the prior art, programming operation of a flash memory cell is mostly performed by using channel or conventional source-side hot electron injection, but the flash memory is limited by physical dimensions under the condition that feature sizes are continuously reduced, and the flash memory is faced with the problems of how to improve programming efficiency and the like on the basis of reducing the dimensions of devices.
Disclosure of Invention
The invention aims to provide a flash memory, a manufacturing method and an operating method thereof, so as to improve the programming efficiency of the flash memory.
In order to achieve the above object, the present invention provides a method for manufacturing a flash memory, comprising:
providing a semiconductor substrate, wherein a well region is formed in the semiconductor substrate;
Forming a first grid structure and a second grid structure which are spaced on the well region, wherein the first grid structure comprises a first floating gate layer and a first control grid layer which are sequentially stacked from bottom to top, and the second grid structure comprises a second floating gate layer and a second control grid layer which are sequentially stacked from bottom to top;
Forming a first side wall layer, wherein the first side wall layer covers two side walls of the first grid structure and two side walls of the second grid structure;
Forming a word line oxide layer, wherein the word line oxide layer covers the well region between the first gate structure and the second gate structure;
forming a word line, wherein the word line is formed between the first gate structure and the second gate structure, and covers the word line oxide layer and a first side wall layer between the first gate structure and the second gate structure; and
First bit lines and second bit lines are formed, the first bit lines being formed in the well region on a side of the first gate structure remote from the word lines, the second bit lines being formed in the well region on a side of the second gate structure remote from the word lines.
Optionally, in the method for manufacturing a flash memory, the first gate structure further includes a first floating gate oxide layer and a first inter-gate dielectric layer, the first floating gate oxide layer is formed between the first floating gate layer and the semiconductor substrate, and the first inter-gate dielectric layer is formed between the first floating gate layer and the first control gate layer; the second gate structure further comprises a second floating gate oxide layer and a second inter-gate dielectric layer, wherein the second floating gate oxide layer is formed between the second floating gate layer and the semiconductor substrate, and the second inter-gate dielectric layer is formed between the second floating gate layer and the second control gate layer.
Optionally, in the method for manufacturing a flash memory, the method for forming the first gate structure and the second gate structure includes:
Forming a floating gate oxide material layer and a floating gate material layer on the well region in sequence, wherein the floating gate material layer is provided with a first opening;
Forming an inter-gate dielectric layer, a control gate material layer and a hard mask layer in sequence, wherein the inter-gate dielectric layer covers the bottom wall and the side wall of the first opening and extends to cover the floating gate material layer, the control gate material layer fills the first opening and covers the inter-gate dielectric layer, and the hard mask layer covers the control gate material layer;
The hard mask layer and the control gate material layer are sequentially etched to form a first control gate layer and a second control gate layer, the floating gate material layer is etched to form a first floating gate layer and a second floating gate layer, the inter-gate dielectric layer is etched to form a first inter-gate dielectric layer and a second inter-gate dielectric layer, and the floating gate oxide material layer is etched to form a first floating gate oxide layer and a second floating gate oxide layer, wherein a second opening is formed between the first control gate layer and the second control gate layer, the second opening is perpendicular to the first opening, and the second opening extends between the first floating gate layer and the second floating gate layer.
Optionally, in the method for manufacturing a flash memory, before forming the floating gate material layer, the method for manufacturing a flash memory further includes: forming at least two shallow trench isolation structures in the semiconductor substrate, wherein the well region surrounds the shallow trench isolation structures, and the top surface of each shallow trench isolation structure is flush with the top surface of the floating gate material layer;
and after the floating gate material layer is formed, the shallow trench isolation structure is further etched to form the first opening, and the top surface of the shallow trench isolation structure is flush with the top surface of the floating gate oxide material layer.
Optionally, in the method for manufacturing a flash memory, the thickness of the first floating gate layer and the thickness of the second floating gate layer are both 400 angstroms to 1000 angstroms.
Optionally, in the method for manufacturing a flash memory, the thickness of the word line oxide layer is 25-65 angstroms.
Optionally, in the method for manufacturing a flash memory, after the word line is formed, before the first bit line and the second bit line are formed, a second sidewall layer is further formed, and the second sidewall layer covers the first sidewall layer on a sidewall of the first gate structure and the second gate structure away from the word line;
and after the second side wall layer is formed, performing ion implantation on the semiconductor substrate by taking the second side wall layer as a mask so as to form the first bit line and the second bit line.
Based on the same inventive concept, the present invention also provides a flash memory comprising:
A semiconductor substrate;
a well region formed in the semiconductor substrate;
the first grid structure and the second grid structure are arranged on the well region at intervals, wherein the first grid structure comprises a first floating gate layer and a first control gate layer which are sequentially stacked from bottom to top, and the second grid structure comprises a second floating gate layer and a second control gate layer which are sequentially stacked from bottom to top;
A first side wall layer covering both side walls of the first gate structure and both side walls of the second gate structure;
A word line oxide layer covering a well region between the first gate structure and the second gate structure;
a word line formed between the first gate structure and the second gate structure, and covering the word line oxide layer and a first sidewall layer between the first gate structure and the second gate structure; and
A first bit line and a second bit line, the first bit line being formed in the well region on a side of the first gate structure remote from the word line, the second bit line being formed in the well region on a side of the second gate structure remote from the word line.
Optionally, in the flash memory, the flash memory further includes a second sidewall layer, where the second sidewall layer covers the first sidewall layer on a sidewall of the first gate structure and the second gate structure away from the word line.
Based on the same inventive concept, the invention also provides an operation method of the flash memory, comprising the following steps: providing a flash memory as described above;
Sequentially performing an erase operation, a program operation and a read operation on the flash memory, wherein when the flash memory is subjected to the erase operation, a first voltage is applied to the first control layer, a second voltage is applied to the well region, and a zero voltage is applied to the second control gate layer or the first control gate layer is left empty, so that the first gate structure is erased;
Applying a third voltage on the word line, a fourth voltage on the first control gate layer, a fifth voltage on the second control gate layer, a sixth voltage on the first bit line, a seventh voltage on the second bit line, and a zero voltage on the well region to program the first gate structure when performing a program operation on the flash memory;
In a read operation of the flash memory, an eighth voltage is applied to the word line, the fifth voltage is applied to the second control gate layer, a ninth voltage is applied to the first bit line, and a zero voltage is applied to both the second bit line and the well region to read the first gate structure.
Optionally, in the operation method of the flash memory, the first voltage is between-5V and-10V, the second voltage is between 5V and 10V, the third voltage is between 0.5V and 2V, the fourth voltage is between 5V and 10V, the fifth voltage is between 4V and 6V, the sixth voltage is between 3V and 6V, the seventh voltage is between 0.1V and 1V, the eighth voltage is between 1V and 3V, and the ninth voltage is between 0.5V and 2V.
In summary, the present invention provides a flash memory, a method for manufacturing the same, and a method for operating the same, in which only a first sidewall layer is used to isolate a word line from a first gate structure and a second gate structure, so that the size of the flash memory can be reduced, and the coupling efficiency between a first control gate layer and a first floating gate layer and between a second control gate layer and a second floating gate layer can be improved, thereby improving the programming efficiency. In addition, in the operation method of the flash memory, electrons in the first floating gate layer can tunnel into the well region by applying a first voltage to the first control gate layer, applying a second voltage to the well region and applying a zero voltage to the second control gate layer or making the second control gate layer empty, so that the electrons in the first floating gate layer are erased, namely, an erase operation is performed through an FN tunneling effect between the first floating gate layer and the well region. In addition, in the erasing process, voltage does not need to be applied to the word line, so that the pressure difference between the word line and the first control gate layer can be reduced, the thickness of the side wall layer between the first gate structure and the word line is narrowed due to the fact that only the first side wall layer is arranged between the first gate structure and the word line, the size of the flash memory is reduced, meanwhile, the length of the first control gate layer and the length of the second control gate layer can be correspondingly increased on the basis that the requirement of the overall size of the flash memory is met, and the coupling efficiency of the control gate layer to the floating gate layer can be increased. In addition, during the erasing process, the word line gate oxide layer does not need to bear high voltage, so that breakdown of the word line gate oxide layer is not caused, the thickness of the word line gate oxide layer can be thinned, and therefore the size of the word line can be shortened, and the size of the memory is reduced.
Drawings
FIG. 1 is a flow chart of a method for manufacturing a flash memory according to an embodiment of the invention;
fig. 2 to 4 are schematic cross-sectional views of structures formed in a method for manufacturing a flash memory according to an embodiment of the present invention;
FIG. 5 is a top view of a flash memory according to an embodiment of the present invention after etching shallow trench isolation structures;
FIG. 6 is a schematic cross-sectional view of the structure in the direction A-A' of FIG. 5;
fig. 7 is a top view of a control gate material layer formed in a method of manufacturing a flash memory according to an embodiment of the present invention;
FIG. 8 is a schematic cross-sectional view of the structure in the direction A-A' of FIG. 7;
FIG. 9 is a schematic cross-sectional view of the structure in the direction B-B' of FIG. 7;
fig. 10 is a schematic cross-sectional view of a first gate structure and a second gate structure formed in a method of manufacturing a flash memory according to an embodiment of the present invention;
FIG. 11 is a top view of a flash memory according to an embodiment of the present invention after forming a first sidewall layer;
FIG. 12 is a schematic cross-sectional view taken along the direction C-C' of FIG. 11;
FIG. 13 is a schematic cross-sectional view of a flash memory device according to an embodiment of the present invention after forming word lines;
FIG. 14 is a schematic cross-sectional view of a flash memory according to an embodiment of the present invention after forming a second sidewall layer;
FIG. 15 is a flow chart of a method of operating a flash memory according to an embodiment of the invention;
Wherein reference numerals are as follows:
100-a semiconductor substrate; 101-well region; 1011-N type well region; 1012-P type well region; 110-shallow trench isolation structures; 120-a floating gate oxide material layer; 120 a-a first floating gate oxide layer; 120 b-a second floating gate oxide layer; 130-a layer of floating gate material; 130 a-a first floating gate layer; 130 b-a second floating gate layer; 131-a first opening; 140-an inter-gate dielectric layer; 140 a-a first inter-gate dielectric layer; 140 b-a second inter-gate dielectric layer; 150-a control gate material layer; 150 a-a first control gate layer; 150 b-a second control gate layer; 160-a hard mask layer; 160 a-a second opening; 170-a first side wall layer; 180-word line oxide; 190-word lines; 200-a second side wall layer; 210 a-a first bit line; 210 b-a second bit line.
Detailed Description
The following describes the flash memory, the manufacturing method and the operation method thereof in detail with reference to the drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Referring to fig. 1, a flow chart of a method for manufacturing a flash memory according to an embodiment of the invention is shown. As shown in fig. 1, the method for manufacturing the flash memory includes:
Step S1: providing a semiconductor substrate, wherein a well region is formed in the semiconductor substrate;
step S2: forming a first grid structure and a second grid structure which are arranged at intervals on the well region, wherein the first grid structure comprises a first floating gate layer and a first control grid layer which are sequentially stacked from bottom to top, and the second grid structure comprises a second floating gate layer and a second control grid layer which are sequentially stacked from bottom to top;
Step S3: forming a first side wall layer, wherein the first side wall layer covers two side walls of the first grid structure and two side walls of the second grid structure;
Step S4: forming a word line oxide layer, wherein the word line oxide layer covers a well region between the first gate structure and the second gate structure;
step S5: forming a word line, wherein the word line is formed between the first gate structure and the second gate structure, and covers the word line oxide layer and a first side wall layer between the first gate structure and the second gate structure; and
Step S6: first bit lines and second bit lines are formed, the first bit lines being formed in the well region on a side of the first gate structure remote from the word lines, the second bit lines being formed in the well region on a side of the second gate structure remote from the word lines.
Fig. 2 to 4 are schematic structural views of a flash memory according to an embodiment of the present invention; FIG. 5 is a top view of a flash memory according to an embodiment of the present invention after etching shallow trench isolation structures; FIG. 6 is a schematic cross-sectional view of the structure in the direction A-A' of FIG. 5; fig. 7 is a top view of a control gate material layer formed in a method of manufacturing a flash memory according to an embodiment of the present invention; FIG. 8 is a schematic cross-sectional view of the structure in the direction A-A' of FIG. 7; FIG. 9 is a schematic cross-sectional view of the structure in the direction B-B' of FIG. 7; fig. 10 is a schematic cross-sectional view of a first gate structure and a second gate structure formed in a method of manufacturing a flash memory according to an embodiment of the present invention; FIG. 11 is a top view of a flash memory according to an embodiment of the present invention after forming a first sidewall layer; FIG. 12 is a schematic cross-sectional view taken along the direction C-C' of FIG. 10; FIG. 13 is a schematic cross-sectional view of a flash memory device according to an embodiment of the present invention after forming word lines; fig. 14 is a schematic cross-sectional view of a flash memory according to an embodiment of the invention after forming a second sidewall layer. The method for manufacturing the flash memory according to the present embodiment will be described in more detail with reference to fig. 2 to 14.
First, step S1 is performed, and as shown in fig. 2 and 3, a semiconductor substrate 100 is provided, and a well region is formed in the semiconductor substrate 100. The semiconductor substrate 100 may be a P-type substrate, the well region 101 is formed in the semiconductor substrate 100, the well region 101 includes a P-type well region (P-well) 1012 and an N-type well region (N-well) 1011, the P-type well region (P-well) 1012 is formed in the N-type well region (N-well) 1011, the P-type well region (P-well) 1012 may be formed by a P-type ion implantation process, and the N-type well region 1011 may be formed by an N-type ion implantation process.
As shown in fig. 2, before forming the well region, at least two shallow trench isolation structures 110 are formed in the semiconductor substrate 100, and all the shallow trench isolation structures 110 are sequentially arranged along a second direction X, wherein a top surface of each shallow trench isolation structure 110 is higher than a top surface of the semiconductor substrate 100, and the second direction X is perpendicular to the first direction Y.
The specific forming method of the shallow trench isolation structure 110 includes: first, a pad nitride layer (not shown) and a patterned photoresist layer (not shown) are formed on the semiconductor substrate 100, wherein the patterned photoresist layer has a photoresist layer opening therein; then, sequentially etching the pad nitride layer and the semiconductor substrate 100 by using the patterned photoresist layer as a mask to form a shallow trench, wherein the shallow trench penetrates through the pad nitride layer and extends into the semiconductor substrate 100; then, forming an isolation layer by utilizing a high aspect ratio process or a high-density plasma chemical vapor deposition process, wherein the isolation layer fills the shallow trench and covers the pad nitride layer; and planarizing the isolation layer to the pad nitride layer surface to form a shallow trench isolation structure 110; next, the pad nitride layer is removed by a wet etching process to expose the semiconductor substrate 100. After the pad nitride layer is removed, a portion of the sidewalls of the shallow trench isolation structure 110 is exposed.
Next, step S2 is performed, as shown in fig. 3 to 11, to form a first gate structure and a second gate structure on the well region 101, where the first gate structure includes a first floating gate layer 130a and a first control gate layer 150a that are sequentially stacked from bottom to top, and the second gate structure includes a second floating gate layer 130b and a second control gate layer 150b that are sequentially stacked from bottom to top. The first gate structure and the second gate structure are arranged along the first direction Y and extend along the second direction X.
In addition, as shown in fig. 10, the first gate structure further includes a first floating gate oxide layer 120a and a first inter-gate dielectric layer 140a, the first floating gate oxide layer 120a is formed between the first floating gate layer 130a and the semiconductor substrate 100, and the first inter-gate dielectric layer 140a is formed between the first floating gate layer 130a and the first control gate layer 150 a. The second gate structure further includes a second floating gate oxide layer 120b and a second inter-gate dielectric layer 140b, the second floating gate oxide layer 120b is formed between the semiconductor substrate 100 and the second floating gate layer 130b, and the second inter-gate dielectric layer 140b is formed between the second floating gate layer 130b and the second control gate layer 150 b. The thickness of the first floating gate layer 130a and the second floating gate layer 130b may be, for example, 400 to 1000 angstroms, such as 600 angstroms, 800 angstroms, or 1000 angstroms. The thicknesses of the first floating gate layer 130a and the second floating gate layer 130b are 400-1000 angstroms, which can increase the coupling area between the first floating gate layer and the second floating gate layer and the subsequently formed word lines, thereby improving the coupling efficiency and thus the programming efficiency of the flash memory. Since the flash memory is erased by FN tunneling erase in this embodiment, the thickness of the floating gate material layer 130 is not limited, and thus the coupling area between the subsequently formed first and second floating gate layers and the word line is not limited (in the prior art, the high voltage difference between the floating gate layer and the word line is used for erasing, so that the thickness of the floating gate layer needs to be limited to limit the coupling area between the floating gate layer and the word line in order to avoid affecting the erasing efficiency).
In this embodiment, the method for forming the first gate structure and the second gate structure includes: first, as shown in fig. 4, a floating gate oxide material layer 120 and a floating gate material layer 130 are sequentially formed on the well region 101, the floating gate material layer 130 has a first opening 131 therein, and the thickness of the floating gate material layer 130 may be 400-1000 angstroms. The top surface of the floating gate oxide material layer 120 is lower than the top surface of the shallow trench isolation structure 110, the top surface of the floating gate material layer 130 is flush with the top surface of the shallow trench isolation structure 110, and the sidewalls of the floating gate oxide material layer 120 and the sidewalls of the floating gate material layer 130 are both in contact with the sidewalls of the shallow trench isolation structure 110. The forming method of the floating gate oxide layer further comprises the following steps: a floating gate oxide material layer 120 is formed on the well region 101 by a furnace tube process, and the thickness of the floating gate oxide material layer 120 may be 80-100 angstroms.
In this embodiment, the material of the floating gate material layer 130 may be doped polysilicon. The method for forming the floating gate material layer 130 further includes: the floating gate material layer is deposited on the global surface of the semiconductor substrate 100 by a chemical vapor deposition process, and the floating gate material layer on the shallow trench isolation structure 110 is removed by a back etching process or chemical mechanical polishing, i.e. only the floating gate material layer 130 on the well region 101 is remained, so that the top surface of the floating gate material layer 130 is flush with the top surface of the shallow trench isolation structure 110. As shown in fig. 5 and 6, after the floating gate material layer 130 is formed, the shallow trench isolation structure 110 is etched to form the first opening 131, and the top surface of the shallow trench isolation structure 110 is made flush with the top surface of the floating gate oxide material layer 120.
Next, as shown in fig. 7 and 9, an inter-gate dielectric layer 140, a control gate material layer 150 and a hard mask layer 160 are sequentially formed, wherein the inter-gate dielectric layer 140 covers the bottom wall and the side wall of the first opening 131 and extends to cover the floating gate material layer 130, and the control gate material layer 150 fills the first opening 131 and covers the inter-gate dielectric layer 140, that is, the inter-gate dielectric layer 140 is located between the floating gate material layer 130 and the control gate material layer 150. As shown in fig. 8, since the control gate material layer 150 not only covers the floating gate material layer 130 but also fills the first opening 131 in the floating gate material layer 130, and the thickness of the floating gate material layer 120 is 400-1000 angstroms, the coupling area between the control gate material layer 150 and the floating gate material layer 130 is larger, thereby improving the coupling efficiency between the first floating gate layer 130a and the first control gate layer 150a and between the second floating gate layer 130b and the second control gate layer 150b, which are formed later, and improving the programming efficiency.
As shown in fig. 9, the hard mask layer 160 covers the control gate material layer 150, and the hard mask layer 160 may be made of silicon nitride, which may protect the top surface of the control gate material layer 150 during the subsequent etching process. After forming the hard mask layer 160, a patterned photoresist layer (not shown) having a photoresist opening (opening for defining a position of a word line) may be formed on the hard mask layer 160, and then the hard mask layer 160 and the control gate material layer 150 are sequentially etched using a dry etching process to form the first control gate layer 150a and the second control gate layer 150b, and the inter-gate dielectric layer 140 is etched to form the first inter-gate dielectric layer 140a and the second inter-gate dielectric layer 140b, and the floating gate material layer 130 is etched to form the first floating gate layer 130a and the second floating gate layer 130b, and the floating gate oxide material layer 120 is etched to form the first floating gate oxide layer 120a and the second floating gate oxide layer 120b, as shown in fig. 10. The first control gate layer 150a and the second control gate layer 150b have a second opening 160a therebetween, the second opening 160a is perpendicular to the first opening 131, and the second opening 160a extends between the first floating gate layer 130a and the second floating gate layer 130 b. That is, after the first gate structure and the second gate structure are formed, a second opening 160a is formed between the first gate structure and the second gate structure for defining the position of the word line.
As shown in fig. 10, the first inter-gate dielectric layer 140a is formed between the first control gate layer 150a and the first floating gate layer 130a and the shallow trench isolation structure 110 to isolate the first control gate layer 150a from the first floating gate layer 130a and to isolate the first control gate layer 150a from the shallow trench isolation structure 110. The second inter-gate dielectric layer 140b is formed between the second control gate layer 150b and the second floating gate layer 130a and the shallow trench isolation structure 110 to isolate the second control gate layer 150b from the second floating gate layer 130b and to isolate the second control gate layer 150b from the shallow trench isolation structure 110.
Next, step S3 is performed, as shown in fig. 11 and fig. 12, a first sidewall layer 170 is formed, the first sidewall layer 170 covers two sidewalls of the first gate structure and two sidewalls of the second gate structure, and the material of the first sidewall layer 170 is silicon dioxide. Further, the specific forming method of the first sidewall layer 170 includes: first, a first sidewall material layer is formed on the global surface of the semiconductor substrate on which the first gate structure and the second gate structure are formed by adopting a furnace tube process, a Chemical Vapor Deposition (CVD) process or an atomic layer deposition process and the like. Then, the first sidewall material layer on the top surface of the hard mask layer 160 and the top surface of the semiconductor substrate 100 may be removed by self-aligned etching without a photomask, that is, the first sidewall material layers on both sidewalls of the first gate structure and the second gate structure are remained, so as to form a first sidewall layer 170, and the first sidewall layer 170 may cover part or all of both sidewalls of the hard mask layer 160, so as to perform better isolation. The first sidewall layer 170 may be used to isolate subsequently formed word lines from the first and second gate structures.
In this embodiment, only the first sidewall layer 170 is used to isolate the subsequently formed word line from the first gate structure and the second gate structure, and in the erasing process, no voltage needs to be applied to the word line, so that the voltage difference between the word line and the control gate can be reduced, therefore, only one first sidewall layer 170 is required to be disposed between the first control gate layer 150a and the second control gate layer 150b and the word line 190, and only one first sidewall layer 170 is required to be disposed, so that the thickness of the first sidewall layer 170 between the first control gate layer 150a and the second control gate layer 150b and the word line 190 is reduced, thereby reducing the size of the flash memory. Meanwhile, since only one first sidewall layer 170 is used, the lengths of the first control gate layer 150a and the second control gate layer 150b (e.g., the dimension in the direction of L 1 in fig. 10) can be correspondingly increased to increase the coupling efficiency between the first control gate layer 150a and the first floating gate layer 130a and to increase the coupling efficiency between the second control gate layer 150b and the second floating gate layer 130b on the basis of meeting the overall size requirement of the flash memory. The thickness of the first sidewall 170 may be, for example, 100 a to 300 a.
Next, step S3 is performed, where a word line oxide layer 180 is formed, the word line oxide layer 180 covers the well region 101 between the first gate structure and the second gate structure, and the word line oxide layer 180 is used to isolate the well region 101 from the word line 180. Since the flash memory is erased by FN tunneling erase in the subsequent process, the word line gate oxide 180 does not need to bear high voltage during the erase process, so that breakdown of the word line gate oxide 210 is not caused, and the thickness of the word line gate oxide 210 can be reduced to 25-65 angstroms.
Next, step S5 is performed, as shown in fig. 13, a word line 190 is formed between the first gate structure and the second gate structure, and the word line covers the word line oxide layer 180 and the first sidewall layer 170 between the first gate structure and the second gate structure. That is, the word line 190 is filled in the second opening 160a between the first gate structure and the second gate structure, the word line 190 extends along the second direction X, and the top surface of the word line 190 may be lower than the top surface of the hard mask layer 160, so as to facilitate a protective layer (e.g., a silicon oxide layer or a photoresist layer) formed on the word line 190 later, and prevent the word line 190 from being damaged in subsequent processes. The word line 190 may be made of polysilicon. Further, since the word line 190 is erased by the FN tunneling erase method, no voltage is applied to the word line 190, and thus the dimension of the word line 190 in the longitudinal direction can be shortened. As shown in fig. 13, the dimension L 2 of the word line 190 in the length direction in the present embodiment may be, for example, 40 nm to 60 nm (the dimension of the word line in the length direction in the related art is typically 70 nm to 90 nm) to reduce the size of the memory.
After forming the word line 190, as shown in fig. 14, a second sidewall layer 200 is further formed, where the second sidewall layer 200 covers the first gate structure and the first sidewall layer 170 on a sidewall of the second gate structure away from the word line 190. The material of the second sidewall layer 200 may be different from that of the first sidewall layer 170, for example, the material of the first sidewall layer 170 may be silicon oxide, and then the material of the second sidewall layer 200 may be silicon nitride, and the thickness of the second sidewall layer 200 may be, for example, 100 to 200 angstroms, and the second sidewall layer 200 may protect the first gate structure and the second gate structure from ion breakdown during the subsequent ion implantation to form a bit line.
Next, step S6 is performed, as shown in fig. 14, to form a first bit line 210a and a second bit line 210b, wherein the first bit line 210a is formed in the well region 101 on a side of the first gate structure away from the word line 190, and the second bit line 210b is formed in the well region 101 on a side of the second gate structure away from the word line 190. The specific method comprises the following steps: ion implantation is performed on the semiconductor substrate 100 with the second sidewall layer 200 as a mask, so as to form the first bit line 210a and the second bit line 210b. Typically, the semiconductor substrate 100 is annealed after the ion implantation process, in order to allow ions to more easily diffuse to predetermined locations, and also to repair defects generated to the crystal lattice of the surface of the semiconductor substrate when the ion implantation process is performed. And eliminating lattice defects and internal stress in the semiconductor substrate by using heat energy in the annealing process, and recovering the integrity of the lattice. At the same time, the implanted doping atoms are diffused to the substitutional sites of the silicon atoms, so that the doping elements generate electrical characteristics.
Based on the same inventive concept, the present invention also provides a flash memory, as shown in fig. 14, comprising: a semiconductor substrate 100; a well region 101 formed in the semiconductor substrate 100; a first gate structure and a second gate structure disposed on the well region 101 at intervals; a first sidewall layer 170 covering both sidewalls of the first gate structure and both sidewalls of the second gate structure; a word line 190 formed between the first gate structure and the second gate structure and covering the first sidewall layer 170 between the first gate structure and the second gate structure; and a first bit line 210a and a second bit line 210b, the first bit line 210a being formed in the well region 101 on a side of the first gate structure remote from the word line 190, the second bit line 210b being formed in the well region 101 on a side of the second gate structure remote from the word line 190. In addition, the flash memory further includes a second sidewall layer, where the second sidewall layer covers the first sidewall layer 170 on a sidewall of the first gate structure and the second gate structure away from the word line 190.
Fig. 15 is a flowchart illustrating an operation method of the flash memory according to an embodiment of the invention. Based on the same inventive concept, the invention also provides an operation method of the flash memory, which comprises the following steps:
Step S10: a flash memory as described above is provided.
Step S20: and sequentially performing an erase operation, a program operation and a read operation on the flash memory, wherein when the flash memory is subjected to the erase operation, a first voltage is applied to the first control gate layer, a second voltage is applied to the well region 101, and a zero voltage is applied to the second control gate layer or the second control gate layer is left empty, so that the first gate structure is erased.
Specifically, with continued reference to fig. 13, the voltage applied to the first gate structure is a voltage applied to the first control gate layer 150a, the first voltage may be, for example, between-5V and-10V, and the second voltage may be, for example, between 5V and 10V, so that FN Tunneling (F-N Tunneling) between the first floating gate layer 130a in the first gate structure and the well region 101 (herein referred to as the P-type well region 1012 in the well region 101) can be ensured by the first voltage and the second voltage, thereby erasing electrons in the first floating gate layer 130a of the first gate structure, and further erasing operation of the flash memory can be achieved. I.e. by the FN tunneling effect. In addition, during the erasing process, no voltage needs to be applied to the word line 190, so that a voltage difference between the word line 190 and the first control gate layer 150a of the first gate structure can be reduced, the voltage difference born by the first sidewall layer 170 is reduced, and breakdown of the first sidewall layer 170 can be avoided.
In a programming operation of the flash memory, a third voltage is applied to the word line 190, a fourth voltage is applied to the first control gate layer 150a, a fifth voltage is applied to the second control gate layer 150b, a sixth voltage is applied to the first bit line 210a, a seventh voltage is applied to the second bit line 210b, and a zero voltage is applied to the well region 101 to program the first gate structure. The fourth voltage is 5V-10V, the fifth voltage is 4V-6V, the sixth voltage is 3V-6V, and the seventh voltage is 0.1V-1V. Because the coupling area between the first control gate layer 150a and the first floating gate layer 130a in the first gate structure is larger, the programming efficiency can be improved during the programming process.
In this embodiment, in the read operation of the flash memory, an eighth voltage is applied to the word line 190, the fifth voltage is applied to the second control gate layer 150b, a ninth voltage is applied to the first bit line 210a, and a zero voltage is applied to both the second bit line 210b and the well region 101 to read the first gate structure. The eighth voltage may be, for example, 1V to 3V, and the ninth voltage may be, for example, 0.5V to 2V.
The invention provides a flash memory, a manufacturing method and an operating method thereof, wherein in the flash memory, word lines are isolated from a first grid structure and a second grid structure by only adopting a first side wall layer, so that the size of the flash memory can be reduced, and the coupling efficiency between a first floating gate layer and a first control grid layer and between a second floating gate layer and a second control grid layer can be improved, thereby improving the programming efficiency. In addition, in the operation method of the flash memory, by applying a first voltage to a first gate structure of the flash memory, applying a second voltage to a well region and applying a zero voltage to a second gate structure, electrons in the first gate structure can tunnel into the well region, so that electrons in the first gate structure are erased, namely, an erasing operation is performed through a FN tunneling effect, in the erasing process, voltage does not need to be applied to a word line, so that the pressure difference between the word line and a control gate can be reduced, the thickness of the first side wall layer is reduced, the size of the flash memory is reduced, and meanwhile, the lengths of the first control gate layer and the second control gate layer can be correspondingly increased on the basis of meeting the requirement of the overall size of the flash memory so as to increase the coupling efficiency of the control gate to the floating gate. The pressure difference is reduced, and the first side wall layer is prevented from being broken down. In addition, in the erasing process, the word line grating oxide layer does not need to bear high voltage, so that breakdown of the word line grating oxide layer is not caused, the thickness of the word line grating oxide layer can be thinned, and the size of the word line grating can be shortened, so that the size of a memory is reduced.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (10)
1. A flash memory, the flash memory comprising:
A semiconductor substrate;
a well region formed in the semiconductor substrate;
the first grid structure and the second grid structure are arranged on the well region at intervals, wherein the first grid structure comprises a first floating gate layer and a first control gate layer which are sequentially stacked from bottom to top, and the second grid structure comprises a second floating gate layer and a second control gate layer which are sequentially stacked from bottom to top;
A first side wall layer covering both side walls of the first gate structure and both side walls of the second gate structure;
A word line oxide layer covering a well region between the first gate structure and the second gate structure;
a word line formed between the first gate structure and the second gate structure, and covering the word line oxide layer and a first sidewall layer between the first gate structure and the second gate structure; and
A first bit line and a second bit line, the first bit line being formed in the well region on a side of the first gate structure remote from the word line, the second bit line being formed in the well region on a side of the second gate structure remote from the word line;
Applying a first voltage on the first control gate layer, applying a second voltage on the well region, and applying a zero voltage on the second control gate layer or leaving the first control gate layer empty when performing an erase operation on the flash memory, so as to erase the first gate structure;
Applying a third voltage on the word line, a fourth voltage on the first control gate layer, a fifth voltage on the second control gate layer, a sixth voltage on the first bit line, a seventh voltage on the second bit line, and a zero voltage on the well region to program the first gate structure when performing a program operation on the flash memory;
In a read operation of the flash memory, an eighth voltage is applied to the word line, the fifth voltage is applied to the second control gate layer, a ninth voltage is applied to the first bit line, and a zero voltage is applied to both the second bit line and the well region to read the first gate structure.
2. The flash memory of claim 1, further comprising a second sidewall layer covering the first sidewall layer on a sidewall of the first gate structure and the second gate structure remote from the word line.
3. The flash memory of claim 1, wherein the first voltage is-5V to-10V, the second voltage is 5V to 10V, the third voltage is 0.5V to 2V, the fourth voltage is 5V to 10V, the fifth voltage is 4V to 6V, the sixth voltage is 3V to 6V, the seventh voltage is 0.1V to 1V, the eighth voltage is 1V to 3V, and the ninth voltage is 0.5V to 2V.
4. A method of manufacturing the flash memory according to any one of claims 1 to 3, comprising:
providing a semiconductor substrate, wherein a well region is formed in the semiconductor substrate;
Forming a first grid structure and a second grid structure which are spaced on the well region, wherein the first grid structure comprises a first floating gate layer and a first control grid layer which are sequentially stacked from bottom to top, and the second grid structure comprises a second floating gate layer and a second control grid layer which are sequentially stacked from bottom to top;
Forming a first side wall layer, wherein the first side wall layer covers two side walls of the first grid structure and two side walls of the second grid structure;
Forming a word line oxide layer, wherein the word line oxide layer covers the well region between the first gate structure and the second gate structure;
forming a word line, wherein the word line is formed between the first gate structure and the second gate structure, and covers the word line oxide layer and a first side wall layer between the first gate structure and the second gate structure; and
First bit lines and second bit lines are formed, the first bit lines being formed in the well region on a side of the first gate structure remote from the word lines, the second bit lines being formed in the well region on a side of the second gate structure remote from the word lines.
5. The method of manufacturing a flash memory device of claim 4, wherein the first gate structure further comprises a first floating gate oxide layer and a first inter-gate dielectric layer, the first floating gate oxide layer being formed between the first floating gate layer and the semiconductor substrate, the first inter-gate dielectric layer being formed between the first floating gate layer and the first control gate layer; the second gate structure further comprises a second floating gate oxide layer and a second inter-gate dielectric layer, wherein the second floating gate oxide layer is formed between the second floating gate layer and the semiconductor substrate, and the second inter-gate dielectric layer is formed between the second floating gate layer and the second control gate layer.
6. The method of manufacturing a flash memory device of claim 5, wherein the forming of the first gate structure and the second gate structure comprises:
Forming a floating gate oxide material layer and a floating gate material layer on the well region in sequence, wherein the floating gate material layer is provided with a first opening;
Forming an inter-gate dielectric layer, a control gate material layer and a hard mask layer in sequence, wherein the inter-gate dielectric layer covers the bottom wall and the side wall of the first opening and extends to cover the floating gate material layer, the control gate material layer fills the first opening and covers the inter-gate dielectric layer, and the hard mask layer covers the control gate material layer;
The hard mask layer and the control gate material layer are sequentially etched to form a first control gate layer and a second control gate layer, the floating gate material layer is etched to form a first floating gate layer and a second floating gate layer, the inter-gate dielectric layer is etched to form a first inter-gate dielectric layer and a second inter-gate dielectric layer, and the floating gate oxide material layer is etched to form a first floating gate oxide layer and a second floating gate oxide layer, wherein a second opening is formed between the first control gate layer and the second control gate layer, the second opening is perpendicular to the first opening, and the second opening extends between the first floating gate layer and the second floating gate layer.
7. The method of manufacturing a flash memory of claim 6, wherein prior to forming the layer of floating gate material, the method of manufacturing a flash memory further comprises: forming at least two shallow trench isolation structures in the semiconductor substrate, wherein the well region surrounds the shallow trench isolation structures, and the top surface of each shallow trench isolation structure is flush with the top surface of the floating gate material layer;
and after the floating gate material layer is formed, the shallow trench isolation structure is further etched to form the first opening, and the top surface of the shallow trench isolation structure is flush with the top surface of the floating gate oxide material layer.
8. The method of manufacturing a flash memory device according to claim 7, wherein the thickness of the first floating gate layer and the thickness of the second floating gate layer are each 400 to 1000 angstroms.
9. The method of claim 4, wherein the word line oxide layers each have a thickness of 25 a to 65 a.
10. The method of claim 7, further comprising forming a second sidewall layer after forming the word line and before forming the first bit line and the second bit line, the second sidewall layer covering the first sidewall layer on a sidewall of the first gate structure and the second gate structure remote from the word line;
and after the second side wall layer is formed, performing ion implantation on the semiconductor substrate by taking the second side wall layer as a mask so as to form the first bit line and the second bit line.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101853704A (en) * | 2010-05-28 | 2010-10-06 | 上海宏力半导体制造有限公司 | Erasing method of split-gate flash memory of shared word line |
| CN102104044A (en) * | 2009-12-17 | 2011-06-22 | 中芯国际集成电路制造(上海)有限公司 | Separate gate flash memory and manufacturing method thereof |
| CN102938406A (en) * | 2012-11-21 | 2013-02-20 | 上海宏力半导体制造有限公司 | Split gate type flash memory and forming method thereof |
| CN103165615A (en) * | 2011-12-19 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Grid-divided flash memory and forming method of the same |
| CN103219288A (en) * | 2013-03-22 | 2013-07-24 | 上海宏力半导体制造有限公司 | Semiconductor device and forming method thereof |
| CN104752434A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Memory device and forming method thereof |
| CN106206445A (en) * | 2015-04-29 | 2016-12-07 | 中芯国际集成电路制造(上海)有限公司 | The forming method of memory construction |
| CN112185973A (en) * | 2020-10-27 | 2021-01-05 | 上海华虹宏力半导体制造有限公司 | Memory, manufacturing method and operating method of memory |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI220560B (en) * | 2003-10-27 | 2004-08-21 | Powerchip Semiconductor Corp | NAND flash memory cell architecture, NAND flash memory cell array, manufacturing method and operating method of the same |
| US20090098721A1 (en) * | 2007-10-16 | 2009-04-16 | Michael-Y Liu | Method of fabricating a flash memory |
-
2021
- 2021-09-29 CN CN202111150389.4A patent/CN113903789B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102104044A (en) * | 2009-12-17 | 2011-06-22 | 中芯国际集成电路制造(上海)有限公司 | Separate gate flash memory and manufacturing method thereof |
| CN101853704A (en) * | 2010-05-28 | 2010-10-06 | 上海宏力半导体制造有限公司 | Erasing method of split-gate flash memory of shared word line |
| CN103165615A (en) * | 2011-12-19 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Grid-divided flash memory and forming method of the same |
| CN102938406A (en) * | 2012-11-21 | 2013-02-20 | 上海宏力半导体制造有限公司 | Split gate type flash memory and forming method thereof |
| CN103219288A (en) * | 2013-03-22 | 2013-07-24 | 上海宏力半导体制造有限公司 | Semiconductor device and forming method thereof |
| CN104752434A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Memory device and forming method thereof |
| CN106206445A (en) * | 2015-04-29 | 2016-12-07 | 中芯国际集成电路制造(上海)有限公司 | The forming method of memory construction |
| CN112185973A (en) * | 2020-10-27 | 2021-01-05 | 上海华虹宏力半导体制造有限公司 | Memory, manufacturing method and operating method of memory |
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