CN103219288A - Semiconductor device and forming method thereof - Google Patents
Semiconductor device and forming method thereof Download PDFInfo
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- CN103219288A CN103219288A CN2013100954176A CN201310095417A CN103219288A CN 103219288 A CN103219288 A CN 103219288A CN 2013100954176 A CN2013100954176 A CN 2013100954176A CN 201310095417 A CN201310095417 A CN 201310095417A CN 103219288 A CN103219288 A CN 103219288A
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Abstract
Provided are a semiconductor device and a forming method of the semiconductor device. The forming method of the semiconductor device comprises the steps of providing a semiconductor substrate, wherein the semiconductor substrate is provided with a capacitance area; forming a flash memory unit on the surface, in the capacitance area, of the semiconductor substrate, wherein the flash memory unit comprises a tunneling oxide layer arranged on the surface of the semiconductor substrate, and a word line layer arranged on the surface of the tunneling oxide layer; forming a medium layer on the surface of the word line layer; forming an electrode layer on the surface of the medium layer; and forming electric conducting plugs which are respectively and electrically connected with the word line layer and the electrode layer. The forming method of the semiconductor device is simple in technology, and reduces production cost.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of semiconductor device and forming method thereof.
Background technology
Polycrystalline silicon-on-insulator-polysilicon (PIP, Poly-Insulator-Poly) capacitor and polysilicon-polysilicon silicon-substrate (PPS, Poly-Poly-Substrate) capacitor is widely used in preventing the frequency demodulation of noise and analogue device in logical circuit or flash memories circuit.
Please refer to Fig. 1, is the cross-sectional view of existing P IP electric capacity, comprising: Semiconductor substrate 10, be formed with fleet plough groove isolation structure 11 in the described Semiconductor substrate 10, and described fleet plough groove isolation structure 11 surfaces and Semiconductor substrate 10 flush; Be positioned at first polysilicon layer 13 on described fleet plough groove isolation structure 11 surfaces, and described first polysilicon layer 13 is doped with N type ion; Be positioned at first dielectric layer 14 on described first polysilicon layer 13 surfaces; Be positioned at second polysilicon layer 15 on described first dielectric layer 14 surfaces; Need to prove that described first polysilicon layer 13 is connected with the conductive plunger (not shown) respectively with second polysilicon layer 15.
Please refer to Fig. 2, is the cross-sectional view of existing P PS electric capacity, comprising: Semiconductor substrate 20, be formed with dopant well 29 in the described Semiconductor substrate 20, and the fleet plough groove isolation structure 21 that is positioned at described dopant well 29 both sides; Be positioned at the tunneling medium layer 22 on described dopant well 29 surfaces; Be positioned at first polysilicon layer 23 on described tunneling medium layer 22 surfaces, and described first polysilicon layer 23 is doped with N type ion; Be positioned at first dielectric layer 24 on described first polysilicon layer 23 surfaces; Be positioned at second polysilicon layer 25 on described first dielectric layer 24 surfaces; Need to prove that described first polysilicon layer 23, second polysilicon layer 25 and dopant well 29 are connected with the conductive plunger (not shown) respectively.
Yet, when in existing flash memories circuit, forming PIP electric capacity or PPS electric capacity, the processing step complexity, production cost is higher.
The related data of the formation method of more capacitor please be joined the Chinese patent file that publication number is CN102117780.
Summary of the invention
The problem that the present invention solves provides a kind of semiconductor device and forming method thereof, is reduced at the processing step that forms semiconductor capacitor in the flash memories circuit, and reduces production cost.
For addressing the above problem, the invention provides a kind of formation method of semiconductor device, comprising: Semiconductor substrate is provided, and described Semiconductor substrate has capacitive region; Semiconductor substrate surface in described capacitive region forms flash cell, and described flash cell comprises: the word line layer that is positioned at the tunnel oxide of semiconductor substrate surface and is positioned at described tunnel oxide laminar surface; Form dielectric layer on described word line layer surface; Form electrode layer on described dielectric layer surface; Form the conductive plunger that is electrically connected with word line layer and electrode layer respectively.
Optionally, described flash cell also comprises: the floating gate layer that is positioned at the tunnel oxide laminar surface of word line layer both sides, be positioned at second dielectric layer on described floating gate layer surface, and the control grid layer that is positioned at the described second dielectric layer surface, isolate by first dielectric layer electricity between described floating gate layer, second dielectric layer and control grid layer and the word line layer.
Optionally, described second dielectric layer is the overlay structure of silica-silicon-nitride and silicon oxide, and the material of described floating gate layer and control grid layer is a polysilicon, and the material of described first dielectric layer is silica and one or both combinations of silicon nitride.
Optionally, described Semiconductor substrate also has the memory block, when the semiconductor substrate surface of described capacitive region forms flash cell, semiconductor substrate surface in the memory block forms flash cell, and identical in capacitive region with the technology that the memory block forms flash cell, the structure of formed flash cell is identical.
Optionally, described Semiconductor substrate also has logic area, when the word line layer surface of described capacitive region forms dielectric layer, semiconductor substrate surface at logic area forms dielectric layer, when the dielectric layer surface of described capacitive region forms electrode layer, dielectric layer surface at logic area forms electrode layer, and the dielectric layer of described logic area is as the gate dielectric layer of logic transistor, and the electrode layer of described logic area is as the grid layer of logic transistor.
Optionally, after the semiconductor substrate surface of logic area forms electrode layer, form side wall, in the Semiconductor substrate of described electrode layer and side wall both sides, form source region and drain region at the dielectric layer of described logic area and the semiconductor substrate surface of electrode layer both sides.
Optionally, have fleet plough groove isolation structure in the Semiconductor substrate of described capacitive region, form described flash cell on described fleet plough groove isolation structure surface.
Optionally, have well region in the Semiconductor substrate of described capacitive region, form flash cell on described well region surface.
Optionally, the material of described tunnel oxide and dielectric layer is a silica, and the material of described word line layer and electrode layer is a polysilicon, and the material of described conductive plunger is copper, tungsten or aluminium.
Accordingly, the present invention also provides above-mentioned each method of a kind of employing formed semiconductor device, comprising: Semiconductor substrate, and described Semiconductor substrate has capacitive region; Be positioned at the flash cell of the semiconductor substrate surface of described capacitive region, described flash cell comprises: the word line layer that is positioned at the tunnel oxide of semiconductor substrate surface and is positioned at described tunnel oxide laminar surface; Be positioned at the dielectric layer on described word line layer surface; Be positioned at the electrode layer on described dielectric layer surface; The conductive plunger that is electrically connected with word line layer and electrode layer respectively.
Compared with prior art, technical scheme of the present invention has the following advantages:
Surface in the Semiconductor substrate capacitive region forms flash cell, owing to comprise the tunnel oxide that is positioned at semiconductor substrate surface in the described flash cell, and the word line layer that is positioned at described tunnel oxide laminar surface, therefore, described word line layer can be as one of two-layer electrode of semicoductor capacitor; Secondly, in the flash cell that the flash cell of described capacitive region can be used to store in forming circuit, the employing same process forms, make the word line layer of described capacitive region need not to carry out extra deposition and etching technics can form, and need not to make extra mask blank, can simplify technology, reduce cost.
Further, the electrode layer that forms dielectric layer and be positioned at the dielectric layer surface on described word line layer surface; Described electrode layer can be as another layer electrode of semicoductor capacitor, and described dielectric layer can be used in word line layer and the electrode layer of isolation as electrode, forms semicoductor capacitor in capacitive region; And, when described capacitive region forms dielectric layer and electrode layer, can form dielectric layer and electrode layer at the semiconductor substrate surface of logic area, described dielectric layer is as the gate dielectric layer of logic transistor, electrode layer is as the gate electrode layer of logic transistor, further simplified manufacturing process, and reduced cost.
Described semiconductor device adopts the word line layer of flash cell as one deck electrode, adopts electrode layer as another layer electrode, and adopts the dielectric layer electricity to isolate described word line layer and electrode layer, and described semiconductor capacitor helps the further integrated of system.
Description of drawings
Fig. 1 is the cross-sectional view of existing P IP electric capacity;
Fig. 2 is the cross-sectional view of existing P PS electric capacity;
Fig. 3 to Fig. 7 is the cross-sectional view in the forming process of semiconductor device of the embodiment of the invention.
Embodiment
As stated in the Background Art, when in existing flash memories circuit, forming PIP electric capacity or PPS electric capacity, the processing step complexity, production cost is higher.
Comprise flash memory cell device, logical device and capacitor in the existing flash memories circuit, wherein, capacitor forms when forming logical device.With PIP electric capacity is example, please continue with reference to figure 1, after fleet plough groove isolation structure 11 surfaces formed first polysilicon layer 13, when described first polysilicon layer 13 surfaces formed first dielectric layer 14, Semiconductor substrate 10 surfaces that form logic transistor at needs formed gate dielectric layer; When formation is positioned at second polysilicon layer 15 on described first dielectric layer 14 surfaces, form gate electrode layer on described gate dielectric layer surface; Afterwards, the semiconductor substrate surface in described gate dielectric layer and gate electrode layer both sides forms side wall, and forms source region and drain region, promptly can form logic transistor.In addition, the method that forms PPS electric capacity in the flash memories circuit is similar to the method for above-mentioned formation PIP electric capacity, does not give unnecessary details at this.
Yet, discover through the present inventor, as shown in Figure 1, though first dielectric layer 14 and second polysilicon layer 15 can form in gate dielectric layer that forms logic transistor and gate electrode layer, simplify processing step with this, but first polysilicon layer 13 that is formed at fleet plough groove isolation structure 11 surfaces still needs by extra depositing operation, photoetching process and etching technics form, increased extra processing step, and need the extra mask blank of making to form described first polysilicon layer 13, so the processing step complexity, and production cost is higher.
Further study through the present inventor, when the semiconductor substrate surface of memory block forms flash cell, adopt the technology that forms described flash cell to form flash cell on the surface of Semiconductor substrate capacitive region, described flash cell comprises: the word line layer that is positioned at the tunnel oxide of semiconductor substrate surface and is positioned at described tunnel oxide laminar surface; Wherein, described word line layer can be as one of two-layer electrode of formed capacitor; Afterwards, the electrode layer that forms dielectric layer and be positioned at the dielectric layer surface on described word line layer surface; Described electrode layer can be as another layer electrode of formed capacitor, and described dielectric layer can be used in word line layer and the electrode layer of isolation as electrode, thereby form semicoductor capacitor in capacitive region.The simplified manufacturing process of described semicoductor capacitor, and production cost reduces.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Fig. 3 to Fig. 7 is the cross-sectional view in the forming process of semiconductor capacitor of the embodiment of the invention.
Please refer to Fig. 3, Semiconductor substrate 200 is provided, described Semiconductor substrate 200 has capacitive region II, memory block I and logic area III.
Described Semiconductor substrate 200 is used to subsequent technique that workbench is provided; Described Semiconductor substrate 200 is silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI) substrate, germanium on insulator (GOI) substrate or III-V compounds of group substrate (for example gallium nitride or GaAs etc.).
In the present embodiment, described Semiconductor substrate 200 is used to form the flash memories circuit, and described flash memories circuit comprises memory device, logic transistor and capacitor, and therefore, described Semiconductor substrate 200 has memory block I, capacitive region II and logic area III; Described memory block I is used to form memory device, and described logic area III is used to form logic transistor, and described capacitive region II is used to form semiconductor capacitor.
The follow-up semiconductor capacitor that forms at described capacitive region II is PIP electric capacity or PPS electric capacity, and described PIP electric capacity or PPS electric capacity have higher unit-area capacitance value, and operating voltage is higher, help improving the performance of flash memories circuit.
In one embodiment, formed capacitor is a PIP electric capacity, forms fleet plough groove isolation structure (not shown), the flush of the surface of described fleet plough groove isolation structure and Semiconductor substrate 200 in the Semiconductor substrate 200 of described capacitive region II; Follow-up formed semiconductor capacitor is positioned at described fleet plough groove isolation structure surface; The material of described fleet plough groove isolation structure is a silica, and the formation technology of described fleet plough groove isolation structure is well known to those skilled in the art, and does not give unnecessary details at this.
In another embodiment, formed capacitor is a PPS electric capacity, adopts ion implantation technology to form the well region (not shown) in the Semiconductor substrate 200 of described capacitive region II, and the preferable ion that is mixed is a n type ion; Follow-uply be positioned at described well region surface at formed semiconductor capacitor, especially when the dopant ion in the described well region was n type ion, the charge carrier that moves in the semiconductor capacitor was an electronics, the better performances of formed semiconductor capacitor.The method that described employing ion implantation technology forms well region is well known to those skilled in the art, and does not give unnecessary details at this.Need to prove, also be formed with fleet plough groove isolation structure in the described Semiconductor substrate 200, other zones of described well region and Semiconductor substrate are isolated.
Please refer to Fig. 4, Semiconductor substrate 200 surfaces at described capacitive region II and memory block I form flash cell respectively, and described flash cell comprises: the word line layer 202 that is positioned at the tunnel oxide 201 on Semiconductor substrate 200 surfaces and is positioned at described tunnel oxide laminar surface.
The flash cell that forms at memory block I is used for being used to realize at the flash memories circuit memory function of circuit; Forming the technological process of described flash cell and the structure of formed flash cell can decide according to concrete technical need.
Described flash cell comprises the tunnel oxide 201 that is positioned at Semiconductor substrate 200 surfaces and is positioned at the word line layer 202 on tunnel oxide 201 surfaces that therefore described word line layer 202 is isolated with Semiconductor substrate 200 electricity.And the present inventor finds, described word line layer 202 with Semiconductor substrate 200 electricity isolation can be as one deck electrode in the semicoductor capacitor.
Further, form flash cell simultaneously at memory block I and capacitive region II, wherein, the word line layer 202 in the flash cell of capacitive region II can be as one deck electrode of formed semiconductor capacitor; Simultaneously form dielectric layer and electrode layer on word line layer 202 surfaces of described capacitive region II when follow-up when forming logic transistor, described electrode layer can be as another layer electrode in the semiconductor capacitor.Therefore, when capacitive region II formed semiconductor capacitor, the mask blank that need not to increase any processing step or be used for photoetching process can form in the device that forms memory block I and logic area III, processing step is simplified, and can greatly be saved production cost.
Described flash cell also comprises: the floating gate layer 203 that is positioned at word line layer 202 both sides, be positioned at second dielectric layer 204 on described floating gate layer 203 surfaces, and the control grid layer 205 that is positioned at described second dielectric layer 204 surfaces, isolate by first dielectric layer, 206 electricity between described floating gate layer 203, second dielectric layer 204 and control grid layer 205 and the word line layer 202, and described floating gate layer 203 is isolated by first dielectric layer 206 and Semiconductor substrate electricity.
Described second dielectric layer 204 is the overlay structure of silica-silicon-nitride and silicon oxide (ONO), and described silica-silicon-nitride and silicon oxide overlay structure has less defects, lower electric field strength, can suppress leakage current effectively; The material of described floating gate layer 203 and control grid layer 205 is a polysilicon, and the material of described first dielectric layer 206 is one or both combinations in silica and the silicon nitride, and the material of described tunnel oxide 201 is a silica; The material of described word line layer 202 is polysilicon, and is preferable, has n type dopant ion in the described polysilicon, and the word line layer 202 internal conductance rates with dopant ion are higher, help improving device performance; Described dopant ion can be doped in the word line layer 202 by ion implantation technology or in-situ doped technology.
In the present embodiment, the formation technology of described flash cell is: form insulation film successively on Semiconductor substrate 200 surfaces, be positioned at the floating boom film on insulation film surface, the control gate film that is positioned at second dielectric film of floating boom film surface and is positioned at the second dielectric film surface; Form silicon nitride layer at described control gate film surface, have first opening that exposes the control gate film in the described silicon nitride layer, the size of described first opening and position with need be corresponding in the position of the flash cell of memory block I and capacitive region II formation; Sidewall surfaces at described first opening forms first side wall; With described first side wall and silicon nitride layer is the described control gate film of mask etching, second dielectric film, floating boom film and insulation film, till exposing Semiconductor substrate 200, in described control gate film, second dielectric film and floating boom film, form second opening; Sidewall surfaces at described second opening forms second side wall; After forming second side wall, form tunnel oxide 201 on Semiconductor substrate 200 surfaces of described second open bottom, form word line layer 202 on described tunnel oxide 201 surfaces, the surface of described word line layer 202 is not higher than the surface of described silicon nitride layer; After forming word line layer, remove described silicon nitride layer, with the word line layer 202 and first side wall is the described control gate film of mask etching, second dielectric film, floating boom film and tunnel oxide film, till exposing Semiconductor substrate, form control grid layer 205, second dielectric layer 204 and floating gate layer 203, and form separator in the sidewall surfaces in described control grid layer 205, second dielectric layer 204, floating gate layer 203 and tunnel oxide 201 outsides; Described first side wall, second side wall, insulation film and separator constitute described first dielectric layer 206.
Need to prove, all carry out simultaneously, therefore, need not to adopt extra technology can form the bottom electrode of semiconductor capacitor, simplified processing step in each road technology of memory block I and capacitive region II formation flash cell; And, form in the technical process of flash cell at memory block I and capacitive region II, the mask blank that is used for photoetching process that is adopted is identical, therefore need not the extra mask blank that is used to form the semiconductor capacitor bottom electrode of making, and the cost of making described mask blank is higher, thereby present embodiment can greatly reduce production costs.
The quantity of flash cell that is formed at capacitive region II in the present embodiment is more than or equal to 1, and promptly subsequent technique can form the semiconductor capacitor more than or equal to 1; The quantity of the flash cell that forms at capacitive region II is decided according to concrete circuit design demand, when needs form big electric capacity in circuit, can form the several semiconductor capacitor at capacitive region II, and it is in parallel that described several semiconductor capacitor is constituted, thereby reach the purpose that increases capacitance.
Please refer to Fig. 5, on word line layer 202 surfaces of capacitive region II and Semiconductor substrate 200 surfaces of the logic area III electrode layer 208 that forms dielectric layer 207 respectively and be positioned at described dielectric layer 207 surfaces.
The dielectric layer 207 and the electrode layer 208 that are formed at logic area III are used to form logic transistor, and wherein, dielectric layer 207 is as the gate dielectric layer of logic transistor, and described electrode layer 208 is as the grid layer of logic transistor; And the electrode layer 208 that is formed at capacitive region II word line layer 202 surfaces is used for another layer electrode as semiconductor capacitor, and the dielectric layer 207 between word line layer 202 and electrode layer 208 is as the dielectric layer of isolating two-layer electrode.Because dielectric layer 207 and the electrode layer 208 of logic area III and capacitive region II form simultaneously, have further simplified processing step.
The material of described dielectric layer 207 is a silica, and the material of described electrode layer 208 is a polysilicon, and the formation technology of described dielectric layer 207 and electrode layer 208 is: form dielectric film on Semiconductor substrate 200 surfaces; Form electrode film on described dielectric film surface; Etched portions dielectric film and electrode film until word line layer 202 surfaces that expose Semiconductor substrate 200 and memory block I, form dielectric layer 207 and electrode layer 208 at logic area III and capacitive region II respectively.
Need to prove, after Semiconductor substrate 200 surfaces of logic area III form electrode layer 208, form the side wall (not shown) at the dielectric layer 207 of logic area III and Semiconductor substrate 200 surfaces of electrode layer 208 both sides, in the Semiconductor substrate 200 of described electrode layer 208 and side wall both sides, form source region and drain region (not shown).When logic area III forms side wall, can form side wall in the flash cell both sides of memory block I and capacitive region II; When logic area III forms source region and drain region, can form source region and drain region in the flash cell both sides of memory block I.
Please refer to Fig. 6 and Fig. 7, Fig. 7 is the vertical view structure chart of capacitive region II among Fig. 6, forms the conductive plunger 209 that is electrically connected with word line layer 202 and electrode layer 208 respectively at capacitive region II.
The material of described conductive plunger 209 is copper, tungsten or aluminium; Be respectively applied for two-layer electrode as formed semiconductor capacitor owing to be positioned at the word line layer 202 of capacitive region II and electrode layer 208, therefore described conductive plunger 209 is used for making respectively the two-layer electrode of described semiconductor capacitor to be electrically connected with other semiconductor device; The quantity of the conductive plunger 209 that is electrically connected with word line layer 202 or the electrode layer 208 of capacitive region II is more than or equal to 1, when described conductive plunger 209 when being a plurality of, helps increasing electric current, improves the performance of semiconductor capacitor.
Need to prove, please refer to Fig. 7, the shape of described word line layer 202 and electrode layer 208 differs, wherein, the border of described word line layer 202 protrudes in the border of described electrode layer 208, so that conductive plunger 209 can directly be electrically connected with word line layer 202, and need not to pass electrode layer 208, can simplify technology, and make device performance more stable.
In one embodiment, when formed capacitor was PPS electric capacity, formed semiconductor capacitor was positioned at the well region surface of Semiconductor substrate 200; When forming the conductive plunger is electrically connected with word line layer 202 and electrode layer 208 209, at the surperficial formation of described well region conductive plunger 209, and the conductive plunger 209 on described well region surface does not contact with flash cell.
In another embodiment, when formed capacitor was PIP electric capacity, formed semiconductor capacitor was positioned at the fleet plough groove isolation structure surface, and described conductive plunger 209 only is electrically connected with word line layer 202 and electrode layer 208.
Need to prove, when capacitive region II forms conductive plunger 209, can form conductive plunger respectively, be used to make memory block I also can be connected with external electric with the formed device of logic area III at memory block I and logic area III.
Present embodiment forms flash cell at memory block I and capacitive region II simultaneously, because described flash cell comprises tunnel oxide 201 that is positioned at semiconductor substrate surface and the word line layer 202 that is positioned at described tunnel oxide 201 surfaces, the word line layer 202 that therefore is positioned at capacitive region II can be as one deck electrode of semiconductor capacitor; Afterwards, form dielectric layer 207 and electrode layer 208 on word line layer 202 surfaces of capacitive region II and Semiconductor substrate 200 surfaces of logic area III simultaneously; The electrode layer 208 that is positioned at capacitive region II can be as the opposite side electrode of semiconductor capacitor, and is isolated mutually by dielectric layer 207 between the formed two-layer electrode; Thus, when forming described semiconductor capacitor, need not increases extra processing step, and need not to make extra mask blank, thereby simplifies technology and save manufacturing cost.
Accordingly, present embodiment also provides a kind of semiconductor capacitor, please continue to comprise with reference to figure 6: Semiconductor substrate 200, and described Semiconductor substrate 200 has capacitive region II; Be positioned at the flash cell on Semiconductor substrate 200 surfaces of described capacitive region II, described flash cell comprises: the word line layer 202 that is positioned at the tunnel oxide 201 on Semiconductor substrate 200 surfaces and is positioned at described tunnel oxide 201 surfaces; Be positioned at the dielectric layer 207 on described word line layer 202 surfaces; Be positioned at the electrode layer 208 on described dielectric layer 207 surfaces; The conductive plunger 209 that is electrically connected with word line layer 202 and electrode layer 208 respectively.
Described Semiconductor substrate 200 also has memory block I and logic area III, and the semiconductor substrate surface of described memory block I has flash cell, and the semiconductor substrate surface of described logic area III has the logic transistor that comprises dielectric layer 207 and electrode layer 208; Described logic transistor also comprises: be positioned at the side wall (not shown) on Semiconductor substrate 200 surfaces of described dielectric layer 207 and electrode layer 208 both sides and source region and the drain region that is positioned at the Semiconductor substrate 200 of described electrode layer 208 and side wall both sides.
The word line layer 202 of capacitive region II and electrode layer 208 be respectively as the two-layer electrode of semiconductor capacitor, and isolated by dielectric layer 207; Wherein, the word line layer 202 of capacitive region II is isolated by tunnel oxide 201 and Semiconductor substrate 200 electricity, and therefore the word line layer 202 of described capacitive region II can be as one deck electrode of described semiconductor capacitor; At capacitive region II, described electrode layer 208 is isolated by dielectric layer 207 and word line layer 202 electricity, and therefore described electrode layer 208 can be as another layer electrode of described semiconductor capacitor; In addition, the quantity of the flash cell of capacitive region II is more than or equal to 1, and promptly the quantity of semiconductor capacitor is more than or equal to 1.
Described flash cell also comprises: the floating gate layer 203 that is positioned at tunnel oxide 201 surfaces of word line layer 202 both sides, be positioned at second dielectric layer 204 on described floating gate layer 203 surfaces, and the control grid layer 205 that is positioned at described second dielectric layer 204 surfaces, isolate by first dielectric layer, 206 electricity between described floating gate layer 203, second dielectric layer 204 and control grid layer 205 and the word line layer 202.
Described second dielectric layer 204 is the overlay structure of silica-silicon-nitride and silicon oxide, the material of described floating gate layer 203 and control grid layer 205 is a polysilicon, the material of described first dielectric layer 206 is one or both combinations in silica and the silicon nitride, the material of described tunnel oxide 201 and dielectric layer 207 is a silica, and the material of word line layer 202 and electrode layer 208 is a polysilicon; The material of described conductive plunger 209 is copper, tungsten or aluminium, and the quantity of the conductive plunger 208 that is electrically connected with word line layer 202 or the electrode layer 208 of capacitive region II is more than or equal to 1.
In one embodiment, described semiconductor capacitor is a PIP electric capacity, have fleet plough groove isolation structure in the Semiconductor substrate 200 of described capacitive region II, the flush of the surface of described fleet plough groove isolation structure and Semiconductor substrate 200, semiconductor capacitor is positioned at described fleet plough groove isolation structure surface.
In another embodiment, described semiconductor capacitor is a PPS electric capacity, has well region in the Semiconductor substrate 200 of described capacitive region II, has n type dopant ion in the described well region, and semiconductor capacitor is positioned at described well region surface; And described well region surface also has conductive plunger 209.
In the semiconductor capacitor of present embodiment, word line layer 202 in the flash cell of capacitive region II is as one deck electrode, and the electrode layer 208 that is positioned at described word line 202 surfaces is as another layer electrode, and described word line 202 is isolated by dielectric layer 207 and described electrode layer 208 electricity.Described semiconductor capacitor helps the further integrated of system.
In sum, surface in the Semiconductor substrate capacitive region forms flash cell, owing to comprise the tunnel oxide that is positioned at semiconductor substrate surface in the described flash cell, and the word line layer that is positioned at described tunnel oxide laminar surface, therefore, described word line layer can be as one of two-layer electrode of semicoductor capacitor; Secondly, in the flash cell that the flash cell of described capacitive region can be used to store in forming circuit, the employing same process forms, make the word line layer of described capacitive region need not to carry out extra deposition and etching technics can form, and need not to make extra mask blank, can simplify technology, reduce cost.
Further, the electrode layer that forms dielectric layer and be positioned at the dielectric layer surface on described word line layer surface; Described electrode layer can be as another layer electrode of semicoductor capacitor, and described dielectric layer can be used in word line layer and the electrode layer of isolation as electrode, forms semicoductor capacitor in capacitive region; And, when described capacitive region forms dielectric layer and electrode layer, can form dielectric layer and electrode layer at the semiconductor substrate surface of logic area, described dielectric layer is as the gate dielectric layer of logic transistor, electrode layer is as the gate electrode layer of logic transistor, further simplified manufacturing process, and reduced cost.
Described semiconductor device adopts the word line layer of flash cell as one deck electrode, adopts electrode layer as another layer electrode, and adopts the dielectric layer electricity to isolate described word line layer and electrode layer, and described semiconductor capacitor helps the further integrated of system.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (10)
1. the formation method of a semiconductor device is characterized in that, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate has capacitive region;
Semiconductor substrate surface in described capacitive region forms flash cell, and described flash cell comprises: the word line layer that is positioned at the tunnel oxide of semiconductor substrate surface and is positioned at described tunnel oxide laminar surface;
Form dielectric layer on described word line layer surface;
Form electrode layer on described dielectric layer surface;
Form the conductive plunger that is electrically connected with word line layer and electrode layer respectively.
2. the formation method of semiconductor device according to claim 1, it is characterized in that, described flash cell also comprises: the floating gate layer that is positioned at the tunnel oxide laminar surface of word line layer both sides, be positioned at second dielectric layer on described floating gate layer surface, and the control grid layer that is positioned at the described second dielectric layer surface, isolate by first dielectric layer electricity between described floating gate layer, second dielectric layer and control grid layer and the word line layer.
3. as the formation method of semiconductor device as described in the claim 2, it is characterized in that, described second dielectric layer is the overlay structure of silica-silicon-nitride and silicon oxide, the material of described floating gate layer and control grid layer is a polysilicon, and the material of described first dielectric layer is one or both combinations in silica and the silicon nitride.
4. the formation method of semiconductor device according to claim 1, it is characterized in that, described Semiconductor substrate also has the memory block, when the semiconductor substrate surface of described capacitive region forms flash cell, semiconductor substrate surface in the memory block forms flash cell, and identical in capacitive region with the technology that the memory block forms flash cell, the structure of formed flash cell is identical.
5. the formation method of semiconductor device according to claim 1, it is characterized in that, described Semiconductor substrate also has logic area, when the word line layer surface of described capacitive region forms dielectric layer, semiconductor substrate surface at logic area forms dielectric layer, when the dielectric layer surface of described capacitive region forms electrode layer, dielectric layer surface at logic area forms electrode layer, the dielectric layer of described logic area is as the gate dielectric layer of logic transistor, and the electrode layer of described logic area is as the grid layer of logic transistor.
6. as the formation method of semiconductor device as described in the claim 5, it is characterized in that, after the semiconductor substrate surface of logic area forms electrode layer, form side wall at the dielectric layer of described logic area and the semiconductor substrate surface of electrode layer both sides, in the Semiconductor substrate of described electrode layer and side wall both sides, form source region and drain region.
7. the formation method of semiconductor device according to claim 1 is characterized in that having fleet plough groove isolation structure in the Semiconductor substrate of described capacitive region, forms described flash cell on described fleet plough groove isolation structure surface.
8. the formation method of semiconductor device according to claim 1 is characterized in that having well region in the Semiconductor substrate of described capacitive region, forms flash cell on described well region surface.
9. the formation method of semiconductor device according to claim 1 is characterized in that the material of described tunnel oxide and dielectric layer is a silica, and the material of described word line layer and electrode layer is a polysilicon, and the material of described conductive plunger is copper, tungsten or aluminium.
10. the semiconductor device that forms of each method in employing such as the claim 1 to 9 is characterized in that, comprising: Semiconductor substrate, and described Semiconductor substrate has capacitive region; Be positioned at the flash cell of the semiconductor substrate surface of described capacitive region, described flash cell comprises: the word line layer that is positioned at the tunnel oxide of semiconductor substrate surface and is positioned at described tunnel oxide laminar surface; Be positioned at the dielectric layer on described word line layer surface; Be positioned at the electrode layer on described dielectric layer surface; The conductive plunger that is electrically connected with word line layer and electrode layer respectively.
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