CN112908857A - Method for manufacturing semiconductor device - Google Patents
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- CN112908857A CN112908857A CN202110258208.3A CN202110258208A CN112908857A CN 112908857 A CN112908857 A CN 112908857A CN 202110258208 A CN202110258208 A CN 202110258208A CN 112908857 A CN112908857 A CN 112908857A
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- 238000000034 method Methods 0.000 title claims abstract description 70
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims description 28
- 150000004767 nitrides Chemical class 0.000 claims abstract description 87
- 230000008569 process Effects 0.000 claims abstract description 39
- 238000005530 etching Methods 0.000 claims abstract description 19
- 230000005641 tunneling Effects 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 18
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 14
- 230000008878 coupling Effects 0.000 claims description 12
- 238000010168 coupling process Methods 0.000 claims description 12
- 238000005859 coupling reaction Methods 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 125000006850 spacer group Chemical group 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 abstract description 12
- 238000001312 dry etching Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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Abstract
The invention provides a preparation method of a semiconductor device, which comprises the following steps: first, a first groove is formed, and then a second nitride layer which is located on the side wall of the first groove and at least extends from the side wall of the inter-gate dielectric layer to the side wall of a part of the first nitride layer is formed. And removing the floating gate layer exposed from the bottom wall of the first groove to form a second groove in the floating gate layer. And laterally etching the second nitride layer to thin the second nitride layer so that the bottom of the second nitride layer can expose the top corner of part of the floating gate layer. And forming a tunneling dielectric layer and covering at least the exposed surface of the floating gate layer in the second groove. Finally, word lines are formed to fill the first trenches and the second trenches. Therefore, the corner of the floating gate is formed without separately forming an oxide layer, and the corner can be formed only by thinning the second nitride layer. The erasing performance of the device can be improved by increasing the relative coverage area between the floating gate layer and the word line, the preparation process is simplified, the process is simple, and the time cost and the economic cost are reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a preparation method of a semiconductor device.
Background
Currently, flash memory has been widely used as the best choice for non-volatile memory applications due to its advantages of high density, low price, electrical programmability, etc. The erase capability of flash memory is always one of the important parameters for determining the quality of flash memory. Generally, in the erasing process, high and low voltages are applied to the word line and the control gate in the flash memory, so that a high potential difference and an electric field strength are formed between the floating gate and the word line, electrons stored in the floating gate tunnel through the tunneling oxide layer, and the potential on the floating gate changes from negative to positive, thereby changing the storage state, i.e. realizing the transition between "0" and "1". Indeed, it is readily understood by those skilled in the art that the relative coverage area of the floating gate layer and the word line has some effect on the erase field strength. The larger the relative coverage area, the stronger the electric field intensity generated at the time of erasing.
Therefore, in order to improve the erasing performance of the flash memory, in the existing preparation process, before the floating gate layer is etched, an oxide layer is firstly formed, and then a protective oxide layer side wall is formed by dry etching so as to cover a part of the floating gate layer. And etching the floating gate layer, and removing the formed oxide layer side wall, so that the covered part of the floating gate layer is exposed, and a corner of the floating gate layer is formed. Therefore, the relative coverage area of the corner of the floating gate layer and the word line is far larger than that of the floating gate layer and the word line in a vertical mode, so that the electric field intensity is enhanced and the erasing capacity is improved during erasing.
However, as the critical dimension of the semiconductor device is gradually reduced and the performance requirement of the semiconductor device is higher and higher, the improved method of increasing the thickness of the oxide layer to further enlarge the relative coverage area between the corner of the floating gate layer and the word line not only increases the process difficulty and reduces the yield, but also increases the time cost and the economic cost.
Therefore, a new method for manufacturing a semiconductor device is needed to increase the relative coverage area between the corner of the floating gate layer and the word line, improve the erasing performance of the flash memory, and reduce the time cost and the economic cost.
Disclosure of Invention
The invention aims to provide a preparation method of a semiconductor device, which aims to solve at least one problem of how to improve the erasing performance of a flash memory, how to reduce the process complexity and how to reduce the time cost and the economic cost.
In order to solve the above technical problem, the present invention provides a method for manufacturing a semiconductor device, including:
providing a semiconductor substrate, wherein a floating gate layer, an inter-gate dielectric layer, a control gate layer and a first nitride layer are sequentially formed on the substrate;
forming a first groove, wherein the first groove sequentially penetrates through the first nitride layer, the control gate layer and the inter-gate dielectric layer and exposes the top surface of the floating gate layer;
forming a second nitride layer, wherein the second nitride layer is positioned on the side wall of the first groove and at least extends from the side wall of the inter-gate dielectric layer to the side wall of a part of the first nitride layer;
removing the floating gate layer exposed from the bottom wall of the first groove to form a second groove in the floating gate layer, wherein the first groove is communicated with the second groove;
performing lateral etching on the second nitride layer to thin the second nitride layer so that the bottom of the second nitride layer can expose part of the top corner of the floating gate layer;
forming a tunneling dielectric layer at least covering the exposed surface of the floating gate layer in the second groove;
forming a word line filling the first trench and the second trench.
Optionally, in the method for manufacturing a semiconductor device, the thickness range of the second nitride layer is as follows: 400 angstroms to 600 angstroms.
Optionally, in the preparation method of the semiconductor device, a wet etching process is used to laterally etch the second nitride layer; the adopted etching liquid comprises phosphoric acid, and the temperature range of the phosphoric acid is 140-170 ℃.
Optionally, in the preparation method of the semiconductor device, after the second nitride layer is laterally etched, the thickness range of the remaining second nitride layer is as follows: 200 angstroms to 400 angstroms.
Optionally, in the method for manufacturing a semiconductor device, after the second trench is formed and before the second nitride layer is laterally etched, the method for manufacturing a semiconductor device further includes: performing a rapid thermal oxidation process on inner walls of the first trench and the second trench; wherein the process temperature is as follows: 750-950 ℃ and 5-15 seconds of process time.
Optionally, in the method for manufacturing a semiconductor device, before forming the first trench, the method for manufacturing a semiconductor device further includes:
forming a third groove which penetrates through the first nitride layer and exposes the top surface of the control grid layer;
forming an oxide layer, wherein the oxide layer covers the inner wall of the third groove and the upper surface of the first nitride layer;
and etching the oxide layer by adopting a dry method to form an oxide layer side wall, wherein the oxide layer side wall covers the side wall of the third groove.
Optionally, in the preparation method of the semiconductor device, after the oxide layer sidewall is formed, the control gate layer exposed from the bottom wall of the third trench and the inter-gate dielectric layer below the control gate layer are removed to form the first trench.
Optionally, in the preparation method of the semiconductor device, the second nitride layer covers the sidewalls of the oxide layer sidewall, the sidewalls of the control gate layer and the sidewalls of the inter-gate dielectric layer, which are exposed.
Optionally, in the preparation method of the semiconductor device, the tunneling dielectric layer is formed by a thermal oxidation process or a floating gate sidewall process, and a process temperature for forming the tunneling dielectric layer is 900-1200 ℃.
Optionally, in the method for manufacturing a semiconductor device, the provided semiconductor substrate further includes a coupling oxide layer; the coupling oxide layer is formed between the floating gate layer and the substrate, and the inter-gate dielectric layer is an ONO (oxide-nitride-oxide) film layer formed by stacking silicon oxide, silicon nitride and silicon oxide; the second groove penetrates through the floating gate layer and the coupling oxide layer in sequence.
In summary, the present invention provides a method for manufacturing a semiconductor device, including: providing a semiconductor substrate, and sequentially forming a floating gate layer, an inter-gate dielectric layer, a control gate layer and a first nitride layer on the substrate. And forming a first groove, wherein the first groove sequentially penetrates through the first nitride layer, the control gate layer and the inter-gate dielectric layer and exposes out of the top surface of the floating gate layer. And forming a second nitride layer which is positioned on the side wall of the first groove and at least extends from the side wall of the inter-gate dielectric layer to the side wall of part of the first nitride layer. And removing the floating gate layer exposed from the bottom wall of the first groove to form a second groove in the floating gate layer, wherein the first groove is communicated with the second groove. And laterally etching the second nitride layer to thin the second nitride layer, so that the bottom of the second nitride layer can expose part of the top corner of the floating gate layer. And forming a tunneling dielectric layer which at least covers the exposed surface of the floating gate layer in the second groove. Forming a word line filling the first trench and the second trench. Therefore, the corner of the floating gate is formed without separately forming an oxide layer, and the corner can be formed only by thinning the second nitride layer. The erasing performance of the device can be improved by increasing the relative coverage area between the floating gate layer and the word line, the preparation process is simplified, the process is simple, and the time cost and the economic cost are reduced.
Drawings
Fig. 1 is a flowchart of a method of manufacturing a semiconductor device of an embodiment of the present invention;
FIGS. 2-10 are schematic diagrams of semiconductor structures at various steps of an embodiment of the present invention;
wherein the reference numerals are:
100-a substrate; 101-a coupling oxide layer; 102-a floating gate layer; 103-an inter-gate dielectric layer; 104-a control gate layer; 105-a first nitride layer; 106-oxide layer side wall; 107-a second nitride layer; 108-tunneling oxide layer; 109-word lines; p1-first trench; p2-second trench; p3-third trench; m-a corner of the floating gate layer; the corners of the N-tunnel oxide layer.
Detailed Description
To further clarify the objects, advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is to be noted that the drawings are in greatly simplified form and are not to scale, but are merely intended to facilitate and clarify the explanation of the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently. It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.
In order to solve the above technical problem, the present embodiment provides a method for manufacturing a semiconductor device, referring to fig. 1, the method for manufacturing a semiconductor device includes:
step one S10: providing a semiconductor substrate, and sequentially forming a floating gate layer, an inter-gate dielectric layer, a control gate layer and a first nitride layer on the substrate.
Step two S20: and forming a first groove, wherein the first groove sequentially penetrates through the first nitride layer, the control gate layer and the inter-gate dielectric layer and exposes out of the top surface of the floating gate layer.
Step three S30: and forming a second nitride layer which is positioned on the side wall of the first groove and at least extends from the side wall of the inter-gate dielectric layer to the side wall of part of the first nitride layer.
Step four S40: and removing the floating gate layer exposed from the bottom wall of the first groove to form a second groove in the floating gate layer, wherein the first groove is communicated with the second groove.
Step five S50: and laterally etching the second nitride layer to thin the second nitride layer, so that the bottom of the second nitride layer can expose part of the top corner of the floating gate layer.
Step six S60: and forming a tunneling dielectric layer which at least covers the exposed surface of the floating gate layer in the second groove.
Step seven S70: forming a word line filling the first trench and the second trench.
The method for manufacturing the semiconductor device will be described in detail below with reference to fig. 2 to 10.
Step one S10: referring to fig. 2-4, a semiconductor substrate 100 is provided, wherein a floating gate layer 102, an inter-gate dielectric layer 103, a control gate layer 104 and a first nitride layer 105 are sequentially formed on the substrate 100.
Referring to fig. 2, the semiconductor structure further includes: a coupling oxide layer 101, wherein the coupling oxide layer 101 is formed between the floating gate layer 102 and the substrate 100. The inter-gate dielectric layer 103 is an ONO film layer formed by stacking silicon oxide, silicon nitride and silicon oxide. That is, the coupling oxide layer 101, the floating gate layer 102, the inter-gate dielectric layer 103, the control gate layer 104, and the first nitride layer 105 are sequentially formed on the substrate 100.
Referring to fig. 3-4, the first nitride layer 105 is etched by a dry etching process or a wet etching process to form a third trench P3, wherein the third trench P3 penetrates through the first nitride layer 105. After the third trench P3 is formed, an oxide layer (not shown) is formed to cover the inner wall of the third trench P3 and the upper surface of the first nitride layer 105. And then, dry etching the oxide layer to form an oxide layer sidewall spacer 106, wherein the oxide layer sidewall spacer 106 covers the sidewall of the third trench P3.
Forming an oxide layer sidewall spacer 106, wherein the oxide layer sidewall spacer 106 covers the sidewall of the third trench P3. The first nitride layer 105 includes silicon nitride, and the oxide layer sidewall 106 includes silicon oxide.
Step two S20: referring to fig. 5, a first trench P1 is formed, and the first trench P1 penetrates through the first nitride layer 105, the control gate layer 104 and the inter-gate dielectric layer 103 in sequence and exposes the top surface of the floating gate layer 102.
The first trench P1 may be etched by a wet etching process or a dry etching process. After the oxide layer spacers 106 are formed, the control gate layer 104 exposed from the bottom wall of the third trench P3 is removed, and then the inter-gate dielectric layer 103 is further extension etched to expose a portion of the floating gate layer 102, so as to form the first trench P1. That is, the first trench P1 is formed by extension etching of the third trench P3.
Step three S30: referring to fig. 6, a second nitride layer 107 is formed, wherein the second nitride layer 107 is located on the sidewall of the first trench P1 and extends from the sidewall of the inter-gate dielectric layer 103 to a portion of the sidewall of the first nitride layer 105. That is, the second nitride layer 107 covers the sidewalls of the oxide layer spacers 106, the sidewalls of the control gate layer 104 and the sidewalls of the inter-gate dielectric layer 103, which are exposed.
Wherein the thickness range of the second nitride layer 107 is formed as follows: 400 angstroms to 600 angstroms. Optionally 400 angstroms, 500 angstroms or 600 angstroms. In this embodiment, the thickness of the second nitride layer 107 is thicker than the normal isolation thickness required by the semiconductor device, and the purpose is to expose the corner of the floating gate layer 102 by thinning the second nitride layer 107, so as to increase the relative coverage area between the floating gate layer 102 and the word line 109 (shown in fig. 10 in the subsequent formation), and further enhance the electric field strength during erasing, so as to improve the erasing performance of the device. Compared with the prior art, the process links of growing the oxide layer, forming the oxide layer protection side wall by etching and subsequently removing the oxide layer protection side wall are saved, and the economic cost is reduced. And the time spent on growing the oxide layer by adopting the furnace tube process is far more than the time spent on forming the thickened second nitride layer 107 in the embodiment, so that the time cost for preparing the device is saved.
Step four S40: referring to fig. 7, the floating gate layer 102 exposed from the bottom wall of the first trench P1 is removed to form a second trench P2 in the floating gate layer 102, and the first trench P1 is communicated with the second trench P2.
The second nitride layer 107 covers the side wall of the first trench P1 in the form of a side wall, so that a part of the floating gate layer 102 is exposed from the bottom wall of the first trench P1, and the floating gate layer 102 and the coupling oxide layer 101 are sequentially etched in an extending manner by using a wet etching process or a dry etching process. To form the second trench P2. The second trench P2 penetrates through the floating gate layer 102 and the coupling oxide layer 101 and exposes a portion of the substrate 100.
Step five S50: referring to fig. 8, the second nitride layer 107 is laterally etched to thin the second nitride layer 107, so that the bottom of the second nitride layer 107 can expose a portion of the top corner M of the floating gate layer 102.
After forming the second trench P2 and before performing lateral etching on the second nitride layer 107, the method for manufacturing a semiconductor device according to this embodiment further includes: a rapid thermal oxidation process is performed on the inner walls of the first and second trenches P1 and P2 to form a thin oxide layer (not shown). The oxide layer covers the exposed top surface of the floating gate layer 102 to protect the topography of the top surface of the floating gate layer 102, and certain influence of etching liquid hot phosphoric acid on the top surface of the floating gate layer 102 is avoided when the second nitride layer 107 is subjected to lateral etching in the subsequent process. Thus, performing the rapid thermal oxidation process can form a better corner M profile (as shown in FIG. 8). Further, the temperature of the rapid thermal oxidation process is as follows: 750-950 ℃ and 5-15 seconds of process time.
Further, a wet etching process is used to selectively etch the second nitride layer 107 laterally. And the adopted etching solution comprises phosphoric acid, and the temperature range of the phosphoric acid is 140-170 ℃, so that the etching speed of the second nitride layer 107 is about 50 angstroms per minute. Further, after removing a part of the thickness of the second nitride layer 107, the thickness of the remaining second nitride layer 107 ranges from: 200-400 angstroms, and optionally 200, 300 or 400 angstroms, to satisfy the function of isolating the word line from other layers. In this range, the exposed area of the corner M of the floating gate layer 102 can be controlled by retaining a greater or lesser thickness of the second nitride layer 107, thereby satisfying various requirements of the device for erasing performance. When the exposed area of the corner M of the floating gate layer 102 is large, that is, the remaining second nitride layer 107 is thin, the erasing performance is strong; when the exposed area of the corner M of the floating gate layer 102 is small, i.e., the remaining second nitride layer 107 is thick, the erasing performance is weak.
Therefore, in this example, the corner M of the floating gate layer 102 can be exposed only by reducing the thickness of the second nitride layer 107, so as to enhance the device erasing capability, and not only the process complexity is low, the product yield can be ensured, but also the time cost and the economic cost are reduced.
Step six S60: referring to fig. 9, a tunnel dielectric layer 108 is formed, wherein the tunnel dielectric layer 108 at least covers the exposed surface of the floating gate layer 102 in the second trench P2.
The tunnel dielectric layer 108 is used to separate the floating gate layer 102 and the word line (as shown in fig. 10). The tunnel oxide layer 108 is formed by a thermal oxidation process or a floating gate sidewall process, and the process temperature for forming the tunnel dielectric layer 108 is 900-1200 ℃. The tunnel oxide layer 108 covers sidewalls of the first trench P1 and the second trench P2, and a bottom wall of the second trench P2. And a corner N of the tunnel oxide layer 108 is formed at a corner M of the floating gate layer 102. That is, the tunnel oxide layer 108 forms a corner N along the contour of the corner M of the floating gate layer 102 to ensure the required coverage area of the floating gate layer 102 and the word line 109.
Step seven S70: referring to fig. 10, a word line 109 is formed, and the word line 109 fills the first trench P1 and the second trench P2.
After the tunnel oxide layer 108 is formed, the word line 109 is formed on the tunnel oxide layer 108, and the word line 109 covers a corner N of the tunnel oxide layer 108. The material of the word line 109 includes polysilicon, and the word line 109 is formed to cover the top surface of the first nitride layer 105, and the top surface of the word line 109 is made flush with the top surface of the first nitride layer 105 by a chemical mechanical polishing process. Further, an oxide layer is formed on the top surface of the word line 109 by a thermal oxidation process to protect the word line 109. The subsequent manufacturing process is a process step well known to those skilled in the art and will not be described herein.
In summary, the method for manufacturing the semiconductor device provided in this embodiment does not need to separately form a sacrificial oxide layer sidewall to form the corner of the floating gate 102, and can be implemented by only thinning the second nitride layer 107. The erasing performance of the device can be improved by increasing the relative coverage area between the floating gate layer 102 and the word line 109, the preparation process is simplified, the process is simple, and the time cost and the economic cost are reduced.
It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
Claims (10)
1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, wherein a floating gate layer, an inter-gate dielectric layer, a control gate layer and a first nitride layer are sequentially formed on the substrate;
forming a first groove, wherein the first groove sequentially penetrates through the first nitride layer, the control gate layer and the inter-gate dielectric layer and exposes the top surface of the floating gate layer;
forming a second nitride layer, wherein the second nitride layer is positioned on the side wall of the first groove and at least extends from the side wall of the inter-gate dielectric layer to the side wall of a part of the first nitride layer;
removing the floating gate layer exposed from the bottom wall of the first groove to form a second groove in the floating gate layer, wherein the first groove is communicated with the second groove;
performing lateral etching on the second nitride layer to thin the second nitride layer so that the bottom of the second nitride layer can expose part of the top corner of the floating gate layer;
forming a tunneling dielectric layer at least covering the exposed surface of the floating gate layer in the second groove;
forming a word line filling the first trench and the second trench.
2. The method according to claim 1, wherein the second nitride layer is formed to have a thickness in a range of: 400 angstroms to 600 angstroms.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the second nitride layer is laterally etched by a wet etching process; the adopted etching liquid comprises phosphoric acid, and the temperature range of the phosphoric acid is 140-170 ℃.
4. The method for manufacturing a semiconductor device according to claim 1, wherein after the lateral etching of the second nitride layer, the thickness of the remaining second nitride layer ranges from: 200 angstroms to 400 angstroms.
5. The method for manufacturing a semiconductor device according to claim 1, wherein after the forming of the second trench and before the performing of the lateral etching on the second nitride layer, the method further comprises: performing a rapid thermal oxidation process on inner walls of the first trench and the second trench; wherein the process temperature is as follows: 750-950 ℃ and 5-15 seconds of process time.
6. The method for manufacturing a semiconductor device according to claim 1, wherein before the forming of the first trench, the method for manufacturing a semiconductor device further comprises:
forming a third groove which penetrates through the first nitride layer and exposes the top surface of the control grid layer;
forming an oxide layer, wherein the oxide layer covers the inner wall of the third groove and the upper surface of the first nitride layer;
and etching the oxide layer by adopting a dry method to form an oxide layer side wall, wherein the oxide layer side wall covers the side wall of the third groove.
7. The method of claim 6, wherein after the formation of the oxide layer sidewall spacers, the control gate layer exposed from the bottom wall of the third trench and the inter-gate dielectric layer under the control gate layer are removed to form the first trench.
8. The method for manufacturing the semiconductor device according to claim 6, wherein the second nitride layer covers sidewalls of the oxide layer sidewall and sidewalls of the exposed control gate layer and sidewalls of the inter-gate dielectric layer.
9. The method for manufacturing a semiconductor device according to claim 1, wherein the tunnel dielectric layer is formed by a thermal oxidation process or a floating gate sidewall process, and a process temperature for forming the tunnel dielectric layer is 900-1200 ℃.
10. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate further comprises a coupling oxide layer; the coupling oxide layer is formed between the floating gate layer and the substrate, and the inter-gate dielectric layer is an ONO (oxide-nitride-oxide) film layer formed by stacking silicon oxide, silicon nitride and silicon oxide; the second groove penetrates through the floating gate layer and the coupling oxide layer in sequence.
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