CN102543716A - Method for forming salicide block layer - Google Patents
Method for forming salicide block layer Download PDFInfo
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- CN102543716A CN102543716A CN2012100610751A CN201210061075A CN102543716A CN 102543716 A CN102543716 A CN 102543716A CN 2012100610751 A CN2012100610751 A CN 2012100610751A CN 201210061075 A CN201210061075 A CN 201210061075A CN 102543716 A CN102543716 A CN 102543716A
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- layer
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- metal silicide
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- blocking layer
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Abstract
The invention relates to a method for forming a salicide block layer. The method comprises the following steps of: providing a substrate, wherein an isolation structure is arranged in the substrate, a first gate structure and a second gate structure are arranged on the surfaces of the substrate on two sides of the isolation structure respectively, and a light doping source and drain injection region is formed in the substrate on the two sides of the first gate structure; depositing a silicon rich oxide (SRO) layer; performing ion implantation on the two sides of the first gate structure so as to form a heavy doping source and drain injection region; depositing a silane layer; coating photoresist, and photoetching to form a first window, wherein an area of the first gate structure is exposed from the first window; removing the silane layer from the first window by dry etching; removing the SRO layer from the first window by wet etching; and removing the photoresist. Due to the adoption of the salicide block layer with the SRO layer and the silane layer, the SRO has a higher extinction coefficient compared with silica, and damage of plasma ultraviolet light to the substrate can be reduced; and therefore, the uniformity of threshold voltage is improved.
Description
Technical field
The present invention relates to semiconductor applications, particularly a kind of formation method of blocking layer of metal silicide.
Background technology
Make very lagre scale integrated circuit (VLSIC) in the Self-Aligned Refractory silicide process, most active areas are covered by low-resistance refractory metal silicide.But the zone that has; For example high resistance polysilicon can not have refractory metal silicide with the isolation active area; These zones need barrier layer protected in silicide process, need earlier in this section the zone form blocking layer of metal silicide (salicide block layer, SAB); The characteristic of utilizing blocking layer of metal silicide can not react with metals such as titanium or cobalts is to prevent forming metal silicide in the subregion.
In the very lagre scale integrated circuit (VLSIC) manufacturing process, refractory metal such as titanium, cobalt, nickel often are used as the generation silicide.Simultaneously, silicon dioxide and silylation layer are widely used in the barrier layer.The formation method of prior art blocking layer of metal silicide may further comprise the steps: shown in Fig. 1 a; One substrate 100 is provided; Have isolation structure 101 in the said substrate 100 and be used to isolate adjacent device cell; Said isolation structure 101 both sides are respectively first grid structure 102 and second grid structure 103, have lightly-doped source in the substrate of said first grid structure 102 both sides and leak injection region 104; The side wall 1033 that the side wall 1023 that said first grid structure 102 comprises grid oxic horizon 1021, is positioned at the polysilicon gate 1022 on the grid oxic horizon 1021 and is positioned at the polysilicon gate both sides, second grid structure 103 comprise grid oxic horizon 1031, are positioned at the polysilicon gate 1032 on the grid oxic horizon 1031 and are positioned at the polysilicon gate both sides; Shown in Fig. 1 b, deposition one silicon dioxide layer 105 on substrate 100, the step of said deposition of silica layer 105 adopts N2O and SiH4 as reacting gas, and the volume ratio of said N2O and SiH4 is 15: 1; Shown in Fig. 1 c, ion is carried out in first grid structure 102 both sides inject, form heavy-doped source and leak injection region 106, and carry out rapid thermal treatment; Shown in Fig. 1 d, deposit a silylation layer 107; Shown in Fig. 1 e, apply photoresist 108, photoetching forms the first window 108a, and the heavy-doped source that exposes said first grid structure 102 and both sides thereof in the said first window 108a leaks injection region 106; Shown in Fig. 1 f, dry etching is removed the silylation layer 107 in the first window 108a; Shown in Fig. 1 g, wet etching is removed the silica 1 05 in the first window 108a, shown in Fig. 1 h, removes photoresist 108, forms the blocking layer of metal silicide structure of being made up of silicon dioxide layer 105 and silylation layer 107.
There is high-frequency ac voltage in silicon dioxide in the blocking layer of metal silicide in the reaction chamber in the plasma etch process of dry etching, minority carrier generation speed does not catch up with change in voltage in the substrate, and device is in dark spent condition.Shown in Fig. 1 i; With PMOS is example, and the ultraviolet ray excited electron-hole pair of plasma generation injects to grid oxic horizon under AC field, finally makes the hole be captured in the grid oxic horizon; Thereby cause the PMOS threshold voltage to become big, and threshold voltage is inhomogeneous.
Summary of the invention
The formation method that the purpose of this invention is to provide a kind of blocking layer of metal silicide is to improve the uniformity of threshold voltage.
Technical solution of the present invention is a kind of formation method of blocking layer of metal silicide, may further comprise the steps:
One substrate is provided, has isolation structure in the said substrate, be formed with first grid structure and second grid structure on the substrate surface of said isolation structure both sides respectively, have lightly-doped source in the substrate of said first grid structure both sides and leak the injection region;
Deposition silicon rich silicon dioxide layer on substrate;
Ion is carried out in first grid structure both sides inject, form heavy-doped source and leak the injection region, and carry out rapid thermal treatment;
Deposit a silylation layer;
Apply photoresist, photoetching forms first window, and the heavy-doped source that exposes said first grid structure and both sides thereof in said first window leaks the injection region;
Dry etching is removed the silylation layer in first window;
Wet etching is removed the silicon rich silicon dioxide layer in first window;
Remove photoresist, form the blocking layer of metal silicide structure.
As preferably: the step of said deposition silicon rich silicon dioxide layer adopts N
2O and SiH
4As reacting gas.
As preferably: said N
2O and SiH
4Flow-rate ratio be 8.1: 1-8.5: 1.
As preferably: the thickness of said silicon rich silicon dioxide layer is the 315-385 dust.
As preferably: the thickness of said silylation layer is 1200 dusts.
As preferably: the step of said dry etching silylation layer adopts CF gas.
As preferably: said wet etching silicon rich silicon dioxide layer adopts HF solution.
Compared with prior art; The present invention adopts the blocking layer of metal silicide of ground floor silicon rich silicon dioxide layer and second layer silylation layer; The silicon dioxide that said silicon rich silicon dioxide is compared prior art has than high extinction coefficient; Can reduce the influence of dry etching process ionic medium body ultraviolet ray (Plasma UV), therefore can effectively stop plasma damage, improve the uniformity of threshold voltage substrate.
Description of drawings
Fig. 1 a-1h is the profile of each processing step in the prior art blocking layer of metal silicide formation method.
Fig. 1 i is the sketch map of prior art blocking layer of metal silicide in dry etching.
Fig. 2 is the process chart of blocking layer of metal silicide formation method of the present invention.
Fig. 3 a-3h is the profile of each processing step in the blocking layer of metal silicide formation method of the present invention.
Embodiment
The present invention below will combine accompanying drawing to do further to detail:
A lot of details have been set forth in the following description so that make much of the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention does not receive the restriction of following disclosed practical implementation.
Secondly, the present invention utilizes sketch map to be described in detail, when the embodiment of the invention is detailed; For ease of explanation; The profile of expression device architecture can be disobeyed general ratio and done local the amplification, and said sketch map is instance, and it should not limit the scope of the present invention's protection at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 2 shows the process chart of blocking layer of metal silicide formation method of the present invention
See also shown in Figure 2, in the present embodiment,
In step 201; Shown in Fig. 3 a; One substrate 300 is provided; Have isolation structure 301 in the said substrate 300, be formed with first grid structure 302 and second grid structure 303 on the substrate surface of said isolation structure 301 both sides respectively, said first grid structure 302 both sides have lightly-doped source and leak injection region 304; The side wall 3023 that said first grid structure 302 comprises grid oxic horizon 3021, is positioned at the polysilicon gate 3022 on the grid oxic horizon 3021 and is positioned at the grid both sides; The side wall 3033 that said second grid structure 303 comprises grid oxic horizon 3031, is positioned at the polysilicon gate 3032 on the grid oxic horizon 3031 and is positioned at the grid both sides; Said first grid for example can be a control gate, and said second grid for example can be a floating boom;
In step 202, shown in Fig. 3 b, deposition silicon rich silicon dioxide layer on substrate 300 (silicon rich oxide, SRO) 305, the step of said deposition silicon rich silicon dioxide layer 305 adopts N
2O and SiH
4As reacting gas, said N
2O and SiH
4Flow-rate ratio be 8.1: 1-8.5: 1, in the present embodiment, said N
2O and SiH
4Flow-rate ratio be 8.3: 1, the thickness of said silicon rich silicon dioxide layer 305 is the 315-385 dust;
In step 203, shown in Fig. 3 c, ion is carried out in first grid structure 302 both sides inject, form heavy-doped source and leak injection region 306, and carry out rapid thermal treatment;
In step 204, shown in Fig. 3 d, deposit a silylation layer 307, the thickness of said silylation layer 307 is 1200 dusts;
In step 205, shown in Fig. 3 e, apply photoresist 308, photoetching forms the first window 308a, and the heavy-doped source that exposes said first grid structure 302 and both sides thereof in the said first window 308a leaks injection region 306; The zone that 308 region covered of graphical back photoresist are high resistant requires its surface can not form metal silicide, for this reason, needs on this zone, to form blocking layer of metal silicide;
In step 206, shown in Fig. 3 f, dry etching is removed the silylation layer 307 in the first window 308a, and the step of said dry etching silylation layer 307 adopts CF gas;
Compared with prior art; The present invention adopts the blocking layer of metal silicide of ground floor silicon rich silicon dioxide layer 305 and second layer silylation layer 307; Said silicon rich silicon dioxide is compared silicon dioxide and is had than high extinction coefficient; Can reduce the influence of dry etching process ionic medium body ultraviolet ray (Plasma UV), therefore can effectively stop plasma damage, improve the uniformity of threshold voltage substrate.
In step 207, shown in Fig. 3 g, wet etching is removed the silicon rich silicon dioxide layer 305 in the first window 308a, and said wet etching silicon rich silicon dioxide layer 305 adopts HF solution.
In step 208, shown in Fig. 3 h, remove photoresist 308, obtain the blocking layer of metal silicide structure of silicon rich silicon dioxide layer 305 and silylation layer 307 compositions.
The above is merely preferred embodiment of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to the covering scope of claim of the present invention.
Claims (7)
1. the formation method of a blocking layer of metal silicide is characterized in that, may further comprise the steps:
One substrate is provided, has isolation structure in the said substrate, be formed with first grid structure and second grid structure on the substrate surface of said isolation structure both sides respectively, have lightly-doped source in the substrate of said first grid structure both sides and leak the injection region;
Deposition silicon rich silicon dioxide layer on substrate;
Ion is carried out in first grid structure both sides inject, form heavy-doped source and leak the injection region, and carry out rapid thermal treatment;
Deposit a silylation layer;
Apply photoresist, photoetching forms first window, and the heavy-doped source that exposes said first grid structure and both sides thereof in said first window leaks the injection region;
Dry etching is removed the silylation layer in first window;
Wet etching is removed the silicon rich silicon dioxide layer in first window;
Remove photoresist, form the blocking layer of metal silicide structure.
2. the formation method of blocking layer of metal silicide according to claim 1 is characterized in that: the step employing N of said deposition silicon rich silicon dioxide layer
2O and SiH
4As reacting gas.
3. the formation method of blocking layer of metal silicide according to claim 2 is characterized in that: said N
2O and SiH
4Flow-rate ratio be 8.1: 1-8.5: 1.
4. the formation method of blocking layer of metal silicide according to claim 1, it is characterized in that: the thickness of said silicon rich silicon dioxide layer is the 315-385 dust.
5. the formation method of blocking layer of metal silicide according to claim 1, it is characterized in that: the thickness of said silylation layer is 1200 dusts.
6. the formation method of blocking layer of metal silicide according to claim 1 is characterized in that: the step employing CF gas of said dry etching silylation layer.
7. the formation method of blocking layer of metal silicide according to claim 1 is characterized in that: said wet etching silicon rich silicon dioxide layer employing HF solution.
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| CN201210061075.1A CN102543716B (en) | 2012-03-09 | 2012-03-09 | The forming method of blocking layer of metal silicide |
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| CN201210061075.1A CN102543716B (en) | 2012-03-09 | 2012-03-09 | The forming method of blocking layer of metal silicide |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8956937B2 (en) | 2013-03-14 | 2015-02-17 | Shanghai Huali Microelectronics Corporation | Method of depositing the metal barrier layer comprising silicon dioxide |
| CN110534499A (en) * | 2019-09-29 | 2019-12-03 | 武汉新芯集成电路制造有限公司 | Semiconductor devices and preparation method thereof |
| CN115377012A (en) * | 2021-05-21 | 2022-11-22 | 北方集成电路技术创新中心(北京)有限公司 | Method for forming semiconductor structure |
| CN115720479A (en) * | 2022-11-23 | 2023-02-28 | 惠科股份有限公司 | Quantum dot layer preparation method and display panel |
| CN115377012B (en) * | 2021-05-21 | 2024-04-19 | 北方集成电路技术创新中心(北京)有限公司 | Method for forming semiconductor structure |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6207514B1 (en) * | 1999-01-04 | 2001-03-27 | International Business Machines Corporation | Method for forming borderless gate structures and apparatus formed thereby |
| US6900104B1 (en) * | 2004-02-27 | 2005-05-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming offset spacer manufacturing for critical dimension precision |
| CN100499147C (en) * | 2006-04-29 | 2009-06-10 | 联华电子股份有限公司 | Image sensing element and method for making the same |
-
2012
- 2012-03-09 CN CN201210061075.1A patent/CN102543716B/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8956937B2 (en) | 2013-03-14 | 2015-02-17 | Shanghai Huali Microelectronics Corporation | Method of depositing the metal barrier layer comprising silicon dioxide |
| CN110534499A (en) * | 2019-09-29 | 2019-12-03 | 武汉新芯集成电路制造有限公司 | Semiconductor devices and preparation method thereof |
| CN115377012A (en) * | 2021-05-21 | 2022-11-22 | 北方集成电路技术创新中心(北京)有限公司 | Method for forming semiconductor structure |
| CN115377012B (en) * | 2021-05-21 | 2024-04-19 | 北方集成电路技术创新中心(北京)有限公司 | Method for forming semiconductor structure |
| CN115720479A (en) * | 2022-11-23 | 2023-02-28 | 惠科股份有限公司 | Quantum dot layer preparation method and display panel |
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| Publication number | Publication date |
|---|---|
| CN102543716B (en) | 2017-03-01 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140504 |
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Effective date of registration: 20140504 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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