CN104916779B - Semiconductor devices, its manufacturing method and its manufacturing device - Google Patents
Semiconductor devices, its manufacturing method and its manufacturing device Download PDFInfo
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- CN104916779B CN104916779B CN201510111838.2A CN201510111838A CN104916779B CN 104916779 B CN104916779 B CN 104916779B CN 201510111838 A CN201510111838 A CN 201510111838A CN 104916779 B CN104916779 B CN 104916779B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 112
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 43
- 239000007789 gas Substances 0.000 claims abstract description 85
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 62
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 33
- 239000001257 hydrogen Substances 0.000 claims abstract description 17
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 17
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 14
- 230000001681 protective effect Effects 0.000 claims description 24
- 230000015572 biosynthetic process Effects 0.000 claims description 22
- 238000011161 development Methods 0.000 claims description 19
- -1 silicon halide Chemical class 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 229910052736 halogen Inorganic materials 0.000 claims description 11
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 8
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 6
- 150000002367 halogens Chemical class 0.000 claims description 4
- 125000005843 halogen group Chemical group 0.000 claims description 3
- 150000002431 hydrogen Chemical class 0.000 claims description 3
- 239000011787 zinc oxide Substances 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims 1
- 229910052731 fluorine Inorganic materials 0.000 abstract description 37
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 32
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 27
- 239000011737 fluorine Substances 0.000 abstract description 23
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 16
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 abstract description 16
- 125000001153 fluoro group Chemical group F* 0.000 abstract description 14
- 230000003071 parasitic effect Effects 0.000 abstract description 8
- 238000002161 passivation Methods 0.000 abstract description 4
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 abstract 1
- 239000010408 film Substances 0.000 description 297
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 22
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 21
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 20
- 238000000034 method Methods 0.000 description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 238000009826 distribution Methods 0.000 description 13
- 238000009616 inductively coupled plasma Methods 0.000 description 12
- 239000000758 substrate Substances 0.000 description 12
- 238000005229 chemical vapour deposition Methods 0.000 description 11
- 238000001259 photo etching Methods 0.000 description 11
- 238000005240 physical vapour deposition Methods 0.000 description 11
- 101100489577 Solanum lycopersicum TFT10 gene Proteins 0.000 description 10
- 238000004380 ashing Methods 0.000 description 10
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 239000011733 molybdenum Substances 0.000 description 9
- 229910052750 molybdenum Inorganic materials 0.000 description 9
- 238000001039 wet etching Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 8
- 230000007547 defect Effects 0.000 description 7
- 238000003860 storage Methods 0.000 description 7
- 239000010936 titanium Substances 0.000 description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 239000004411 aluminium Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 239000003795 chemical substances by application Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 230000037452 priming Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000003384 imaging method Methods 0.000 description 3
- 230000002401 inhibitory effect Effects 0.000 description 3
- 238000009434 installation Methods 0.000 description 3
- 238000003754 machining Methods 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- 238000009489 vacuum treatment Methods 0.000 description 3
- 229910008284 Si—F Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000001687 destabilization Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 210000002858 crystal cell Anatomy 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000003682 fluorination reaction Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 1
- OUUQCZGPVNCOIJ-UHFFFAOYSA-N hydroperoxyl Chemical compound O[O] OUUQCZGPVNCOIJ-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 description 1
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
Abstract
Present invention offer can prevent the characteristic variations of oxide semiconductor and the lesser semiconductor devices of parasitic capacitance, its manufacturing method and its producing device.Have from underlying layer stacked gate electrode (12), in the TFT (10) of lit-par-lit structure made of IGZO film (40) and channel protection film (17), channel protection film is locally removed by that there will be the photoresist mask of the width for the width for reflecting gate electrode (41a) to be used as mask, to make the locally exposure of IGZO film, remaining be partially disposed in of the part of the exposure of IGZO film and channel protection film is mixed from silicon fluoride gas and nitrogen, in the plasma that processing gas without containing hydrogen generates, and the part of the exposure of IGZO film and the remaining part of channel protection film are covered using the passivating film (18) being made of the silicon nitride film containing fluorine, when forming passivating film, fluorine atom self-passivation film is set to spread to the part of the exposure of IGZO film and form source area Domain (15), drain region (16).
Description
Technical field
The present invention relates to semiconductor devices, its manufacturing method and its manufactures that oxide semiconductor is applied to channel to fill
It sets.
Background technique
In the past, in the field of panel display board, LCD element is used mostly, but in recent years, LCD element is not used only,
In order to realize piece display (Japanese: シ ー ト デ ィ ス プ レ イ), next-generation slim TV and promote organic EL
(Electrouminescence) application of element.Organic EL element is the light-emitting component of emissive type, different from liquid crystal cell,
It does not need backlight, therefore can be realized more slim display.
Organic EL element is current drive-type element, in the thin film transistor (TFT) (TFT:Thin for being applied to organic EL element
Film Transistor) in, need to realize the switch motion of high speed, still, now, due to being mainly used as the composition material of channel
The electron mobility of the amorphous silicon of material is not too much high, and therefore, amorphous silicon is not particularly suited for the constituent material of the channel of organic EL.
It is therefore proposed that a kind of oxide semiconductor that will obtain higher electron mobility is applied to the TFT of channel.
As oxide semiconductor used in such TFT, there is known for example by indium (In), gallium (Ga) and zinc (Zn) this three
The IGZO that oxide is constituted is (for example, referring to non-patent literature 1.), even IGZO noncrystalline state, it may have higher electronics moves
Shifting rate is (for example, 10cm2/ (Vs) or more), it therefore, can when the oxide semiconductors such as IGZO to be applied to the channel of TFT
Realize the switch motion of high speed.Technology by oxide semiconductors such as IGZO applied to the channel of TFT, not only for organic EL member
The effect of part is very big, also very big for the effect of LCD element.
In addition, being protected from the damage of extraneous ion, moisture in order to reliably protect channel in TFT, TFT has
The protective film of channel being made of such as silicon nitride (SiN) film etc. is (for example, referring to patent document 1.).In addition, utilize etc. from
Daughter CVD (Chemical Vapor Deposition: chemical vapor deposition) in the case where forming silicon nitride film, is mostly
By silane (SiH4) it is used as silicon source and by ammonia (NH3) it is used as nitrogen source, but silane and ammonia is made to form silicon nitride using plasma
When film, hydroperoxyl radical, hydrogen ion can be entered in silicon nitride film in the form of hydrogen atom, and in general, protective film contains
A large amount of hydrogen atom.
Hydrogen atom contained by protective film can spread to channel and be detached from the oxygen atom in IGZO, to make the spy of IGZO
Property, for example threshold voltage (Vth) change, therefore, study following method: utilize silica (SiO2) film covering channel up and down
Later, the protective film of channel being made of silicon nitride film is formed, the reliability for being heat-treated and improving IGZO is then applied.
Patent document 1: Japan Patent 3148183
Non-patent literature 1: " for realizing the oxide semiconductor TFT of frivolous piece display ", three Pu Itou Kentaros etc. write,
(Japanese: Toshiba レ ビ ュ ー) Vol.67No.1 (2012) comments in Toshiba
Summary of the invention
Problems to be solved by the invention
However, because the residual of hydrogen atom, into or there are the semiconductors of hydrogen atom in silicon nitride film due to other reasons
In device, when IGZO is applied to LCD element, organic EL element, it is difficult to prevent IGZO due to the hydrogen atom in silicon nitride film
Generate characteristic variations.
The object of the present invention is to provide one kind can prevent oxide semiconductor characteristic variations semiconductor devices,
The manufacturing method of semiconductor devices and the manufacturing device of semiconductor devices.
The solution to the problem
In order to realize the purpose, the present invention provides a kind of manufacturing method of semiconductor devices, and the semiconductor devices is by grid
The lit-par-lit structure that electrode, semiconductor film and the insulating film being laminated on the semiconductor film are constituted, the semiconductor film is by aoxidizing
Object semiconductor is constituted, which is characterized in that the manufacturing method of the semiconductor devices the following steps are included: semiconductor film exposure step,
In the semiconductor film exposure step, the insulating film is locally removed and the gate electrode is used as mask, to make
The semiconductor film locally exposure；Protective film forming step makes in the protective film forming step by silicon halide gas and nitrogenous
Made of gas mixing, the processing gas without containing hydrogen generate plasma, at least by the part of the exposure of the semiconductor film
It is placed in the plasma, and cover using the protective film being made of halogen silicon nitride film the exposure of the semiconductor film
The remaining part of part and the insulating film.
In order to realize the purpose, the present invention provides a kind of manufacturing device of semiconductor devices, has by gate electrode, half
The lit-par-lit structure that electrically conductive film and the insulating film being laminated on the semiconductor film are constituted, the semiconductor film is by oxide semiconductor
It constitutes, which is characterized in that locally removed the insulating film and gate electrode is used as mask, thus using by halogen
The protective film that silicon nitride film is constituted covers the part of the exposure of the semiconductor film and the remaining part of the insulating film, should
Halogen silicon nitride film using mixed from silicon halide gas and nitrogenous gas, processing gas without containing hydrogen generates etc.
What gas ions were formed.
In order to realize the purpose, the present invention provides a kind of semiconductor devices, have by gate electrode, semiconductor film and
The lit-par-lit structure that the insulating film being laminated on the semiconductor film is constituted, the semiconductor film are made of oxide semiconductor, special
Sign is that the insulating film is partially removed and makes the semiconductor film locally exposure, the exposure of at least described semiconductor film
Part is covered by protective film, and the concentration for covering the fluorine atom in the part of the exposure of the semiconductor film is higher than in the insulating film
Fluorine atom concentration.
The effect of invention
Using the present invention, the protective film of semiconductor film is covered by being made of halogen silicon nitride film, which is
It is formed using the plasma that processing gas mix from silicon halide gas and nitrogenous gas, without containing hydrogen generates,
Therefore, be able to suppress in protective film and contain hydrogen atom, further, it is possible to using be originated from silicon halide gas, expand into semiconductor film
Scattered halogen atom carrys out the defects of repairing semiconductor film and the stability of characteristics of the oxide semiconductor that makes semiconductor film.
Detailed description of the invention
Fig. 1 is the section view that outlined the structure of TFT of the semiconductor devices as the 1st embodiment of the invention
Figure.
Fig. 2 is the plasma CVD film forming for the manufacturing device that outlined the semiconductor devices as present embodiment
The cross-sectional view of the structure of device.
Fig. 3 is the process chart of the manufacturing method of the TFT of the manufacturing method of the semiconductor devices as present embodiment.
Fig. 4 is the process chart of the manufacturing method of the TFT of the manufacturing method of the semiconductor devices as present embodiment.
Fig. 5 is the cross-sectional view that outlined the structure of the variation of TFT of the semiconductor devices as present embodiment.
Fig. 6 is the section view that outlined the structure of TFT of the semiconductor devices as the 2nd embodiment of the invention
Figure.
Fig. 7 is the process chart of the manufacturing method of the TFT of the manufacturing method of the semiconductor devices as present embodiment.
Fig. 8 is the process chart of the manufacturing method of the TFT of the manufacturing method of the semiconductor devices as present embodiment.
Specific embodiment
Hereinafter, illustrating embodiments of the present invention while referring to attached drawing.
Firstly, bottom gate thin film transistor (TFT) of the explanation as the semiconductor devices of the 1st embodiment of the invention.
Fig. 1 is the cross-sectional view that outlined the structure of TFT of the semiconductor devices as present embodiment.In addition,
In Fig. 1, for convenience, the structure of TFT is not illustrated only, further it is shown that the structure with the TFT portion of terminal manufactured simultaneously is (referring to figure
Middle right side).
In Fig. 1, the multiple TFT10 formed on the substrate 11 include: gate electrode 12, are formed on the substrate 11；Grid are exhausted
Velum 13, covering grid electrode 12；Channel 14 (semiconductor film) is formed on gate insulating film 13 and is made of IGZO；Source electrode
Region 15 and drain region 16, the source region 15 and drain region 16 are respectively formed in the both sides of channel 14；Channel protection film
17 (insulating films) cover channel 14；It is passivated (passivation) film 18 (protective film), the entire channel protection film 17 of covering,
Cover a part of source region 15 and a part of drain region 16；Source wiring 19 is formed on source region 15,
The source wiring 19 is in contact through passivating film 18 with source region 15；Drain electrode distribution 20, be formed in drain region 16 it
On, which is in contact through passivating film 18 with drain region 16；Organic planarization film 21 covers source wiring
19, drain electrode distribution 20；And pixel electrode 22, cover organic planarization film 21.That is, TFT10 has the successively layer from lower section
Lit-par-lit structure made of stacked gate electrode 12, channel 14 and channel protection film 17.
Passivating film 18 is made of the silicon nitride film containing fluorine and is formed a film by using the CVD of plasma, source area
Domain 15 and drain region 16 are made of the IGZO that electric conductivity improves (metallization), and channel 14, the width of channel protection film 17 are anti-
The width of gate electrode 12 is reflected (specifically, the width of channel 14, channel protection film 17 is in the error range of photoetching and gate electrode
12 it is of same size).
Next, plasma CVD film formation device of the explanation as the manufacturing device of the semiconductor devices of present embodiment.
The particularly preferably use when being passivated the film forming of film 18 of this plasma CVD film formation device.
Fig. 2 is the plasma CVD film forming for the manufacturing device that outlined the semiconductor devices as present embodiment
The cross-sectional view of the structure of device.
In Fig. 2, plasma CVD film formation device 23 for example, chamber 24, for substantially framework shape, for holding
Receive the substrate 11 of TFT10 to be formed on；Mounting table 25 is configured at the bottom of the chamber 24 and the upper table in mounting table 25
Substrate 11 is placed on face；ICP antenna 26 is configured in the mode opposite with the mounting table 25 of the inside of chamber 24 in chamber 24
Outside；And window member 27, it constitutes the top of chamber 24 and is arranged between mounting table 25 and ICP antenna 26.
Chamber 24 has exhaust apparatus (not shown), which vacuumizes in chamber 24 and make chamber 24
Inner pressure relief.The window member 27 of chamber 24 is made of dielectric, which separates the inside and outside of chamber 24.
Window member 27 is supported on the side wall of chamber 24 across insulating component (not shown), and window member 27 and chamber 24 be not straight
Contact, from without conducting.In addition, window member 27, which has, can at least cover the substrate 11 for being placed in mounting table 25
The size of whole surface.In addition, window member 27 can also be made of multiple cutting plates.
3 gas introduction ports 28,29,30 are equipped in the side wall of chamber 24, gas introduction port 28 is via gas introduction tube 31
Be connected with silicon halide gas supply part 32 of the configuration in the outside of chamber 24, gas introduction port 29 via gas introduction tube 33 with
It configures the nitrogenous gas supply unit 34 in the outside of chamber 24 to be connected, gas introduction port 30 is via gas introduction tube 35 and configuration
Rare gas supply unit 36 in the outside of chamber 24 is connected.
Silicon halide gas supply part 32 does not contain the halogen of hydrogen atom via gas introduction port 28 to the supply of the inside of chamber 24
SiClx gas, such as silicon fluoride (SiF4) gas, nitrogenous gas supply unit 34 is via gas introduction port 29 to the inside of chamber 24
Supply does not contain nitrogenous gas, such as nitrogen (N of hydrogen atom2), rare gas supply unit 36 is via gas introduction port 30 to chamber
The inside of room 24 supplies rare gas, such as argon gas.That is, to the inside of chamber 24 supply by silicon fluoride gas and nitrogen mixing and
At, processing gas without containing hydrogen.In addition, processing gas is other than including silicon fluoride gas, nitrogen, it also may include not
Gas containing hydrogen, the rare gas such as argon gas.
Each gas introduction tube 31,33,35 has mass flow controller, valve (not shown), so as to lead to from gas
The flow that entrance 28,29,30 supplies each gas to come is adjusted.
ICP antenna 26 is made of and the cricoid conducting wire of the upper surface configuration along window member 27 via adaptation 37 and height
Frequency power 38 is connected.High-frequency current from high frequency electric source 38 flows in ICP antenna 26, which makes ICP antenna
26 generate magnetic field in the inside of chamber 24 across window member 27.The magnetic field is generated because of high-frequency current, therefore can be changed over time
Change, the magnetic field changed over time generates induction field, by the electronics after induction field acceleration and is directed in chamber 24
Molecule, the atomic collision of gas and generate inductively coupled plasma body.
In plasma CVD film formation device 23, the inside for being supplied to chamber 24 is made using inductively coupled plasma body
Silicon fluoride gas, nitrogen generate plasma, and the film forming of the silicon nitride film containing fluorine is carried out by CVD, covering is consequently formed
Entire channel protection film 17, the passivating film 18 for covering a part of source region 15 and a part of drain region 16.At this point, by
Hydrogen atom is not contained in silicon fluoride gas, nitrogen, and therefore, the silicon nitride film containing fluorine for being used to form passivating film 18 does not contain
Hydrogen atom from processing gas.
On the other hand, micro moisture on the substrate 11, nothing are adsorbed on when existing in chamber 24 in conveying substrate 11
The moisture generated due to method is by the environmental factor other than processing gas such as moisture that exhaust apparatus fully completely removes, therefore,
Sometimes with the minimal amount of hydrogen atom from the moisture in the silicon nitride film containing fluorine for being used to form passivating film 18.That is,
Although the amount of the hydrogen atom contained in passivating film 18 can be inhibited as far as possible by using the processing gas without containing hydrogen atom
(presence for inhibiting hydrogen atom), but still contain minimal amount of hydrogen atom in passivating film 18.In addition, formed a film containing fluorine
The main component of silicon nitride film is silicon nitride, and it is former that dispersedly there are the fluorine generated because silicon fluoride gas decomposes in silicon nitride
Son.
The bond energy of the N-N key in Si-F key, nitrogen in silicon fluoride gas is higher, and (the former is 595kJ/mol, the latter
For 945kJ/mol), but the density of the inductively coupled plasma body due to using ICP antenna 26 to generate is very high, can make
Silicon fluoride gas with Si-F key, the nitrogen with N-N key generate plasma.
The argon gas that rare gas supply unit 36 is supplied is not used to directly constitute the material gas of silicon nitride film, but its
Following complementary effect etc. can be played in film process: by the fluorination as the material gas for directly constituting silicon nitride film
Silicon gas and nitrogen are adjusted to appropriate concentration, and then are easy to carry out the electric discharge for generating inductively coupled plasma body.
In addition, plasma CVD film formation device 23 further includes controller 39, which is used for plasma CVD
The movement of each constitutive requirements of film formation device 23 is controlled.
In addition, the silicon halide gas without containing hydrogen atom that silicon halide gas supply part 32 is supplied is not limited to silicon fluoride
Gas is also possible to other silicon halide gases, such as silicon chloride (SiCl4), what nitrogenous gas supply unit 34 was supplied contains nitrogen
Body is not limited to nitrogen, is also possible to other nitrogenous gas.
Next, illustrating the manufacturing method of the semiconductor devices of present embodiment.
Fig. 3 and Fig. 4 is the process of the manufacturing method of the TFT of the manufacturing method of the semiconductor devices as present embodiment
Figure.
Firstly, by the following method on the substrate 11 formed have defined width gate electrode 12 ((A) of Fig. 3): i.e. into
Row metal (for example, copper (Cu)/molybdenum (Mo), titanium (Ti)/aluminium (Al)/titanium, molybdenum (Mo)/aluminium/molybdenum) based on PVD (Physical
Vapor Deposition: physical vapour deposition (PVD)) film forming, carry out by development of photoresist be defined pattern photoetching,
Carry out the etching using the photoresist after development and the removing of photoresist.
Then, by CVD, formed in a manner of covering grid electrode 12 gate insulating film 13 that is made of silica (Fig. 3's
(B)) IGZO film 40 (semiconductor film) then, is formed, at this point, the part on gate insulating film 13 is by the following method with cover grid
The mode formation width of electrode 12 is wider than the IGZO film 40 ((C) of Fig. 3) of the width of gate electrode 12: carry out IGZO based on PVD
Film forming, carry out by development of photoresist be defined pattern photoetching, carry out the erosion using the photoresist after development
The removing of quarter and photoresist.
Then, it by CVD, is formed and is separately formed by silica or by silica and nitridation in a manner of covering IGZO film 40
The channel protection film that the combination of silicon is constituted is with insulating film 52 ((D) of Fig. 3), then to cover channel protection film insulating film 52
The mode of whole surface applies photoresist 41 ((E) of Fig. 3).
Then, from figure lower section (lower section of lit-par-lit structure) irradiation exposure light 42, with to photoresist 41 carry out
Exposure and imaging ((F) of Fig. 3).At this point, gate electrode 12 blocks the light 42 of exposure and plays the effect of mask, photoresist
A part (not having the part marked using shade in figure) of light 42 in 41, that exposure is not covered by gate electrode 12 is not had
It is exposed.
Later, the photoresist 41 after exposure is dissolved using developer solution and removed it, to make channel protection film
With insulating film 52 exposure, but due to it is in photoresist 41, not by gate electrode 12 cover ultraviolet 42 a part do not have
It is dissolved by the developing, therefore, forms the width with the width for reflecting gate electrode 12 on channel protection film insulating film 52
Degree (specifically, for the width of same size with gate electrode 12, but in photoetching, because of the interference of the light for exposure, refraction
Deng and some errors are generated in the width transferred in the transfer of width, therefore, in present embodiment and aftermentioned 2nd real
It applies in mode, " identical width " refers to identical width in the error range generated in photoresist.) it is photic anti-
It loses agent mask 41a ((G) of Fig. 3).
Then, by the way that channel protection film insulate using photoresist mask 41a as the dry ecthing of mask or wet etching
The part of film 52 not covered by photoresist mask 41a removes, to make the locally exposure of IGZO film 40, that is, make IGZO
The part exposure (semiconductor film exposure step) in addition to position corresponding with photoresist mask 41a of film 40.At this point,
Only remain the part of channel protection film insulating film 52 covered by photoresist mask 41a, which forms channel and protect
Cuticula 17, the width of the width reflection photoresist mask 41a of channel protection film 17 is (specifically, channel protection film 17
Width is of same size with photoresist mask 41a's) ((H) of Fig. 3).
Then, being removed photoresist mask 41a by wet removing (Japanese: ウ ェ ッ ト is removed) or ashing makes channel
The exposure of protective film 17 ((A) of Fig. 4) then in plasma CVD film formation device 23, makes to be mixed by silicon fluoride gas and nitrogen
Made of conjunction, the processing gas without containing hydrogen generates the plasma containing fluorine and by CVD covers ditch using passivating film 18
Pipe protection film 17 and locally exposed IGZO film 40 ((B) of Fig. 4) (protective film forming step), the passivating film 18 are deposited by inhibiting
It is constituted in the silicon nitride film containing fluorine of hydrogen atom.
When being passivated the film forming of film 18, since the part of the exposure of IGZO film 40 is placed in the plasma containing fluorine
In, therefore, the electric conductivity of the part of IGZO film 40 rises, and electric current is readily flowed.On the other hand, since IGZO film 40 is by ditch
The part that pipe protection film 17 covers is not placed in the plasma containing fluorine, therefore, the part with the exposure of IGZO film 40
It compares, electric conductivity does not rise.That is, the part that the electric conductivity of IGZO film 40 does not rise is sandwiched in as shown in (B) of Fig. 4
Between the part that the electric conductivity of IGZO film 40 rises, therefore, the part constituting channel that the electric conductivity of IGZO film 40 does not rise
The part that the electric conductivity of 14, IGZO films 40 rises constitutes source region 15 and drain region 16.In addition, due to IGZO film 40
The part covered by channel protection film 17 becomes channel 14, therefore, the width (tool of the width reflection channel protection film 17 of channel 14
For body, the width of channel 14 and channel protection film 17 it is of same size).
Moreover, it is not necessary to rise the electric conductivity of all parts of IGZO film 40 along film thickness direction, as long as making IGZO film 40
At least surface resistivity lower than IGZO film 40 other parts resistivity.
The reason of electric conductivity of the part of the exposure of IGZO film 40 rises be, in the plasma existing fluoro free radical
Deng only selectively importeding into the source region 15 in IGZO film 40, drain region 16, the fluorine being directed in IGZO film 40
It plays a role as alms giver, reduces the resistivity of the source region for being imported with fluorine 15, drain region 16 selectively.In addition,
In TFT10, fluorine atom is spread from channel 14 of the silicon nitride film containing fluorine of passivating film 18 into IGZO film 40 is constituted, thus
Terminate the dangling bond for being present in channel 14 as defect.Lacking for the channel 14 for the electrical characteristics destabilization for making TFT10 is repaired as a result,
It falls into, also improves the electrical characteristics of TFT10.
In addition, in general, when gate electrode overlaps (overlap) with source electrode, drain electrode, can be generated in TFT
Parasitic capacitance.If parasitic capacitance is larger, can make to decline (Δ from the voltage until playing when driving when voltage is kept in TFT
Vp) become larger, it is therefore preferable that gate electrode and source electrode, drain electrode is inhibited to overlap to reduce parasitic capacitance.
In contrast, in TFT10, when being passivated the film forming of film 18, by IGZO film 40 not by ditch pipe protection
What film 17 covered is partially disposed in plasma and forms source region 15, drain region 16.Positioned at source region 15 and drain electrode
The width of channel 14 between region 16 is of same size with channel protection film 17, the width and photoresist of channel protection film 17
Agent mask 41a's is of same size, also, the width of photoresist mask 41a and gate electrode 12 is of same size.That is, due to
The width of channel 14 is of same size with gate electrode 12, therefore, the distance between source region 15 and drain region 16 and grid electricity
Pole 12 it is of same size.Thus, in TFT10, gate electrode 12 does not overlap with source region 15, drain region 16, Neng Goufang
Only parasitic capacitance is generated due to gate electrode 12 and source region 15, drain region 16 overlap.
Then, apply and photoresist 43 and carry out exposure and imaging ((C) of Fig. 4) on passivating film 18, and utilize with
The photoresist 43 is that the dry ecthing of mask or wet etching remove a part of passivating film 18, to make source region
15,16 part exposure ((D) of Fig. 4) of drain region.
Then, photoresist 43 ((E) of Fig. 4) is removed using wet etching, is formed by the following method and part exposure
Source region 15, drain region 16 source wiring 19, the drain electrode distribution 20 ((F) of Fig. 4) that are in contact: it is for example golden to carry out conductor
The film process based on PVD belonged to carry out the photoetching by development of photoresist for defined pattern, after carrying out using development
The etching of photoresist and the removing of photoresist.In addition, the construction as source wiring 19, drain electrode distribution 20, energy
Enough using copper/molybdenum lit-par-lit structure, titanium/aluminium/titanium lit-par-lit structure and molybdenum/aluminium/molybdenum lit-par-lit structure etc..
Then, covering source wiring 19, drain electrode are formed by the coating of photonasty organic material, photoetching, development, firing
The organic planarization film 21 ((G) of Fig. 4) of wiring 20, then, forms pixel on organic planarization film 21 by the following method
Electrode 22 ((H) of Fig. 4) and complete present treatment: the film forming based on PVD of conductor such as metal is carried out development of photoresist
For the photoetching of defined pattern, the etching using the photoresist after development and the removing of photoresist are carried out.
Using the manufacturing method of the TFT of Fig. 3 and Fig. 4, the blunt of the IGZO film 40 locally exposed from channel protection film 17 is covered
Change film 18 be made of the silicon nitride film containing fluorine, should silicon nitride film containing fluorine be using by silicon fluoride gas and nitrogen mixing and
At, the plasma containing fluorine that processing gas without containing hydrogen generates formed, therefore, fluorine atom in passivating film 18
Concentration is greater than the concentration of the fluorine atom in channel protection film 17.As a result, can be improved compared with channel 14 and constitute source region
15, the concentration of the fluorine atom in the IGZO film 40 of drain region 16 can prevent as a result, in TFT10 because of gate electrode 12 and source
Pole electrode 15, drain electrode 16 overlap and generate parasitic capacitance and can obtain good TFT characteristic.
In addition, the fluorine atom for being originated from silicon fluoride gas is spread to channel 14, to terminate as defect and be present in channel
14 dangling bond, it is thus possible to enough improve characteristic, the reliability of the IGZO of constituting channel 14.The manufacturing method of the TFT of Fig. 3 and Fig. 4
In the diffusion based on fluorine atom effect solve the problems, such as it is as follows, that is, even if there are micro hydrogen atom in IGZO film 40,
Its influence is also larger, the destabilization of device caused by the presence for the hydrogen atom that can not be completely removed.
In the manufacturing method of the TFT of described Fig. 3 and Fig. 4, passivating film has been carried out in plasma CVD film formation device 23
18 film forming, it is also possible to execute following processing in plasma CVD film formation device 23: being carried out using dry ecthing or wet etching
Channel protection film 17 formation ((H) of Fig. 3), utilize it is wet removing or ashing carry out photoresist mask 41a removal
((A) of Fig. 4).Especially, implementing the formation of channel protection film 17 using dry ecthing and implementing photic resist using ashing
In the case where the removal for losing agent mask 41a, dry ecthing, ashing are in the same manner as plasma CVD film forming also in vacuum processing environment
Therefore lower implementation can utilize the same vacuum processing such as same chamber or the multichamber system under same vacuum environment
Device forms a film to implement dry ecthing, ashing and plasma CVD, so as to simplify the structure of chamber, vacuum treatment installation.
In addition, TFT10 is continuously under vacuum environment in the manufacturing method of the TFT of described Fig. 3 and Fig. 4, until IGZO
Until the part of film 40 exposed because removing channel protection film 17 is passivated the covering of film 18, the part of the exposure of IGZO film 40 is not
It can be contacted with outside air (especially, containing the atmosphere of moisture), as a result, it is possible to prevent IGZO film 40 from producing because of adhesive water
Raw defect.
In the manufacturing method of the TFT of described Fig. 3 and Fig. 4, it is passivated the film forming of film 18, by a part of passivating film 18
It removes and makes source region 15,16 part exposure of drain region, later, form source wiring 19, drain electrode distribution 20, then formed
Organic planarization film 21 is not but it is also possible to be after the film forming for being passivated film 18, by a part removal of passivating film 18
And the organic planarization film 21 of pattern as defined in being formed in the case where not forming source wiring 19, drain electrode distribution 20, by with this
Organic planarization film 21 is that a part of passivating film 18 is removed and makes source region 15, leakage by the dry ecthing of mask or wet etching
The 16 part exposure of polar region domain.
In this case, it as shown in figure 5, on organic planarization film 21, is formed and source region 15,16 phase of drain region
Source wiring 19, the drain electrode distribution 20 of contact, and organic planarization film 21, source wiring 19, drain electrode distribution 20 are by dike material (バ Application
Network material) 44 coverings, pixel electrode 22 is formed on dike material 44.Match between locally exposed drain electrode distribution 20 and pixel electrode 22
It is equipped with the portion machine EL 45, drain electrode distribution 20 plays a role as the cathode electrode in organic portion EL 45, and pixel electrode 22 is used as organic EL
The anode electrode in portion 45 plays a role.
Next, top gate type TFT of the explanation as the semiconductor devices of the 2nd embodiment of the invention.
Fig. 6 is the cross-sectional view that outlined the structure of TFT of the semiconductor devices as present embodiment.
In Fig. 6, the multiple TFT46 formed on the substrate 11 include: priming coat 47, be separately formed by silica or by
The combination of silica and silicon nitride is constituted and is formed on the substrate 11；Channel 14 is formed on priming coat 47 and by IGZO structure
At；Source region 15 and drain region 16, the source region 15 and drain region 16 are respectively formed in the both sides of channel 14；Grid are exhausted
Velum 48 (insulating film) covers channel 14；Gate electrode 49 is formed on gate insulating film 48；Passivating film 18 (protective film),
It covers entire gate electrode 49, cover a part of source region 15 and a part of drain region 16；Source wiring 19 is formed
On source region 15, which is in contact through passivating film 18 with source region 15；Drain electrode distribution 20, shape
At on drain region 16, which is in contact through passivating film 18 with drain region 16；Organic planarization film
21, cover source wiring 19, drain electrode distribution 20；And pixel electrode 22, cover organic planarization film 21.That is, TFT46 has
There is lit-par-lit structure made of stacking gradually channel 14, gate insulating film 48 and gate electrode 49 from lower section.
In TFT46, channel 14, gate insulating film 48 width reflection gate electrode 49 width (specifically, channel 14,
The width of gate insulating film 48 is of same size with gate electrode 49).In addition, when being passivated the film forming of film 18, with the 1st embodiment party
Formula is similarly, it is preferable to use plasma CVD film formation device 23.
Next, illustrating the manufacturing method of the semiconductor devices of present embodiment.
Fig. 7 and Fig. 8 is the process of the manufacturing method of the TFT of the manufacturing method of the semiconductor devices as present embodiment
Figure.
Firstly, forming priming coat 47 on the substrate 11, IGZO film 40 (semiconductor film) then is formed, at this point, by as follows
Method is formed locally IGZO film 40 ((A) of Fig. 7) on priming coat 47: carrying out the film forming based on PVD of IGZO, carries out light
Causing resist development is the photoetching of defined pattern, carries out the etching and photoresist using the photoresist after development
Removing.
Then, by CVD, the gate insulating film insulating film being made of silica is formed in a manner of covering IGZO film 40
53, then, formed on the substrate 11 by the film forming based on PVD of metal (for example, copper/molybdenum, titanium/aluminium/titanium, molybdenum/aluminium/molybdenum)
Cover the grid metal film 50 ((B) of Fig. 7) of gate insulating film insulating film 53.
Then, photoresist (not shown) is applied in a manner of the whole surface of cover grid metal film 50, and from figure
The light (not shown) of top (top of lit-par-lit structure) irradiation exposure and photoresist is exposed, thus as defined in making
The photoresist mask 51a of pattern develops ((C) of Fig. 7) in the top of IGZO film 40.
Then, by as the dry ecthing of mask or wet etching that grid metal film 50 is selective using photoresist mask 51a
Ground removal, thus make gate insulating film insulating film 53 locally exposure, that is, make gate insulating film insulating film 53 remove and photoresist
Part exposure other than the corresponding position agent mask 51a.At this point, only remain grid metal film 50 by photoresist mask
The part of 51a covering, the remaining part of grid metal film 50 constitute gate electrode 49, and the width of gate electrode 49 reflects photoresist
Mask 51a width (specifically, the width of gate electrode 49 in the range of the machining accuracy of the processing based on mask with it is photic
Etching mask 51a's is of same size) ((D) of Fig. 7).
Also, after making the exposure of gate insulating film 48, continuing to progress with photoresist mask 51a, gate electrode 49 is
Dry ecthing or the wet etching of mask and by gate insulating film insulating film 53 be not masked covering part remove, to make
40 part exposure of IGZO film, that is, make the part exposure (semiconductor in addition to position corresponding with gate electrode 49 of IGZO film 40
Film exposure step).At this point, only remaining the part of gate insulating film insulating film 53 covered by gate electrode 49, which is formed
Gate insulating film 48, the width of the width reflection gate electrode 49 of gate insulating film 48 is (specifically, the width of gate insulating film 48 is being based on
It is of same size with gate electrode 49 in the range of the machining accuracy of mask) ((E) of Fig. 7).
Then, being removed photoresist mask 51a by wet removing or ashing makes gate electrode 49 expose (Fig. 7's
(F)), then, in plasma CVD film formation device 23, make being mixed by silicon fluoride gas and nitrogen, without containing hydrogen
Processing gas generates plasma, by CVD, comes covering grid electrode 49 and locally exposed IGZO film 40 using passivating film 18
((G) of Fig. 7) (protective film forming step), the passivating film 18 is by inhibiting the silicon nitride film structure containing fluorine there are hydrogen atom
At.
In a same manner as in the first embodiment, in the present embodiment, when being passivated the film forming of film 18, due to IGZO film
The part of 40 exposure is placed in the plasma containing fluorine gas, therefore, the electric conductivity of the part of IGZO film 40 rise and
Constitute source region 15 and drain region 16, the gate electrode 49 to be played a role as mask and gate insulating film 48 of IGZO film 40
The part of covering is not placed in the plasma containing fluorine gas, therefore, compared with the part of the exposure of IGZO film 40, is led
Electrically without rising and constituting channel 14.In addition, the part covered by gate electrode 49 due to IGZO film 40 becomes channel 14, because
This, the width of the width reflection gate electrode 49 of channel 14 is (specifically, the width of channel 14 is in the machining accuracy based on mask
It is of same size with gate electrode 49 in range).In addition, in a same manner as in the first embodiment, in the present embodiment, self-passivation film
18 also enter in channel 14 to the fluorine atom that IGZO film 40 is spread, to repair the defect of channel 14.
In addition, in TFT46, the width and gate electrode 49 of the channel 14 between source region 15 and drain region 16
It is of same size, therefore, the distance between source region 15 and drain region 16 are of same size with gate electrode 49.Thus,
In TFT46, gate electrode 49 does not overlap with source region 15, drain region 16, can prevent because of gate electrode 49 and source region
15, drain region 16 overlaps and generates parasitic capacitance.
Then, apply and photoresist 43 and carry out exposure and imaging ((H) of Fig. 7) on passivating film 18, and utilize with
The photoresist 43 is that the dry ecthing of mask or wet etching remove a part of passivating film 18, to make source region
15,16 part exposure ((A) of Fig. 8) of drain region.
Then, photoresist 43 ((B) of Fig. 8) is removed using wet removing, is formed by the following method and part exposure
Source region 15, drain region 16 source wiring 19, the drain electrode distribution 20 ((C) of Fig. 8) that are in contact: it is for example golden to carry out conductor
The film forming carried out based on PVD belonged to carries out the photoetching by development of photoresist for defined pattern, after carrying out using development
The etching of photoresist and the removing of photoresist.
Then, covering source wiring 19, drain electrode are formed by the coating of photonasty organic material, photoetching, development, firing
The organic planarization film 21 ((D) of Fig. 8) of wiring 20, then, forms pixel on organic planarization film 21 by the following method
Electrode 22 ((E) of Fig. 8), to complete present treatment: carrying out the film forming of conductor such as metal carried out based on PVD, carry out light
Causing resist development is the photoetching of defined pattern, carries out the etching and photoresist using the photoresist after development
Removing.
Using the manufacturing method of the TFT of Fig. 7 and Fig. 8, the passivation of the IGZO film 40 locally exposed from gate insulating film 48 is covered
Film 18 is made of the silicon nitride film containing fluorine, and being somebody's turn to do the silicon nitride film containing fluorine is mixed using by silicon fluoride gas and nitrogen
, the plasma containing fluorine that processing gas without containing hydrogen generates formed, therefore, fluorine atom in passivating film 18 it is dense
Degree is greater than the concentration of the fluorine atom in gate insulating film 48.As a result, compared with channel 14, can be improved constitute source region 15,
The concentration of fluorine atom in the IGZO film 40 of drain region 16 can prevent as a result, in TFT46 because of gate electrode 12 and source electrode
Electrode 15, drain electrode 16 overlap and generate parasitic capacitance and can obtain good TFT characteristic.In addition, being originated from silicon fluoride
The fluorine atom of gas is spread to channel 14, so that the dangling bond of channel 14 is terminated as defect and be present in, it is thus possible to enough improve
Characteristic, the reliability of the IGZO of constituting channel 14.
In the manufacturing method of the TFT of described Fig. 7 and Fig. 8, passivating film has been carried out in plasma CVD film formation device 23
18 film forming, it is also possible to execute following processing in plasma CVD film formation device 23: being carried out using dry ecthing or wet etching
Gate insulating film 48 formation ((E) of Fig. 7), using it is wet removing or ashing come the removal of the photoresist mask 51a carried out
((F) of Fig. 7).In addition, implementing the formation of gate insulating film 48 using dry ecthing and implementing photoresist using ashing
In the case where the removal of mask 51a, dry ecthing, ashing are also real under vacuum processing environment in the same manner as plasma CVD film forming
It applies, therefore, the same vacuum treatment installation such as same chamber or the multichamber system under same vacuum environment can be utilized
Come implement dry ecthing, ashing and plasma CVD film forming, so as to simplify chamber, vacuum treatment installation structure and can
Prevent IGZO film 40 from generating defect because of adhesive water.
More than, the present invention is illustrated using each embodiment, but the present invention is not limited to each embodiments.
For example, in each embodiment, IGZO film 40 has been used as semiconductor film, but semiconductor film and unlimited
In this, also can be used by other than IGZO oxide semiconductor film, at least contain conduct such as ITZO, IGO, ZnO, AZO
The film that the oxide semiconductor of the zinc oxide of constitution element is constituted.In addition, in each embodiment, illustrate as it is equal from
Daughter CVD film formation device and use include the window member 27 being made of dielectric and the ICP antenna 26 outside chamber 24 electricity
The case where feeling coupled plasma apparatus, as long as but it is possible to being that can generate using plasma CVD film formation device of the invention
The inductance coupled plasma device of high-density plasma, it is just without being limited thereto, for example, in inductance coupled plasma device
In, window member can also be made of the other materials other than dielectric, alternatively, ICP antenna can also be set in chamber.
The purpose of the present invention, which can also be accomplished in that, to be stored with for realizing the function of each embodiment
The storage medium of the program code of the software of energy is supplied to computer, such as controller 39, is read and is held by the CPU of controller 39
The program code that row is stored in storage medium.
In this case, the function of the embodiment, program generation are realized from the program code itself that storage medium is read
Code and the storage medium for being stored with the program code constitute the present invention.
In addition, as the storage medium for supplying program code, if can storing said program code, such as
RAM, NV-RAM, Off ロ ッ ピ ー (registered trademark) disk (i.e. floppy disk), hard disk, photomagneto disk, CD-ROM, CD-R, CD-RW,
The CDs such as DVD (DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), tape, non-volatile storage card and others
ROM etc..Alternatively, can also be by from other calculating (not shown) being connected with internet, commercial network or local area network etc.
Machine, database etc. are downloaded said program code and are supplied to controller 39.
In addition, the function of the embodiment can not only be realized by executing the program code read by controller 39,
But also including following situations: practical by progress such as the OS (operating system) that is operated in CPU according to the instruction of the program code
Processing part or all, realize the function of the embodiment through this process.
Also, further include following situations: being written in the program code read from storage medium and be inserted in controller 39
Expansion board, in memory possessed by the functional expansion unit that is connected with controller 39 after, according to the program code
Instruction, part or all of actual processing is carried out by the expansion board, the had CPU of functional expansion unit etc., is led to
The processing is crossed to realize the function of the embodiment.
The form of said program code can also be by utilizing object code (object code), interpretive program
(interpreter) program code executed, the morphosises such as script data (script data) for being supplied to OS.
Description of symbols
10,46,TFT；12,49, gate electrode；14, channel；15, source region；16, drain region；17, channel protection film；
18, passivating film；23, plasma CVD film formation device；40, IGZO film；48, gate insulating film.
Claims (7)
1. a kind of manufacturing method of semiconductor devices, which has by gate electrode, semiconductor film and partly leads at this
The lit-par-lit structure that the insulating film being laminated on body film is constituted, the semiconductor film are made of oxide semiconductor, which is characterized in that
The manufacturing method of the semiconductor devices the following steps are included:
Semiconductor film exposure step will be described and the gate electrode is used as mask in the semiconductor film exposure step
Insulating film locally removes, to make the semiconductor film locally exposure；
Protective film forming step makes being mixed by silicon halide gas and nitrogenous gas, no in the protective film forming step
Processing gas containing hydrogen generates plasma that is halogen and not containing hydrogen, and at least part by the exposure of the semiconductor film is set
In the plasma, thus the resistivity on at least surface of the part of the exposure of the semiconductor film is lower than the semiconductor
The resistivity of the other parts of film, the part of the exposure of the semiconductor film constitutes source region and drain region, described partly to lead
The part constituting channel that the remaining part by the insulating film of body film covers, while using being made of halogen silicon nitride film
Protective film covers the part of the exposure of the semiconductor film and the remaining part of the insulating film.
2. the manufacturing method of semiconductor devices according to claim 1, which is characterized in that
In the protective film forming step, make residual by the insulating film of the halogen atom from the protective film to semiconductor film
Part covering part diffusion.
3. the manufacturing method of semiconductor devices according to claim 1 or 2, which is characterized in that
In the protective film forming step, make being placed in the plasma for the part of the exposure of the semiconductor film
Resistivity of the partial resistivity lower than the part of the semiconductor film covered by the insulating film.
4. the manufacturing method of semiconductor devices according to claim 1 or 2, which is characterized in that
In the lit-par-lit structure, the gate electrode, the semiconductor film and the insulating film are stacked gradually from lower section,
Before the semiconductor film exposure step, the insulating film is covered using photoresist, from the lit-par-lit structure
The light of lower section irradiation exposure and the photoresist is exposed and is developed,
In the semiconductor film exposure step, by using the etching of the photoresist after the development by the insulation
Film locally removes,
When from the light of the lower section irradiation exposure of the lit-par-lit structure, after the gate electrode is made the development as mask
The width of photoresist reflect the width of the gate electrode.
5. the manufacturing method of semiconductor devices according to claim 1 or 2, which is characterized in that
In the lit-par-lit structure, the semiconductor film, the insulating film and the gate electrode are stacked gradually from lower section,
Before the semiconductor film exposure step, the insulating film is covered using conductive film and covers institute using photoresist
Conductive film is stated, the photoresist is exposed and is developed from the light of the top irradiation exposure of the lit-par-lit structure,
Photoresist after the development is used as mask and the conductive film is etched, is consequently formed described with reflecting
The gate electrode of the width of the width of photoresist, then, in the semiconductor film exposure step, by that described will show
The photoresist of movie queen and the gate electrode of the formation are used as mask and are etched to the insulating film, so that being formed has
Reflect the insulating film of the width of the width of the gate electrode.
6. the manufacturing method of semiconductor devices according to claim 1 or 2, which is characterized in that
The oxide semiconductor at least contains the zinc oxide as constitution element.
7. a kind of manufacturing device of semiconductor devices, which has by gate electrode, semiconductor film and partly leads at this
The lit-par-lit structure that the insulating film being laminated on body film is constituted, the semiconductor film are made of oxide semiconductor, which is characterized in that
The insulating film is locally removed and the gate electrode is used as mask, to be constituted using by halogen silicon nitride film
Protective film cover the part of the exposure of the semiconductor film and the remaining part of the insulating film, the halogen silicon nitride film
It is using the halogen of processing gas generation mixed from silicon halide gas and nitrogenous gas, without containing hydrogen and without containing hydrogen
Plasma formed,
Wherein, the halogen of processing gas generation mix from silicon halide gas and nitrogenous gas, without containing hydrogen is being utilized
And in the step of forming the protective film without containing the plasma of hydrogen, the part of the exposure of the semiconductor film constitutes source area
Domain and drain region, the part constituting channel that the remaining part by the insulating film of the semiconductor film covers,
Wherein, the resistivity on at least surface of the part of the exposure of the semiconductor film is lower than the other parts of the semiconductor film
Resistivity, the part of the exposure of the semiconductor film constitutes source region and drain region, the semiconductor film it is described
The part constituting channel of the remaining part covering of insulating film.
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| JP2014049797A JP6412322B2 (en) | 2014-03-13 | 2014-03-13 | Semiconductor device, manufacturing method thereof, and manufacturing apparatus thereof |
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| US10749036B2 (en) | 2018-08-03 | 2020-08-18 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Oxide semiconductor thin film transistor having spaced channel and barrier strips and manufacturing method thereof |
| CN109256429B (en) * | 2018-08-03 | 2021-01-26 | Tcl华星光电技术有限公司 | Oxide semiconductor thin film transistor and manufacturing method thereof |
| CN110828486B (en) * | 2019-11-19 | 2023-05-12 | 云谷（固安）科技有限公司 | Display panel manufacturing method and display panel |
| WO2021134423A1 (en) * | 2019-12-31 | 2021-07-08 | 广州新视界光电科技有限公司 | Method for preparing thin film transistor |
| CN112687706A (en) * | 2020-12-29 | 2021-04-20 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
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