TW201603145A - Semiconductor device, manufacturing method thereof, and manufacturing apparatus - Google Patents

Abstract

The present invention provides a semiconductor device capable of preventing a characteristic change in an oxide semiconductor and having small parasitic capacitance, and a method for manufacturing the same. In a TFT (10) having a laminated structure where a gate electrode (12), an IGZO film (40), and a channel protective film (17) are laminated from the bottom, the IGZO film (40) is partially exposed (drawing 3(H)) by partially removing the channel protective film (17) using a photoresist mask (41a) with a width, in which the width of a gate electrode (12) is reflected, as a mask. The exposed IGZO film (40) and remaining channel protective film (17) are covered with a passivation film (18) composed of a fluorine-containing silicon nitride film formed by being exposed to plasma from process gas, which is obtained by mixing silicon tetrafluoride gas and nitrogen gas and does not contain hydrogen. Moreover, a source area (15) or a drain area (16) is formed by diffusing boron atoms from the passivation film (18) in the exposed IGZO film (40) when the passivation film (18) is formed.

Description

Semiconductor device, method of manufacturing the same, and manufacturing device

The present invention relates to a semiconductor device using an oxide semiconductor for a channel, a method of manufacturing the same, and a device for manufacturing the same.

In the field of flat panel displays, LCD elements have been used in many fields. However, in recent years, not only the use of LCD elements, but also the use of organic EL (Electro-Current) elements has progressed in order to realize thin-film displays or new-generation thin-type televisions. The organic EL element is a self-luminous type of light-emitting element, and unlike a liquid crystal element, a thinner display can be realized because a backlight is not required.

The organic EL element is a current-driven type element. In a thin film transistor (TFT: Thin Film Transistor) suitable for an organic EL element, high-speed switching operation must be realized. However, as a constituent material of the channel, it is mainly used. The electron mobility of the crystalline germanium is not so high, and the amorphous germanium is not suitable for the constituent material of the channel for the organic EL.

Therefore, there has been proposed a TFT in which an oxide semiconductor having high electron mobility can be used for a channel. As an oxide semiconductor used in such a TFT, for example, IGZO made of an oxide of indium (In), gallium (Ga), and zinc (Zn) is known (for example, see Non-Patent Document 1), and the IGZO system is In the amorphous state, since it has a relatively high electron mobility (for example, 10 cm ² /(V.s) or more), when an oxide semiconductor such as IGZO is used in the channel of the TFT, high-speed switching operation can be realized. By. The application to the channel of the TFT of the oxide semiconductor such as IGZO is not only an organic EL element, but also an effect on the LCD element.

In the TFT, for example, a protective film having a channel formed by a tantalum nitride (SiN) film or the like is provided in order to protect the channel from ions or moisture in the outside (see, for example, Patent Document 1). However, when a tantalum nitride film is formed by plasma CVD (Chemical Vapor Deposition), it is used as a halogen source, using decane (SiH ₄ ), and as a nitrogen source, ammonia (NH ₃ ) is used as a nitrogen source. However, when a tantalum nitride film is formed by using plasma from methanthan and ammonia, a hydrogen radical or a hydrogen ion enters the tantalum nitride film as a hydrogen atom. Generally, the protective film contains a large amount of hydrogen. atom.

The hydrogen atom contained in the protective film diffuses into the channel to detach the oxygen atom in the IGZO, and the characteristics of the IGZO, for example, the threshold voltage (Vth), are changed, and the cerium oxide (SiO ₂ ) film is examined. After the coating channel is placed above and below, the protective film of the channel formed by the tantalum nitride film is formed into a film, and heat treatment is added to improve the reliability of IGZO.

[Previous Technical Literature] [Patent Literature]

[Patent Document 1] Japanese Patent No. 3148183

[Non-patent literature]

[Non-Patent Document 1] "Improved Thin Film Display Oxide Semiconductor TFT", Miura Kentaro, Toshiba Review Vol. 67 No. 1 (2012)

However, in a semiconductor device in which a hydrogen atom exists in a tantalum nitride film via residual, intrusion or other reasons of hydrogen atoms, when IGZO is applied to an LCD element or an organic EL element, hydrogen atoms in the tantalum nitride film are prevented. The change in the characteristics of IGZO is difficult.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of preventing a change in characteristics of an oxide semiconductor, a method of manufacturing the same, and a device for manufacturing the same.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a gate electrode, a semiconductor film formed of an oxide semiconductor, and a method of manufacturing a semiconductor device in which a laminated film of an insulating film is laminated on the semiconductor film. It is characterized in that the semiconductor film is partially removed by using the gate electrode as a mask, the semiconductor film is partially exposed, and the semiconductor film is exposed, and the halogenated germanium gas is mixed. And a gas containing nitrogen gas, which does not contain hydrogen, causes plasma to be generated, and at least exposes the exposed semiconductor film to the plasma, and is coated with a protective film made of a halogen-containing tantalum nitride film. The exposed semiconductor film and the protective film forming step of the remaining insulating film remain.

In order to achieve the above object, a semiconductor device manufacturing apparatus of the present invention includes a gate electrode, a semiconductor film formed of an oxide semiconductor, and a semiconductor device manufacturing apparatus in which a laminated film of an insulating film is laminated on the semiconductor film. The use of the gate electrode as a mask, the partial removal of the insulating film, and the partially exposed semiconductor film and the remaining insulating film are mixed with a hafnium halide gas and a nitrogen-containing gas. And it is covered by a protective film made of a halogen-containing tantalum nitride film formed by a plasma containing a hydrogen-containing processing gas.

In order to achieve the above object, a semiconductor device of the present invention includes a gate electrode, a semiconductor film formed of an oxide semiconductor, and a semiconductor device in which an insulating film is laminated on the semiconductor film, and is characterized in that it is partially removed. The semiconductor film is partially exposed by the insulating film, and at least the protective semiconductor film covers the exposed semiconductor film, and the concentration of fluorine atoms in the protective film covering the exposed semiconductor film is higher than the fluorine atom in the insulating film. The concentration is high.

According to the present invention, the protective film covering the semiconductor film is formed by a halogen-containing tantalum nitride film formed by mixing a halogenated germanium gas and a nitrogen-containing gas and using a plasma generated from a process gas containing no hydrogen. Therefore, the inclusion of hydrogen atoms in the protective film is suppressed, and the halogen atoms diffused in the semiconductor film by the hafnium halide gas can repair the defects in the semiconductor film and stabilize the characteristics of the oxide semiconductor of the semiconductor film. By.

10,46‧‧‧TFT

12,46‧‧‧gate electrode

14‧‧‧ passage

15‧‧‧Source range

16‧‧‧Bunging area

17‧‧‧Channel protective film

18‧‧‧ Passivation film

23‧‧‧ Plasma CVD film forming device

40‧‧‧IGZO film

48‧‧‧gate insulating film

FIG. 1 is a cross-sectional view schematically showing a configuration of a TFT as a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view schematically showing a configuration of a plasma CVD film forming apparatus as a manufacturing apparatus of the semiconductor device of the embodiment.

Fig. 3 is a view showing a method of manufacturing a TFT as a method of manufacturing a semiconductor device of the embodiment.

Fig. 4 is a view showing a method of manufacturing a TFT as a method of manufacturing a semiconductor device of the embodiment.

Fig. 5 is a cross-sectional view schematically showing a configuration of a modification of the TFT of the semiconductor device of the embodiment.

Fig. 6 is a cross-sectional view schematically showing a configuration of a TFT as a semiconductor device according to a second embodiment of the present invention.

Fig. 7 is a view showing a method of manufacturing a TFT according to a method of manufacturing a semiconductor device of the embodiment.

Fig. 8 is a view showing a method of manufacturing a TFT as a method of manufacturing a semiconductor device of the embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

First, a bottom gate type thin transistor (TFT) which is a semiconductor device according to the first embodiment of the present invention will be described.

Fig. 1 is a cross-sectional view schematically showing a configuration of a TFT as a semiconductor device according to the present embodiment. However, in FIG. 1, it is convenient to construct not only the structure of the TFT but also the terminal portion which is manufactured simultaneously with the TFT (see the right side in the drawing).

In Fig. 1, a plurality of TFTs 10 formed on a substrate 11 are provided with a gate electrode 12 formed on a substrate 11, a gate insulating film 13 covering the gate electrode 12, and a gate insulating film. 13 and a channel 14 (semiconductor film) formed by IGZO, and a source range 15 and a drain range 16 which are formed on both sides of the channel 14, and a channel protective film 17 (insulating film) of the covered channel 14 And partially covering the passivation film 18 (protective film) of the channel protective film 17 or the source range 15 and the drain region 16 and forming the source region 15 through the passivation film 18 and the source range The source wiring 19 that is in contact with 15 and the gate wiring 20 that is formed on the drain region 16 and that is in contact with the drain region 16 through the passivation film 18, and the organic planarization of the covered source wiring 19 or the drain wiring 20 The film 21 and the pixel electrode 22 covering the organic planarizing film 21 are provided. In other words, the TFT 10 has a laminated structure in which the gate electrode 12, the channel 14 and the channel protective film 17 are laminated in this order from the lower side.

The passivation film 18 is formed of a fluorinated tantalum nitride film. The film is formed by plasma CVD, and the source range 15 and the drain range 16 are formed by conductivity enhancement (metallization) IGZO, and the width of the channel 14 or the channel protection film 17 is reflected to reflect the gate electrode 12. The width (specifically, the width of the channel 14 or the channel protective film 17 is the same as the width of the gate electrode 12 within the error range of the light lithography).

Next, a plasma CVD film forming apparatus as a manufacturing apparatus of the semiconductor device of the present embodiment will be described. This plasma CVD film forming apparatus is particularly preferably used when the passivation film 18 is formed into a film.

FIG. 2 is a cross-sectional view schematically showing a configuration of a plasma CVD film forming apparatus as a manufacturing apparatus of the semiconductor device of the embodiment.

In FIG. 2, the plasma CVD film forming apparatus 23 includes, for example, a processing chamber 24 that accommodates a substrate 11 having a TFT 11 formed thereon, and a processing chamber 24 disposed in the processing chamber 24, and the substrate 11 is placed. The mounting table 25 placed on the upper surface, and the ICP antenna 26 disposed on the outside of the processing chamber 24 opposite to the mounting table 25 inside the processing chamber 24, and the apex portion constituting the processing chamber 24 are interposed in the load. The window member 27 between the stage 25 and the ICP antenna 26 is placed.

The processing chamber 24 has an exhaust device (not shown) that vacuum-treats the processing chamber 24 to decompress the inside of the processing chamber 24. The window member 27 of the processing chamber 24 is formed of a dielectric body that separates the inside and the outside of the processing chamber 24.

The window member 27 is supported by an insulating member (not shown) Holder is on the side wall of the processing chamber 24, and the window member 27 is not in direct contact with the processing chamber 24, but is not electrically conductive. Further, the window member 27 has a size that can cover at least the entire substrate 11 placed on the mounting table 25. However, the window member 27 can also be constructed from a plurality of divided pieces.

Three gas introduction ports 28, 29, and 30 are provided in the side wall of the processing chamber 24, and the gas introduction port 28 is connected to the halogenated gas supply portion 32 disposed outside the processing chamber 24 by the gas introduction pipe 31. The gas introduction port 29 is connected to the nitrogen-containing gas supply unit 34 disposed outside the processing chamber 24 by the gas introduction pipe 33, and the gas introduction port 30 is connected to the gas introduction pipe 35 and disposed in the processing chamber. 24 external rare gas supply unit 36.

The halogen halide gas supply unit 32 supplies a halogen halide gas containing no hydrogen atoms, for example, a halogenated halogen (SiF ₄ ) gas to the inside of the processing chamber 24 through the gas introduction port 28, and the nitrogen-containing gas supply unit 34 is provided. A gas containing nitrogen gas, such as nitrogen (N ₂ ) gas, is supplied to the inside of the processing chamber 24 through the gas introduction port 29, and the rare gas supply unit 36 is supplied to the processing chamber 24 through the gas introduction port 30. Inside, a rare gas such as argon is supplied. That is, the inside of the processing chamber 24 is mixed with a cesium fluoride gas and nitrogen gas, and a processing gas containing no hydrogen is supplied. However, the treatment gas system may contain a gas containing no hydrogen, for example, a rare gas such as argon gas, in addition to cesium fluoride gas or nitrogen.

Each of the gas introduction pipes 31, 33, and 35 has a flow rate controller or a valve (none of which is shown), and adjusts the flow rates of the respective gases supplied from the gas introduction ports 28, 29, and 30.

The ICP antenna 26 is formed of an annular wire disposed along the upper surface of the window member 27, and is connected to the high frequency power source 38 by the adjuster 37. The high frequency current from the high frequency power source 38 flows through the ICP antenna 26, which is coupled to the ICP antenna 26, and the window member 27 causes the magnetic field to be generated inside the processing chamber 24. The magnetic field changes temporally due to the high frequency current, but the magnetic field that changes temporally generates an induction field, and the electrons accelerated by the induced electric field and the gas that is introduced into the processing chamber 24 The molecular or atomic conflicts produce an inductively coupled plasma.

In the plasma CVD film forming apparatus 23, a plasma is generated from a cesium fluoride gas or nitrogen gas supplied to the inside of the processing chamber 24 via inductively coupled plasma, and a cerium nitride film based on fluorination by CVD is formed. At the time of film formation, the passivation film 18 which partially covers the channel protective film 17 or the source range 15 and the drain range 16 is formed. At this time, neither of the cesium fluoride gas nor the nitrogen gas contains a hydrogen atom, and the ruthenium nitride film forming the fluorine-containing film of the passivation film 18 does not contain a hydrogen atom due to the processing gas.

On the other hand, in the case where the substrate 11 is transported, a small amount of moisture adsorbed on the substrate 11 or a process gas such as moisture which cannot be sufficiently removed by the exhaust device is present in the processing chamber due to moisture due to environmental factors. In the case of 24, the hydrogen atom due to the moisture has a cerium nitride film which is contained in the fluorine film forming the passivation film 18 in a very small amount. In other words, when a processing gas containing no hydrogen atom is used, the amount of hydrogen atoms contained in the passivation film 18 can be suppressed as much as possible (inhibition of the presence of hydrogen atoms), but The passivation film 18 still contains a very small amount of hydrogen atoms. However, the main component of the ruthenium nitride film of the fluorine-containing film to be formed is tantalum nitride, and in the tantalum nitride, fluorine atoms generated by decomposition of the cesium fluoride gas are dispersed.

The Si-F bond of the cesium fluoride gas or the NN bond bond energy of nitrogen is high (the former is 595 kJ/mol, the latter is 945 kJ/mol), but the inductively coupled plasma system using the ICP antenna 26 is very dense. High, it can be generated from a cesium fluoride gas or nitrogen gas with Si-F bonding or NN bonding.

The argon gas supplied from the rare gas supply unit 36 is not present in the material gas directly constituting the tantalum nitride film, but the cesium fluoride gas and nitrogen gas which directly constitute the material gas of the tantalum nitride film are adjusted to an appropriate concentration. Further, as a discharge for generating an inductively coupled plasma or the like, it is possible to achieve an auxiliary function in the film formation process.

Further, the plasma CVD film forming apparatus 23 further includes a controller 39 that controls the operation of each component of the plasma CVD film forming apparatus 23.

However, the hafnium halide gas system which does not contain the hydrogen atom supplied from the hafnium halide gas supply unit 32 is not limited to the hafnium fluoride gas, but may be other hafnium halide gas such as barium chloride (SiCl ₄ ) and nitrogen. The nitrogen-containing system supplied from the gas supply unit 34 is not limited to nitrogen gas, and may be other nitrogen-containing gas.

Next, a method of manufacturing the semiconductor device of the present embodiment will be described.

3 and 4 are related to the semiconductor of the embodiment. A drawing of a method of manufacturing a TFT of a method of manufacturing a device.

First, after film formation by PVD (Physical Vapor Deposition) via a metal (for example, copper (Cu) / molybdenum (Mo), titanium (Ti) / aluminum (Al) / titanium or molybdenum (Mo) / aluminum / molybdenum, The photoresist is developed into a specific pattern of photolithography, and the photoresist electrode of the developed photoresist and the stripping of the photoresist are used to form a gate electrode 12 having a specific width on the substrate 11 (FIG. 3 (FIG. 3) A)).

Next, the gate electrode 12 is formed by CVD, and the gate insulating film 13 made of the hafnium oxide film is formed (FIG. 3(B)), and the IGZO film 40 (semiconductor film) is formed. At the time of film formation by PVD of IGZO, the photoresist is developed into a photolithography of a specific pattern, and etching using the developed photoresist and peeling of the photoresist are performed on the gate insulating film 13. The IGZO film 40 having a width wider than that of the gate electrode 12 is partially formed to cover the gate electrode 12 (Fig. 3(C)).

Then, the IGZO film 40 is coated by CVD, and the channel protective film 52 made of a combination of yttrium oxide alone or yttrium oxide and tantalum nitride is formed into a film (Fig. 3(D)), and further, The photoresist 41 is entirely coated on the insulating film 52 for the channel protective film (Fig. 3(E)).

Next, the light 42 for exposure is irradiated from the lower side in the figure (below the laminated structure), and the photoresist 41 is exposed and developed (FIG. 3 (F)). At this time, the gate electrode 12 functions as a mask for blocking the light 42 for exposure, and is a part of the photoresist 41 that is blocked from the light 42 for exposure via the gate electrode 12 (in the figure). The part that is not shaded is not exposed.

Thereafter, the exposed photoresist 41 is dissolved by the developing solution. The channel protective film is exposed to the insulating film 52, but a portion of the photoresist 41 that is blocked from the ultraviolet light 42 via the gate electrode 12 is not dissolved by the developing solution, and is reflected. The width of the width of the gate electrode 12 (specifically, the width of the gate electrode 12 is the same as the width of the gate electrode 12, but in the photolithography, the width is transferred by interference or refraction of light used for exposure or the like. In the second embodiment of the present embodiment and the second embodiment to be described later, the "same width" means that the error width in the photoresist is the same width. The photoresist mask 41a is formed on the channel protective film insulating film 52 (Fig. 3(G)).

Then, the portion of the photoresist mask 41a that is not covered by the insulating film 52 for the channel protective film is removed by dry etching or wet etching using the photoresist mask 41a as a mask, so that the IGZO film 40 corresponds to light. The portion of the resist mask 41a is partially exposed (the semiconductor film exposure step). At this time, only the channel protective film insulating film 52 where the photoresist mask 41a is covered remains, and the channel protective film 17 is formed, and the width of the channel protective film 17 is reflected to reflect the width of the photoresist mask 41a ( Specifically, the width of the channel protective film 17 is the same as the width of the photoresist mask 41a (Fig. 3(H)).

Next, the photoresist mask 41a is removed by wet peeling or ashing, the channel protective film 17 is exposed (FIG. 4(A)), and further, in the plasma CVD film forming apparatus 23, cesium fluoride gas is mixed. And nitrogen gas, and a treatment gas containing no hydrogen to form a plasma containing fluorine, and coated with a lanthanum nitride film which suppresses the presence of hydrogen atoms by CVD. The IGZO film 40 and the channel protective film 17 (FIG. 4(B)) partially exposed by the passivation film 18 (protective film forming step).

When the passivation film 18 is formed into a film, the exposed IGZO film 40 is exposed to a plasma containing fluorine, and the conductivity of the IGZO film 40 rises, and the current easily flows. On the other hand, the IGZO film 40 covered by the channel protective film 17 is not exposed to the plasma containing fluorine, and the conductivity is not increased as compared with the exposed IGZO film 40. In other words, as shown in FIG. 4(B), the IGZO film 40 whose conductivity is not increased is sandwiched between the IGZO film 40 having an increased conductivity, and the IGZO film 40 whose conductivity is not increased constitutes the channel 14, and the conductivity is increased. The IGZO film 40 constitutes a source range 15 and a drain range 16. Further, the IGZO film 40 covered by the channel protective film 17 serves as the channel 14, and the width of the channel 14 is reflected to reflect the width of the channel protective film 17 (specifically, the width of the channel 14 becomes the channel protective film 17). The width is the same).

However, the IGZO film 40 does not have to have a conductivity increase in all portions along the film thickness direction, and at least the surface resistivity may be lower than the other portion of the IGZO film 40.

The increased conductivity of the exposed IGZO film 40 is introduced into the IGZO film by selectively introducing a fluorine radical or the like which is present in the plasma into the source range 15 or the drain range 16 of the IGZO film 40. The fluorine in 40 acts as a donor, and the impedance ratio of the source range 15 or the drain range 16 into which fluorine is introduced is selectively reduced. Further, in the TFT 10, from the tantalum nitride film constituting the fluorine-containing film of the passivation film 18, the fluorine atoms are diffused in the channel 14 in the IGZO film 40, in the channel 14. Ending the unsaturated bond that exists as a defect. Thereby, the defects of the channel 14 which destabilizes the electrical characteristics of the TFT 10 are repaired, and the electrical characteristics of the TFT 10 are also improved.

However, in general, in a TFT, when a gate electrode overlaps (overlaps) a source electrode or a drain electrode, a parasitic capacitance is generated. When the parasitic capacitance is large, the voltage drop (ΔVp) from the time of driving the TFT to the voltage holding becomes larger, and the case where the gate electrode is prevented from overlapping with the source electrode or the drain electrode and the parasitic capacitance is reduced is good.

On the other hand, in the TFT 10, when the passivation film 18 is formed into a film, the IGZO film 40 not covered by the channel protective film 17 is exposed to the plasma to form the source range 15 or the drain range 16. The width of the channel 14 existing between the source range 15 and the drain range 16 is the same as the width of the channel protection film 17, and the width of the channel protection film 17 is the same as the width of the photoresist mask 41a. The width of the photoresist mask 41a is the same as the width of the gate electrode 12. That is, the width of the channel 14 is the same as the width of the gate electrode 12, and the distance between the source range 15 and the drain range 16 is the same as the width of the gate electrode 12. Accordingly, in the TFT 10, the gate electrode 12 is not overlapped with the source range 15 or the drain range 16, and generation of parasitic due to the overlap of the gate electrode 12 and the source range 15 or the drain region 16 can be prevented. The case of capacitors.

Next, the photoresist 43 is applied onto the passivation film 18, and further exposed to light (FIG. 4(C)), and the passivation film is removed by dry etching or wet etching using the photoresist 43 as a mask. One of the portions 18 partially exposes the source range 15 or the drain range 16 (Fig. 4(D)).

Next, the photoresist 43 is removed by wet etching (FIG. 4(E)), and a photo-lithography in which a photoresist is developed into a specific pattern through a conductor, for example, a PVD film through a metal, is used. The source wiring 19 or the drain wiring 20 (FIG. 4(F)) which is in contact with the partially exposed source range 15 or the drain range 16 is formed by etching of the photoresist and peeling of the photoresist. However, as the structure of the source wiring 19 or the drain wiring 20, a laminated structure of copper/molybdenum, a laminated structure of titanium/aluminum/titanium, or a laminated structure of molybdenum/aluminum/molybdenum can be applied.

Next, application of a photosensitive organic material, photolithography, development, and firing are performed to cover the source wiring 19 or the organic planarization film 21 of the drain wiring 20 (FIG. 4(G)), and further, The conductor, for example, a film of PVD through a metal, develops a photoresist as a photolithography of a specific pattern, and etches the developed photoresist and peels off the photoresist onto the organic planarization film 21. The pixel electrode 22 is formed (Fig. 4 (H)), and the present process is ended.

According to the manufacturing method of the TFT of FIGS. 3 and 4, the passivation film 18 of the IGZO film 40 partially exposed from the channel protective film 17 is mixed with barium fluoride gas and nitrogen gas, and the use contains no hydrogen. The concentration of the fluorine atom in the passivation film 18 becomes a fluorine atom in the channel protective film 17 due to the formation of the fluorine-containing tantalum nitride film formed by the plasma of the fluorine gas generated by the gas. The concentration is large. As a result, the concentration of the fluorine atoms constituting the IGZO film 40 of the source range 15 or the drain range 16 can be increased as compared with the channel 14, and therefore, the gate electrode 12 and the source can be prevented from being generated in the TFT 10. The parasitic capacitance caused by the overlap of the range 15 or the drain range 16 can be obtained at the same time. TFT characteristics.

In addition, the fluorine atom caused by the cesium fluoride gas diffuses in the channel 14 and ends the channel 14 and ends the unsaturated bond which is a defect, so that the characteristics or reliability of the IGZO constituting the channel 14 can be improved. By. The effect of diffusion of the fluorine atom through the method of manufacturing the TFT of FIGS. 3 and 4 is that even if hydrogen atoms are present in the IGZO film 40 as a trace amount, the influence is exceeded, and the existence of the hydrogen atom which cannot be removed is solved. The problem of instability of the device.

In the method of manufacturing the TFT of FIGS. 3 and 4 described above, the passivation film 18 is formed in the plasma CVD film forming apparatus 23, but the channel protective film 17 is formed by dry etching or wet etching (FIG. 3). (H)), or removal of the photoresist mask 41a via wet peeling or ashing (Fig. 4(A)) may also be carried out in the plasma CVD film forming apparatus 23. In particular, the formation of the channel protective film 17 is performed by dry etching, and the removal of the photoresist mask 41a is performed by ashing, and the dry etching or ashing is performed in a vacuum processing environment in the same manner as the plasma CVD film formation. For the sake of implementation, dry etching, ashing, and plasma CVD can be formed into a film, and the same processing chamber or a multi-processing chamber system under the same vacuum environment can be used for the same vacuum processing device, and the processing chamber can be further processed. Or the composition of the vacuum processing device is a simple constructor.

Further, in the method of manufacturing the TFT of FIGS. 3 and 4 described above, the IGZO film 40 exposed through the removal of the channel protective film 17 is covered until the passivation film 18 is applied, and the TFT 10 is continuously left in a vacuum environment. Therefore, the exposed IGZO film 40 is not out of the air (especially Contact with the atmosphere containing moisture, as a result, it is possible to prevent the occurrence of defects of the IGZO film 40 that adheres via moisture.

In the method of manufacturing the TFT of FIGS. 3 and 4 described above, the passivation film 18 is formed into a film, and a part of the passivation film 18 is removed to partially expose the source region 15 or the drain region 16 to form a source wiring. 19 or the drain wiring 20, and the organic planarizing film 21 is further formed, but after the film formation of the passivation film 18, a part of the passivation film 18 is removed, and the source wiring 19 or the gate wiring 20 is not formed, and a specific type is formed. The patterned organic planarizing film 21 is partially removed from the passivation film 18 by dry etching or wet etching using the organic planarizing film 21 as a mask, and partially exposes the source range 15 or the drain region 16 .

In this case, as shown in FIG. 5, the source wiring 19 or the drain wiring 20 which is in contact with the source range 15 or the drain range 16 is formed on the organic planarizing film 21, and the organic planarizing film 21 is further formed. The source wiring 19 or the drain wiring 20 is covered by the contact material 44, and the pixel electrode 22 is formed on the contact material 44. The organic EL portion 45 is disposed between the partially exposed drain wiring 20 and the pixel electrode 22, and the drain wiring 20 functions as a cathode electrode of the organic EL portion 45, and the pixel electrode 22 serves as an organic The anode electrode of the EL portion 45 functions.

Next, a TFT having a top gate type as a semiconductor device according to a second embodiment of the present invention will be described.

Fig. 6 is a cross-sectional view schematically showing the configuration of a TFT as a semiconductor device according to the present embodiment.

In Fig. 6, a plurality of TFTs 46 formed on a substrate 11 are provided with an undercoat layer 47 formed of yttrium oxide alone or a combination of yttrium oxide and tantalum nitride formed on the substrate 11, and formed on the undercoat layer. a channel 14 formed of IGZO, and a source range 15 and a drain range 16 formed on both sides of the channel 14, and a gate insulating film 48 (insulating film) covering the channel 14, and A gate electrode 49 formed on the gate insulating film 48, and a passivation film 18 (protective film) partially or completely covering the gate electrode 49 or the drain region 16 and the drain region 16 are formed and formed on the source a source line 19 that penetrates the passivation film 18 and is in contact with the source range 15 in the pole range 15 and a drain line 20 that is formed on the drain region 16 and that passes through the passivation film 18 and is in contact with the drain region 16, and The organic planarizing film 21 covering the source wiring 19 or the drain wiring 20 and the pixel electrode 22 covering the organic planarizing film 21 are covered. In other words, the TFT 46 has a laminated structure in which the channel 14, the gate insulating film 48, and the gate electrode 49 are laminated in this order from the bottom.

In the TFT 46, the width of the channel 14 or the gate insulating film 48 is reflected to reflect the width of the gate electrode 49 (specifically, the width of the channel 14 or the gate insulating film 48 is the same as the width of the gate electrode 49). Further, in the film formation system of the passivation film 18, the plasma CVD film forming apparatus 23 is preferably used in the same manner as in the first embodiment.

Next, a method of manufacturing the semiconductor device of the present embodiment will be described.

FIG. 7 and FIG. 8 are views showing a method of manufacturing a TFT according to the method of manufacturing the semiconductor device of the embodiment.

First, an undercoat layer 47 is formed on the substrate 11, and an IGZO film 40 (semiconductor film) is formed. However, at this time, the photoresist is developed into a specific pattern by film formation by PVD of IGZO. The lithography, the IGZO film 40 is partially formed on the undercoat layer 47 by etching using the developed photoresist and peeling off by the photoresist (Fig. 7(A)).

Next, the IGZO film 40 is coated by CVD, and the gate insulating film 53 made of yttrium oxide is formed into a film by the insulating film 53 and further passed through a metal (for example, copper/molybdenum, titanium/aluminum/titanium or molybdenum/aluminum In the film formation of PVD of /molybdenum), a gate metal film 50 covering the insulating film 53 for a gate insulating film is formed on the substrate 11 (Fig. 7(B)).

Next, the coated gate metal film 50 is entirely coated with a photoresist (not shown), and the light for exposure (not shown) is irradiated from the upper side (upper side of the laminated structure) to expose the photoresist. The photoresist mask 51a of a specific pattern is developed above the IGZO film 40 (FIG. 7(C)).

Next, the gate metal film 50 is selectively removed by dry etching or wet etching using the photoresist mask 51a as a mask, and the gate insulating film 53 is made to correspond to the photoresist mask 51a. In addition, it is partially exposed. At this time, only the gate metal film 50 covered by the photoresist mask 51a remains, and the remaining gate metal film 50 constitutes the gate electrode 49, but reflects the width of the gate electrode 49. The width of the photoresist mask 51a (specifically, the width of the gate electrode 49 is within the range of processing accuracy through the processing of the mask, and becomes the same as the width of the photoresist mask 51a) (FIG. 7 (FIG. 7) D)).

Moreover, after the gate insulating film 48 is exposed, the light is also continuously continued The resist mask 51a or the gate electrode 49 is dry-etched or wet-etched as a mask to remove a portion not covered by the mask of the insulating film 53 for a gate insulating film, so that the IGZO film 40 corresponds to the gate electrode. Except for 49, it is partially exposed (semiconductor film exposure step). At this time, only the gate insulating film 48 is formed by the insulating film 53 for the gate insulating film covered by the gate electrode 49, and the width of the gate insulating film 48 is reflected by the width of the gate electrode 49 (specifically In other words, the width of the gate insulating film 48 is the same as the width of the gate electrode 49 within the range of accuracy of processing through the photomask (Fig. 7(E)).

Then, the photoresist mask 51a is removed by wet peeling or ashing to expose the gate electrode 49 (FIG. 7(F)), and further, the plasma CVD film forming apparatus 23 is mixed with cesium fluoride gas. And the IGZO film 40 partially exposed by the passivation film 18 formed by the passivation film formed by the argon-containing cerium film which suppresses the presence of hydrogen atoms by CVD, and the like Gate electrode 49 (Fig. 7(G)) (protective film forming step).

Also in the present embodiment, as in the first embodiment, when the passivation film 18 is formed, the exposed IGZO film 40 is exposed to a plasma containing a fluorine gas, and the conductivity is increased. The IGZO film 40 which is covered by the gate electrode 49 and the gate insulating film 48 which functions as a photomask is not exposed to the plasma containing fluorine gas, and constitutes the source range 15 and the drain range 16. Compared with the exposed IGZO film 40, the conductivity is not increased to form the channel 14. In addition, the IGZO film 40 covered by the gate electrode 49 becomes the channel 14, and The width of the channel 14 reflects the width of the gate electrode 49 (specifically, the width of the channel 14 is within the range of processing accuracy through the reticle and becomes the same as the width of the gate electrode 49). However, in the present embodiment, as in the first embodiment, the fluorine atoms diffused from the passivation film 18 to the IGZO film 40 also enter the channel 14 to repair the defects of the channel 14.

Further, in the TFT 46, the width of the channel 14 existing between the source range 15 and the drain range 16 is the same as the width of the gate electrode 49, and the distance between the source range 15 and the drain range 16 is It is the same width as the gate electrode 49. Accordingly, in the TFT 46, the gate electrode 49 is not overlapped with the source range 15 or the drain range 16, and the occurrence of parasitic due to the overlap of the gate electrode 49 and the source range 15 or the drain region 16 can be prevented. The case of capacitors.

Next, the photoresist 43 is applied onto the passivation film 18, and further exposed for development (FIG. 7(H)), and the passivation film is removed by dry etching or wet etching using the photoresist 43 as a mask. One of the portions 18 partially exposes the source range 15 or the drain range 16 (Fig. 8(A)).

Next, the photoresist 43 is removed by wet peeling (FIG. 8(B)), and a film of PVD is formed through a conductor, for example, via a metal, and the photoresist is developed into a specific pattern of light lithography. The source wiring 19 or the drain wiring 20 (FIG. 8(C)) which is in contact with the partially exposed source range 15 or the drain range 16 is formed by etching of the photoresist and peeling of the photoresist.

Next, formation of a photosensitive organic material, photolithography, development, and firing to cover the source wiring 19 or the drain wiring 20 The planarizing film 21 (Fig. 8(D)), and further, through a conductor, for example, a film of PVD through a metal, the photoresist is developed into a specific pattern of light lithography, and the developed photoresist is used. The etching of the agent and the peeling of the photoresist remove the pixel electrode 22 on the organic planarizing film 21 (Fig. 8(E)), and the present process is terminated.

According to the manufacturing method of the TFT of FIGS. 7 and 8, the passivation film 18 of the IGZO film 40 partially exposed from the gate insulating film 48 is mixed with barium fluoride gas and nitrogen gas, and the use contains never contained. The argon-containing ytterbium nitride film formed by the plasma generated by the hydrogen processing gas is formed so that the concentration of the fluorine atom in the passivation film 18 becomes the fluorine atom in the gate insulating film 48. The concentration is high. As a result, the concentration of the fluorine atoms constituting the IGZO film 40 of the source range 15 or the drain range 16 can be increased as compared with the channel 14, and therefore, the gate electrode 12 and the source can be prevented from being generated in the TFT 10. In the case of the parasitic capacitance caused by the overlap of the range 15 or the drain range 16, at the same time, good TFT characteristics can be obtained. In addition, the fluorine atom caused by the cesium fluoride gas diffuses in the channel 14 and ends the channel 14 and ends the unsaturated bond which is a defect, so that the characteristics or reliability of the IGZO constituting the channel 14 can be improved. By.

In the method of manufacturing the TFT of FIGS. 7 and 8 described above, the passivation film 18 is formed in the plasma CVD film forming apparatus 23, but the gate insulating film 48 is formed by dry etching or wet etching (Fig. 7(E)), or removal of the photoresist mask 51a via wet peeling or ashing (Fig. 7(F)) may also be performed in the plasma CVD film forming apparatus 23. Further, the formation of the gate insulating film 48 is performed by dry etching, and the photoresist is applied via ashing. The removal of the mask 51a, dry etching or ashing is carried out in a vacuum processing environment in the same manner as the plasma CVD film formation, and dry etching, ashing, and plasma CVD can be formed into a film, in the same processing chamber. The vacuum processing apparatus of the same processing chamber system or the like in the same vacuum environment can be implemented to further simplify the configuration of the processing chamber or the vacuum processing apparatus while preventing the defects of the IGZO film 40 via moisture adhesion. Producer.

The present invention has been described above using various embodiments, but the present invention is not limited to the above embodiments.

For example, in the above-described embodiments, the IGZO film 40 is used as the semiconductor film. However, the semiconductor film is not limited thereto, and an oxide semiconductor film other than IGZO may be used. For example, ITZO, IGO, ZnO, or AZO may be used. A film composed of an oxide semiconductor containing at least zinc oxide as a constituent element. Further, in each of the above-described embodiments, a case where the window member 27 made of a dielectric body and the inductively coupled plasma device of the ICP antenna 26 other than the processing chamber 24 are used as the plasma CVD film forming apparatus will be described. However, the plasma CVD film forming apparatus to which the present invention is applicable is, for example, an inductively coupled plasma device for generating high-density plasma, and is not limited thereto, and for example, in an inductively coupled plasma device, a window member It may be composed of other materials than the dielectric, or the ICP antenna may be prepared in the processing chamber.

Further, an object of the present invention is to supply a memory medium for recording a program code of a software that realizes the functions of the above embodiments to a computer. For example, the controller 39 and the CPU of the controller 39 are also implemented by reading the code stored in the memory medium.

In this case, the code itself read from the memory medium becomes a function of the above-described embodiments, and the code and the memory medium in which the code is stored constitute the present inventors.

Further, as a memory medium for supplying a code, for example, a memory RAM, an NVRAM, a floppy disk (registered trademark), a hard disk, a magneto-optical disk, a CD-ROM, a CD-R, a CD-RW, a DVD ( The above-mentioned code of a disc, a magnetic tape, a non-volatile memory card, or other ROM such as a DVD-ROM, a DVD-RAM, a DVD-RW, or a DVD+RW may be used. Alternatively, the code may be supplied to the controller 39 when downloaded from an Internet, a commercial network, or another computer or database (not shown) connected to a local area network or the like.

Further, by executing the program code read by the controller 39, not only the functions of the above-described embodiments but also the OS (operation system) that is carried on the CPU according to the instruction of the program code are actually processed. Some or all of the functions of the above embodiments can be realized by the processing thereof.

Furthermore, the code read from the memory medium is written to the memory provided in the function expansion board of the controller 39 or the function expansion unit connected to the controller 39, and the code is based on the code. It is instructed that the CPU or the like provided in the function expansion board or the function expansion unit performs some or all of the actual processing, and the functions of the above-described embodiments are realized by the processing.

The form of the above code may be obtained from a target code, a code executed by a compiler, and a command code data supplied to the OS.

10‧‧‧TFT

11‧‧‧Substrate

12‧‧‧ gate electrode

13‧‧‧Gate insulation film

14‧‧‧ passage

15‧‧‧Source range

16‧‧‧Bunging area

17‧‧‧Channel protective film

18‧‧‧ Passivation film

19‧‧‧Source wiring

20‧‧‧汲polar wiring

21‧‧‧Organic flattening film

22‧‧‧pixel electrode

Claims (11)

A method of manufacturing a semiconductor device, comprising: a gate electrode; a semiconductor film formed of an oxide semiconductor; and a method of manufacturing a semiconductor device in which a laminated film of an insulating film is laminated on the semiconductor film, characterized in that: The gate electrode is used as a photomask, partially removing the insulating film, exposing the semiconductor film to a partially exposed semiconductor film, and mixing a hafnium halide gas and a nitrogen-containing gas, and never containing hydrogen. Processing a gas to generate plasma, at least exposing the exposed semiconductor film to the plasma, and protecting the exposed semiconductor film and the remaining insulating film by a protective film made of a halogen-containing tantalum nitride film Membrane forming step. In the method of forming a semiconductor device according to the first aspect of the invention, in the protective film forming step, a halogen atom is diffused from the protective film on the semiconductor film covered with the remaining insulating film. The method of manufacturing a semiconductor device according to the first or second aspect of the invention, wherein in the protective film forming step, an impedance ratio of a portion exposed to the plasma of the exposed semiconductor film is compared The resistivity of the portion of the semiconductor film covered by the insulating film is lowered. The method of manufacturing a semiconductor device according to the first or second aspect of the invention, wherein the exposed semiconductor film system constitutes a source In the range of the circumference and the drain, the semiconductor film covered by the remaining insulating film constitutes a channel, and the semiconductor device constitutes a thin transistor. The method of manufacturing a semiconductor device according to the first aspect or the second aspect of the present invention, wherein, in the laminated structure, the gate electrode, the semiconductor film, and the insulating film are laminated in the order from the lower side. In the semiconductor film exposure step, the insulating film is coated with a photoresist, and light for exposure is irradiated from below the laminated structure, and the photoresist is exposed and developed, and the semiconductor film is exposed. The insulating film is partially removed by etching using the photoresist developed as described above, and when the light for exposure is irradiated from below the laminated structure, the gate electrode is used as a mask. The width of the photoresist developed as described above reflects the width of the gate electrode. The method of manufacturing a semiconductor device according to the first or second aspect of the invention, wherein, in the laminated structure, the semiconductor film, the insulating film, and the gate electrode are laminated in the order from the lower side. In the semiconductor film exposure step, the insulating film is covered with a conductive film, the conductive film is coated with a photoresist, and the photoresist is exposed from the light above the laminated structure to expose the photoresist. For example, by using the photoresist as the photomask as described above, the conductive film is etched to form the gate electrode having a width reflecting the width of the photoresist, and further, by performing the above-described image formation Photoresist and the aforementioned shape The gate electrode is used as a photomask, and the insulating film is etched to form the insulating film having a width reflecting the width of the gate electrode. The method of manufacturing a semiconductor device according to the first or second aspect of the invention, wherein the oxide semiconductor is contained in at least zinc oxide as a constituent element. A manufacturing apparatus for a semiconductor device is a semiconductor device including a gate electrode, a semiconductor film formed of an oxide semiconductor, and a semiconductor device in which an insulating film is laminated on the semiconductor film, and the gate device is provided The electrode is used as a photomask, and the insulating film is partially removed, and the partially exposed semiconductor film and the remaining insulating film are mixed with a hafnium halide gas and a nitrogen-containing gas, and hydrogen is never contained. The protective film formed by the halogen-containing tantalum nitride film formed by the plasma generated by the gas is coated. A semiconductor device comprising a gate electrode, a semiconductor film formed of an oxide semiconductor, and a semiconductor device in which an insulating film is laminated on the semiconductor film, wherein the insulating film is partially removed. The semiconductor film is partially exposed, and the exposed semiconductor film is covered by at least a protective film, and the concentration of fluorine atoms in the protective film covering the exposed semiconductor film is higher than that of the fluorine atom in the insulating film. The concentration is high. The semiconductor device according to claim 9, wherein the semiconductor film covered by the remaining insulating film forms a channel, and after being exposed, the semiconductor film structure covered by the protective film In the range of the source and the drain, the semiconductor device is a thin transistor. The semiconductor device according to claim 9 or claim 10, wherein the oxide semiconductor is contained in at least zinc oxide as a constituent element.