JP2015176885A - Semiconductor device, method of manufacturing the same, and device of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing characteristic change of an oxide semiconductor and that has a low parasitic capacitance, and to provide a method of manufacturing the same.SOLUTION: A TFT 10 comprises a lamination structure in which a gate electrode 12, an IGZO film 40, and a channel protection film 17 are laminated from below. In the TFT 10, a channel protection film 17 is partially removed by utilizing as a mask a photoresist mask 41a having a width to which a width of the gate electrode 12 is reflected, and thereby, the IGZO film 40 is partially exposed (Fig. 3(H)). The exposed IGZO film 40 and the remaining channel protection film 17 are exposed to a plasma generated from a process gas in which a silicon fluoride gas and a nitrogen gas are mixed and that contains no hydrogen, and are covered with a passivation film 18 consisting of a fluorine-containing silicon nitride film (Fig. 4(B)). When the passivation film 18 is formed, fluorine atoms are dispersed from the passivation film 18 to the exposed IGZO film 40 to form a source region 15 and a drain region 16.

Description

  The present invention relates to a semiconductor device using an oxide semiconductor for a channel, a manufacturing method thereof, and a manufacturing apparatus thereof.

  Conventionally, LCD elements have been widely used in the field of flat panel displays, but in recent years, not only the use of LCD elements but also the use of organic EL (Electrouminescence) elements to realize sheet displays and next-generation thin televisions. It is out. An organic EL element is a self-luminous light-emitting element, and unlike a liquid crystal element, does not require a backlight, so that a thinner display can be realized.

  An organic EL element is a current-driven element, and it is necessary to realize a high-speed switching operation in a thin film transistor (TFT) applied to the organic EL element. Since amorphous silicon used does not have a high electron mobility, amorphous silicon is not suitable as a constituent material of a channel for organic EL.

Therefore, a TFT using an oxide semiconductor that can obtain high electron mobility for a channel has been proposed. As an oxide semiconductor used in such a TFT, for example, IGZO made of an oxide of indium (In), gallium (Ga), and zinc (Zn) is known (see, for example, Non-Patent Document 1). IGZO has a relatively high electron mobility (for example, 10 cm ² / (V · s) or more) even in an amorphous state. Therefore, when an oxide semiconductor such as IGZO is used for a TFT channel, high-speed switching operation is achieved. Can be realized. The application of an oxide semiconductor such as IGZO to a TFT channel is a technique that is highly effective not only for organic EL elements but also for LCD elements.

In addition, the TFT includes a channel protective film made of, for example, a silicon nitride (SiN) film in order to reliably protect the channel from external ions and moisture (see, for example, Patent Document 1). By the way, when a silicon nitride film is formed by plasma CVD (Chemical Vapor Deposition), silane (SiH ₄ ) is often used as a silicon source and ammonia (NH ₃ ) is often used as a nitrogen source. When a silicon nitride film is formed from ammonia and hydrogen, hydrogen radicals and hydrogen ions enter the silicon nitride film as hydrogen atoms, and the protective film generally contains a large amount of hydrogen atoms.

Hydrogen atoms contained in the protective film diffuse into the channel, and oxygen atoms in the IGZO are desorbed to change the characteristics of the IGZO, for example, the threshold voltage (Vth). Therefore, silicon oxide (SiO ₂ ) is formed above and below the channel. After covering with a film, it has been studied to improve the reliability of IGZO by forming a protective film of a channel made of a silicon nitride film and further applying heat treatment.

Japanese Patent No. 3148183

"Oxide semiconductor TFT for realizing light and thin sheet display", Kentaro Miura et al., Toshiba Review Vol. 67 No. 1 (2012)

  However, when IGZO is applied to an LCD element or an organic EL element in a semiconductor device in which hydrogen atoms exist in the silicon nitride film due to residual, intrusion of hydrogen atoms, or other reasons, the characteristics of IGZO due to the hydrogen atoms in the silicon nitride film It is difficult to prevent change.

  The objective of this invention is providing the semiconductor device which can prevent the characteristic change of an oxide semiconductor, its manufacturing method, and its manufacturing apparatus.

  In order to achieve the above object, a semiconductor device manufacturing method of the present invention includes a gate electrode, a semiconductor film made of an oxide semiconductor, and a semiconductor device manufacturing method including a stacked structure in which an insulating film is stacked on the semiconductor film. A step of exposing the semiconductor film by partially removing the insulating film by using the gate electrode as a mask; and a mixture of a silicon halide gas and a nitrogen-containing gas. A plasma is generated from a process gas not containing hydrogen, at least the exposed semiconductor film is exposed to the plasma, and the exposed semiconductor film and the remaining insulating film are formed of a protective film made of a halogen-containing silicon nitride film. And a protective film forming step for covering.

  In order to achieve the above object, a semiconductor device manufacturing apparatus of the present invention includes a gate electrode, a semiconductor film made of an oxide semiconductor, and a stacked structure in which an insulating film is stacked on the semiconductor film. The semiconductor film partially exposed by removing the insulating film partially using the gate electrode as a mask and the remaining insulating film contain a silicon halide gas and nitrogen. It is characterized by being covered with a protective film made of a halogen-containing silicon nitride film formed by plasma generated from a processing gas containing gas and not containing hydrogen.

  In order to achieve the above object, a semiconductor device of the present invention is a semiconductor device comprising a gate electrode, a semiconductor film made of an oxide semiconductor, and a stacked structure in which an insulating film is stacked on the semiconductor film, The film is partially removed to partially expose the semiconductor film, at least the exposed semiconductor film is covered with a protective film, and the concentration of fluorine atoms in the protective film covering the exposed semiconductor film is It is characterized by being higher than the concentration of fluorine atoms in the film.

  According to the present invention, the protective film covering the semiconductor film is composed of a halogen-containing silicon nitride film formed by using plasma generated from a processing gas not containing hydrogen, in which a silicon halide gas and a nitrogen-containing gas are mixed. Therefore, the inclusion of hydrogen atoms in the protective film is suppressed, and further, defects in the semiconductor film are repaired by halogen atoms diffusing into the semiconductor film due to the silicon halide gas, and the characteristics of the semiconductor oxide semiconductor Can be stabilized.

It is sectional drawing which shows roughly the structure of TFT as a semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows roughly the structure of the plasma CVD film-forming apparatus as a semiconductor device manufacturing apparatus concerning this Embodiment. It is process drawing of the manufacturing method of TFT as a manufacturing method of the semiconductor device which concerns on this Embodiment. It is process drawing of the manufacturing method of TFT as a manufacturing method of the semiconductor device which concerns on this Embodiment. It is sectional drawing which shows roughly the structure of the modification of TFT as a semiconductor device which concerns on this Embodiment. It is sectional drawing which shows roughly the structure of TFT as a semiconductor device which concerns on the 2nd Embodiment of this invention. It is process drawing of the manufacturing method of TFT as a manufacturing method of the semiconductor device which concerns on this Embodiment. It is process drawing of the manufacturing method of TFT as a manufacturing method of the semiconductor device which concerns on this Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  First, a bottom gate type thin transistor (TFT) as a semiconductor device according to the first embodiment of the present invention will be described.

  FIG. 1 is a cross-sectional view schematically showing a configuration of a TFT as a semiconductor device according to the present embodiment. For convenience, FIG. 1 shows not only the structure of the TFT but also the structure of the terminal portion manufactured simultaneously with the TFT (see the right side in the figure).

  In FIG. 1, a large number of TFTs 10 formed on a substrate 11 include a gate electrode 12 formed on the substrate 11, a gate insulating film 13 covering the gate electrode 12, and formed on the gate insulating film 13 and made of IGZO. The channel 14 (semiconductor film), the source region 15 and the drain region 16 formed on both sides of the channel 14, the channel protective film 17 (insulating film) covering the channel 14, all of the channel protective film 17 and the source region 15, a passivation film 18 (protective film) that partially covers the drain region 16, a source wiring 19 that is formed on the source region 15, passes through the passivation film 18, and contacts the source region 15, and the drain region 16 A drain wiring 20 formed above and contacting the drain region 16 through the passivation film 18 and a source wiring 19 It comprises an organic planarization layer 21 covering the drain wire 20, and a pixel electrode 22 which covers the organic planarization layer 21. That is, the TFT 10 has a stacked structure in which the gate electrode 12, the channel 14, and the channel protective film 17 are stacked in this order from below.

  The passivation film 18 is made of a fluorine-containing silicon nitride film, formed by CVD using plasma, the source region 15 and the drain region 16 are made of IGZO with increased conductivity (metallized), and the channel 14 or the channel protective film 17. The width of the gate electrode 12 reflects the width of the gate electrode 12 (specifically, the width of the channel 14 or the channel protective film 17 is the same as the width of the gate electrode 12 within an error range in photolithography).

  Next, a plasma CVD film forming apparatus as a semiconductor device manufacturing apparatus according to the present embodiment will be described. The present plasma CVD film forming apparatus is suitably used particularly when the passivation film 18 is formed.

  FIG. 2 is a cross-sectional view schematically showing a configuration of a plasma CVD film forming apparatus as a semiconductor device manufacturing apparatus according to the present embodiment.

  In FIG. 2, the plasma CVD film forming apparatus 23 has, for example, a substantially casing-shaped chamber 24 that houses the substrate 11 on which the TFT 10 is formed, and is placed at the bottom of the chamber 24 and places the substrate 11 on the top surface. A mounting table 25, an ICP antenna 26 disposed outside the chamber 24 so as to face the mounting table 25 inside the chamber 24, and a ceiling portion of the chamber 24 are configured, and between the mounting table 25 and the ICP antenna 26 And an intervening window member 27.

  The chamber 24 has an exhaust device (not shown), and the exhaust device evacuates the chamber 24 to decompress the inside of the chamber 24. The window member 27 of the chamber 24 is made of a dielectric, and partitions the inside and the outside of the chamber 24.

  The window member 27 is supported on the side wall of the chamber 24 via an insulating member (not shown), and the window member 27 and the chamber 24 are not in direct contact and are not electrically connected. The window member 27 has a size capable of covering at least the entire surface of the substrate 11 placed on the placement table 25. The window member 27 may be composed of a plurality of divided pieces.

  Three gas inlets 28, 29, and 30 are provided on the side wall of the chamber 24, and the gas inlet 28 is connected to a silicon halide gas supply unit 32 disposed outside the chamber 24 through a gas inlet pipe 31. The gas introduction port 29 is connected to the nitrogen-containing gas supply unit 34 disposed outside the chamber 24 through the gas introduction tube 33, and the gas introduction port 30 is disposed outside the chamber 24 through the gas introduction tube 35. The noble gas supply unit 36 is connected.

The silicon halide gas supply unit 32 supplies a silicon halide gas not containing hydrogen atoms, for example, silicon fluoride (SiF ₄ ) gas, into the chamber 24 through the gas inlet 28, and a nitrogen-containing gas supply unit. 34 supplies a nitrogen-containing gas not containing hydrogen atoms, for example, nitrogen (N ₂ ) gas, to the inside of the chamber 24 through the gas introduction port 29, and the rare gas supply unit 36 supplies the chamber through the gas introduction port 30. A rare gas, for example, an argon gas is supplied into the inside of 24. That is, the processing gas not containing hydrogen is supplied into the chamber 24 by mixing silicon fluoride gas and nitrogen gas. Note that the processing gas may contain a gas that does not contain hydrogen in addition to the silicon fluoride gas and the nitrogen gas, for example, a rare gas such as argon gas.

  Each gas introduction pipe 31, 33, 35 has a mass flow controller and a valve (both not shown), and adjusts the flow rate of each gas supplied from the gas introduction ports 28, 29, 30.

  The ICP antenna 26 is formed of an annular conductor disposed along the upper surface of the window member 27, and is connected to a high frequency power source 38 via a matching unit 37. The high frequency current from the high frequency power supply 38 flows through the ICP antenna 26, and the high frequency current causes the ICP antenna 26 to generate a magnetic field inside the chamber 24 through the window member 27. Since the magnetic field is generated due to the high-frequency current and changes with time, the time-changed magnetic field generates an induced electric field, and electrons accelerated by the induced electric field are introduced into the chamber 24. Inductively coupled plasma is generated by collision with gas molecules and atoms.

  The plasma CVD film forming apparatus 23 generates plasma from silicon fluoride gas or nitrogen gas supplied into the chamber 24 by inductively coupled plasma, and forms a fluorine-containing silicon nitride film by CVD, thereby forming a channel protective film. A passivation film 18 is formed to partially cover all 17, the source region 15, and the drain region 16. At this time, since neither silicon fluoride gas nor nitrogen gas contains hydrogen atoms, the fluorine-containing silicon nitride film forming the passivation film 18 does not contain hydrogen atoms resulting from the processing gas.

  On the other hand, since there is moisture in the chamber 24 due to environmental factors other than the processing gas such as a minute amount of moisture adsorbed on the substrate 11 when the substrate 11 is transported and moisture that has not been sufficiently removed by the exhaust device, Hydrogen atoms resulting from the moisture may be contained in a very small amount in the fluorine-containing silicon nitride film that forms the passivation film 18. That is, although the amount of hydrogen atoms contained in the passivation film 18 can be suppressed as much as possible (suppressing the presence of hydrogen atoms) by using a processing gas that does not contain hydrogen atoms, the amount still in the passivation film 18 is still extremely small. Of hydrogen atoms. Note that the main component of the fluorine-containing silicon nitride film to be formed is silicon nitride, and fluorine atoms generated by the decomposition of the silicon fluoride gas are dispersed in the silicon nitride.

  The Si—F bond in silicon fluoride gas and the NN bond in nitrogen gas have high bond energy (the former is 595 kJ / mol, the latter is 945 kJ / mol), but the inductively coupled plasma generated using the ICP antenna 26 has a density. Since it is very high, plasma can be generated from silicon fluoride gas or nitrogen gas having Si-F bond or NN bond.

  The argon gas supplied by the rare gas supply unit 36 is not a material gas that directly constitutes the silicon nitride film, but the silicon fluoride gas and the nitrogen gas that are directly constituting the silicon nitride film are adjusted to appropriate concentrations. Furthermore, it plays an auxiliary role in the film forming process, such as facilitating discharge for generating inductively coupled plasma.

  Further, the plasma CVD film forming apparatus 23 further includes a controller 39, and the controller 39 controls the operation of each component of the plasma CVD film forming apparatus 23.

The silicon halide gas not containing hydrogen atoms supplied by the silicon halide gas supply unit 32 is not limited to silicon fluoride gas, and may be other silicon halide gas, for example, silicon chloride (SiCl ₄ ). In addition, the nitrogen-containing gas supplied by the nitrogen-containing gas supply unit 34 is not limited to nitrogen gas, and may be other nitrogen-containing gas.

  Next, a method for manufacturing a semiconductor device according to the present embodiment will be described.

  3 and 4 are process diagrams of a TFT manufacturing method as a semiconductor device manufacturing method according to the present embodiment.

  First, metal (for example, copper (Cu) / molybdenum (Mo), titanium (Ti) / aluminum (Al) / titanium or molybdenum (Mo) / aluminum / molybdenum) PVD (Physical Vapor Deposition), photoresist A gate electrode 12 having a predetermined width is formed on the substrate 11 through photolithography for developing the substrate into a predetermined pattern, etching using the developed photoresist, and peeling of the photoresist (FIG. 3A).

  Next, a gate insulating film 13 made of silicon oxide is formed so as to cover the gate electrode 12 by CVD (FIG. 3B), and an IGZO film 40 (semiconductor film) is further formed. The width of the gate is set so as to cover the gate electrode 12 on the gate insulating film 13 through PVD film formation, photolithography for developing the photoresist into a predetermined pattern, etching using the developed photoresist, and stripping of the photoresist. An IGZO film 40 wider than the electrode 12 is partially formed (FIG. 3C).

  Next, a channel protective film insulating film 52 made of silicon oxide alone or a combination of silicon oxide and silicon nitride is formed so as to cover the IGZO film 40 by CVD (FIG. 3D), and further, the channel protective film insulating film is formed. A photoresist 41 is applied so as to cover the entire surface of the film 52 (FIG. 3E).

  Next, light 41 for exposure is irradiated from below in the drawing (below the laminated structure) to expose and develop the photoresist 41 (FIG. 3F). At this time, the gate electrode 12 functions as a mask in order to block the exposure light 42, and a part of the photoresist 41 that is shielded from the exposure light 42 by the gate electrode 12 (part not shown by hatching in the drawing). ) Is not exposed.

  Thereafter, the exposed photoresist 41 is dissolved and removed by the developer to expose the channel protective film insulating film 52, but a part of the photoresist 41 shielded from the ultraviolet light 42 by the gate electrode 12 is part of the developer. The width of the gate electrode 12 is reflected (specifically, the width is the same as the width of the gate electrode 12, but in photolithography, due to interference or refraction of light used for exposure) When transferring the width, some error may occur in the transferred width. In this embodiment and the second embodiment to be described later, “same width” is within the range of errors generated in the photoresist. A photoresist mask 41a having the same width is formed on the channel protective film insulating film 52 (FIG. 3G).

  Next, a portion of the channel protective film insulating film 52 that is not covered with the photoresist mask 41a is removed by dry etching or wet etching using the photoresist mask 41a as a mask, and the IGZO film 40 corresponds to the photoresist mask 41a. Exposed partially (Semiconductor film exposure step). At this time, only the channel protective film insulating film 52 in the portion covered by the photoresist mask 41a remains to form the channel protective film 17, and the width of the photoresist mask 41a is reflected in the width of the channel protective film 17. (Specifically, the width of the channel protective film 17 is the same as the width of the photoresist mask 41a) (FIG. 3H).

  Next, the photoresist mask 41a is removed by wet peeling or ashing to expose the channel protective film 17 (FIG. 4A), and in the plasma CVD film forming apparatus 23, silicon fluoride gas and nitrogen gas are mixed. And an IGZO film 40 partially exposed by a passivation film 18 made of a fluorine-containing silicon nitride film in which fluorine-containing plasma is generated from a processing gas not containing hydrogen and the presence of hydrogen atoms is suppressed by CVD. The film 17 is covered (FIG. 4B) (protective film forming step).

  When the passivation film 18 is formed, the exposed IGZO film 40 is exposed to the fluorine-containing plasma, so that the conductivity of the IGZO film 40 is increased and current flows easily. On the other hand, since the IGZO film 40 covered with the channel protective film 17 is not exposed to the fluorine-containing plasma, the conductivity does not increase as compared with the exposed IGZO film 40. That is, as shown in FIG. 4B, since the IGZO film 40 whose conductivity is not increased is sandwiched between the IGZO films 40 whose conductivity is increased, the IGZO film 40 whose conductivity is not increased constitutes the channel 14. The IGZO film 40 having increased conductivity constitutes the source region 15 and the drain region 16. Further, since the IGZO film 40 covered with the channel protective film 17 becomes the channel 14, the width of the channel 14 reflects the width of the channel protective film 17 (specifically, the width of the channel 14 is the channel protective film). It is the same as the width of 17).

  Note that the conductivity of all portions of the IGZO film 40 does not need to increase along the film thickness direction, and at least the surface resistivity only needs to be lower than the resistivity of other portions of the IGZO film 40.

  The conductivity of the exposed IGZO film 40 increases because fluorine radicals and the like existing in the plasma are selectively introduced only into the source region 15 and the drain region 16 in the IGZO film 40 and introduced into the IGZO film 40. This is because fluorine acts as a donor and the resistivity of the source region 15 and the drain region 16 into which fluorine is introduced is selectively reduced. In the TFT 10, fluorine atoms diffuse from the fluorine-containing silicon nitride film constituting the passivation film 18 into the channel 14 in the IGZO film 40, and terminate the dangling bonds that exist as defects in the channel 14. Thereby, the defect of the channel 14 that destabilizes the electrical characteristics of the TFT 10 is repaired, and the electrical characteristics of the TFT 10 are also improved.

  By the way, normally, in the TFT, when the gate electrode overlaps with the source electrode and the drain electrode, a parasitic capacitance is generated. If the parasitic capacitance is large, the voltage drop (ΔVp) from the time of driving the TFT to the time of voltage holding becomes large. Therefore, it is preferable to reduce the parasitic capacitance by suppressing the overlap of the gate electrode with the source electrode and the drain electrode.

  On the other hand, in the TFT 10, when the passivation film 18 is formed, the source region 15 and the drain region 16 are formed by exposing the IGZO film 40 not covered with the channel protective film 17 to plasma. The width of the channel 14 existing between the source region 15 and the drain region 16 is the same as the width of the channel protective film 17, the width of the channel protective film 17 is the same as the width of the photoresist mask 41a, and the photoresist The width of the mask 41 a is the same as the width of the gate electrode 12. That is, since the width of the channel 14 is the same as the width of the gate electrode 12, the distance between the source region 15 and the drain region 16 is the same as the width of the gate electrode 12. Therefore, in the TFT 10, the gate electrode 12 does not overlap with the source region 15 and the drain region 16, and it is possible to prevent the parasitic capacitance caused by the overlap between the gate electrode 12 and the source region 15 and the drain region 16. it can.

  Next, a photoresist 43 is applied on the passivation film 18, further exposed and developed (FIG. 4C), and a part of the passivation film 18 is removed by dry etching or wet etching using the photoresist 43 as a mask. Then, the source region 15 and the drain region 16 are partially exposed (FIG. 4D).

  Next, the photoresist 43 is removed by wet etching (FIG. 4E), and a conductor, for example, metal PVD film formation, photolithography for developing the photoresist into a predetermined pattern, and the developed photoresist are used. A source wiring 19 and a drain wiring 20 which are in contact with the partially exposed source region 15 and drain region 16 through etching and photoresist stripping are formed (FIG. 4F). As the structure of the source wiring 19 and the drain wiring 20, a copper / molybdenum laminated structure, a titanium / aluminum / titanium laminated structure, a molybdenum / aluminum / molybdenum laminated structure, or the like can be applied.

  Next, an organic planarization film 21 that covers the source wiring 19 and the drain wiring 20 is formed through application of a photosensitive organic material, photolithography, development, and baking (FIG. 4G), and a conductor, for example, a metal PVD A pixel electrode 22 is formed on the organic planarizing film 21 through film formation by photolithography, photolithography for developing the photoresist into a predetermined pattern, etching using the developed photoresist, and stripping of the photoresist (FIG. 4H) ), This process is terminated.

  3 and 4, the passivation film 18 covering the IGZO film 40 partially exposed from the channel protective film 17 is mixed with silicon fluoride gas and nitrogen gas and does not contain hydrogen. Since the fluorine-containing silicon nitride film is formed by using plasma containing fluorine generated from the processing gas, the concentration of fluorine atoms in the passivation film 18 is higher than the concentration of fluorine atoms in the channel protective film 17. As a result, the concentration of fluorine atoms in the IGZO film 40 constituting the source region 15 and the drain region 16 can be increased as compared with the channel 14, so that the gate electrode 12, the source electrode 15, and the drain electrode 16 in the TFT 10. It is possible to obtain good TFT characteristics while preventing the occurrence of parasitic capacitance due to the superposition of.

  Further, since fluorine atoms resulting from the silicon fluoride gas diffuse into the channel 14 and terminate dangling bonds existing as defects in the channel 14, the characteristics and reliability of the IGZO constituting the channel 14 can be improved. . The effect of fluorine atom diffusion in the TFT manufacturing method of FIG. 3 and FIG. 4 exceeds the effect even if a small amount of hydrogen atoms are present in the IGZO film 40, and the effect of the device due to the presence of hydrogen atoms that cannot be completely removed. Solve the problem of destabilization.

  In the TFT manufacturing method of FIGS. 3 and 4 described above, the passivation film 18 is formed in the plasma CVD film forming apparatus 23. However, the channel protective film 17 is formed by dry etching or wet etching (FIG. 3 (H)), The removal of the photoresist mask 41a by wet peeling or ashing (FIG. 4A) may also be performed in the plasma CVD film forming apparatus 23. In particular, when the channel protective film 17 is formed by dry etching and the photoresist mask 41a is removed by ashing, the dry etching and ashing are performed in a vacuum processing environment in the same manner as the plasma CVD film formation. , Dry etching, ashing and plasma CVD film formation can be performed in the same chamber or the same vacuum processing apparatus such as a multi-chamber system in the same vacuum environment, and the configuration of the chamber and the vacuum processing apparatus can be simplified. Can be made.

  3 and 4 described above, the TFT 10 continues to remain in a vacuum environment until the IGZO film 40 exposed by the removal of the channel protective film 17 is covered with the passivation film 18, so that the exposed IGZO is exposed. The film 40 does not come into contact with the outside air (in particular, the atmosphere containing moisture), and as a result, generation of defects in the IGZO film 40 due to adhesion of moisture can be prevented.

  In the TFT manufacturing method of FIGS. 3 and 4 described above, the passivation film 18 is formed, a part of the passivation film 18 is removed and the source region 15 and the drain region 16 are partially exposed, and then the source wiring is formed. 19 and the drain wiring 20 are formed, and the organic planarization film 21 is further formed. However, after the passivation film 18 is formed, the source wiring 19 and the drain wiring 20 are not removed without removing a part of the passivation film 18. The organic planarization film 21 having a predetermined pattern is formed without forming a portion of the passivation film 18, and a part of the passivation film 18 is removed by dry etching or wet etching using the organic planarization film 21 as a mask. Region 16 may be partially exposed.

  In this case, as shown in FIG. 5, the source wiring 19 and the drain wiring 20 that are in contact with the source region 15 and the drain region 16 are formed on the organic planarization film 21, and the organic planarization film 21 and the source wiring 19 are further formed. The drain wiring 20 is covered with the bank material 44, and the pixel electrode 22 is formed on the bank material 44. An organic EL portion 45 is disposed between the drain wiring 20 and the pixel electrode 22 that are partially exposed. The drain wiring 20 functions as a cathode electrode of the organic EL portion 45, and the pixel electrode 22 is an anode electrode of the organic EL portion 45. Function as.

  Next, a top gate type TFT as a semiconductor device according to a second embodiment of the present invention will be described.

  FIG. 6 is a cross-sectional view schematically showing a configuration of a TFT as a semiconductor device according to the present embodiment.

  In FIG. 6, a large number of TFTs 46 formed on the substrate 11 are formed on the undercoat layer 47 made of silicon oxide alone or a combination of silicon oxide and silicon nitride formed on the substrate 11, and on the undercoat layer 47. A channel 14 made of IGZO, a source region 15 and a drain region 16 formed on both sides of the channel 14, a gate insulating film 48 (insulating film) covering the channel 14, and a gate formed on the gate insulating film 48 An electrode 49, a passivation film 18 (protective film) that partially covers all of the gate electrode 49, the source region 15, and the drain region 16, and a source region 15 that penetrates the passivation film 18 and is formed on the source region 15. Formed on the drain region 16 and the source wiring 19 in contact with the drain, penetrating the passivation film 18 and draining It comprises a drain wiring 20 in contact with the region 16, the organic planarization layer 21 to cover the source wiring 19 and drain wiring 20, and a pixel electrode 22 which covers the organic planarization layer 21. That is, the TFT 46 has a stacked structure in which the channel 14, the gate insulating film 48, and the gate electrode 49 are stacked in this order from the bottom.

  In the TFT 46, the width of the channel 14 and the gate insulating film 48 reflects the width of the gate electrode 49 (specifically, the width of the channel 14 and the gate insulating film 48 is the same as the width of the gate electrode 49). In addition, as in the case of the first embodiment, a plasma CVD film forming apparatus 23 is suitably used for forming the passivation film 18.

  Next, a method for manufacturing a semiconductor device according to the present embodiment will be described.

  7 and 8 are process diagrams of a TFT manufacturing method as a semiconductor device manufacturing method according to the present embodiment.

  First, an undercoat layer 47 is formed on the substrate 11, and further an IGZO film 40 (semiconductor film) is formed. At this time, film formation by PVD of IGZO, photolithography for developing a photoresist into a predetermined pattern, An IGZO film 40 is partially formed on the undercoat layer 47 through etching using the developed photoresist and peeling of the photoresist (FIG. 7A).

  Next, an insulating film 53 for gate insulating film made of silicon oxide is formed so as to cover the IGZO film 40 by CVD, and a metal (for example, copper / molybdenum, titanium / aluminum / titanium or molybdenum / aluminum / molybdenum) is formed. A gate metal film 50 covering the gate insulating film insulating film 53 is formed on the substrate 11 through film formation by PVD (FIG. 7B).

  Next, a photoresist (not shown) is applied so as to cover the entire surface of the gate metal film 50, and exposure light (not shown) is irradiated from above in the figure (above the laminated structure) to expose the photoresist. A photoresist mask 51a having a predetermined pattern is developed above the IGZO film 40 (FIG. 7C).

  Next, the gate metal film 50 is selectively removed by dry etching or wet etching using the photoresist mask 51a as a mask, so that the gate insulating film insulating film 53 is partially exposed except for the portion corresponding to the photoresist mask 51a. . At this time, only the gate metal film 50 in the portion covered with the photoresist mask 51a remains, and the remaining gate metal film 50 constitutes the gate electrode 49. The width of the gate electrode 49 includes the width of the photoresist mask 51a. (Specifically, the width of the gate electrode 49 is the same as the width of the photoresist mask 51a within the range of the processing accuracy of the mask) (FIG. 7D).

  Further, after the gate insulating film 48 is exposed, dry etching or wet etching using the photoresist mask 51a or the gate electrode 49 as a mask is continued to remove a portion of the gate insulating film insulating film 53 that is not covered with the mask. Then, the IGZO film 40 is partially exposed at a portion other than the portion corresponding to the gate electrode 49 (semiconductor film exposure step). At this time, only the gate insulating film insulating film 53 in the portion covered by the gate electrode 49 remains to form the gate insulating film 48, and the width of the gate insulating film 48 reflects the width of the gate electrode 49 ( Specifically, the width of the gate insulating film 48 is the same as the width of the gate electrode 49 within the range of the processing accuracy by the mask) (FIG. 7E).

  Next, the photoresist mask 51a is removed by wet peeling or ashing to expose the gate electrode 49 (FIG. 7F), and in the plasma CVD film forming apparatus 23, silicon fluoride gas and nitrogen gas are mixed, Further, plasma is generated from a processing gas not containing hydrogen, and the IGZO film 40 and the gate electrode 49 partially exposed by the passivation film 18 made of a fluorine-containing silicon nitride film in which the presence of hydrogen atoms is suppressed by CVD are covered (FIG. 7 (G)) (protective film formation step).

  Also in the present embodiment, as in the first embodiment, when the passivation film 18 is formed, the exposed IGZO film 40 is exposed to the plasma containing fluorine gas, so that the conductivity is increased and the source region 15 is increased. Since the IGZO film 40 that constitutes the drain region 16 and is covered with the gate electrode 49 and the gate insulating film 48 functioning as a mask is not exposed to the plasma containing fluorine gas, the conductivity is higher than that of the exposed IGZO film 40. Instead, the channel 14 is configured. Further, since the IGZO film 40 covered with the gate electrode 49 becomes the channel 14, the width of the channel 14 reflects the width of the gate electrode 49 (specifically, the width of the channel 14 depends on the processing accuracy by the mask). Within the range, it becomes the same as the width of the gate electrode 49). In the present embodiment, as in the first embodiment, fluorine atoms diffused from the passivation film 18 to the IGZO film 40 also enter the channel 14 to repair the defects in the channel 14.

  In the TFT 46, the width of the channel 14 existing between the source region 15 and the drain region 16 is the same as the width of the gate electrode 49, so that the distance between the source region 15 and the drain region 16 is the width of the gate electrode 49. Is the same. Therefore, in the TFT 46, the gate electrode 49 does not overlap with the source region 15 and the drain region 16, and it is possible to prevent the parasitic capacitance caused by the overlap between the gate electrode 49 and the source region 15 and the drain region 16. it can.

  Next, a photoresist 43 is applied on the passivation film 18, further exposed and developed (FIG. 7H), and a part of the passivation film 18 is removed by dry etching or wet etching using the photoresist 43 as a mask. Then, the source region 15 and the drain region 16 are partially exposed (FIG. 8A).

  Next, the photoresist 43 is removed by wet peeling (FIG. 8B), and a conductor, for example, metal PVD film formation, photolithography for developing the photoresist into a predetermined pattern, and the developed photoresist are used. A source wiring 19 and a drain wiring 20 are formed in contact with the partially exposed source region 15 and drain region 16 through etching and stripping of the photoresist (FIG. 8C).

  Next, an organic planarization film 21 that covers the source wiring 19 and the drain wiring 20 is formed through application of a photosensitive organic material, photolithography, development, and baking (FIG. 8D), and further, a conductor, for example, a PVD of a metal A pixel electrode 22 is formed on the organic planarizing film 21 through film formation by photolithography, photolithography for developing the photoresist into a predetermined pattern, etching using the developed photoresist, and peeling of the photoresist (FIG. 8E). ), This process is terminated.

  7 and 8, the passivation film 18 covering the IGZO film 40 partially exposed from the gate insulating film 48 is a mixture of silicon fluoride gas and nitrogen gas and does not contain hydrogen. Since the fluorine-containing silicon nitride film is formed using plasma generated from the processing gas, the concentration of fluorine atoms in the passivation film 18 is higher than the concentration of fluorine atoms in the gate insulating film 48. As a result, the concentration of fluorine atoms in the IGZO film 40 constituting the source region 15 and the drain region 16 can be increased as compared with the channel 14, so that the gate electrode 12, the source electrode 15, and the drain electrode 16 in the TFT 10. It is possible to obtain good TFT characteristics while preventing the occurrence of parasitic capacitance due to the superposition of. Further, since fluorine atoms resulting from the silicon fluoride gas diffuse into the channel 14 and terminate dangling bonds existing as defects in the channel 14, the characteristics and reliability of the IGZO constituting the channel 14 can be improved. .

  In the TFT manufacturing method of FIGS. 7 and 8 described above, the passivation film 18 is formed in the plasma CVD film forming apparatus 23. However, the formation of the gate insulating film 48 by dry etching or wet etching (FIG. 7E) or The removal of the photoresist mask 51a by wet peeling or ashing (FIG. 7F) may also be performed in the plasma CVD film forming apparatus 23. In addition, when the gate insulating film 48 is formed by dry etching and the photoresist mask 51a is removed by ashing, the dry etching and ashing are performed in a vacuum processing environment in the same manner as the plasma CVD film formation. , Dry etching, ashing and plasma CVD film formation can be performed in the same chamber or the same vacuum processing apparatus such as a multi-chamber system in the same vacuum environment, and the configuration of the chamber and the vacuum processing apparatus can be simplified. In addition, the generation of defects in the IGZO film 40 due to the adhesion of moisture can be prevented.

  As mentioned above, although this invention was demonstrated using each embodiment, this invention is not limited to each embodiment mentioned above.

  For example, in each of the above-described embodiments, the IGZO film 40 is used as the semiconductor film. However, the semiconductor film is not limited to this, and an oxide semiconductor film other than IGZO, for example, at least oxidation of ITZO, IGO, ZnO, AZO, or the like. A film formed using an oxide semiconductor containing zinc as a constituent element may be used. In each of the above-described embodiments, the case where an inductively coupled plasma apparatus including a dielectric window member 27 and an ICP antenna 26 outside the chamber 24 is used as the plasma CVD film forming apparatus has been described. The plasma CVD film forming apparatus to which the present invention is applicable is not limited to this as long as it is an inductively coupled plasma apparatus that generates high-density plasma. For example, in an inductively coupled plasma apparatus, a window member other than a dielectric is used. It may be composed of other materials, or an ICP antenna may be provided in the chamber.

  Another object of the present invention is to supply a computer, for example, the controller 39, with a storage medium that records software program codes for realizing the functions of the above-described embodiments, and the CPU of the controller 39 is stored in the storage medium. It is also achieved by reading and executing the program code.

  In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the program code and the storage medium storing the program code constitute the present invention.

  Examples of the storage medium for supplying the program code include RAM, NV-RAM, floppy (registered trademark) disk, hard disk, magneto-optical disk, CD-ROM, CD-R, CD-RW, DVD (DVD). -ROM, DVD-RAM, DVD-RW, DVD + RW) and other optical disks, magnetic tapes, non-volatile memory cards, other ROMs, etc., as long as they can store the program code. Alternatively, the program code may be supplied to the controller 39 by downloading from another computer or database (not shown) connected to the Internet, a commercial network, a local area network, or the like.

  Further, by executing the program code read by the controller 39, not only the functions of the above-described embodiments are realized, but also an OS (operating system) running on the CPU based on an instruction of the program code. ) Etc. perform part or all of actual processing, and the functions of the above-described embodiments are realized by the processing.

  Further, after the program code read from the storage medium is written in the memory provided in the function expansion board inserted into the controller 39 or the function expansion unit connected to the controller 39, the program code is read based on the instruction of the program code. A case where the CPU of the function expansion board or the function expansion unit performs part or all of the actual processing and the functions of the above-described embodiments are realized by the processing is also included.

  The form of the program code may include an object code, a program code executed by an interpreter, script data supplied to the OS, and the like.

10,46 TFT
12, 49 Gate electrode 14 Channel 15 Source region 16 Drain region 17 Channel protective film 18 Passivation film 23 Plasma CVD film forming apparatus 40 IGZO film 48 Gate insulating film

Claims (11)

A semiconductor device comprising a gate electrode, a semiconductor film made of an oxide semiconductor, and a stacked structure in which an insulating film is stacked on the semiconductor film,
A semiconductor film exposing step of partially exposing the semiconductor film by partially removing the insulating film using the gate electrode as a mask;
A plasma is generated from a processing gas containing a mixture of a silicon halide gas and a nitrogen-containing gas and not containing hydrogen, exposing at least the exposed semiconductor film to the plasma, and exposing the exposed semiconductor film and the remaining insulating film. And a protective film forming step of covering with a protective film made of a halogen-containing silicon nitride film.   2. The method of manufacturing a semiconductor device according to claim 1, wherein in the protective film forming step, halogen atoms are diffused from the protective film into the semiconductor film covered with the remaining insulating film.   2. The protective film forming step, wherein a resistivity of a portion of the exposed semiconductor film exposed to the plasma is made lower than a resistivity of a portion of the semiconductor film covered with the insulating film. Or the manufacturing method of the semiconductor device of 2.   4. The exposed semiconductor film constitutes a source region and a drain region, the semiconductor film covered with the remaining insulating film constitutes a channel, and the semiconductor device constitutes a thin transistor. The manufacturing method of the semiconductor device of any one of these. In the stacked structure, the gate electrode, the semiconductor film and the insulating film are stacked in this order from below,
Prior to the semiconductor film exposure step, the insulating film is covered with a photoresist, and the photoresist is exposed and developed by irradiating exposure light from below the laminated structure,
In the semiconductor film exposing step, the insulating film is partially removed by etching using the developed photoresist,
The width of the gate electrode is reflected in the width of the developed photoresist by using the gate electrode as a mask when the exposure light is irradiated from below the laminated structure. 5. A method for manufacturing a semiconductor device according to any one of 4 above. In the stacked structure, the semiconductor film, the insulating film and the gate electrode are stacked in this order from below.
Prior to the semiconductor film exposure step, the insulating film is covered with a conductive film, the conductive film is covered with a photoresist, and the photoresist is exposed and developed by irradiating exposure light from above the stacked structure, The gate electrode having a width reflecting the width of the photoresist is formed by etching the conductive film using the developed photoresist as a mask, and further, the developed photoresist and the 5. The insulating film having a width reflecting the width of the gate electrode is formed by etching the insulating film using the formed gate electrode as a mask. A method for manufacturing a semiconductor device according to claim 1.   The method for manufacturing a semiconductor device according to claim 1, wherein the oxide semiconductor contains at least zinc oxide as a constituent element. A semiconductor device manufacturing apparatus comprising a gate electrode, a semiconductor film made of an oxide semiconductor, and a stacked structure in which an insulating film is stacked on the semiconductor film,
By partially removing the insulating film using the gate electrode as a mask, the partially exposed semiconductor film and the remaining insulating film are mixed with a silicon halide gas and a nitrogen-containing gas. An apparatus for manufacturing a semiconductor device, which is covered with a protective film made of a halogen-containing silicon nitride film formed by plasma generated from a processing gas not containing hydrogen. A semiconductor device comprising a gate electrode, a semiconductor film made of an oxide semiconductor, and a stacked structure in which an insulating film is stacked on the semiconductor film,
The insulating film is partially removed and the semiconductor film is partially exposed;
At least the exposed semiconductor film is covered with a protective film;
A semiconductor device, wherein a concentration of fluorine atoms in a protective film covering the exposed semiconductor film is higher than a concentration of fluorine atoms in the insulating film.   The semiconductor film covered with the remaining insulating film constitutes a channel, the semiconductor film covered with the protective film after being exposed constitutes a source region and a drain region, and the semiconductor device constitutes a thin transistor. The semiconductor device according to claim 9.   The semiconductor device according to claim 9 or 10, wherein the oxide semiconductor contains at least zinc oxide as a constituent element.

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