CN108288652B - Thin film transistor, manufacturing method thereof, array substrate and display panel - Google Patents
Thin film transistor, manufacturing method thereof, array substrate and display panel Download PDFInfo
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- CN108288652B CN108288652B CN201810186748.3A CN201810186748A CN108288652B CN 108288652 B CN108288652 B CN 108288652B CN 201810186748 A CN201810186748 A CN 201810186748A CN 108288652 B CN108288652 B CN 108288652B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
Abstract
The invention provides a thin film transistor, a manufacturing method thereof, an array substrate and a display panel. The preparation method of the thin film transistor comprises the following steps: forming a channel region of a thin film transistor; and processing the channel region to form a cavity layer on the surface of the channel region. Wherein processing the channel region comprises: in the chemical vapor deposition equipment, borane plasma is adopted to treat the surface of the channel region, and a hole layer with positive charge holes is formed on the surface of the channel region. The thin film transistor includes a channel region having a hole layer formed on a surface thereof. Wherein the hole layer has positively charged holes formed therein. According to the invention, the hole layer is formed on the surface of the channel region, and the hole unit with positive charges in the hole layer is compounded with the electrons transferred to the surface of the channel region, so that a current channel possibly formed on the surface of the channel region is avoided, the leakage current is effectively reduced, and the characteristics of the thin film transistor are improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a thin film transistor, a manufacturing method thereof, an array substrate and a display panel.
Background
In the field of flat panel Display technology, Thin Film Transistor Liquid Crystal displays (TFT-LCDs) have the characteristics of small size, low power consumption, no radiation, relatively low manufacturing cost, and the like, and are increasingly used in the field of high-performance Display. The main structure of the TFT-LCD comprises an array substrate and a color film substrate which are paired, wherein the array substrate comprises a plurality of pixel units which are arranged in a matrix mode, the pixel units are vertically crossed and limited by a plurality of grid lines and a plurality of data lines, and the thin film transistor is arranged at the crossed position of the grid lines and the data lines.
The thin film transistor includes a gate electrode, an active layer, a source electrode, and a drain electrode, wherein the active layer includes a source region contacting the source electrode, a drain region contacting the drain electrode, and a channel region between the source region and the drain region. When the thin film transistor is in an on state, a channel region of the active layer is changed from a semiconductor state to a conductor state, forming a conductive channel.
The leakage current (Ioff) characteristic is an important parameter of the thin film transistor, and if it is too large, it affects the switching characteristics of the thin film transistor, thereby causing defects such as display unevenness, white, gray, dirt, crosstalk (cross talk) on the display screen of the TFT-LCD. At present, in the prior art, the leakage current of the thin film transistor is generally reduced by reducing the channel width to length ratio, but reducing the channel width to length ratio can reduce the on current (Ion) of the thin film transistor, so that the current solution for reducing the leakage current of the thin film transistor has an unsatisfactory effect.
Therefore, how to effectively reduce the leakage current of the thin film transistor is an urgent technical problem to be solved in the field.
Disclosure of Invention
The technical problem to be solved by the embodiments of the present invention is to provide a thin film transistor, a method for manufacturing the thin film transistor, an array substrate, and a display panel, so as to effectively reduce a leakage current of the thin film transistor.
In order to solve the above technical problem, an embodiment of the present invention provides a method for manufacturing a thin film transistor, including:
forming a channel region of a thin film transistor;
and processing the channel region to form a cavity layer on the surface of the channel region.
Optionally, processing the channel region to form a hole layer on a surface of the channel region includes:
in the chemical vapor deposition equipment, borane plasma is adopted to treat the surface of the channel region, and a hole layer with positive charge holes is formed on the surface of the channel region.
Optionally, the hole layer has a thickness of 0.1nm to 1.0 nm.
Optionally, the gas flow of the borane plasma is 100sccm to 500sccm, the gas pressure is 50Pa to 200Pa, and the processing time is 10s to 50 s.
Optionally, the electrode distance between the surface of the channel region and the chemical vapor deposition equipment is 50 mm-300 mm, the power of the chemical vapor deposition equipment is 1000W-8000W, and the current is 5A-50A.
In order to solve the above technical problem, an embodiment of the present invention further provides a thin film transistor, including a channel region, where a hole layer is formed on a surface of the channel region.
Optionally, the hole layer has a thickness of 0.1nm to 1.0 nm.
Optionally, positively charged holes are formed in the hole layer.
The embodiment of the invention also provides an array substrate which comprises the thin film transistor.
The embodiment of the invention also provides a display panel which comprises the array substrate.
According to the thin film transistor and the manufacturing method thereof, the array substrate and the display panel provided by the embodiment of the invention, the hole layer is formed on the surface of the channel region, and the hole layer is compounded with the electrons transferred to the surface of the channel region by using the holes with positive charges in the hole layer, so that a current channel possibly formed on the surface of the channel region is avoided, the leakage current is effectively reduced, and the characteristics of the thin film transistor are improved.
Of course, not all of the advantages described above need to be achieved at the same time in the practice of any one product or method of the invention. Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the embodiments of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention. The shapes and sizes of the various elements in the drawings are not to scale and are merely intended to illustrate the invention.
FIG. 1 is a flow chart of a method of fabricating a thin film transistor according to the present invention;
FIG. 2 is a schematic diagram illustrating a gate structure layer after patterning according to a first embodiment of the present invention;
FIG. 3 is a schematic view illustrating an active layer pattern according to a first embodiment of the present invention;
fig. 4 is a schematic view after forming a source electrode and a drain electrode pattern according to the first embodiment of the present invention;
FIG. 5 is a schematic view illustrating a surface treatment of a channel region according to a first embodiment of the present invention;
FIG. 6 is a diagram illustrating a passivation layer pattern formed according to a second embodiment of the present invention;
fig. 7 is a diagram illustrating a pixel electrode pattern formed according to a second embodiment of the invention.
Description of reference numerals:
10-a substrate; 11-a gate electrode; 12-a gate insulating layer;
13-an active layer; 14-a source electrode; 15-a drain electrode;
16-a passivation layer; 17-pixel electrodes; 20-a hole layer.
Detailed Description
The following detailed description of embodiments of the invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
The inventor of the present application finds that the reason for forming the leakage current Ioff for the conventional channel region etching type thin film transistor is as follows: because the surface of the channel region is damaged by plasma in etching, when the thin film transistor is in an off state, electrons are completely transferred to the surface of the channel region under the influence of an electric field, and at the moment, if a voltage difference exists between the source electrode and the drain electrode, the electrons transferred to the surface of the channel region form a current channel, so that a leakage current Ioff is formed.
The technical solution of the embodiment of the present invention is explained in detail by the specific embodiment below.
First embodiment
In order to effectively reduce the leakage current of the thin film transistor, the present embodiment provides a solution for forming a hole layer on the surface of the channel region. Fig. 1 is a flowchart of a method for manufacturing a thin film transistor according to the present invention, and as shown in fig. 1, the method for manufacturing a thin film transistor includes:
s1, forming a channel region of the thin film transistor;
and S2, processing the channel region to form a hole layer on the surface of the channel region.
According to the preparation method of the thin film transistor, the hole layer is formed on the surface of the channel region, and the hole layer is compounded with the electrons transferred to the surface of the channel region by using the positive holes in the hole layer, so that a current channel possibly formed on the surface of the channel region is avoided, the leakage current is effectively reduced, and the characteristics of the thin film transistor are improved.
Wherein, step S2 includes: in the chemical vapor deposition equipment, borane plasma is adopted to treat the surface of the channel region, and a hole layer with positive charge holes is formed on the surface of the channel region. Preferably, the thickness of the hole layer is 0.1nm to 1.0 nm.
When the surface of the channel region is processed, the gas flow of the borane plasma is 100 sccm-500 sccm, the gas pressure is 50 Pa-200 Pa, and the processing time is 10 s-50 s.
When the surface of the channel region is treated, the electrode distance between the surface of the channel region and the chemical vapor deposition equipment is 50-300 mm, the power of the chemical vapor deposition equipment is 1000-8000W, and the current is 5-50A.
The technical solution of the present embodiment is further described by the manufacturing process of the thin film transistor.
Fig. 2 to 7 are schematic diagrams illustrating a thin film transistor according to a first embodiment of the present invention. The "patterning process" in the embodiment of the present invention includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, and is a mature preparation process. The deposition may be performed by a known process such as sputtering, evaporation, chemical vapor deposition, etc., the coating may be performed by a known coating process, and the etching may be performed by a known method, which is not particularly limited herein.
In the first patterning process, a gate structure layer is formed on the substrate through a patterning process, wherein the gate structure layer includes a gate electrode, a gate line (not shown), and a gate insulating layer. The forming of the gate structure layer includes: a gate metal film is deposited on a substrate 10, a layer of photoresist is coated, the photoresist is exposed and developed using a single tone mask, the gate metal film is etched and the remaining photoresist is stripped, forming a gate electrode 11 and a gate line (not shown) pattern, and then a gate insulating layer 12 is deposited, as shown in fig. 2. The gate metal film can be made of copper, aluminum, molybdenum and other metals or a composite film layer consisting of any two or more films of copper, aluminum and molybdenum, the thickness of the gate metal film is 100 nm-1000 nm, and the gate metal film is deposited in a magnetron sputtering (Sputter) mode. The photoresist can adopt positive photoresist with the thickness of 1-4 μm, and the exposed photoresist reacts with the developing solution, and the photoresist shielded by the mask plate is remained. The etching can adopt wet etching, the substrate which is exposed and developed is placed in etching liquid for etching, the main components of the etching liquid are phosphoric acid, acetic acid, nitric acid, water and the like, the etching temperature is 40-80 ℃, and the etching time is 40-80 s. The gate insulating layer can be a composite film layer composed of any two or more of silicon oxide SiOx, silicon nitride SiNx, or silicon oxide, silicon oxynitride, and silicon nitride.
In the second composition process, an active layer pattern is formed on the substrate with the grid structure layer through the composition process. The forming of the active layer pattern includes: depositing an active layer film on the substrate with the gate structure layer, coating a layer of photoresist, exposing and developing the photoresist by using a single-tone mask, etching the active layer film and stripping the residual photoresist to form an active layer 13 pattern, as shown in fig. 3. Wherein, silicon semiconductor material can be used for the active layer film.
In the third patterning process, a source electrode and a drain electrode pattern are formed on the substrate on which the active layer pattern is formed through the patterning process. Forming the source and drain electrode patterns includes: depositing a source and drain metal film on the substrate with the structural pattern, coating a layer of photoresist, exposing and developing the photoresist by using a single-tone mask, etching the source and drain metal film, and stripping the residual photoresist to form a source electrode 14, a drain electrode 15, a data line (not shown) and a channel region pattern, as shown in fig. 4. The source electrode 14 is in contact with one end of the active layer 13 to form a source region, the drain electrode 15 is in contact with the other end of the active layer 13 to form a drain region, and a channel region is formed between the source electrode 14 and the drain electrode 15. The source-drain metal film can be made of copper, aluminum, molybdenum and other metals, the thickness is 100 nm-1000 nm, and the source-drain metal film is deposited in a magnetron sputtering (Sputter) mode.
In actual preparation, the third patterning process may form a channel region pattern by wet etching and then dry etching, that is, the source electrode 14, the drain electrode 15 and the data line pattern are formed by wet etching equipment, and then transferred to dry etching equipment for channel region etching. And after the etching of the channel region is finished, processing the surface of the channel region. The channel region surface treatment comprises the following steps: the substrate on which the channel region etching is completed is placed in a Chemical Vapor Deposition (CVD) apparatus, and a borane (B2H6) plasma is used to treat the surface of the channel region. In the surface treatment, borane in a CVD device is ionized into plasma, and then is implanted into the surface of a channel region to form a cavity layer in a manner similar to ion implantation, wherein the gas flow rate of the borane B2H6 is 100 sccm-500 sccm, the gas pressure is 50 Pa-200 Pa, and the treatment time is 10 s-50 s. The chemical vapor deposition equipment used for surface treatment has the power of 1000W-8000W and the current of 5A-50A, and the electrode distance between the surface of the channel region and the chemical vapor deposition equipment is controlled to be 50 mm-300 mm. In the borane plasma treatment, part of boron atoms enter the active layer from the surface of the channel region, the boron atoms entering the active layer form a bond with silicon atoms in the active layer to form a hole unit, a hole layer 20 with positive charge holes is formed on the surface of the active layer, and the thickness of the hole layer 20 is 0.1nm to 1.0nm, as shown in fig. 5. In the embodiment of the invention, the surface of the channel region is treated by the borane plasma, and the surface defects caused by etching the channel region can be compensated, so that the quantity of electrons transferred to the surface of the channel region is reduced when the thin film transistor is in a closed state.
The embodiment provides a preparation method of a back channel etching type thin film transistor, after channel region etching is completed, borane plasma processing is carried out on the surface of a channel region, boron atoms entering the active layer and silicon in the active layer form a bond to form a positive hole unit, and a positive hole layer is formed on the surface of the channel region. When the thin film transistor is in an off state, when electrons migrate to the hole layer, the migrated electrons recombine with holes in the hole layer, and even if a voltage difference exists between the source electrode and the drain electrode, a current channel is not formed on the surface of the channel region. Furthermore, the surface of the channel region is treated by borane plasma, surface defects caused by etching the channel region are made up, the quantity of electrons transferred to the surface of the active layer is reduced when the thin film transistor is in a closed state, and the probability of forming a current channel on the surface of the channel region is further reduced. Therefore, the embodiment effectively reduces the leakage current of the thin film transistor and effectively improves the characteristics of the thin film transistor.
Second embodiment
Based on the technical idea of the embodiment of the invention, the embodiment of the invention also provides a thin film transistor which is prepared by adopting the preparation method of the thin film transistor of the first embodiment. As shown in fig. 5, the thin film transistor of the present embodiment includes:
a substrate 10;
a gate electrode 11 disposed on the substrate 10;
a gate insulating layer 12 covering the gate electrode 11;
an active layer 13 disposed on the gate insulating layer 12;
and a source electrode 14 and a drain electrode 15 disposed on the active layer 13, a channel region is formed between the source electrode 14 and the drain electrode 15, and a hole layer 20 is formed on a surface of the channel region.
The thickness of the hole layer 20 is 0.1 nm-1.0 nm, positive charge holes are formed in the hole layer 20, the hole layer 20 is formed by treating the surface of the channel region with borane plasma, and the positive charge holes in the hole layer 20 are formed by bonding boron atoms into an active layer of the channel region and silicon in the active layer through treatment of borane B2H6 plasma.
The gate electrode 11, the source electrode 14, and the drain electrode 15 may be made of copper, aluminum, molybdenum, or other metals, or a composite film layer made of any two or more films of copper, aluminum, and molybdenum, the gate insulating layer 11 may be made of silicon oxide SiOx or silicon nitride SiNx, or a composite film layer made of any two or more films of silicon oxide, silicon oxynitride, and silicon nitride, and the active layer may be made of a silicon semiconductor.
The embodiment provides the thin film transistor, and the hole layer with the positive charge hole unit is formed on the surface of the channel region, so that the leakage current of the thin film transistor is effectively reduced, and the characteristics of the thin film transistor are effectively improved. Third embodiment
Based on the technical concept of the embodiment of the invention, the embodiment of the invention also provides an array substrate and a preparation method thereof. The preparation method of the array substrate of the embodiment comprises the following steps:
the first to third patterning processes are the same as those of the first embodiment described above.
In the fourth patterning process, a passivation layer pattern is formed on the substrate on which the structure pattern is formed through the patterning process. Forming the passivation layer pattern includes: depositing a passivation layer film on the substrate with the structural pattern, coating a layer of photoresist, exposing and developing the photoresist by using a single-tone mask, etching the passivation layer film and stripping the residual photoresist to form a passivation layer 16 with a via hole, wherein the via hole is located at the position of the drain electrode 15, and the surface of the drain electrode 15 is exposed in the via hole, as shown in fig. 6. The passivation layer film can be silicon oxide, silicon nitride or silicon oxynitride, or a composite film layer consisting of any two or more of silicon oxide, silicon oxynitride and silicon nitride.
In the fifth patterning process, a pixel electrode pattern is formed on the substrate on which the structure pattern is formed through the patterning process. Forming the pixel electrode pattern includes: depositing a transparent conductive film on the substrate with the structural pattern, coating a layer of photoresist, exposing and developing the photoresist by using a single-tone mask, etching the transparent conductive film and stripping the residual photoresist to form a pixel electrode 17 pattern, wherein the pixel electrode 17 is connected with the drain electrode 15 through a via hole, as shown in fig. 7. The transparent conductive film may be Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).
The array substrate prepared by the preparation method of the array substrate comprises the following steps:
a substrate 10;
a gate electrode 11 disposed on the substrate 10;
a gate insulating layer 12 covering the gate electrode 11;
an active layer 13 disposed on the gate insulating layer 12;
a source electrode 14 and a drain electrode 15 disposed on the active layer 13, wherein a channel region is formed between the source electrode 14 and the drain electrode 15, and a hole layer 20 is formed on the surface of the channel region;
a passivation layer 16 covering the source electrode 14, the drain electrode 15 and the channel region, wherein the passivation layer 16 is provided with a via hole, and the via hole exposes the surface of the drain electrode 15;
and a pixel electrode 17 disposed on the passivation layer 16, the pixel electrode 17 being connected to the drain electrode 15 through a via hole.
The passivation layer 16 may be made of SiOx or SiNx, or a composite film formed by two or more films of SiOx, SiNx, or silicon nitride, and the pixel electrode 17 may be made of ITO or IZO.
In this embodiment, as in the previous embodiment, the leakage current of the thin film transistor is effectively reduced, and the characteristics of the thin film transistor are effectively improved.
It should be noted that, although the structure of the thin film transistor and the array substrate has been described by taking the five patterning processes as an example, other patterning processes may be adopted in practical implementation, and the present invention is not limited in detail herein. For example, the thin film transistor is manufactured by a secondary patterning process or the array substrate is manufactured by a four-time patterning process, and the secondary patterning process and the third patterning process are combined into a patterning process using a halftone mask or a gray tone mask. The method specifically comprises the following steps: depositing an active layer film and a source drain metal film on a gate insulating layer in sequence, coating a layer of photoresist on the source drain metal film, carrying out step exposure and development on the photoresist by adopting a halftone mask or a gray tone mask, forming an unexposed area at the positions of a source electrode, a drain electrode and a data line pattern, forming the photoresist with a first thickness, forming a partial exposed area at the position of a channel area pattern, forming the photoresist with a second thickness, forming a complete exposed area at other positions, and having no photoresist, wherein the first thickness is greater than the second thickness. And etching the source drain metal film and the active layer film of the complete exposure area by a first etching process, performing photoresist ashing treatment to remove the second thickness of the photoresist on the whole and expose part of the source drain metal film of the exposure area, etching part of the source drain metal film of the exposure area by a second etching process, and stripping the rest of the photoresist to form patterns of the active layer, the source electrode, the drain electrode and the channel area.
Although the structures of the thin film transistor and the array substrate have been described above as a bottom gate structure, the present invention can be applied to a top gate structure in practical implementation.
Fourth embodiment
An embodiment of the present invention further provides a display panel, including the thin film transistor according to the second embodiment or the array substrate according to the third embodiment. The display device may be an LCD display panel, an Organic Light-Emitting Diode (OLED) display panel, or the like. The display panel may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
In the description of the embodiments of the present invention, it should be understood that the terms "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be construed as limiting the present invention.
In the description of the embodiments of the present invention, it should be noted that, unless explicitly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (6)
1. A method for manufacturing a thin film transistor includes:
forming a channel region of a thin film transistor;
in chemical vapor deposition equipment, treating the surface of the channel region by adopting borane plasma, and forming a hole layer with positive charge holes on the surface of the channel region, wherein the thickness of the hole layer is 0.1 nm-1.0 nm; in the borane plasma treatment, part of boron atoms enter the active layer from the surface of the channel region, and the boron atoms entering the active layer form a bond with silicon atoms in the active layer to form a hole unit.
2. The method according to claim 1, wherein the borane plasma has a gas flow rate of 100sccm to 500sccm, a gas pressure of 50Pa to 200Pa, and a treatment time of 10s to 50 s.
3. The method according to claim 1, wherein the distance between the surface of the channel region and the electrode of the CVD apparatus is 50mm to 300mm, the power of the CVD apparatus is 1000W to 8000W, and the current is 5A to 50A.
4. A thin film transistor prepared by the preparation method of the thin film transistor according to any one of claims 1 to 3, comprising a channel region, wherein a positively charged hole layer is formed on the surface of the channel region, and the thickness of the hole layer is 0.1nm to 1.0 nm.
5. An array substrate comprising the thin film transistor according to claim 4.
6. A display panel comprising the array substrate according to claim 5.
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