CN102468239A - Method for manufacturing semiconductor device - Google Patents
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- CN102468239A CN102468239A CN2010105472918A CN201010547291A CN102468239A CN 102468239 A CN102468239 A CN 102468239A CN 2010105472918 A CN2010105472918 A CN 2010105472918A CN 201010547291 A CN201010547291 A CN 201010547291A CN 102468239 A CN102468239 A CN 102468239A
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Abstract
The invention discloses a method for manufacturing a semiconductor device. The method comprises a step of additionally providing a self-alignment stop layer between a first dielectric layer and a second dielectric layer which are arranged above a grid structure and a side wall layer. With the adoption of the method, contact holes above the grid can be avoided being etched into a metal silicide under the grid or the gate, thereby leakage current caused by the manufactured semiconductor device is avoided.
Description
Technical field
The present invention relates to semiconductor technology, particularly a kind of manufacture method of semiconductor device.
Background technology
Fig. 1～Figure 14 is the process generalized section of the manufacture method of semiconductor device in the prior art, and this method mainly comprises:
Step 101 referring to Fig. 1, provides semi-conductive substrate 1001, on Semiconductor substrate 1001, forms N trap 1002, P trap 1003 and shallow channel isolation area (STI) 1004.
At first, adopt twin well process to define the active area of N type metal oxide semiconductor (NMOS) pipe and P-type mos (PMOS) pipe, thereby obtain N trap 1002 and P trap 1003.
Then, on Semiconductor substrate 1001, form STI 1004, be used for the active area of formed NMOS pipe of electric insulation and PMOS pipe.
Step 102; Referring to Fig. 2; At Semiconductor substrate 1001 superficial growth gate oxide and deposit spathic silicons, and utilize technologies such as photoetching, etching and ion injection above P trap 1003, to form the grid structure 1005 of NMOS pipe, above N trap 1002, form the grid structure 1006 that PMOS manages.
In this step, at first carry out the growth of gate oxide; Then, through chemical vapor deposition method, at wafer surface deposition one deck polysilicon, thickness is about 500～2000 dusts; Afterwards, through technologies such as photoetching, etching and ion injections, produce the grid structure of NMOS pipe and PMOS pipe.
Grid structure according to the invention comprises grid that is made up of polysilicon and the gate oxide that is positioned at the grid below.
Step 103 referring to Fig. 3, is carried out lightly doped drain (LDD) and is injected, and on the Semiconductor substrate 1001 of NMOS tube grid structure 1005 both sides, forms lightly doped drain 1007 and light dope source electrode 1008.
The ion that injects is N type element, for example phosphorus or arsenic.
Under the promotion of demands such as semiconductor device miniatureization, densification, high speed and system integration, the width of grid structure constantly reduces, and the channel length of its below also constantly reduces; Yet the voltage of drain terminal does not significantly reduce; This has just caused the increase at the electric field of drain terminal, and near the electric charge making has bigger energy, and these hot carriers might be passed through gate oxide; Caused the increase of leakage current; Therefore, need to adopt some means to reduce the possibility that leakage current occurs, inject like LDD.
Step 104 referring to Fig. 4, is carried out LDD and is injected, and on the Semiconductor substrate 1001 of gate pmos electrode structure 1006 both sides, forms lightly doped drain 1009 and light dope source electrode 1010.
The ion that injects is P type element, for example boron or indium.
Step 105 is referring to Fig. 5, on Semiconductor substrate 1001 surfaces deposition of silica (SiO successively
2) and silicon nitride (Si
3N
4), and adopt the silicon nitride on dry etch process etched wafer surface, and adopt the silicon dioxide on wet-etching technology etched wafer surface, form side wall layer 1011 in grid structure 1005 both sides of NMOS pipe, grid structure 1006 both sides of PMOS pipe.
Wherein, side wall layer 1011 comprises the first side wall layer and second side wall layer, and the first side wall layer is the silicon dioxide after the etching, and second side wall layer is the silicon nitride after the etching.Certainly, in the prior art, side wall layer also possibly be other structures, since irrelevant with the present invention, so no longer other structures of offside parietal layer are described in detail.
Step 106, referring to Fig. 6, the grid structure 1005 side walls layers 1011 of managing with NMOS carry out the ion injection as mask, thereby form the drain electrode 1012 and source electrode 1013 of NMOS pipe.
The ion that injects is a N type element, and it is more bigger than the junction depth that carries out LDD and inject back formation that for example phosphorus or arsenic, N type ion inject junction depth that the back forms.
Need to prove that because side wall layer 1011 can be used as the protective layer of grid structure 1005, the ion that therefore injects is difficult to get into grid, thereby only the Semiconductor substrate 1001 of grid structure both sides has been realized injection, and final drain electrode 1012 and the source electrode 1013 of forming.
Step 107, referring to Fig. 7, the grid structure 1006 side walls layers 1011 of managing with PMOS carry out the ion injection as mask, thereby form the drain electrode 1014 and source electrode 1015 of PMOS pipe.
The ion that injects is a P type element, and for example boron or indium, P type ion inject junction depth that the back forms to carry out LDD to inject the junction depth that the back forms bigger.
Step 108 referring to Fig. 8, is implemented silicide process, is exactly that nickel deposited (Ni), titanium (Ti) or cobalt (Co) wait any metal and since these metals can with pasc reaction, but not can with Si oxide such as silicon dioxide (SiO
2) or silicon nitride such as silicon nitride (Si
3N
4) wait reaction, thus only can be on the grid structure that exposes 1005, grid structure 1006 surfaces and Semiconductor substrate 1001 surfaces, and the metal reaction of silicon and deposition forms metal silicide 1016.
Step 109, referring to Fig. 9, deposition-etch stops layer 1017.
The main component of etching stop layer 1017 is a silicon nitride.
Step 110 referring to Figure 10, is being carved metallization medium layer 1018 on the etching stop layer 1017, and the distance on the surface of formed dielectric layer 1018 and Semiconductor substrate 1001 surfaces representes that with a a is the surface of dielectric layer and the preset distance of semiconductor substrate surface.
Step 111 referring to Figure 11, is carried out dry etching to dielectric layer 1018 and etching stop layer 1017, forms contact hole.
Mostly the gas of dry etching is to contain the gas of fluorine (F) element, for example methane (CF
4), difluoromethane (CH
2F
2).
In practical application; According to the residing position of contact hole, roughly contact hole is divided into following three types: be positioned at first contact hole 1019 on the grid structure, be positioned at substrate surface second contact hole 1020, part is positioned on the grid structure and part is positioned at the 3rd contact hole 1021 of substrate surface.
So far, this flow process finishes.
Yet; Shown in figure 11, because the hole depth of first contact hole 1019 and second contact hole 1020 has significant difference, the part that the 3rd contact hole 1021 is positioned on the grid structure also has significant difference with the hole depth that is positioned at the part of substrate surface; Therefore; When dielectric layer 1018 and etching stop layer 1017 were carried out etching, might this thing happens: when first contact hole 1019 had been etched to metal silicide 1016 surperficial, second contact hole 1020 also be etched to the surface of metal silicide 1016; When second contact hole 1020 has been etched to metal silicide 1016 surperficial; First contact hole 1019 has been etched in the metal silicide 1016 even possibly has been etched to the gate surface of metal silicide 1016 belows, similarly, also is identical situation for two parts of the 3rd contact hole 1021.Thus it is clear that, in the method for semiconductor manufacturing of prior art, in the process that forms contact hole, might cause the damage of metal silicide, thereby the semiconductor device that possibly cause processing produces leakage current (leakage).
Summary of the invention
In view of this, the present invention provides a kind of manufacture method of semiconductor device, and the semiconductor device that can avoid processing produces leakage current.
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of manufacture method of semiconductor device; On Semiconductor substrate, form etching stop layer; Not by grid structure, grid structure side walls layer region covered, this method also comprises in grid structure, grid structure side walls layer and the semiconductor substrate surface of said etching stop layer covering semiconductor substrate surface:
On etching stop layer, form first dielectric layer, the surface of said first dielectric layer and the distance b of semiconductor substrate surface are less than predeterminable range;
On said first dielectric layer, form autoregistration and stop layer, said autoregistration is stopped layer carrying out etching, the autoregistration after the etching stops layer and covers grid structure and grid structure side walls layer on the Semiconductor substrate;
Deposit second dielectric layer, the surface of post-depositional second dielectric layer and the distance of semiconductor substrate surface equal said predeterminable range;
Successively said second dielectric layer, said first dielectric layer and said etching stop layer are carried out etching, in said second dielectric layer, said first dielectric layer and said etching stop layer, form contact hole.
Before forming said etching stop layer, this method further comprises:
Form grid structure at semiconductor substrate surface;
Carry out lightly doped drain LDD to Semiconductor substrate and inject, on the Semiconductor substrate of grid structure both sides, form lightly doped drain and light dope source electrode;
Form side wall layer in the grid structure both sides;
Carry out ion to Semiconductor substrate and inject, on the Semiconductor substrate of side wall layer both sides, form drain electrode and source electrode;
Adopt silicide process to form metal silicide on grid structure surface and semiconductor substrate surface.The distance b is
to
Saidly autoregistration stopped the method that layer carries out etching comprise:
Stop to form on the layer photoresistance glue PR in autoregistration;
PR is made public, develops, form photoengraving pattern, said photoengraving pattern covers grid structure and the grid structure side walls layer on the Semiconductor substrate;
According to photoengraving pattern autoregistration is stopped layer and carry out dry etching;
Remove photoengraving pattern.
Saidly autoregistration is stopped the gas that layer carries out dry etching be: methane and/or difluoromethane.
Said autoregistration stops layer and is silicon oxynitride.
The thickness that said autoregistration stops layer is 200 dust to 500 dusts.
In the manufacture method of a kind of semiconductor device provided by the present invention; Between first dielectric layer above grid structure and the side wall layer and second dielectric layer, increase autoregistration and stopped layer; When forming contact hole; The etch rate of first dielectric layer and second dielectric layer is than very fast, and it is slow that autoregistration stops the etch rate of layer, the formation speed of the contact hole of the grid top of therefore having slowed down; And the hole depth of the contact hole of grid top is less than the hole depth of the contact hole of all the other positions; This just makes that the formation time of contact hole of the contact hole that is positioned at the grid top and all the other positions is almost consistent, has avoided the contact hole of grid top to be etched in the metal silicide or grid of its below, so has avoided the semiconductor device generation leakage current (leakage) processed.
Description of drawings
Fig. 1～Figure 11 is the process generalized section of the manufacture method of semiconductor device in the prior art.
Figure 12 is the flow chart of the manufacture method of a kind of semiconductor device provided by the present invention.
Figure 13～Figure 27 is the process generalized section of embodiment of the manufacture method of a kind of semiconductor device provided by the present invention.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, scheme according to the invention is done to specify further.
Core concept of the present invention is: increased autoregistration between first dielectric layer above grid structure and side wall layer and second dielectric layer and stopped layer; When forming contact hole; The etch rate of first dielectric layer and second dielectric layer is than very fast; Autoregistration stop the layer etch rate slow; Therefore the slowed down formation speed of contact hole of grid top, and the hole depth of the contact hole of grid top is less than the hole depth of the contact hole of all the other positions, this just makes that the formation time of contact hole of the contact hole that is positioned at the grid top and all the other positions is almost consistent; Avoided the contact hole of grid top to be etched in the metal silicide or grid of its below, the semiconductor device of therefore having avoided processing produces leakage current (leakage).
Figure 12 is the flow chart of the manufacture method of a kind of semiconductor device provided by the present invention.Shown in figure 12, this method may further comprise the steps:
So far, this flow process finishes.
Through an embodiment technical scheme of the present invention is elaborated below.
Figure 13～Figure 27 is the process generalized section of embodiment of the manufacture method of a kind of semiconductor device provided by the present invention, and this method mainly comprises:
Step 201 referring to Figure 13, provides semi-conductive substrate 1001, on Semiconductor substrate 1001, forms N trap 1002, P trap 1003 and shallow channel isolation area (STI) 1004.
Step 202; Referring to Figure 14; At Semiconductor substrate 1001 superficial growth gate oxide and deposit spathic silicons, and utilize technologies such as photoetching, etching and ion injection above P trap 1003, to form the grid structure 1005 of NMOS pipe, above N trap 1002, form the grid structure 1006 that PMOS manages.
Step 203 referring to Figure 15, is carried out lightly doped drain (LDD) and is injected, and on the Semiconductor substrate 1001 of NMOS tube grid structure 1005 both sides, forms lightly doped drain 1007 and light dope source electrode 1008.
Step 204 referring to Figure 16, is carried out LDD and is injected, and on the Semiconductor substrate 1001 of gate pmos electrode structure 1006 both sides, forms lightly doped drain 1009 and light dope source electrode 1010.
Step 205 is referring to Figure 17, on Semiconductor substrate 1001 surfaces deposition of silica (SiO successively
2) and silicon nitride (Si
3N
4), and adopt the silicon nitride on dry etch process etched wafer surface, and adopt the silicon dioxide on wet-etching technology etched wafer surface, form side wall layer 1011 in grid structure 1005 both sides of NMOS pipe, grid structure 1006 both sides of PMOS pipe.
Step 206, referring to Figure 18, the grid structure 1005 side walls layers 1011 of managing with NMOS carry out the ion injection as mask, thereby form the drain electrode 1012 and source electrode 1013 of NMOS pipe.
Step 207, referring to Figure 19, the grid structure 1006 side walls layers 1011 of managing with PMOS carry out the ion injection as mask, thereby form the drain electrode 1014 and source electrode 1015 of PMOS pipe.
Step 208; Referring to Figure 20, implement silicide process, nickel deposited (Ni), titanium (Ti) or cobalt (Co) wait any metal; On the grid structure that exposes 1005, grid structure 1006 surfaces and Semiconductor substrate 1001 surfaces, the metal reaction of silicon and deposition forms metal silicide 1016.
Step 209, referring to Figure 21, deposition-etch stops layer 1017.
Above-mentioned steps 201～209 is identical with prior art, but 101～109 the relevant introduction step by step of reference background technology department is introduced here no longer in detail.
Step 210; Referring to Figure 22; Carving metallization medium layer 1018 on the etching stop layer 1017, the surface of formed dielectric layer 1018 representes with b with the distances on Semiconductor substrate 1001 surfaces, b less than the surface of dielectric layer and semiconductor substrate surface preset apart from a.
In the present invention, can dielectric layer 1018 notes be made first dielectric layer.
Preferably,
Step 211, referring to Figure 23, the deposition autoregistration stops layer 1022.
Preferably, to stop layer 1022 main component be silicon oxynitride (SiON) in autoregistration.
The thickness c that autoregistration stops layer 1022 is 200 dusts (A)～500 dusts (A).
Step 212 referring to Figure 24, stops spin coating photoresistance glue (PR) on the layer 1022 in autoregistration, and PR is made public, develops, thereby forms photoengraving pattern 1023.
In photoengraving pattern 1023, PR overlies gate structure and grid structure side walls layer, and come out in all the other places.Shown in figure 24, the width of PR equals the width and the grid structure side walls layer 1011 width sum of grid structure 1005 (or grid structure 1006) in the photoengraving pattern 1023.
In addition, in actual use, under PR, also can apply bottom antireflective coating (BARC); When being coated with BARC; After subsequent step forms photoengraving pattern, also need further BARC to be carried out etching, behind the removal photoengraving pattern according to photoengraving pattern; Also further remove BARC, wherein etching BARC can be with reference to the content of prior art with the method for removing BARC.
Step 213 referring to Figure 25, is a mask with photoengraving pattern 1023, stops layer and 1022 carries out dry etching exposing autoregistration, removes photoengraving pattern 1023 then.
Wherein, mostly the gas of dry etching is to contain the gas of fluorine (F) element, for example methane (CF
4) and/or difluoromethane (CH
2F
2) etc.
The method of removing photoengraving pattern 1023 can be: adopt oxygen that photoengraving pattern 1023 is carried out ashing.
After autoregistration stopped layer 1022 etching, the autoregistration after the etching stopped layer 1022 overlies gate structure and grid structure side walls layer, and is come out in all the other places.
Step 214, referring to Figure 26, deposition and the identical dielectric substance of dielectric layer 1018 compositions, the surface of post-depositional dielectric substance and Semiconductor substrate 1001 surperficial distances equal to preset apart from a.
In the present invention, can the dielectric substance note that newly deposits be made second dielectric layer.
Illustrate; If the material of dielectric layer 1018 is that the K value is 2.1 SiOC; The dielectric substance that then this step deposited also is 2.1 SiOC for the K value, that is to say, must guarantee that the material of the dielectric layer 1018 that dielectric substance that step 214 deposited and step 210 are deposited is identical.Because the material of the dielectric layer 1018 that the dielectric substance of new deposition and step 210 are deposited is identical, so in Figure 26, also use the dielectric substance of the new deposition of label 1018 expressions.
Those skilled in the art can understand; After step 214 is finished; The structure difference with the prior art of dielectric layer 1018 is: in dielectric layer 1018, be equivalent to increase autoregistration and stop layer 1022; Autoregistration stops layer 1022 overlies gate structure and grid structure side walls layer, and is come out in all the other places.
In the present invention, increasing the purpose that autoregistration stops layer 1022 is: when the subsequent etching contact hole, etching gas is methane (CF for example
4) stop layer 1022 for dielectric layer 1018 and autoregistration and have than higher selection ratio, in other words, for a kind of etching gas, the etch rate of dielectric layer 1018 is than very fast, and that autoregistration stops the etch rate of layer 1022 is slow.Like this; For first contact hole 1019; Stop layer 1022 the time when being etched to autoregistration, it is very slow that etch rate can become, the etch rate of first contact hole 1019 that has been equivalent to slow down; And for second contact hole 1020; Stop layer 1022 owing to only above grid structure and its side wall layer, be provided with autoregistration, carry out etching so need not that autoregistration is stopped layer 1022, the etch rate of second contact hole 1020 is greater than the etch rate of first contact hole 1019; And since the hole depth of first contact hole 1019 less than the hole depth of second contact hole 1020; So just might make the etch period of the win contact hole 1019 and second contact hole 1020 almost consistent, avoid following situation of the prior art to take place: when second contact hole 1020 was etched to metal silicide 1016 surperficial, first contact hole 1019 had been etched in the metal silicide 1016 even possibly has been etched to the gate surface of metal silicide 1016 belows.
Step 215 referring to Figure 27, is carried out etching to dielectric layer 1018 and etching stop layer 1017, forms contact hole.
Need to prove that before dielectric layer 1018 and etching stop layer 1017 are carried out etching, also need adopt the position of photoetching process definition contact hole, the concrete grammar of photoetching and step 212 are similar with 213, can be with reference to aforementioned description.But it should be noted that in step 212, can apply BARC under the PR and also can omit BARC, and when the position of definition contact hole, all under PR, apply BARC generally speaking that this is because lithographic accuracy required than higher during the position of definition contact hole.
In order clearly to introduce step 215, the last figure among Figure 27 is the etching process sketch map, and figure below of Figure 27 is the sketch map after etching finishes.Last figure from Figure 27 can find out, because etching gas methane (CF for example
4) stop layer 1022 for dielectric layer 1018 and autoregistration and have than higher selection ratio; Therefore; Autoregistration stops the etch rate that layer 1022 has slowed down first contact hole 1019; When first contact hole 1019 only was etched to autoregistration and stops layer 1022 lower surface, second contact hole 1020 was crossed autoregistration already and is stopped layer 1022 a pairing horizontal plane.
Shown in the last figure among Figure 27, in etching process, the lower surface of first contact hole 1019 and metal silicide 1016 upper surfaces distance are d1; The lower surface of second contact hole 1020 and metal silicide 1016 upper surfaces distance are d2, and lower surface and metal silicide 1016 upper surfaces distance that the 3rd contact hole 1021 is positioned at the part of substrate surface are d3, and lower surface and metal silicide 1016 upper surfaces distance that the 3rd contact hole 1021 is positioned at the part on the grid structure are d4; Preferably, d1=d2=d3=d4, visible; For three contact holes; Remaining etching distance (d1, d2, d3, d4) equates that etch rate also equates, can guarantee that then the three is etched to the upper surface of metal silicide 1016 in the identical time; Avoid the damage of metal silicide 1016, thereby avoided the generation of leakage current.
In addition, existing experiment shows, in dielectric layer, increases autoregistration and stops the insulation property almost not influence of layer to dielectric layer.
So far, this flow process finishes.
According to technical scheme provided by the present invention; Between first dielectric layer above grid structure and the side wall layer and second dielectric layer, increase autoregistration and stopped layer; When forming contact hole; The etch rate of first dielectric layer and second dielectric layer is than very fast, and it is slow that autoregistration stops the etch rate of layer, the formation speed of the contact hole of the grid top of therefore having slowed down; And the hole depth of the contact hole of grid top is less than the hole depth of the contact hole of all the other positions; This just makes that the formation time of contact hole of the contact hole that is positioned at the grid top and all the other positions is almost consistent, has avoided the contact hole of grid top to be etched in the metal silicide or grid of its below, so has avoided the semiconductor device generation leakage current (leakage) processed.
The above is merely preferred embodiment of the present invention, is not to be used to limit protection scope of the present invention.All within spirit of the present invention and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. the manufacture method of a semiconductor device; On Semiconductor substrate, form etching stop layer; Not by grid structure, grid structure side walls layer region covered, this method also comprises in grid structure, grid structure side walls layer and the semiconductor substrate surface of said etching stop layer covering semiconductor substrate surface:
On etching stop layer, form first dielectric layer, the surface of said first dielectric layer and the distance of semiconductor substrate surface are less than predeterminable range;
On said first dielectric layer, form autoregistration and stop layer, said autoregistration is stopped layer carrying out etching, the autoregistration after the etching stops layer and covers grid structure and grid structure side walls layer on the Semiconductor substrate;
Deposit second dielectric layer, the surface of post-depositional second dielectric layer and the distance of semiconductor substrate surface equal said predeterminable range;
Successively said second dielectric layer, said first dielectric layer and said etching stop layer are carried out etching, in said second dielectric layer, said first dielectric layer and said etching stop layer, form contact hole.
2. method according to claim 1 is characterized in that, before forming said etching stop layer, this method further comprises:
Form grid structure at semiconductor substrate surface;
Carry out lightly doped drain LDD to Semiconductor substrate and inject, on the Semiconductor substrate of grid structure both sides, form lightly doped drain and light dope source electrode;
Form side wall layer in the grid structure both sides;
Carry out ion to Semiconductor substrate and inject, on the Semiconductor substrate of side wall layer both sides, form drain electrode and source electrode;
Adopt silicide process to form metal silicide on grid structure surface and semiconductor substrate surface.
3. method according to claim 2; It is characterized in that said distance b is that
is to
4. method according to claim 2 is characterized in that, saidly autoregistration is stopped the method that layer carries out etching comprises:
Stop to form on the layer photoresistance glue PR in autoregistration;
PR is made public, develops, form photoengraving pattern, said photoengraving pattern covers grid structure and the grid structure side walls layer on the Semiconductor substrate;
According to photoengraving pattern autoregistration is stopped layer and carry out dry etching;
Remove photoengraving pattern.
5. method according to claim 4 is characterized in that, saidly autoregistration is stopped the gas that layer carries out dry etching is: methane and/or difluoromethane.
6. method according to claim 5 is characterized in that, said autoregistration stops layer and is silicon oxynitride.
7. method according to claim 6 is characterized in that, the thickness that said autoregistration stops layer is 200 dust to 500 dusts.
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|---|---|---|---|
| CN2010105472918A CN102468239A (en) | 2010-11-16 | 2010-11-16 | Method for manufacturing semiconductor device |
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|---|---|---|---|
| CN2010105472918A CN102468239A (en) | 2010-11-16 | 2010-11-16 | Method for manufacturing semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104779206A (en) * | 2014-01-13 | 2015-07-15 | 北大方正集团有限公司 | CMOS (complementary metal oxide semiconductor) and manufacturing method thereof |
| CN113539809A (en) * | 2021-07-19 | 2021-10-22 | 长鑫存储技术有限公司 | Preparation method of semiconductor structure and semiconductor structure |
| CN116544180A (en) * | 2023-07-03 | 2023-08-04 | 合肥晶合集成电路股份有限公司 | Manufacturing method of semiconductor structure |
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