CN101777494B - Method for manufacturing semiconductor devices - Google Patents

Method for manufacturing semiconductor devices Download PDF

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CN101777494B
CN101777494B CN2009100451433A CN200910045143A CN101777494B CN 101777494 B CN101777494 B CN 101777494B CN 2009100451433 A CN2009100451433 A CN 2009100451433A CN 200910045143 A CN200910045143 A CN 200910045143A CN 101777494 B CN101777494 B CN 101777494B
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layer
grid
etching
substrate
polysilicon layer
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CN101777494A (en
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王国华
吴汉明
张海洋
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

The invention discloses a method for manufacturing semiconductor devices, and a semiconductor substrate, a gate oxide layer deposited on the substrate and a polysilicon layer positioned on the gate oxide layer are comprised. The method also comprises the following steps of: taking patterned light resistance glue as a mask film for etching the polysilicon layer; taking the patterned light resistance glue and etched polysilicon layer as shielding, and pouring deep irons into the substrate to form a source electrode and a drain electrode; carrying out secondary patterning on the patterned light resistance glue for forming the gate; taking the secondarily patterned light resistance glue as the mask to etch the polysilicon layer for the second time for forming the gate; taking the gate as the shielding, and pouring the light irons into the substrate; and depositing a silicon nitride layer with stress on the gate and the surface of the substrate. A side wall layer does not need to be set by adopting the method, the stress greater than the prior art is obtained, and carrier mobility in channels can flexibly and effectively adjusted.

Description

The manufacture method of semiconductor device
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly have the manufacture method of semiconductor device of the silicon nitride layer of stress.
Background technology
At present, when making semiconductor device, can use silicon nitride in transistor channel, to cause stress, thereby regulate carrier mobility in the raceway groove.The relative position of the stress state that the stress that is caused depends on silicon nitride itself and this part relevant raceway groove.Stress is big more, and the mobility of charge carrier rate is big more in the raceway groove.In the prior art, the semiconductor device technology process that forms the silicon nitride layer with stress in Figure 1A, forms grid 3 on Semiconductor substrate 1 shown in Figure 1A to 1E, between substrate 1 and grid 3, be gate oxide 2.Next shown in Figure 1B, form the first side wall layer 4 in the both sides of grid 3, can pass through chemical gaseous phase depositing process deposit one deck silica, etching forms the first side wall layer 4 then, and thickness is about tens nanometers.The first side wall layer 4 that forms reserves the distance of shallow ion injection region horizontal proliferation in the follow-up rapid thermal anneal process; Can guarantee the channel width of grid 3 belows; Be used to the short-channel effect of avoiding following shallow ion injection technology to bring; Cause channel width to narrow down, the situation of punch-through and leakage current occurs.Shown in Fig. 1 C, utilize grid 3 and the first side wall layer 4 for shielding, carry out the shallow ion injection technology, and carry out follow-up rapid thermal anneal process, like laser annealing, make the horizontal proliferation of shallow ion injection region, form shallow doped drain (LDD) district 5.Impaired lattice was repaired when rapid thermal annealing can also inject ion simultaneously, and can make the ion distribution of injection even.Shown in Fig. 1 D, forming second side wall layer 6 in the both sides of the first side wall layer 4 then, is shielding with the first side wall layer 4 and second side wall layer 6, carries out the deep ion implantation step, with formation source electrode 7 and drain electrode 8, and carries out annealing process.At last, shown in Fig. 1 E, remove second side wall layer 6, and deposition has the silicon nitride layer 9 of stress, the side and substrate 1 surface of this silicon nitride layer 9 cover gate 3, the first side wall layer 4.The stress that silicon nitride layer 9 is had can grid 3 and the first side wall layer 4 below it be passed to the channel part in the Semiconductor substrate; Wherein, Channel part is defined by the part between source electrode and the drain electrode, and the length of channel part is the distance L between source electrode and the drain electrode., play the effect of regulating carrier mobility in the raceway groove so thereby raceway groove has also had corresponding stress.But in the prior art; When deposition has the silicon nitride layer of stress; Because the existence of the first side wall layer makes the stress that pairing groove branch has under the first side wall layer, transmits through the first side wall layer; Therefore can not introduce more stress, thus can not be more flexibly and regulate carrier mobility in the raceway groove effectively.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of manufacture method of semiconductor device, and this method need not set up side wall layer, just can regulate carrier mobility in the raceway groove more flexibly effectively.
For achieving the above object, technical scheme of the present invention specifically is achieved in that
The invention provides a kind of manufacture method of semiconductor device, comprise Semiconductor substrate, be deposited on the gate oxide on the substrate and be positioned at the polysilicon layer on the gate oxide, key is that this method also comprises:
Photoresistance glue with patterning is mask, the said polysilicon layer of etching;
With the photoresistance glue of said patterning and the polysilicon layer of etching is shielding, in said substrate, carries out deep ion and injects, and forms source electrode and drain electrode;
The photoresistance glue of said patterning is used to form the patterning second time of grid;
The photoresistance glue of patterning is mask with said second time, and the said polysilicon layer of etching forms grid for the second time, and gate lateral wall layer is not set up in said grid both sides;
With said grid is shielding, in said substrate, carries out shallow ion and injects;
Deposit silicon nitride layer at said grid and substrate surface with stress.
This method further is included in and deposits catalytic oxidation silicon layer and hard mask layer on the said polysilicon layer successively.
Said photoresistance glue with patterning is mask, during the said polysilicon layer of etching, successively hard mask layer and catalytic oxidation silicon layer is carried out etching.
Further be included in before the formation grid, the photoresistance glue of patterning is mask with the second time, successively hard mask layer and catalytic oxidation layer is carried out the etching second time.
Said formation grid be with the second time etching hard mask layer and catalytic oxidation layer be shielding, polysilicon layer is carried out second time etching to form grid.
Saidly polysilicon layer is carried out second time etching form after the grid, further comprise the step of removing hard mask layer.
This method further is included in grid and substrate surface cvd silicon oxide laying before in to said substrate, carrying out the shallow ion injection.
Perhaps, shallow ion carries out annealing process after injecting in said deep ion injection.
Visible by above-mentioned technical scheme, the manufacture method of the semiconductor device of the silicon nitride layer with stress provided by the invention need not set up side wall layer; Carry out deep ion earlier and inject, carry out shallow ion again and inject, thereby make in the prior art; Raceway groove transmits the part of stress through side wall layer; Silicon nitride layer directly contacts with channel part in the present invention, obtains the stress bigger than prior art, therefore can regulate carrier mobility in the raceway groove more flexibly effectively.
Description of drawings
Figure 1A to 1E is the manufacturing method of semiconductor device that prior art has the silicon nitride layer of stress.
Fig. 2 A to 2H is the manufacturing method of semiconductor device that the preferred embodiment of the present invention has the silicon nitride layer of stress.
Embodiment
For make the object of the invention, technical scheme, and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, to further explain of the present invention.
The manufacture method of the semiconductor device of the silicon nitride layer with stress provided by the invention need not set up side wall layer, carries out deep ion earlier and injects; Carrying out shallow ion again injects; Thereby make in the prior art, raceway groove is through the part of side wall layer transmission stress, and silicon nitride layer directly contacts with channel part in the present invention; Obtain the stress bigger, therefore can regulate carrier mobility in the raceway groove more flexibly effectively than prior art.
In order to obtain having the silicon nitride layer semiconductor device of stress, the manufacture method of semiconductor device of the present invention is elaborated below in conjunction with Fig. 2 A to 2D.
Fig. 2 A to 2H is the device profile map of preferred embodiment of the present invention manufacturing method of semiconductor device.
Step 1; On Semiconductor substrate 1, generate earlier the gate oxide 202 of 5～20 nanometer thickness, on this gate oxide 202, deposit the polysilicon layer 203 of 50～150 nanometer thickness again, if directly on polysilicon layer 203, form the photoresistance glue of patterning then; Inject at the follow-up deep ion that carries out so; Form in the process of source electrode and drain electrode, the infiltration capacity of keeping out the injection ion owing to photoresistance glue is limited, possibly have some injection ions and infiltrate polysilicon layer 203 through photoresistance glue.So in the present embodiment; In order to reduce damage to polysilicon layer; Elder generation's growth one deck catalytic oxidation silicon layer 204 on polysilicon layer 203, deposition hard mask layer 205 on catalytic oxidation silicon layer 204 is silicon nitride layer again; Silicon nitride layer is dense, the mask material in the time of can being used as suitable injection.The stress that catalytic oxidation silicon layer 204 brings polysilicon layer 203 in order to the silicon nitride layer that weakens as hard mask layer.At last, on hard mask layer 205, form the photoresistance glue-line 206 of patterning.Shown in Fig. 2 A.
Step 2; Photoresistance glue-line 206 with patterning is a mask, and etching hard mask layer 205, catalytic oxidation silicon layer 204 and polysilicon layer 203 are shielding with the photoresistance glue 206 of patterning, hard mask layer 205, catalytic oxidation silicon layer 204 and the polysilicon layer 203 that etching is crossed then successively; In Semiconductor substrate 1, carrying out deep ion injects; Ion energy is 0.5 million electron volt to 2 million electron volts, forms source electrode 7 and drain electrode 8, and carries out annealing process.Shown in Fig. 2 B.
In the present embodiment, gate oxide 202 is arranged, so when deep ion injects, can protect Semiconductor substrate 1 to avoid damage effectively owing on Semiconductor substrate 1, generate.
Step 3 is carried out the patterning second time with the photoresistance glue-line 206 of above-mentioned patterning, obtains the photoresistance glue-line 216 of patterning for the second time, for the second time the size of the photoresistance glue-line 216 of patterning be used for defining the characteristic size of the grid that will form, shown in Fig. 2 C.
Step 4, the photoresistance glue-line 216 of patterning is a mask with the second time, successively hard mask layer and catalytic oxidation layer is carried out the etching second time, lithographic method is the dry method or the wet etching of prior art, shown in Fig. 2 D.
Step 5; Remove the photoresistance glue-line 216 of patterning for the second time, and with the second time etching catalytic oxidation layer and hard mask layer be shielding, polysilicon layer 203 is carried out the etching second time; Form and the measure-alike grid 213 of the photoresistance glue-line 216 of patterning for the second time, shown in Fig. 2 E.In the present embodiment, removing for the second time, the photoresistance glue-line 216 of patterning can be isotropic wet etching such as nitric acid and hydrofluoric acid.
Step 6 is removed hard mask layer, and at grid 213 and the thin silicon oxide liner bed course 207 of Semiconductor substrate 1 surface deposition one deck; Thickness is about 5 nanometers; When being used to prevent carry out below the shallow ion injection, grid or substrate are caused damage, shown in Fig. 2 F; Because the catalytic oxidation silicon layer 204 under gate oxide 202 and the hard mask layer; All be silicon oxide layer,, and also cover the last layer silica in the side of grid 213 so the silicon oxide liner bed course 207 of deposition covers gate oxide 202 and catalytic oxidation silicon layer 204 just.In the present embodiment, the removal of hard mask layer can be hot phosphoric acid.
Step 7 is shielding with grid 213, carries out the shallow ion injection technology, and the energy that ion injects is about 200 to 1000 electron-volts, and carries out rta technique, forms LDD district 5, shown in Fig. 2 G.
Step 8 has the silicon nitride layer 9 of stress at grid 213 and Semiconductor substrate 1 surface deposition, shown in Fig. 2 H.
Because the thickness of oxide liner 207 (being about 5 nanometers) is very thin; With respect to side wall layer of the prior art (being about tens nanometers) thus can ignore; So the grid that has side wall layer compared to prior art is when deposition has the silicon nitride of stress; The present invention can obtain bigger stress, thereby can regulate carrier mobility in the raceway groove more neatly.
In addition, the protective layer when the present invention selects hard mask layer to inject as deep ion can reach the purpose of when ion injects, protecting grid.The present invention also selective oxidation silicon liner layer is the protective layer of shallow ion grid or substrate when injecting, if do not have hard mask layer or silicon oxide liner bed course also can reach the object of the invention, so be exactly in order to realize the present invention better as preferred embodiment.
Processing method of the present invention can be widely applied in many application; And many suitable materials capable of using and method are made; Above-mentioned is to explain through preferred embodiment; Certainly the present invention is not limited to this specific embodiment, and the general replacement that those skilled in the art knew is encompassed in protection scope of the present invention far and away.

Claims (8)

1. the manufacture method of a semiconductor device comprises Semiconductor substrate, is deposited on the gate oxide on the substrate and is positioned at the polysilicon layer on the gate oxide, it is characterized in that this method also comprises:
Photoresistance glue with patterning is mask, the said polysilicon layer of etching;
With the photoresistance glue of said patterning and the polysilicon layer of etching is shielding, in said substrate, carries out deep ion and injects, and forms source electrode and drain electrode;
The photoresistance glue of said patterning is used to form the patterning second time of grid;
The photoresistance glue of patterning is mask with said second time, and the said polysilicon layer of etching forms grid for the second time, and gate lateral wall layer is not set up in said grid both sides;
With said grid is shielding, in said substrate, carries out shallow ion and injects;
Deposit silicon nitride layer at said grid and substrate surface with stress.
2. the method for claim 1 is characterized in that, this method further is included in and deposits catalytic oxidation silicon layer and hard mask layer on the said polysilicon layer successively.
3. method as claimed in claim 2 is characterized in that, said photoresistance glue with patterning is mask, during the said polysilicon layer of etching, successively hard mask layer and catalytic oxidation silicon layer is carried out etching.
4. method as claimed in claim 3 is characterized in that, further is included in to form before the grid, and the photoresistance glue of patterning is mask with the second time, successively hard mask layer and catalytic oxidation layer is carried out the etching second time.
5. method as claimed in claim 4 is characterized in that, said formation grid be with the second time etching hard mask layer and catalytic oxidation layer be shielding, polysilicon layer is carried out second time etching to form grid.
6. method as claimed in claim 5 is characterized in that, saidly polysilicon layer is carried out second time etching forms after the grid, further comprises the step of removing hard mask layer.
7. like claim 1 or 6 described methods, it is characterized in that, in to said substrate, carry out preceding this method of shallow ion injection and further be included in grid and substrate surface cvd silicon oxide laying.
8. the method for claim 1 is characterized in that, injects perhaps at said deep ion and after shallow ion injects, carries out annealing process.
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CN102543741B (en) * 2010-12-23 2016-03-30 中芯国际集成电路制造(上海)有限公司 The manufacture method of P-type mos pipe
CN103165425B (en) * 2011-12-08 2015-07-15 中芯国际集成电路制造(上海)有限公司 Method for forming fin formula field-effect tube grid side wall layer
CN103794485A (en) * 2012-11-02 2014-05-14 中芯国际集成电路制造(上海)有限公司 Formation method for polysilicon structure
CN106328505B (en) * 2015-07-01 2019-07-30 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure
JP7007407B2 (en) * 2017-07-06 2022-02-10 アプライド マテリアルズ インコーポレイテッド How to form a stack of multiple deposited semiconductor layers
CN112992663B (en) * 2019-12-16 2022-09-16 无锡华润上华科技有限公司 Manufacturing method of high-voltage CMOS, high-voltage CMOS and electronic device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5032535A (en) * 1988-04-26 1991-07-16 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US5476802A (en) * 1991-08-26 1995-12-19 Semiconductor Energy Laboratory Co., Ltd. Method for forming an insulated gate field effect transistor
US5604138A (en) * 1993-12-16 1997-02-18 Goldstar Electron Co., Ltd. Process for making a semiconductor MOS transistor
US6528376B1 (en) * 2001-11-30 2003-03-04 Taiwan Semiconductor Manufacturing Co., Ltd. Sacrificial spacer layer method for fabricating field effect transistor (FET) device
CN1601709A (en) * 2003-09-25 2005-03-30 旺宏电子股份有限公司 Method for fabricating a mosfet and reducing line width of gate structure
CN101170066A (en) * 2006-10-24 2008-04-30 联华电子股份有限公司 Semiconductor component and its making method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5032535A (en) * 1988-04-26 1991-07-16 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US5476802A (en) * 1991-08-26 1995-12-19 Semiconductor Energy Laboratory Co., Ltd. Method for forming an insulated gate field effect transistor
US5604138A (en) * 1993-12-16 1997-02-18 Goldstar Electron Co., Ltd. Process for making a semiconductor MOS transistor
US6528376B1 (en) * 2001-11-30 2003-03-04 Taiwan Semiconductor Manufacturing Co., Ltd. Sacrificial spacer layer method for fabricating field effect transistor (FET) device
CN1601709A (en) * 2003-09-25 2005-03-30 旺宏电子股份有限公司 Method for fabricating a mosfet and reducing line width of gate structure
CN101170066A (en) * 2006-10-24 2008-04-30 联华电子股份有限公司 Semiconductor component and its making method

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