CN102610506A - Method for etching bi-grid oxide layer in BCD technology - Google Patents
Method for etching bi-grid oxide layer in BCD technology Download PDFInfo
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- CN102610506A CN102610506A CN2012100815126A CN201210081512A CN102610506A CN 102610506 A CN102610506 A CN 102610506A CN 2012100815126 A CN2012100815126 A CN 2012100815126A CN 201210081512 A CN201210081512 A CN 201210081512A CN 102610506 A CN102610506 A CN 102610506A
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Abstract
The invention relates to a method for etching a bi-grid oxide layer in BCD technology, which comprises the following steps: providing a substrate, wherein the substrate comprises a high-voltage component area and a low-voltage component area which are arranged in parallel; forming grid oxide layers of the high-voltage component area and the low-voltage component area on the substrate in a thermal oxidation method, wherein the thickness of the grid oxide layer of the high-voltage component area is larger than that of the grid oxide layer of the low-voltage component area; depositing polycrystalline silicon on the grid oxide layers of the high-voltage component area and the low-voltage component area; etching the polycrystalline silicon so as to form grids of the high-voltage component area and the low-voltage component area, and stopping to etch on the grid oxide layer of the low-voltage component area; processing an etching procedure so as to remove the grid oxide layer of the high-voltage component area; and making the grids of the high-voltage component area and the low-voltage component area as masks so as to form source/drain areas of the high-voltage component area and the low-voltage component area. The method disclosed by The invention solves a problem that the active region of the low-voltage element is damaged by the high-voltage element and the low-voltage element in a simultaneously-removing procedure because of the thickness difference of the grid oxide layers so as to cause leakage and unavailable isolation, or the source/drain region of the high-voltage element cannot form silicide.
Description
Technical field
The present invention relates to semiconductor applications, the lithographic method of bigrid oxide layer in particularly a kind of BCD technology.
Background technology
BCD technology is a kind of monolithic integrated technique technology, and this technology can be made Bipolar, CMOS and DMOS device on same chip, abbreviate BCD technology as.BCD technology is owing to combine above three kinds of devices advantage separately, when receiving increasing concern, also is widely used.For example; BCD technology high-voltage driving element and module thereof are (like LDNMOS; DDDMOS, DECMOS or the like) be widely used in field, especially deep-submicrons such as PDP driving, LCD driving, OLED driving, motor driven (like 0.18um; 0.13um) BCD technology high-voltage device is widely used in the solution of SOC (System on Chip, system level chip).
Deep-submicron is (like 0.18um; 0.13um) in the BCD technology; The grid of high tension apparatus and drain terminal all are high pressure; How high tension apparatus is realized and the compatibility of low voltage CMOS (1.8V or 1.3V) is an important problems, and deep-submicron BCD technology is compared with 0.35umBCD technology and also will be increased some technology levels inevitably simultaneously.In 0.18um 60V BCD (grid and drain terminal operating voltage all are DMOS of 60 volts) technology, the thickness of the thickness of the grid oxic horizon of 60V high pressure DMOS and low pressure 0.18umCMOS grid oxic horizon differs nearly 1000A.In the etching technics of polysilicon gate (Poly Gate); During etch polysilicon to the selection of grid oxic horizon (Gate oxide) than being very high; But it is lower to the selection of silicon substrate when the etching grid oxic horizon than very; If grid oxic horizon etching surplus is too big, following silicon substrate is caused damage with regard to being easy to.As according to traditional process at deep-submicron (0.18um; 0.13um) after the etching of high pressure BCD technology polysilicon gate; The active area of high tension apparatus will remain very thick grid oxic horizon; Because the etching of polysilicon gate is to rest on the grid oxic horizon of low voltage CMOS, this etching can not be clean the grid oxic horizon etching of high tension apparatus, otherwise will damage the substrate in the source/drain region of low voltage CMOS.If the source of high tension apparatus/drain region remains very thick grid oxic horizon and do not remove totally simultaneously, follow-up especially silicon alloy technology will be injected to follow-up ion; Cause great influence; Therefore, traditional BCD technology, otherwise be exactly to make high tension apparatus source/drain region can not form metal silicide; Otherwise be exactly in silicon alloy technology selective etch to low voltage CMOS source/drain region particularly the active area at isolation structure edge cause damage, and cause an isolated failure or electric leakage even circuit malfunction.
Summary of the invention
The lithographic method that the purpose of this invention is to provide bigrid oxide layer in a kind of BCD technology; To improve the compatibility of low-voltage device and high tension apparatus, solve the problem that the damage of low-voltage device active area, electric leakage and isolated failure and high tension apparatus can't form metal silicide.
Technical solution of the present invention is the lithographic method of bigrid oxide layer in a kind of BCD technology, may further comprise the steps:
One substrate is provided, and said substrate comprises high voltage device regions arranged side by side and low-voltage device district;
In the high voltage device regions of said substrate and low-voltage device district, form the gate oxide of high voltage device regions and the gate oxide in low-voltage device district, the gate oxide thickness of said high voltage device regions is greater than the gate oxide in low-voltage device district;
Deposit spathic silicon on the gate oxide in the gate oxide of said high voltage device regions and low-voltage device district;
Etch polysilicon forms the grid in said high voltage device regions and low-voltage device district, rests on the gate oxide in low-voltage device district;
Grid with said high voltage device regions is a mask, and etching is removed the gate oxide of said high voltage device regions except that the grid below;
As mask, form the source/drain region in high voltage device regions and low-voltage device district with the grid in said high voltage device regions and low-voltage device district.
As preferably: the formation of the gate oxide in the gate oxide of said high voltage device regions and low-voltage device district may further comprise the steps:
Thermal oxidation first grid oxide layer in the high voltage device regions of said substrate and low-voltage device district;
Etching is removed the first grid oxide layer in the low-voltage device district;
Thermal oxidation second gate oxide on low-voltage device district and high voltage device regions, the gate oxide of said high voltage device regions comprises the first grid oxide layer and second gate oxide, the gate oxide in said low-voltage device district comprises second gate oxide;
As preferably: the thickness of the gate oxide of said high voltage device regions is greater than 1000 dusts.
As preferably: the thickness of the gate oxide in said low-voltage device district is less than 50 dusts.
As preferably: in said substrate, be formed with buried regions, be formed with epitaxial loayer in said substrate top surface, the said epitaxial loayer of thermal oxidation is to form first grid oxide layer in said epitaxial loayer.
As preferably: on said substrate, also comprise before the thermal oxidation first grid oxide layer step:
On the substrate in said high tension apparatus zone, form the well region of high tension apparatus;
In said well region, form the drain-drift region of high tension apparatus HVPMOS and the channel region of high tension apparatus LDNMOS;
In said substrate, be formed for the isolation structure of isolating device.
As preferably: said isolation structure is a fleet plough groove isolation structure.
As preferably: before forming said second gate oxide, also be included in the well region that forms low-voltage device in the said substrate.
Compared with prior art; The present invention is in high tension apparatus and low-voltage device grid forming process; Rest on the grid oxic horizon; Etching is removed the grid oxic horizon on the high voltage device regions again, and it is poor because of thickness of grid oxide layer to have solved high tension apparatus and low-voltage device, in the removal process at the same time; The low-voltage device active area that grid oxic horizon on the high voltage device regions causes when removing fully damages and electric leakage and isolated failure, and high tension apparatus source/drain region that the grid oxic horizon on the high voltage device regions causes when not exclusively removing can't form metal silicide.
Description of drawings
Fig. 1 is the flow chart of the lithographic method of bigrid oxide layer in the BCD technology of the present invention;
Fig. 2 a-2m is the profile of each processing step in the lithographic method of bigrid oxide layer in the BCD technology of the present invention.
Embodiment
The present invention below will combine accompanying drawing to do further to detail:
A lot of details have been set forth in the following description so that make much of the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention does not receive the restriction of following disclosed practical implementation.
Secondly, the present invention utilizes sketch map to be described in detail, when the embodiment of the invention is detailed; For ease of explanation; The profile of expression device architecture can be disobeyed general ratio and done local the amplification, and said sketch map is instance, and it should not limit the scope of the present invention's protection at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 1 shows the flow chart of the lithographic method of bigrid oxide layer in the BCD technology of the present invention.
See also shown in Figure 1; The present invention provides the lithographic method of bigrid oxide layer in a kind of BCD technology; Present embodiment mesohigh device is an example with LDNMOS and HVPMOS; Low-voltage device is an example with CMOS, comprises 101 to 108 steps, specifies the concrete operations of each step below in conjunction with accompanying drawing 2a to 2m.
In step 101; Shown in Fig. 2 a; One substrate 200 is provided, comprises high voltage device regions I arranged side by side and low-voltage device district II on the said substrate 200, said substrate 200 can be that silicon substrate, germanium silicon substrate, the 3rd are to pentelide substrate or silicon-on-insulator substrate; Or well known to a person skilled in the art other semiconductive material substrate, what adopt in the present embodiment is the silicon substrate that the P type mixes.In addition, in the present embodiment, also be formed with epitaxial loayer 201 on the said substrate 200, also be formed with buried regions 202 in the substrate 200 below epitaxial loayer 201, the doping type of epitaxial loayer 201 is P types, and the doping type of said buried regions 202 is the N type.
In step 102, on the substrate in said high voltage device regions and low-voltage device district, form the gate oxide of high voltage device regions and the gate oxide in low-voltage device district, the gate oxide thickness of said high voltage device regions is greater than the gate oxide in low-voltage device district; The formation of the gate oxide in the gate oxide of said high voltage device regions and low-voltage device district may further comprise the steps:
Shown in Fig. 2 e, in the present embodiment, in the high voltage device regions I and the low-voltage device district II thermal oxidation first grid oxide layer of said substrate; Promptly thermal oxidation forms first grid oxide layer 207 in epitaxial loayer 201,
Need to prove that present embodiment also comprises before thermal oxidation first grid oxide layer 207 steps in said epitaxial loayer 201:
Shown in Fig. 2 b, at first, inject and annealing process through ion, in the epitaxial loayer 201 of said high tension apparatus zone I, form the well region 203 of high tension apparatus, the doping type of well region 203 is the N type;
Shown in Fig. 2 c, then, in the well region 203 of high tension apparatus, form the drain-drift region 204 of HVPMOS, the doping type of drain-drift region 204 is the P type;
Shown in Fig. 2 d; Then; In said epitaxial loayer 201, form isolation structure 206; Be useful on the LDNMOS that is isolated in the follow-up formation of high voltage device regions I and the isolation structure of HVPMOS in all isolation structures 206, be useful on the PMOS that is isolated in the follow-up formation of low-voltage device district II and the isolation structure of NMOS, also be useful on the isolation structure of isolated high-voltage device region I and low-voltage device district II; Be arranged at the isolation structure in the drift region of high voltage device regions I in addition, be used to improve the breakdown voltage that high tension apparatus causes because of high pressure.Said isolation structure 206 can be fleet plough groove isolation structure, can also be field oxide; Then, the source region part of LDNMOS is carried out the ion injection in said high tension apparatus zone I, in the well region 203 of high tension apparatus, forms the channel region 205 of LDNMOS, and other place is the drift region.
Shown in Fig. 2 f, etching is removed the first grid oxide layer 207 on the low-voltage device district II;
Shown in Fig. 2 h; Thermal oxidation second gate oxide 209 on low-voltage device district II and high voltage device regions I; The gate oxide of said high voltage device regions I comprises the first grid oxide layer 207 and second gate oxide 209, and the gate oxide of said low-voltage device district II comprises second gate oxide 209; The thickness of the gate oxide of said high voltage device regions I is greater than 1000 dusts, and the thickness of the gate oxide of said low-voltage device district II is less than 50 dusts.
Present embodiment also adopts methods such as ion injection before thermal oxidation forms said second gate oxide 209, in the epitaxial loayer 201 of low-voltage device area I I, form the well region 208 of low-voltage device, and shown in Fig. 2 g, said well region 208 can comprise P trap and N trap.
Gate oxide and the gate oxide of low-voltage device district II that said formation has the high voltage device regions I of thickness difference can also adopt other generation types; For example adopt the direct mask of mask plate technology to form gate oxide and the gate oxide of low-voltage device district II of the high voltage device regions I of different-thickness with low-voltage device district II at high voltage device regions I; Perhaps forming one deck with low-voltage device district II through chemical vapour deposition (CVD) or thermal oxidation technology at high voltage device regions I (can be in fact the thickness of the gate oxide of high voltage device regions I than thick oxide layer; For example greater than 1000 dusts); And then etching is removed the certain thickness oxide layer of low-voltage device district II, the gate oxide of the low-voltage device district II of formation predefine thickness (for example being to keep thickness less than 50 dusts).
In step 103, deposit spathic silicon (not shown) on the gate oxide of the gate oxide of high voltage device regions I and low-voltage device district II.
In step 104, shown in Fig. 2 i, etch polysilicon forms the grid 210a of said high voltage device regions I and the grid 210b of low-voltage device district II, rests on the gate oxide of low-voltage device district II.
In step 105, shown in Fig. 2 j, apply photoresist 211, photoetching forms window 211a, exposes high voltage device regions I in the window 211a; Then, shown in Fig. 2 k, be mask with the grid 210a of said high voltage device regions I, etching is removed the gate oxide of said high voltage device regions I except that grid 213a below; Then, shown in figure 21, remove photoresist 211.
In step 106, shown in Fig. 2 m, be mask with the grid 210a of high voltage device regions I and the grid 210b of low-voltage device district II; Form source/drain region 212 of high voltage device regions I and source/drain region 213 of low-voltage device district II; The following adopted silicification technics forms metal silicide and reduces contact resistance, and the gate oxide in said low-voltage device zone is removed in follow-up technology, for example the grid curb wall etching; Etching before metal silicide forms, and follow-up cleaning.
Difference according to concrete type of device; In the high tension apparatus zone; The source region of LDNMOS and the doping type in drain region are the N type, and the source region of HVPMOS and the doping type in drain region are the P type, and in the low-voltage device zone; The source region of PMOS and the doping type in drain region are the P type, and the source region of NMOS and the doping type in drain region are the N type.
So far, present embodiment has been accomplished the forming process of LDNMOS, HVPMOS and cmos device.Certainly, in other specific embodiment, high tension apparatus can also be to well known to a person skilled in the art other high tension apparatus, and low-voltage device can also be to well known to a person skilled in the art other low-voltage device.
The present invention is in high tension apparatus and low-voltage device grid forming process; Rest on the grid oxic horizon; Etching is removed the grid oxic horizon on the high voltage device regions again; It is poor because of thickness of grid oxide layer to have solved high tension apparatus and low-voltage device; In the removal process at the same time, the low-voltage device active area that the grid oxic horizon on the high voltage device regions causes when removing fully damages and electric leakage and isolated failure, and high tension apparatus source/drain region that the grid oxic horizon on the high voltage device regions causes when not exclusively removing can't form metal silicide.
The above is merely preferred embodiment of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to the covering scope of claim of the present invention.
Claims (8)
1. the lithographic method of bigrid oxide layer in the BCD technology is characterized in that, may further comprise the steps:
One substrate is provided, and said substrate comprises high voltage device regions arranged side by side and low-voltage device district;
In the high voltage device regions of said substrate and low-voltage device district, form the gate oxide of high voltage device regions and the gate oxide in low-voltage device district, the gate oxide thickness of said high voltage device regions is greater than the gate oxide in low-voltage device district;
Deposit spathic silicon on the gate oxide in the gate oxide of said high voltage device regions and low-voltage device district;
Etch polysilicon forms the grid in said high voltage device regions and low-voltage device district, rests on the gate oxide in said low-voltage device district;
Grid with said high voltage device regions is a mask, and etching is removed the gate oxide of said high voltage device regions except that the grid below;
As mask, form the source/drain region in high voltage device regions and low-voltage device district with the grid in said high voltage device regions and low-voltage device district.
2. the lithographic method of bigrid oxide layer in the BCD technology according to claim 1 is characterized in that: the formation of the gate oxide in the gate oxide of said high voltage device regions and low-voltage device district may further comprise the steps:
Thermal oxidation first grid oxide layer in the high voltage device regions of said substrate and low-voltage device district;
Etching is removed the first grid oxide layer in the low-voltage device district;
Thermal oxidation second gate oxide on low-voltage device district and high voltage device regions, the gate oxide of said high voltage device regions comprises the first grid oxide layer and second gate oxide, the gate oxide in said low-voltage device district comprises second gate oxide.
3. the lithographic method of bigrid oxide layer in the BCD technology according to claim 1 and 2, it is characterized in that: the thickness of the gate oxide of said high voltage device regions is greater than 1000 dusts.
4. the lithographic method of bigrid oxide layer in the BCD technology according to claim 1 and 2 is characterized in that: the thickness of the gate oxide in said low-voltage device district is less than 50 dusts.
5. the lithographic method of bigrid oxide layer in the BCD technology according to claim 2; It is characterized in that; In said substrate, be formed with buried regions, be formed with epitaxial loayer in said substrate top surface, the said epitaxial loayer of thermal oxidation is to form said first grid oxide layer in said epitaxial loayer.
6. the lithographic method of bigrid oxide layer is characterized in that in the BCD technology according to claim 2, on said substrate, also comprises before the thermal oxidation first grid oxide layer step:
Form the well region of high tension apparatus in the high voltage device regions of said substrate;
In said well region, form the drain-drift region of high tension apparatus HVPMOS and the channel region of high tension apparatus LDNMOS;
In said substrate, be formed for the isolation structure of isolating device.
7. the lithographic method of bigrid oxide layer in the BCD technology according to claim 6 is characterized in that: said isolation structure is a fleet plough groove isolation structure.
8. the lithographic method of bigrid oxide layer in the BCD technology according to claim 2 is characterized in that: before thermal oxidation forms said second gate oxide, also be included in the well region that forms low-voltage device in the low-voltage device district of said substrate.
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| CN2012100815126A CN102610506A (en) | 2012-03-23 | 2012-03-23 | Method for etching bi-grid oxide layer in BCD technology |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109545788A (en) * | 2018-11-28 | 2019-03-29 | 武汉新芯集成电路制造有限公司 | Semiconductor devices and its manufacturing method |
| CN111785689A (en) * | 2020-08-26 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | CMOS device and forming method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5960289A (en) * | 1998-06-22 | 1999-09-28 | Motorola, Inc. | Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region |
| TW393692B (en) * | 1998-12-04 | 2000-06-11 | United Microelectronics Corp | Method for producing dual gate |
| US6100141A (en) * | 1998-11-04 | 2000-08-08 | United Microelectronics Corp. | Method for forming electrostatic discharge (ESD) protection circuit |
| CN102254806A (en) * | 2011-07-04 | 2011-11-23 | 上海先进半导体制造股份有限公司 | Method for double-grid oxide layer in BCD (Bipolar, COMS and DMOS) process |
-
2012
- 2012-03-23 CN CN2012100815126A patent/CN102610506A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5960289A (en) * | 1998-06-22 | 1999-09-28 | Motorola, Inc. | Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region |
| US6100141A (en) * | 1998-11-04 | 2000-08-08 | United Microelectronics Corp. | Method for forming electrostatic discharge (ESD) protection circuit |
| TW393692B (en) * | 1998-12-04 | 2000-06-11 | United Microelectronics Corp | Method for producing dual gate |
| CN102254806A (en) * | 2011-07-04 | 2011-11-23 | 上海先进半导体制造股份有限公司 | Method for double-grid oxide layer in BCD (Bipolar, COMS and DMOS) process |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109545788A (en) * | 2018-11-28 | 2019-03-29 | 武汉新芯集成电路制造有限公司 | Semiconductor devices and its manufacturing method |
| CN111785689A (en) * | 2020-08-26 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | CMOS device and forming method thereof |
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Application publication date: 20120725 |