CN102479713B - MOSFET manufacture method and MOSFET - Google Patents

MOSFET manufacture method and MOSFET Download PDF

Info

Publication number
CN102479713B
CN102479713B CN201010564084.3A CN201010564084A CN102479713B CN 102479713 B CN102479713 B CN 102479713B CN 201010564084 A CN201010564084 A CN 201010564084A CN 102479713 B CN102479713 B CN 102479713B
Authority
CN
China
Prior art keywords
oxide
source region
epi
gate
mosfet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201010564084.3A
Other languages
Chinese (zh)
Other versions
CN102479713A (en
Inventor
阿里耶夫·阿里伽日·马高米道维奇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CSMC Technologies Corp
Original Assignee
CSMC Technologies Corp
Wuxi CSMC Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CSMC Technologies Corp, Wuxi CSMC Semiconductor Co Ltd filed Critical CSMC Technologies Corp
Priority to CN201010564084.3A priority Critical patent/CN102479713B/en
Priority to PCT/CN2011/083107 priority patent/WO2012072020A1/en
Publication of CN102479713A publication Critical patent/CN102479713A/en
Application granted granted Critical
Publication of CN102479713B publication Critical patent/CN102479713B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

Abstract

The embodiment of the invention discloses a kind of MOSFET manufacture method and a kind of MOSFET, the method comprises: form gate oxide and polysilicon gate on the surface at epitaxial loayer; Source region is formed in epi-layer surface; Carry out source region oxidation, in the space on area surface between polysilicon gate and source region, form oxide.The embodiment of the present invention additionally provides a kind of MOSFET, comprise epitaxial loayer, the source region be formed in epi-layer surface, be formed at gate oxide in epi-layer surface and polysilicon gate, on the area surface of described MOSFET, in space between polysilicon gate and source region, be provided with the oxide layer adopting thermal oxide growth technique to be formed.In the embodiment of the present invention, the oxide that area surface is formed is filled with the gap between polysilicon gate edge and source region, adds the thickness of the gate oxide at edge, grid region simultaneously, therefore, it is possible to the possibility that the gate oxide reducing edge, grid region is breakdown.

Description

MOSFET manufacture method and MOSFET
Technical field:
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of MOSFET manufacture method and a kind of MOSFET.
Background technology:
Along with the develop rapidly of semiconductor fabrication, semiconductor device is in order to reach arithmetic speed faster.Larger memory data output and more function, semiconductor wafer, towards higher component density, high integration future development, also comes high to the requirement of its physical structure and manufacturing process.
With MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor, metal oxide semiconductor field effect tube) be example, existing manufacturing process generally includes following step: in the epi-layer surface of semiconductor wafer, form gate oxide and polysilicon layer successively; Grid region figure is formed at polysilicon surface successively by steps such as coating photoresists, on a photoresist marking grid region graphic structure, polysilicon gate etching, removal photoresist; Adopt ion implantation and impurity to push away trap, form tagma; Source region is formed in tagma; Somatomedin layer; Form the contact hole leading to grid region, source region in the dielectric layer; The local interlinkage carrying out metal contact wires completes metallization.As shown in Figure 1, be the partial structurtes schematic diagram of a kind of common MOSFET obtained by existing manufacturing process, specifically comprise: epitaxial loayer 101, polysilicon gate 102, gate oxide 103, source region 104 and tagma 105.
By the research of the partial structurtes schematic diagram to the MOSFET shown in Fig. 1; inventor finds: in this MOSFET, at the marginal position in its grid region, usually can there is space 106 between polysilicon gate 102 and source region 104; and ideally, space 106 should be gate oxide.Space 106 is in follow-up vapor deposition processing procedure, serve as dielectric film, the dielectric oxide that vapor deposition is formed fills region, space 106, because the conductive intensities of dielectric oxide will far be weaker than the gate oxide formed by thermal oxidation, therefore there is grid oxygen punch-through possibly in the gate oxide at edge, grid region, and MOSFET is scrapped.
Summary of the invention
For solving the problems of the technologies described above, the object of the present invention is to provide the manufacture method of a kind of MOSFET and a kind of MOSFET, to solve the problem of the gate oxide generation grid oxygen punch-through at edge, MOSFET grid region, thus improving the useful life of MOSFET.
For achieving the above object, the invention provides following technical scheme:
A kind of MOSFET manufacture method, comprising:
Gate oxide and polysilicon gate is formed on the surface at epitaxial loayer;
Source region is formed in epi-layer surface;
Carry out source region oxidation, in the space on area surface between polysilicon gate and source region, form oxide.
Preferably, form source region in epi-layer surface after, before carrying out source region oxidation, also comprise:
Semiconductor wafer is annealed.
Preferably,
The oxide thickness that area surface is formed is 1 to 3 times of gate oxide thickness.
Preferably,
Temperature when semiconductor wafer is annealed is 800 ~ 900 degrees Celsius, and anneal duration is 14 ~ 16 minutes.
Preferably,
Adopt thermal oxide growth technique to carry out source region oxidation, the duration is 14 ~ 16 minutes.
Preferably, before source region is formed, also comprise:
In described polysilicon gate both sides, push away trap by ion implantation and impurity, form tagma;
Described source region is formed in described tagma.
Preferably, before formation gate oxide and polysilicon layer, also comprise:
The epi-layer surface of semiconductor wafer forms protective oxide film;
Conductive protection regional graphics are formed at protective oxide film by photoetching process;
Push away trap at conductive protection region ion implantation, impurity, form well region;
Remove protective oxide film.
Preferably, after removal protective oxide film, also comprise:
The epi-layer surface of oxide-semiconductor wafer;
In oxide on epitaxial loayer surface, photoetching is formed with source region figure;
Oxide in erosion removal epi-layer surface.
Preferably, after formation source region, also comprise:
Semiconductor wafer epi-layer surface forms dielectric layer;
Form the contact hole leading to grid region, source region in the dielectric layer respectively;
Metallize at described contact hole, obtain grid, source electrode;
Drain electrode is formed at the semiconductor wafer substrate back side.
Present invention also offers a kind of MOSFET, comprise epitaxial loayer, the source region be formed in epi-layer surface, be formed at gate oxide in epi-layer surface and polysilicon gate;
On the area surface of described MOSFET, in the space between polysilicon gate and source region, be provided with the oxide layer adopting thermal oxide growth technique to be formed.
Preferably, the thickness of described oxide layer is 1 ~ 3 times of gate oxide thickness.
The technique effect of the technical scheme that the embodiment of the present invention provides is, in MOSFET, the oxide that area surface is formed is filled with the gap between polysilicon gate edge and source region, add the thickness of the gate oxide at edge, grid region simultaneously, therefore, the possibility that the gate oxide at edge, grid region is breakdown can be reduced, improve the useful life making MOSFET.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the partial structurtes schematic diagram of MOSFET of the prior art;
The partial structurtes schematic diagram of the MOSFET that Fig. 2 provides for the embodiment of the present invention one;
The partial structurtes schematic diagram of the MOSFET that Fig. 3 provides for the embodiment of the present invention two.
Embodiment
In existing MOSFET, the marginal position in its grid region, usually can there is space, and ideally, this space should be gate oxide between polysilicon gate and source region.This space is normally formed in gate oxide corrosion process, in follow-up vapor deposition processing procedure, dielectric oxide can be formed in this space, because the conductive intensities of dielectric oxide will far be weaker than the gate oxide formed by thermal oxidation, therefore there is grid oxygen punch-through possibly in the void area being covered with dielectric oxide, MOSFET is scrapped.
Embodiments provide a kind of MOSFET manufacture method, after source region is formed, dielectric layer comprises: annealed by semiconductor wafer before being formed for this reason; Carry out source region oxidation, on area surface, comprise in the space between polysilicon gate and source region, form oxide.
The embodiment of the present invention additionally provides a kind of MOSFET, on the area surface of described MOSFET, in the space between polysilicon gate and source region, is provided with the oxide layer adopting thermal oxide growth technique to be formed.
It is more than core concept of the present invention, below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Embodiment one:
Present embodiments provide a kind of MOSFET manufacture method, the method is after source region is formed, and dielectric layer comprises before being formed:
Gate oxide and polysilicon gate is formed on the surface at epitaxial loayer;
Source region is formed in epi-layer surface;
Carry out source region oxidation, in the space on area surface between polysilicon gate and source region, form oxide.
It should be noted that, the epitaxial loayer in the present embodiment can be the N formed on the semiconductor wafer -~ N +type structure, the thickness of epitaxial loayer can require to determine according to the embody rule of device, and epitaxial loayer can be positioned at front or the back side of semiconductor wafer.
In this step, the concrete grammar forming gate oxide can be: adopt thermal oxidation technology to form gate oxide in the epi-layer surface of semiconductor wafer substrate, the gate oxide in the present embodiment at least comprises silica, and its thickness can be 20 ~ 50 dusts.The concrete grammar forming polysilicon layer can be: the semiconductor wafer comprising gate oxide is proceeded to low-pressure chemical vapor phase deposition equipment, and silane is passed in the process cavity of equipment, after silane decomposes, polysilicon deposition is on gate oxide surface, and wherein the thickness of polysilicon layer is about 5000 dusts.After polysilicon deposition completes, polysilicon doping operation can also be carried out.
In photoresist layer, by forming grid region figure after exposure and developing procedure, and being mask with photoresist layer, being removed gate oxide and the polysilicon layer of figure outside, grid region by etching process, forming grid region.In this step, specifically can pass through isotropic plasma etching polysilicon gate, also can be completed by wet chemical etch process.
As shown in Figure 2, be the partial structurtes schematic diagram of the MOSFET after the source region oxidation that the present embodiment provides, wherein, 201 is epitaxial loayer, and 202 is polysilicon gate, and 203 is gate oxide, and 204 is source region, and 205 is tagma, and 207 is the oxide that area surface is formed.In the present embodiment, described epitaxial loayer 201 can be N -~ N +type doped structure, described source region 204 is can adulterate for N+ type, can adulterate for P-type in described tagma 205.
Design parameter when semiconductor wafer is annealed in the lehr can be: temperature is 800 ~ 900 degrees Celsius, and anneal duration is 14 ~ 16 minutes, in annealing process, can also pass into nitrogen in annealing furnace, adopts n 2 annealing technique.One preferably annealing way is, during annealing, temperature controls at 850 degrees Celsius, and the duration is 15 minutes.
Generally, gate oxide adopts thermal oxide growth technique to be formed, therefore the electrical and gate oxide in order to the oxide making source region be formed is close, in the present embodiment, thermal oxide growth technique is adopted to carry out source region oxidation, be specifically as follows by hydrogen and oxygen in oxidation reaction chamber, the duration can be 14 ~ 16 minutes, is preferably 15 minutes.
In the technical scheme that the present embodiment provides, the thickness of the oxide that area surface is formed is generally 1 ~ 3 times of gate oxide, and its thickness can also be controlled by the impurity doping concentration controlling source region.
In the present embodiment, the oxide that area surface is formed is filled with the gap between polysilicon gate edge and source region, adds the thickness of the gate oxide at edge, grid region, therefore simultaneously, the possibility that the gate oxide at edge, grid region is breakdown can be reduced, improve the useful life making MOSFET.
Embodiment two:
Present embodiments provide a kind of concrete MOSFET manufacture method, on the basis of the method provided in embodiment one, in the present embodiment, can also comprise before source region is formed:
In described polysilicon gate both sides, push away trap by ion implantation and impurity, form tagma;
Described source region is formed in described tagma.
Take polysilicon gate as mask, in described polysilicon gate both sides, carry out ion implantation, and impurity pushes away trap, form tagma.In subsequent step, source region is formed by implanted dopant in tagma.
In the present embodiment, before formation gate oxide and polysilicon layer, can also form the conductive protection region realizing device isolation for the protection of device in the semiconductor wafer, its implementation can comprise:
The epi-layer surface of semiconductor wafer substrate forms protective oxide film;
Conductive protection regional graphics are formed at protective oxide film by photoetching process;
Push away trap at conductive protection region ion implantation, impurity, form well region;
Remove protective oxide film.
Wherein, protective oxide film can pass into oxygen in high-temperature technology chamber; obtain with silicon generation oxidation reaction; mainly as oxide screen; control in ion implantation process, impurity injects scope and the degree of depth, and protects epi-layer surface from contamination; prevent in ion implantation process, to silicon chip excessive damage.
In addition, in order to define multiple active area respectively in a semiconductor wafer, after above-mentioned removal protective oxide film, before forming grid oxide layer and polysilicon layer, can also comprise:
Step 41, the epi-layer surface of oxide-semiconductor wafer substrates;
Step 42, in the oxide of epi-layer surface, photoetching is formed with source region figure;
Step 43, the oxide of erosion removal epi-layer surface.
Be can be implemented in semiconductor wafer by above-mentioned steps and form multiple active area, and then form multiple semiconductor device.
The method that the embodiment of the present invention provides, after formation source region, can also comprise:
Step 51, the epi-layer surface of semiconductor wafer substrate forms dielectric layer;
Step 52, forms the contact hole leading to grid region, source region in the dielectric layer respectively;
Step 53, metallizes, and obtains grid, source electrode;
Step 54, forms drain electrode at the semiconductor wafer substrate back side.
MOSFET partial structurtes schematic diagram that specifically can be shown in Figure 3, wherein, 201 is the epitaxial loayer of semiconductor wafer, and 202 is the grid region formed after polysilicon gate etching, and 203 is gate oxide, 205 is tagma, 204 is source region, and 207 is the oxide of area surface, and 210 is drain region, 208 is dielectric layer, and 209 for being filled with the through hole of metal material.
Concrete, described epitaxial loayer 201 is can be N -~ N +type doped structure, described source region 204 is can be N +type adulterates, and described tagma 205 can be P -type adulterates, and is formed by with under type: with grid region figure for mask, injects boron ion, and carries out impurity and push away trap, forms P -the tagma of type doping.
Embodiment three:
Corresponding to said method embodiment, the present embodiment additionally provides a kind of MOSFET.
Described MOSFET, comprises epitaxial loayer, the source region be formed in epi-layer surface, is formed at gate oxide in epi-layer surface and polysilicon gate;
On the area surface of described MOSFET, in the space between polysilicon gate and source region, be provided with the oxide layer adopting thermal oxide growth technique to be formed.
Preferably, the thickness of described oxide layer can be 1 ~ 3 times of gate oxide thickness.
Because the present embodiment is that application said method embodiment obtains device architecture embodiment, its similarity can cross-reference, repeats no more.
In the embodiment of the present invention, the oxide that area surface is formed is filled with the gap between polysilicon gate edge and source region, adds the thickness of the gate oxide at edge, grid region, therefore simultaneously, the possibility that the gate oxide at edge, grid region is breakdown can be reduced, improve the useful life making MOSFET.
In this specification, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar portion mutually see.To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.

Claims (7)

1. a MOSFET manufacture method, is characterized in that:
Gate oxide and polysilicon gate is formed on the surface at epitaxial loayer;
Source region is formed in epi-layer surface;
Thermal oxide growth technique is adopted to carry out source region oxidation, duration is 14 ~ 16 minutes, in space on area surface between polysilicon gate and source region, form oxide, described oxide thickness is 1 to 3 times of gate oxide thickness, and the thickness of described gate oxide is controlled by the impurity doping concentration controlling source region;
Wherein, before formation gate oxide and polysilicon layer, also comprise:
The epi-layer surface of semiconductor wafer forms protective oxide film;
Conductive protection regional graphics are formed at protective oxide film by photoetching process;
Push away trap at conductive protection region ion implantation, impurity, form well region;
Remove protective oxide film.
2. method according to claim 1, is characterized in that, after forming source region, before carrying out source region oxidation, also comprises in epi-layer surface:
Semiconductor wafer is annealed.
3. method according to claim 2, is characterized in that:
Temperature when semiconductor wafer is annealed is 800 ~ 900 degrees Celsius, and anneal duration is 14 ~ 16 minutes.
4. method according to claim 1, is characterized in that:
Before source region is formed, also comprise:
In described polysilicon gate both sides, push away trap by ion implantation and impurity, form tagma;
Described source region is formed in described tagma.
5. method according to claim 1, is characterized in that, after removal protective oxide film, also comprises:
The epi-layer surface of oxide-semiconductor wafer;
In oxide on epitaxial loayer surface, photoetching is formed with source region figure;
Oxide in erosion removal epi-layer surface.
6. method according to claim 1, is characterized in that, after formation source region, also comprises:
Semiconductor wafer epi-layer surface forms dielectric layer;
Form the contact hole leading to grid region, source region in the dielectric layer respectively;
Metallize at described contact hole, obtain grid, source electrode;
Drain electrode is formed at the semiconductor wafer substrate back side.
7. a MOSFET, comprises epitaxial loayer, the source region be formed in epi-layer surface, is formed at gate oxide in epi-layer surface and polysilicon gate, it is characterized in that:
On the area surface of described MOSFET, in the space between polysilicon gate and source region, be provided with the oxide layer adopting thermal oxide growth technique to be formed;
The thickness of described oxide layer is 1 ~ 3 times of gate oxide thickness, and the thickness of described gate oxide is controlled by the impurity doping concentration controlling source region;
Wherein, before formation gate oxide and polysilicon layer, also comprise:
The protective oxide film that the epi-layer surface of semiconductor wafer is formed;
By the conductive protection regional graphics that photoetching process is formed at protective oxide film;
Trap is pushed away by ion implantation, impurity, the well region of formation in conductive protection region;
Remove protective oxide film.
CN201010564084.3A 2010-11-29 2010-11-29 MOSFET manufacture method and MOSFET Active CN102479713B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201010564084.3A CN102479713B (en) 2010-11-29 2010-11-29 MOSFET manufacture method and MOSFET
PCT/CN2011/083107 WO2012072020A1 (en) 2010-11-29 2011-11-29 Metal-oxide-semiconductor field-effect transistor (mosfet) and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201010564084.3A CN102479713B (en) 2010-11-29 2010-11-29 MOSFET manufacture method and MOSFET

Publications (2)

Publication Number Publication Date
CN102479713A CN102479713A (en) 2012-05-30
CN102479713B true CN102479713B (en) 2015-09-09

Family

ID=46092294

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201010564084.3A Active CN102479713B (en) 2010-11-29 2010-11-29 MOSFET manufacture method and MOSFET

Country Status (2)

Country Link
CN (1) CN102479713B (en)
WO (1) WO2012072020A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110112065A (en) * 2019-05-10 2019-08-09 德淮半导体有限公司 Semiconductor devices and forming method thereof
CN112103336B (en) * 2020-08-19 2022-09-09 厦门市三安集成电路有限公司 SiC power device and manufacturing method thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1338781A (en) * 2000-08-10 2002-03-06 三洋电机株式会社 Insulated gate semiconductor device and manufacture thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8129779B2 (en) * 2007-09-03 2012-03-06 Rohm Co., Ltd. Trench gate type VDMOSFET device with thicker gate insulation layer portion for reducing gate to source capacitance
JP2009070849A (en) * 2007-09-10 2009-04-02 Rohm Co Ltd Semiconductor device
WO2010119789A1 (en) * 2009-04-13 2010-10-21 ローム株式会社 Semiconductor device and method for manufacturing semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1338781A (en) * 2000-08-10 2002-03-06 三洋电机株式会社 Insulated gate semiconductor device and manufacture thereof

Also Published As

Publication number Publication date
CN102479713A (en) 2012-05-30
WO2012072020A1 (en) 2012-06-07

Similar Documents

Publication Publication Date Title
CN110034067B (en) Semiconductor device and method of forming the same
CN113937005A (en) Method for manufacturing metal oxide semiconductor transistor
CN102479713B (en) MOSFET manufacture method and MOSFET
EP1732112A1 (en) Method for manufacturing semiconductor device
CN107799418A (en) Semiconductor structure and forming method thereof
CN103178014B (en) A kind of manufacture method of U-shaped groove
KR100840662B1 (en) Manufacturing Method of Semiconductor Device
CN108630535B (en) Semiconductor structure and forming method thereof
CN102543716A (en) Method for forming salicide block layer
CN102543823B (en) Production method of shallow trench isolation
CN110581177A (en) Array substrate and preparation method thereof
CN101740391B (en) Fabricating method of NMOS (N-channel Metal Oxide Semiconductor)
CN110867412B (en) Manufacturing method of MOS device
JP3578345B2 (en) Semiconductor device manufacturing method and semiconductor device
CN103346125B (en) Improve the method for the electrical parameter homogeneity of GP cmos device
KR101068135B1 (en) Method for fabricating semiconductor device
CN103578947B (en) A kind of high dielectric metal gates manufacture method
CN102054698B (en) Method for improving threshold voltage of semiconductor device
KR100209232B1 (en) Method of fabricating mosfet of semiconductor device
KR100873816B1 (en) Method for manufacturing transistor
CN101740390A (en) Fabricating method of NMOS (N-channel Metal Oxide Semiconductor) transistor
JPH0442938A (en) Manufacture of semiconductor device
KR100600253B1 (en) Method For Manufacturing Semiconductor Devices
JP2007048840A (en) Semiconductor device and manufacturing method thereof
KR100929063B1 (en) Gate electrode formation method of semiconductor device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20171117

Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8

Patentee after: Wuxi Huarun Shanghua Technology Co., Ltd.

Address before: 214028 Wuxi provincial high tech Industrial Development Zone, Hanjiang Road, No. 5, Jiangsu, China

Co-patentee before: Wuxi Huarun Shanghua Technology Co., Ltd.

Patentee before: Wuxi CSMC Semiconductor Co., Ltd.

TR01 Transfer of patent right