CN101740390A - Fabricating method of NMOS (N-channel Metal Oxide Semiconductor) transistor - Google Patents
Fabricating method of NMOS (N-channel Metal Oxide Semiconductor) transistor Download PDFInfo
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- CN101740390A CN101740390A CN200810202834A CN200810202834A CN101740390A CN 101740390 A CN101740390 A CN 101740390A CN 200810202834 A CN200810202834 A CN 200810202834A CN 200810202834 A CN200810202834 A CN 200810202834A CN 101740390 A CN101740390 A CN 101740390A
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- semiconductor substrate
- polysilicon layer
- pass transistor
- nmos pass
- gate dielectric
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Abstract
The invention provides a fabricating method of an NMOS NMOS (N-channel Metal Oxide Semiconductor) transistor, which comprising the steps of: forming a gate dielectric layer on a semiconductor substrate; forming a polycrystalline silicon layer on the gate dielectric layer and controlling the lattice size of the polycrystalline silicon layer by controlling the pressure of a reaction chamber; etching the polycrystalline silicon layer and the gate dielectric layer to form a grid electrode structure; conducting ion injection in the semiconductor substrate at two sides of a grid electrode by taking the grid electrode structure as a mask to form source/drain electrode extension areas; and after side walls are formed at two sides of the grid electrode structure, forming source/drain electrodes in the semiconductor substrate at the grid electrode structure and the two sides of the side walls. By controlling the pressure of the reaction chamber, the invention controls the lattice size of the polycrystalline silicon layer, and achieves the qualified lattice size, which means that produced turn-off current does not influence the performance of the NMOS transistor.
Description
Technical field
The present invention relates to the semiconductor device processing technology field, relate in particular to the manufacture method of nmos pass transistor.
Background technology
Along with the develop rapidly of semiconductor fabrication, semiconductor device is in order to reach arithmetic speed faster, bigger memory data output and more function, and integrated circuit (IC) chip develops towards higher component density, high integration direction.In the evolution of semiconductor device, the making quality of grid directly affects transistorized performance and quality of semiconductor devices.
It is as follows to have the concrete technology that forms grid in the manufacturing process of nmos pass transistor now: with reference to shown in Figure 1, provide Semiconductor substrate 100, dopant ion in Semiconductor substrate 100 forms P type dopant well (not shown); Form gate dielectric layer 102 with thermal oxidation method or chemical vapour deposition technique on Semiconductor substrate 100, the material of described gate dielectric layer 102 is a silica; On gate dielectric layer 102, form polysilicon layer 104 with chemical vapour deposition technique; On polysilicon layer 104, form photoresist layer (not shown), define gate patterns through exposure imaging technology; With the photoresist layer is mask, injects the ion 105 of desired depth in polysilicon layer 104, in order to reduce the resistivity of polysilicon layer 104 as gate electrode, increases its conductivity, and described ion 105 is a phosphonium ion.
With reference to figure 2, then, continuing with the photoresist layer is mask, and etch polysilicon layer 104 and gate dielectric layer 102 are to exposing Semiconductor substrate 100, and the polysilicon layer 104 after the etching is as grid 104a, with the gate dielectric layer 102a formation grid structure 103 after the etching; After removing photoresist layer, the Semiconductor substrate 100 that will have each rete is put into reative cell, and aerating oxygen 107 oxidation grid 104a surfaces make grid 104a surfacing.
Please refer to Fig. 3, the Semiconductor substrate 100 that will have each rete forms silicon nitride layer (not shown) with chemical vapour deposition technique on Semiconductor substrate 100 and grid 104a after the reative cell taking-up; With dry etching method etch silicon nitride layer, remove the silicon nitride layer on the Semiconductor substrate 100, and form skew clearance wall 106 in grid structure 103 both sides; With grid structure 103 is mask, injects N type ion in Semiconductor substrate 100, forms N type source/drain electrode extension area 108 in the P type dopant well of grid structure 103 both sides.
With reference to shown in Figure 4, on the skew clearance wall 106 of grid structure 103 both sides, form side wall 109; Continuation is a mask with grid structure 106, injects N type ion in Semiconductor substrate 100, forms N type source/drain electrode 110; The Semiconductor substrate 100 that will have each rete and device is put into annealing furnace, and Semiconductor substrate 100 is annealed, and makes the ions diffusion of injection even.
Can also find more information relevant in Chinese patent application 03145409 with technique scheme.
Prior art is in the polysilicon layer process that forms nmos pass transistor, because follow-up side wall technology and the heat budget that the source/the drain electrode thermal annealing is brought can cause the polysilicon layer lattice dimensions after ion injects to become big, and then can cause cut-off current to raise, influence the performance of nmos pass transistor.
Summary of the invention
The problem that the present invention solves provides a kind of manufacture method of nmos pass transistor, prevents that the excessive cut-off current that causes of polysilicon layer lattice dimensions from raising.
For addressing the above problem, the manufacture method of a kind of nmos pass transistor of the present invention comprises: form gate dielectric layer on Semiconductor substrate; On gate dielectric layer, form polysilicon layer, by the lattice dimensions of control reaction chamber pressure control polysilicon layer; Etch polysilicon layer and gate dielectric layer form grid structure; With the grid structure is mask, carries out ion and inject formation source/drain electrode extension area in the Semiconductor substrate of grid both sides; After the grid structure both sides form side wall, formation source/drain electrode in the Semiconductor substrate of grid structure and side wall both sides.
Optionally, the pressure of described reaction chamber is 0.1 holder～0.3 holder.The temperature of described reaction chamber is 590 ℃～620 ℃.
Optionally, the lattice dimensions of polysilicon layer is 2nm～9nm.
Optionally, the method for formation polysilicon layer is chemical vapour deposition technique or Low Pressure Chemical Vapor Deposition.
Optionally, after forming polysilicon layer, also comprise, in polysilicon layer, inject the ion of desired depth.Described ion is a phosphonium ion.
Compared with prior art, the present invention has the following advantages: the lattice dimensions by control reaction chamber pressure control polysilicon layer, and make lattice dimensions reach requirement, promptly the cut-off current of Chan Shenging does not influence the performance of nmos pass transistor.
Description of drawings
Fig. 1 to Fig. 4 is the existing schematic diagram that forms nmos pass transistor;
Fig. 5 is the embodiment flow chart that the present invention forms nmos pass transistor;
Fig. 6 to Figure 10 is the embodiment schematic diagram that the present invention forms nmos pass transistor;
Figure 11 is the lattice dimensions of polysilicon layer and the graph of a relation of reaction chamber pressure;
Figure 12 is the lattice dimensions of polysilicon layer and the graph of a relation of cut-off current (Ioff).
Embodiment
The present invention makes lattice dimensions reach requirement by the lattice dimensions of control reaction chamber pressure control polysilicon layer, and promptly the cut-off current of Chan Shenging (Ioff) does not influence the performance of nmos pass transistor.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Fig. 5 is the embodiment flow chart that the present invention forms nmos pass transistor.Execution in step S11 forms gate dielectric layer on Semiconductor substrate.
The material of described gate dielectric layer is a silica, and the formation method is a thermal oxidation method.
Execution in step S12 forms polysilicon layer on gate dielectric layer, by the lattice dimensions of control reaction chamber pressure control polysilicon layer.
The pressure of reaction chamber is adjusted to 0.1 holder～0.3 holder, and the cut-off current of nmos pass transistor that can make follow-up formation has improved the electrical property of nmos pass transistor less than 10pA/ μ m.
After forming polysilicon layer, also comprise: in polysilicon layer, inject the phosphonium ion of desired depth,, increase its conductivity to reduce the resistivity of polysilicon layer as gate electrode.
Execution in step S13, etch polysilicon layer and gate dielectric layer form grid structure.
Etch polysilicon layer and gate dielectric layer are to exposing Semiconductor substrate, and the polysilicon layer after the etching is a grid, with the gate dielectric layer formation grid structure after the etching.
Execution in step S14 is a mask with the grid structure, carries out ion and inject formation source/drain electrode extension area in the Semiconductor substrate of grid both sides.
In the present embodiment, before formation source/drain electrode extension area, also comprise step: on Semiconductor substrate and grid structure, form silicon nitride layer; The etch silicon nitride layer, with the silicon nitride layer on the removal Semiconductor substrate, and at grid structure both sides formation skew clearance wall.
Execution in step S15, after the grid structure both sides form side wall, formation source/drain electrode in the Semiconductor substrate of grid structure and side wall both sides.
After formation source/drain electrode, the Semiconductor substrate that will have each rete and a device is put into annealing furnace and is carried out annealing process, and ion is spread in Semiconductor substrate evenly.
Fig. 6 to Figure 10 is the embodiment schematic diagram that the present invention forms nmos pass transistor.As shown in Figure 6, provide Semiconductor substrate 200, described Semiconductor substrate 200 can be silicon or silicon-on-insulator (SOI); Be formed with isolation structure (not shown) in Semiconductor substrate, described isolation structure is that shallow trench isolation is from (STI) structure or selective oxidation silicon (LOCOS) isolation structure.Be the NMOS active area between isolation structure, dopant ion in the Semiconductor substrate 200 of NMOS active area forms P type dopant well.
Forming thickness on Semiconductor substrate 200 is the gate dielectric layer 202 of 15 dusts～60 dusts, the material of described gate dielectric layer 202 is silica or silicon oxynitride, if gate dielectric layer 202 is a silica, then form method optional heat oxidizing process, if gate dielectric layer 202 is a silicon oxynitride, then formation method is chosen as chemical vapour deposition technique.
The Semiconductor substrate 200 that will have gate dielectric layer 202 is put into deposition reaction chamber 211, forms the polysilicon layer 204 that thickness is 800 dusts～1200 dusts with chemical vapour deposition technique or Low Pressure Chemical Vapor Deposition on gate dielectric layer 202.
In the present embodiment, the pressure of described reaction chamber 211 is 0.1 holder～0.3 holder.The temperature of described reaction chamber 211 is 590 ℃～620 ℃.Meet when reaction chamber 211 under the situation of above-mentioned condition, the lattice dimensions of polysilicon layer 204 is 2nm～9nm, and the cut-off current that meets the nmos pass transistor generation of follow-up formation does not influence the performance demands of nmos pass transistor.As a preferred embodiment, when the pressure in the reaction chamber 211 was 0.2 holder, the lattice dimensions minimum of the polysilicon layer 204 that obtains was 2.2nm, and cut-off current this moment (Ioff) value then is 0pA/ μ m.And when the lattice dimensions of polysilicon layer 204 during at 2nm～6nm, the value of cut-off current (Ioff) all is 0pA/ μ m, and therefore, it all is optimum value (as Figure 11 and shown in Figure 12) that the reaction pressure of reaction chamber 211 transfers to 0.15 holder～0.3 holder.
Present embodiment, the lattice dimensions of the pressure control polysilicon layer 204 by control reaction chamber 211 makes lattice dimensions reach requirement, makes cut-off current in the follow-up nmos pass transistor not influence the performance of nmos pass transistor.
As shown in Figure 7, the Semiconductor substrate 200 that will have each rete is taken out from reaction chamber 211; Then, on polysilicon layer 204, form photoresist layer (not shown),, define gate patterns through exposure imaging technology; With the photoresist layer is mask, injects the ion 205 of desired depth in polysilicon layer 204, can reduce the resistivity of polysilicon layer 204 as the NMOS gate electrode like this, increases its conductivity; As a preferred embodiment, described ion 205 is a phosphonium ion, and the injection energy is 8KeV, and implantation dosage is 1E15cm
-2
As shown in Figure 8, continuation is mask with the photoresist layer, and etch polysilicon layer 204 and gate dielectric layer 202 are to exposing Semiconductor substrate 200, and the polysilicon layer 204 after the etching is as grid 204a, constitute grid structure 203 with the gate dielectric layer 202a after the etching, described lithographic method can be the dry etching method; After removing photoresist layer, the Semiconductor substrate 200 that will have each rete is put into reative cell, and aerating oxygen 207 oxidation grid 204a surfaces make grid 204a surfacing.
Because after polysilicon layer being carried out ion injection and etching formation grid 204a, grid 204a surface can be uneven, forms leakage current easily.Therefore, need carry out oxidation to grid 204a surface and make it smooth.The flow of described aerating oxygen 207 is 4SLM, and temperature is 1000 ℃, and the time is 8 seconds, and pressure is 780 holders.
As shown in Figure 9, the Semiconductor substrate 200 that will have each rete forms silicon nitride layer (not shown) with chemical vapour deposition technique on Semiconductor substrate 200 and grid 204a after the reative cell taking-up; With dry etching method etch silicon nitride layer, remove the silicon nitride layer on the Semiconductor substrate 200, and form skew clearance wall 206 in grid structure 203 both sides; Along with further diminishing of device size, the channel length of device is more and more littler, it is also more and more littler that the particle of source/drain electrode injects the degree of depth, the effect of skew clearance wall 206 is to improve the channel length of the nmos pass transistor that forms, and reduces short-channel effect and because the hot carrier's effect that short-channel effect causes.In the present embodiment, the thickness of described skew clearance wall 206 may diminish to 80 dusts.
With grid structure 203 and skew clearance wall 206 is mask, carries out ion and inject in the Semiconductor substrate 200 of grid structure 203 both sides, forms N type source/drain electrode extension area 208.
Except that present embodiment, after forming N type source/drain electrode extension area 208, can continue with grid structure 203 is mask, in Semiconductor substrate 200, carry out bag shape and inject (Pocket implant), form bag shape injection region, the conduction type of described bag shape injection region and the conductivity type opposite of N type source/drain electrode extension area 208, its degree of depth is between N type source/drain electrode extension area 208 and follow-up source/drain electrode; Described bag shape injection technology can be used for improving the short-channel effect and the punch-through effect (punch through) of device.
With reference to accompanying drawing 10, on Semiconductor substrate 200, grid structure 203 and skew clearance wall 206, form silicon oxide layer, silicon oxide layer and silicon nitride layer or silicon oxide layer, silicon nitride layer and silicon oxide layer, adopt then to eat-back on the skew clearance wall 206 that (etch-back) method is formed at grid structure 203 both sides to form side wall 209.
Then, be mask with grid structure 203 and side wall 209, in the Semiconductor substrate 200 of grid structure 203 both sides, carry out ion and inject, form N type source/drain electrode 210.
At last, the Semiconductor substrate 200 that will have each rete and device is put into annealing furnace, and Semiconductor substrate 200 is carried out annealing in process, makes the ions diffusion of injection even.
In the present embodiment, what inject in Semiconductor substrate 200 is n type ion, as phosphonium ion or arsenic ion etc.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (7)
1. the manufacture method of a nmos pass transistor is characterized in that, comprising:
On Semiconductor substrate, form gate dielectric layer;
On gate dielectric layer, form polysilicon layer, by the lattice dimensions of control reaction chamber pressure control polysilicon layer;
Etch polysilicon layer and gate dielectric layer form grid structure;
With the grid structure is mask, carries out ion and inject formation source/drain electrode extension area in the Semiconductor substrate of grid both sides;
After the grid structure both sides form side wall, formation source/drain electrode in the Semiconductor substrate of grid structure and side wall both sides.
2. according to the manufacture method of the described nmos pass transistor of claim 1, it is characterized in that the pressure of described reaction chamber is 0.1 holder～0.3 holder.
3. according to the manufacture method of the described nmos pass transistor of claim 2, it is characterized in that the temperature of described reaction chamber is 590 ℃～620 ℃.
4. according to the manufacture method of the described nmos pass transistor of claim 1, it is characterized in that the lattice dimensions of polysilicon layer is 2nm～9nm.
5. according to the manufacture method of the described nmos pass transistor of claim 1, it is characterized in that the method that forms polysilicon layer is chemical vapour deposition technique or Low Pressure Chemical Vapor Deposition.
6. according to the manufacture method of the described nmos pass transistor of claim 1, it is characterized in that, after forming polysilicon layer, also comprise, in polysilicon layer, inject the ion of desired depth.
7. according to the manufacture method of the described nmos pass transistor of claim 6, it is characterized in that described ion is a phosphonium ion.
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| Application Number | Priority Date | Filing Date | Title |
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| CN200810202834A CN101740390A (en) | 2008-11-17 | 2008-11-17 | Fabricating method of NMOS (N-channel Metal Oxide Semiconductor) transistor |
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| CN200810202834A CN101740390A (en) | 2008-11-17 | 2008-11-17 | Fabricating method of NMOS (N-channel Metal Oxide Semiconductor) transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115020335A (en) * | 2022-08-09 | 2022-09-06 | 广州粤芯半导体技术有限公司 | Method for forming semiconductor structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115020335A (en) * | 2022-08-09 | 2022-09-06 | 广州粤芯半导体技术有限公司 | Method for forming semiconductor structure |
| CN115020335B (en) * | 2022-08-09 | 2022-11-04 | 广州粤芯半导体技术有限公司 | Method for forming semiconductor structure |
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Application publication date: 20100616 |