KR101013544B1 - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
KR101013544B1
KR101013544B1 KR1020030047208A KR20030047208A KR101013544B1 KR 101013544 B1 KR101013544 B1 KR 101013544B1 KR 1020030047208 A KR1020030047208 A KR 1020030047208A KR 20030047208 A KR20030047208 A KR 20030047208A KR 101013544 B1 KR101013544 B1 KR 101013544B1
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South Korea
Prior art keywords
gate
ion implantation
substrate
performing
oxide film
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KR1020030047208A
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Korean (ko)
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KR20050007665A (en
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오종혁
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매그나칩 반도체 유한회사
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET

Abstract

The present invention discloses a method for manufacturing a semiconductor device. The disclosed method includes growing a sacrificial oxide film on a surface of a silicon substrate, performing ion and implantation of nitrogen (N) ions simultaneously with well and channel ion implantation into the substrate, and performing a gate oxidation process on the substrate surface. After the gate oxide film is formed, depositing a gate conductive film, etching the gate conductive film and the gate oxide film to form a gate, performing a gate reoxidation process to remove etching damage, and performing LDD ions. Performing implantation, forming spacers on both sidewalls of the gate, performing source / drain ion implantation on the front of the substrate, and annealing the substrate product to source / drain regions having LDD regions in the substrate surface on both sides of the gate. Forming a drain region. According to the present invention, the dopant implanted into the LDD region and the source / drain region by the nitrogen (N) ions diffuses into the well and channel region in a subsequent thermal process by doping nitrogen (N) ions into the well and channel regions. Can be effectively prevented, thereby preventing the short channel effect and the reverse short channel effect caused by the high integration of the device.

Description

Method of manufacturing semiconductor device

1 is a graph illustrating the inverse short channel effect and short channel effect as the gate CD (critical dimension) decreases.

2A to 2D are cross-sectional views illustrating processes for manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

1: silicon substrate 2: device isolation film

3: sacrificial oxide film 4: gate oxide film

5: polysilicon film 6: gate

7 spacer 8 source / drain region

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of improving short channel effects.

As the high integration of semiconductor devices proceeds, the gate CD (Critical Dimension) becomes smaller and smaller, and accordingly, short channel effects such as punchthrough become a big problem. Various techniques have been proposed.

As a method for suppressing the short channel effect, a lightly doped drain (LDD) structure and pocket ion implantation have been adopted. In addition, a method of lowering LDD and source / drain ion implantation energy and reducing thermal budget has also been applied.

However, even in the above-described methods, the control of the short channel effect is not completely achieved.

FIG. 1 is a graph illustrating the inverse short channel effect and the short channel effect as the gate CD decreases. As shown in FIG. 1, a roll off phenomenon occurs due to the short channel effect as the gate CD decreases. Can be.

In particular, such a short channel effect is mainly caused by the lateral diffusion of dopants ion-implanted in the LDD region or the source / drain region, and various methods have been proposed for the control thereof. The diffusivity of boron (B), which is mainly used as a pMOS dopant, is not easy, and is larger in pMOS since it is relatively larger than phosphorus (P) or arsenic (As) used in nMOS.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving the short channel effect in a pMOS, which is devised to solve the above problems.

In order to achieve the above object, the present invention comprises the steps of growing a sacrificial oxide film on the surface of the silicon substrate with a device isolation film; Forming an ion implantation mask exposing a well region and a channel region on the sacrificial oxide film; Ion-implanting nitrogen (N) ions while sequentially performing well and channel ion implantation into the exposed substrate region; Removing the ion implantation mask and the sacrificial oxide film; Performing a gate oxidation process on the substrate resultant to form a gate oxide film on the surface of the substrate; Depositing a gate conductive film on the gate oxide film; Etching the gate conductive layer and the gate oxide layer to form a gate; Performing a gate reoxidation process to remove the etch damage; Performing LDD ion implantation on the entire surface of the substrate; Forming spacers on both side walls of the gate; Performing source / drain ion implantation on the entire surface of the substrate; And annealing the resultant substrate to form source / drain regions having LDD regions in the substrate surfaces on both sides of the gate.

Here, the sacrificial oxide film is grown to a thickness of 500 kPa or less. The nitrogen (N) ion implantation has an ion implantation energy of 100 keV or less on the basis of N2 + ions or an ion implantation energy of 50 keV or less on the basis of N + ions, a dose of 1E13-3E15 atoms / cm 3, and punch-through The generated depth is carried out with the ion implantation depth. The gate oxidation process proceeds to a low temperature plasma oxidation process of 600 ° C or lower.

According to the present invention, the dopant implanted into the LDD region and the source / drain region by the nitrogen (N) ions by doping nitrogen (N) ions into the well and channel regions is transferred to the well and channel regions in a subsequent thermal process. It is possible to effectively prevent the diffusion, thereby preventing the short channel effect and reverse channel effect caused by the high integration of the device.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

According to the present invention, since the nitrogen (N) inhibits the diffusion of boron (B), the boron (B) ion-implanted in the LDD region or the source / drain region is subsequently heat treated by doping nitrogen in the well and channel regions in advance. It is possible to prevent spreading in the city, thereby preventing short channel effects.

On the other hand, the nitrogen (N) doped in the well and channel region tends to diffuse to the surface region when it is subsequently accompanied by a thermal process such as an oxidation process, and thus, the nitrogen containing N Unwanted process results may be associated with the slower oxidation rate than that of silicon containing no nitrogen (N).

Thus, the present invention prevents the diffusion of nitrogen (N) doped in the well and channel regions to the substrate surface by proceeding the subsequent gate oxidation process to a low temperature plasma process of 600 ° C. or less instead of the usual thermal oxidation process.

In detail, a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 2A to 2D.                     

Referring to FIG. 2A, an isolation layer 2 is formed in a field region of the silicon substrate 1 by a shallow trench isolation process. Thereafter, a sacrificial oxidation process is performed on the substrate resultant, thereby growing the sacrificial oxide film 3 on the surface of the substrate active region. The growth thickness of the sacrificial oxide film 3 is adjusted to 500 Å or less. This is because if the growth thickness of the sacrificial oxide film 3 is too thick (more than 500 GPa), it is difficult to control the dopant in the channel region.

Referring to FIG. 2B, an ion implantation mask (not shown) is formed on the sacrificial oxide film 3 through a known lithography process, and then well ion implantation and channel ion implantation of pMOS and nMOS are sequentially performed. At this time, during the well and channel ion implantation of the pMOS and nMOS, nitrogen (N) is implanted at the same time so that nitrogen (N) doping is performed in the substrate 1 to an appropriate depth. In the case of nitrogen (N) ion implantation, the ion implantation energy is 100 keV or less on the basis of N2 + ion, and the ion implantation energy is 50 keV or less on the basis of N + ion, while the dose amount is about 1E13 to 3E15 atoms / cm 3, and the ion implantation depth is for each device. Although different, the target is performed at the depth at which punchthrough occurs.

Meanwhile, the nitrogen (N) ion implantation may be performed first for preamorphization for suppressing channeling of dopants in well and channel ion implantation.

Referring to FIG. 2C, in a state in which an ion implantation mask is removed according to a known photoresist strip process, a sacrificial oxide film on a surface of a substrate is removed by wet cleaning using an HF solution. Thereafter, a gate oxidation process is performed to form a gate oxide film 4 on the surface of the substrate active region, and then a polysilicon film 5 is deposited on the gate oxide film 4 as a gate conductive film, and then the polysilicon is deposited. The film 5 and the gate oxide film 4 are etched to form a gate 6 on the substrate active region.

Here, the gate oxidation process proceeds to a low temperature plasma oxidation process instead of the conventional thermal oxidation process. This is a thermal oxidation process requiring a process temperature of 700 ° C. or higher, and when the gate oxidation process is performed, the oxide layer is formed in each subsequent gate reoxidation process as nitrogen (N) ions doped in the well and channel regions diffuse to the substrate surface. This is because they can be grown to different thicknesses and cause another process defect.

Therefore, the gate oxidation process proceeds to a low temperature plasma oxidation process of 600 ° C or less.

Referring to FIG. 2D, a gate reoxidation process is performed on the substrate resultant to remove etch damage during the gate formation. Then, after performing the LDD ion implantation and annealing process according to a known process, spacers 7 are formed on both side walls of the gate 6.

Next, after source / drain ion implantation, RTA (Rapid Thermal Annealing) is performed to form source / drain regions 8 having LDD regions on the substrate surface on both sides of the gate 6 including the spacers 7. As a result, the semiconductor elements of the present invention, that is, pMOS and nMOS are formed.

Here, the wells and channel regions are doped with nitrogen (N) ions, and the boron (B) in which the nitrogen (N) ions are implanted into the LDD region and the source / drain region during subsequent annealing, that is, the well and Since side diffusion is prevented into the channel region, even if the width of the channel region is reduced due to the decrease of the gate CD, the short channel effect and the reverse short channel effect are prevented.

As described above, according to the present invention, by doping nitrogen (N) ions in the well and channel regions during well ion implantation and channel ion implantation, ion implantation into the LDD region and the source / drain region by such nitrogen (N) ions is performed. It is possible to prevent the diffusion of boron (B) in the dopant, in particular pMOS, into the well and channel regions in subsequent thermal processes, thereby effectively preventing the short channel effect and reverse short channel effect caused by the high integration of the device. Can be.

Therefore, the present invention can easily control the short-channel effect appearing as the gate CD is reduced, it can be advantageously applied to the fabrication of highly integrated devices.

In addition, according to the present invention, when the ion implantation of nitrogen (N) is preceded before the well and channel ion implantation, channeling of the dopant may also be suppressed by using an amorphous silicon substrate, thereby enabling more accurate dopant profile control.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (6)

  1. Growing a sacrificial oxide film on a surface of a silicon substrate provided with a device isolation film;
    Forming an ion implantation mask exposing a well region and a channel region on the sacrificial oxide film;
    Ion-implanting nitrogen (N) ions while sequentially performing well and channel ion implantation into the exposed substrate region;
    Removing the ion implantation mask and the sacrificial oxide film;
    Performing a gate oxidation process on the substrate resultant to form a gate oxide film on the surface of the substrate;
    Depositing a gate conductive film on the gate oxide film;
    Etching the gate conductive layer and the gate oxide layer to form a gate;
    Performing a gate reoxidation process to remove the etch damage;
    Performing LDD ion implantation on the entire surface of the substrate;
    Forming spacers on both side walls of the gate;
    Performing source / drain ion implantation on the entire surface of the substrate; And
    Annealing the substrate output to form source / drain regions having LDD regions in the substrate surface on both sides of the gate,
    The nitrogen (N) ion implantation method is a semiconductor device manufacturing method, characterized in that the depth of punch-through is performed by the ion implantation depth.
  2. The method of claim 1, wherein the sacrificial oxide film is grown to a thickness of 500 GPa or less.
  3. The method of claim 1, wherein the nitrogen (N) ion implantation is performed with an ion implantation energy of 100 keV or less and a dose of 1E13 to 3E15 atoms / cm 3 based on N 2 + ions.
  4. The method of manufacturing a semiconductor device according to claim 1, wherein the nitrogen (N) ion implantation is performed with an ion implantation energy of 50 keV or less and a dose of 1E13 to 3E15 base / cm 3 based on N + ions.
  5. delete
  6. The method of claim 1, wherein the gate oxidation process is performed at a low temperature plasma oxidation process of 600 ° C. or less.
KR1020030047208A 2003-07-11 2003-07-11 Method of manufacturing semiconductor device KR101013544B1 (en)

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KR101013544B1 true KR101013544B1 (en) 2011-02-14

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000014374A (en) * 1998-08-20 2000-03-15 김규현 Method for fabricating gate oxide of mos transistor
KR20010004972A (en) * 1999-06-30 2001-01-15 김영환 Method of forming a gate in a semiconductor device
US6323094B1 (en) * 1998-02-06 2001-11-27 Tsmc Acer Semiconductor Manufacturing Inc. Method to fabricate deep sub-μm CMOSFETs
KR100351913B1 (en) * 2000-12-08 2002-09-12 주식회사 하이닉스반도체 Method for fabricating of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6323094B1 (en) * 1998-02-06 2001-11-27 Tsmc Acer Semiconductor Manufacturing Inc. Method to fabricate deep sub-μm CMOSFETs
KR20000014374A (en) * 1998-08-20 2000-03-15 김규현 Method for fabricating gate oxide of mos transistor
KR20010004972A (en) * 1999-06-30 2001-01-15 김영환 Method of forming a gate in a semiconductor device
KR100351913B1 (en) * 2000-12-08 2002-09-12 주식회사 하이닉스반도체 Method for fabricating of semiconductor device

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