JP2007048840A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of introducing high density impurity into a very shallow region from the surface of a silicon substrate. <P>SOLUTION: The manufacturing method of a semiconductor device forms a shallow junction source/drain region on both sides of a gate structure in a direction of a gate length, the gate structure including a predetermined shape gate insulating film 4 and a gate electrode 5 formed at predetermined positions on a p-type silicon substrate 1. The method comprises an etching process of etching a formation region of the source/drain region to a predetermined depth; a<SP>30</SP>Si layer formation process of depositing a<SP>30</SP>Si layer of a predetermined composition on the p-type silicon substrate 1, and subjecting a<SP>30</SP>Si layer 21 to selective epitaxial growth into the formation region of the source/drain region; and a neutron radiation irradiation process of irradiating neutron radiation 50 to the p-type silicon substrate 1 to form<SP>31</SP>P of predetermined concentration in the<SP>30</SP>Si layer 21. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having an n-type source / drain region containing a high concentration of P (phosphorus) and a manufacturing method thereof.

  When manufacturing a semiconductor device, an ion implantation method is known as a technique for setting a predetermined region on the semiconductor device to an impurity concentration that provides predetermined conductivity. In this ion implantation method, after irradiating a predetermined region on a semiconductor device with an impurity atom as an ion beam, the ion implantation impurity is activated, and damage to the semiconductor device due to collision of ions during ion implantation is recovered. Annealing treatment is performed.

  With recent advances in semiconductor technology, the speed and miniaturization of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) have progressed, and accordingly, there is a need to reduce the resistance between the source and drain. Therefore, the impurity concentration of the source / drain regions must be increased. At this time, an ion implantation method using a large current ion beam is used to increase the amount of impurities to be ion implanted.

Also, In addition to this, a semiconductor device using a Si (silicon) to the n-type, the ³⁰ Si layer is formed on one entire surface of the semiconductor substrate, the ³⁰ Si layer is irradiated with neutrons, the following equation A method of forming ³¹ P by the nuclear reaction (1) to form an n-type Si layer is also known (see, for example, Patent Document 1).

³⁰ Si (n, δ) ³¹ Si → ³¹ P + β (1)

JP-A-4-168722

  By the way, there is a problem of a short channel effect in which current leakage occurs in a deep portion of the substrate as the gate length is shortened by miniaturization of the MOSFET. In order to suppress this, a so-called shallow junction formation technique is required in which impurities are ion-implanted only in the very shallow region of the source / drain region to form a pn junction.

  However, in order to form a shallow junction by an ion implantation method, which is a conventional source / drain region formation method, ions must be implanted with very low energy, but a low energy ion beam is diverged, It is difficult to obtain a sufficient amount of current. In addition, due to damage caused to the silicon substrate by ion collision during ion implantation, in the annealing process performed after ion implantation, the ion implanted impurity diffuses over a wide area in the silicon substrate, and the region where the impurity exists Therefore, it is difficult to form a shallow junction that is limited to a very shallow region. In other words, in an LSI (Large Scale Integrated circuit) that will be further miniaturized in the future, it is extremely difficult to form a shallow junction having a high impurity concentration by the above-described restrictions by the ion implantation method that has been conventionally used. There was a problem that there was.

  Moreover, although the method of making a Si substrate into n type using the nuclear reaction by neutron irradiation is indicated by the said patent document 1, in the case of introduce | transducing an impurity atom in the predetermined area | region of semiconductor devices, such as MOSFET, No specific method was shown.

  The present invention has been made in view of the above, and a method for manufacturing a semiconductor device capable of introducing a high-concentration impurity into a very shallow region from the surface of a silicon substrate, and a semiconductor manufactured by the manufacturing method An object is to provide an apparatus.

In order to solve the above-described problems and achieve the object, the present invention provides a gate structure on both sides in a gate length direction of a gate structure including a gate insulating film having a predetermined shape and a gate electrode formed at a predetermined position on a p-type silicon substrate. A method of manufacturing a semiconductor device for forming a source / drain region having a shallow junction, an etching step for etching the source / drain region formation region to a predetermined depth, and a predetermined composition on the p-type silicon substrate. is the ³⁰ Si layer deposition, and the ³⁰ Si layer formation step of selective epitaxial growth of the ³⁰ Si layer formation region of the source / drain regions, by irradiating neutrons to the p-type silicon substrate, in the ³⁰ Si layer And a neutron beam irradiation step for forming ³¹ P of a predetermined concentration.

The present invention also provides a gate structure formed at a predetermined position on a p-type silicon substrate, source / drain regions formed on both sides of the gate structure in the gate length direction, and elevated on the source / drain regions. a method of manufacturing a semiconductor device having a structure, the p-type silicon was on the substrate is deposited a ³⁰ Si layer of a predetermined composition, and ³⁰ Si layer formation step of selective epitaxial growth of the ³⁰ Si layer on the source / drain regions, Irradiating the p-type silicon substrate with a neutron beam to form a lifted source / drain layer having a predetermined concentration of ³¹ P in the ³⁰ Si layer.

Furthermore, the present invention provides a method for manufacturing a semiconductor device in which p-type source / drain regions are formed on both sides in the gate length direction of a gate structure including a gate insulating film having a predetermined shape and a gate electrode formed at a predetermined position on a silicon substrate. In the method, a ³⁰ Si layer having a predetermined thickness is deposited in a region including the formation region of the gate structure before the gate structure is formed, and the neutron beam is irradiated to the ³⁰ Si layer to obtain a predetermined concentration. A channel region including ³¹ P is formed.

The present invention also provides a ³⁰ Si layer forming step of epitaxially growing a ³⁰ Si layer having a predetermined composition on a p-type silicon substrate, and a mask in which a neutron absorbing material is disposed at a predetermined position, wherein the neutron absorbing material is the p-type A mask placement step of positioning on the p-type silicon substrate in alignment with the gate structure formation region on the silicon substrate, and irradiating the p-type silicon substrate with neutron beams from the mask, anda neutron beam irradiation to form a source / drain region is converted to ³¹ P of a predetermined concentration in the ³⁰ Si layer, a gate structure in the gate structure forming region corresponding to the position of the neutron absorber It is characterized by forming.

  Furthermore, the present invention is a semiconductor device manufactured using the method for manufacturing a semiconductor device according to any one of the above inventions.

  According to the present invention, since a high concentration of n-type impurities is doped even in a very shallow depth from the surface of the p-type silicon substrate, the element size of the semiconductor device can be reduced. .

Further, according to the present invention, the lifted source / drain layer on the source / drain region having the elevated structure has a high impurity ( ³¹ P) concentration by irradiating ³⁰ Si with a neutron beam. , Has high conductivity. As a result, even when a high concentration of impurity atoms cannot be doped in the shallow region of the source / drain region by a method such as ion implantation, the surface resistance of the source / drain region is reduced even if the surface resistivity increases. There is an effect that can be done.

  Furthermore, according to the present invention, it is possible to form a retrograde channel having a very steep impurity concentration profile in the substrate direction.

Furthermore, according to the present invention, since a thin ³⁰ Si layer is formed in a portion to be a source / drain region where a shallow junction is formed in advance and a diffusion layer is formed so as to have a predetermined impurity concentration by neutron irradiation, Compared with the case where the drain region is formed by ion implantation, the depth of the source / drain region can be controlled with high accuracy.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be explained below in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments. The cross-sectional views of the semiconductor devices used in the following embodiments are schematic, and the relationship between the thickness and width of the layers, the ratio of the thicknesses of the layers, and the like are different from the actual ones.

In the present invention, by irradiating a silicon single crystal with a neutron beam, ³⁰ Si present in silicon at a ratio of 3.1% of natural abundance is converted to ³¹ Si. A method of uniformly doping P into silicon by utilizing the conversion to a certain ³¹ P is applied to formation of a source / drain region in a MOSFET.

(First embodiment)
FIG. 1 is a partial cross-sectional view schematically showing an example of the structure of a semiconductor device to which the present invention is applied. FIG. 1 schematically shows an example of the configuration of the main part of a MISFET (Metal Insulator Semiconductor FET) as a semiconductor device. An element isolation insulating film 2 made of a silicon oxide film or the like is formed in the upper surface of a p-type silicon substrate 1 as a semiconductor substrate. A MISFET is formed in the element formation region defined by the element isolation insulating film 2. The MISFET has a gate structure 3 including a gate insulating film 4, a gate electrode 5, and sidewalls 6, and a source / drain region 7 that forms a pair with a channel region below the gate structure 3 interposed therebetween. In the present invention, the source / drain region 7 has a predetermined thickness of up to about 20 nm.

  On the silicon substrate 1, an interlayer insulating film 11 made of a silicon oxide film or the like is formed so as to cover the MISFET. In the interlayer insulating film 11, a plurality of contact plugs 12 connected to the source / drain regions 7 of the MISFET are formed. An upper wiring layer 13 patterned in a predetermined shape is formed on the interlayer insulating film 11, and is electrically connected to the underlying source / drain region 7 through the contact plug 12 formed in the interlayer insulating film 11. It is connected to the.

  Next, a method for manufacturing a semiconductor device according to the present invention will be described. FIGS. 2-1 to 2-5 are diagrams schematically showing an example of the manufacturing procedure of the semiconductor device according to the present invention. Here, the manufacturing procedure of one MISFET electrically isolated by the element isolation insulating film 2 made of the silicon oxide film shown in FIG. 1 is shown.

First, as shown in FIG. 2A, SiO ₂ (silicon dioxide) as a gate insulating film 4 and Poly-Si as a gate electrode 5 are formed on a p-type silicon semiconductor substrate (hereinafter simply referred to as a silicon substrate) 1. Deposit. Thereafter, the gate insulating film 4 and the gate electrode 5 are processed into a predetermined electrode shape by a known photolithography technique and etching technique. Subsequently, as shown in FIG. 2B, a shallow junction having a high impurity concentration is formed on both sides of the gate insulating film 4 and the gate electrode 5 in the gate length direction (left-right direction in the figure) by isotropic etching. Next, a region having a predetermined depth h is etched from the surface of the silicon substrate 1. The depth h at this time is appropriately selected within a range shallower than 20 nm. Etching performed in FIGS. 2-1 to 2-2 may be wet etching using dilute hydrofluoric acid or the like, or may be dry etching such as reactive ion etching, chemical dry etching, or plasma etching.

Next, as shown in FIG. 2C, a ³⁰ Si layer 21 is selectively epitaxially grown by a CVD (Chemical Vapor Deposition) method in the region where the silicon substrate 1 is etched. At this time, the ³⁰ Si layer 21 is formed to a thickness h that fills the etched region of the silicon substrate 1 in FIG. Here, silane isotope gas ³⁰ SiH ₄ is used as a source gas. The reason why the source gas having ³⁰ Si as a constituent element is used is to cause the nuclear reaction shown in the equation (1) of the background art in the step of irradiating neutrons described later. In order to obtain a predetermined concentration of ³¹ P generated in the source / drain region 7 in which the silicon substrate 1 is etched in a later step, the concentration of silane isotope gas ³⁰ SiH ₄ in the source gas is set to ²⁸ SiH. You may make it change with respect to ₄ . However, the selection of the concentration of the isotope gas ³⁰ SiH ₄ is determined by the rate of conversion in the processing step of changing ³⁰ Si to ³¹ P. Further, when the ³⁰ Si layer 21 is selectively epitaxially grown in the etched region of the silicon substrate 1 by the CVD method, an amorphous ³⁰ Si layer 21α is also deposited on the gate electrode 5. The amorphous ³⁰ Si layer 21α on the gate electrode 5 is formed to have a protruding portion 22 that protrudes beyond the gate length of the gate electrode 5, as shown in FIG. That is, the area when the amorphous ³⁰ Si layer 21α is projected onto the silicon substrate 1 is larger than the area when the gate electrode 5 is projected onto the silicon substrate 1.

Next, as shown in FIG. 2-4, a neutron beam 50 from a thermal neutron source is irradiated from a direction perpendicular to the surface of the silicon substrate 1 under predetermined conditions. At this time, in order to obtain a uniform irradiation amount of the neutron beam 50, it is desirable to irradiate the silicon substrate 1 while rotating in the in-plane direction around the normal line at the center of the substrate surface. Thus, conducted nuclear reaction shown in (1) of the background art, ³⁰ Si ³⁰ in the Si layer 21 of the silicon substrate 1 is formed in the etched region is changed to ³¹ P. As a result, as shown in FIG. 2-5, a source / drain region 7 having a desired surface resistivity is obtained. For example, when a thermal neutron flux of 1 × 10 ¹⁶ [n / cm ² · sec] is irradiated for 2.8 hours, the source / drain region 7 having a surface resistivity of 875 [Ω / sq · cm]. Is formed.

The surface resistivity of the source / drain regions 7, appropriately adjusted ³⁰ Si concentration in the film to the film thickness and selective epitaxial growth is selective epitaxial growth of etching amount i.e. ³⁰ Si of the silicon substrate 1, the thermal neutron flux, the irradiation time Can be changed.

At this time, the amorphous ³⁰ Si layer 21α deposited on the gate electrode 5 is also irradiated with the neutron beam 50 to be partially converted to ³¹ P to obtain conductivity. Since the source / drain region 7 is electrically isolated, there is no problem in the operation of the MISFET. Further, as described above, the area of the amorphous ³⁰ Si layer 21α deposited on the gate electrode 5 is larger than that of the gate electrode 5 and has the protruding portion 22, so that it is near the channel region in the source / drain region 7. In this case, neutrons are absorbed by the protrusions 22 of the amorphous ³⁰ Si layer 21α protruding from the upper gate electrode 5, so that the amount converted to ³¹ P is smaller than the other source / drain regions 7. That is, the low concentration impurity region 7a is formed in the source / drain region 7 in the vicinity of the channel region, thereby relaxing the internal electric field of the MISFET and suppressing the hot carrier effect.

Thereafter, the amorphous ³⁰ Si layer 21α on the gate electrode 5 is removed, and processing is performed so that the sidewalls 6 are formed on the side surfaces of the gate electrode 5 and the gate insulating film 4. Then, an interlayer insulating film 11 is formed on the silicon substrate 1 by a known method, contact plugs 12 connected to the source / drain regions 7 are formed on the interlayer insulating film 11, and a predetermined pattern is formed on the interlayer insulating film 11. By forming the upper wiring layer 13 having the semiconductor device, the semiconductor device shown in FIG. 1 is obtained.

According to this method for manufacturing a semiconductor device, a portion corresponding to the gate / drain region 7 forming a shallow junction on the silicon substrate 1 is removed, and a ³⁰ Si layer 21 is selectively epitaxially grown thereon and irradiated with a neutron beam 50. Thus, impurity atoms are introduced only in this portion. FIG. 3 is a diagram schematically showing a profile of the concentration of impurity atoms from the silicon substrate surface in the source / drain regions. In this figure, the horizontal axis represents the depth from the surface of the silicon substrate 1 (here, the surface of the ³⁰ Si layer 21 selectively grown on the source / drain region 7), and the vertical axis represents the silicon substrate 1. It represents the doped impurity concentration. In the conventional ion implantation method, as indicated by a broken line in the figure, the impurity concentration becomes maximum at a certain depth d ₁ from the surface of the silicon substrate 1, and the impurity concentration decreases at a deeper position. Has a profile. On the other hand, according to the impurity atom doping method according to the first embodiment indicated by the solid line, the impurity concentration has a predetermined value at a depth up to h corresponding to the thickness of the ³⁰ Si layer 21 that has been selectively epitaxially grown. In a position deeper than h, there is a profile shape showing an abrupt change in which no impurity concentration exists. In this way, a shallow junction can be formed on the silicon substrate 1.

  Further, in the ion implantation method, a high concentration impurity atom cannot be doped in a shallow region from the surface of the silicon substrate 1 to a depth of about 20 nm. However, according to the method of the first embodiment, the surface of the silicon substrate 1 Even in a shallow region from about 20 nm to a depth of about 20 nm, high-concentration impurity atoms can be doped.

In the above-described example, the silicon substrate 1 having the gate insulating film 4 deposited thereon is used. However, an SOI (Silicon On Insulator) structure substrate may be used as the substrate. The gate insulating film 4 is not limited to SiO ₂ , and may be an oxide containing a transition metal or a rare earth metal, a so-called high dielectric constant (High-k) film. Similarly, the gate electrode 5 is not limited to Poly-Si, and may be a conductive material composed of a transition metal or a compound thereof. Furthermore, in the above-described example, Poly-Si is used for the gate electrode 5, but when this Poly-Si is formed of ³⁰ Si, the gate electrode 5 is simultaneously formed when the source / drain region 7 is formed by neutron irradiation. Alternatively, ³¹ P may be doped and activated by a subsequent heat treatment.

In order to reduce the junction leakage in the vicinity of the junction, the ³⁰ Si concentration is set to a low concentration before neutron irradiation in the vicinity of the junction between the source / drain region 7 and the silicon substrate 1 (for example, When a ³⁰ Si layer is grown in a region where the silicon substrate 1 has been etched, at the initial stage of deposition, the flow rate of the source gas isotope gas ³⁰ SiH ₄ is set lower than the flow rate of ²⁸ SiH ₄ to a predetermined thickness. the after reaching the are, such as by setting high flow rate of ³⁰ SiH _4), it can be arbitrarily set by varying the impurity concentration profile.

Furthermore, in the above-described example, the case where an n-type diffusion layer having a shallow junction is formed in the case of an n-channel MISFET has been described. However, when impurity atoms are introduced into the channel of the MISFET, the same method as described above is used. Can do. However, in this case, before the gate insulating film 4 is deposited, a thin ³⁰ Si layer is deposited on the entire surface of the n-type or non-doped silicon substrate or on the channel region, and irradiated with neutron rays, thereby introducing a retrograde channel (step type). A silicon substrate having a very steep profile in the depth direction, referred to as a channel profile, or an appropriate type of substrate using a similar technique is used. Thus, a gate structure is formed on a silicon substrate having a buried channel, and p-type impurity atoms are implanted into both sides of the gate structure in the gate length direction by an ion implantation method or the like to form a source / drain region made of a p-type diffusion layer. Form.

  According to the first embodiment, high-concentration n-type is also used in a very shallow range from the surface of the p-type silicon substrate 1 (the boundary surface between the gate insulating film 4 and the silicon substrate 1) to 20 nm. It has an effect that the surface resistance of the source / drain region 7 can be lowered by doping impurities.

(Second Embodiment)
In the second embodiment, a method for manufacturing a semiconductor device having an elevated structure in which the source / drain regions are raised in order to reduce the resistance of the source / drain regions will be described. FIG. 4 is a partial cross-sectional view schematically showing an example of the structure of a semiconductor device to which the present invention is applied. This semiconductor device has a structure in which a lifted source / drain layer 8 made of a silicon layer containing high-concentration impurity atoms ³¹ P is formed on the source / drain region 7 in the semiconductor device of FIG. Thus, even when the source / drain region 7 of the semiconductor device has an elevated structure, the impurity concentration of the source / drain region 7 formed on the silicon substrate 1 cannot be increased and the resistance cannot be lowered. Its surface resistance can be lowered. In addition, the same code | symbol is attached | subjected to the component same as 1st Embodiment, and the description is abbreviate | omitted.

  Next, a method for manufacturing a semiconductor device having an elevated structure formed by nuclear conversion using neutron irradiation in a source / drain region according to the present invention will be described. 5A to 5D are diagrams schematically illustrating an example of the manufacturing procedure of the semiconductor device according to the present invention. Here, as in the first embodiment, the manufacturing procedure of one MISFET electrically isolated by an element isolation insulating film (not shown) made of a silicon oxide film is displayed.

  First, as shown in FIG. 5A, a gate insulating film 4 made of a silicon oxide film, a gate electrode 5 made of Poly-Si, and sidewalls 6 made of a silicon oxide film or a silicon nitride film on these side surfaces are included. A p-type silicon substrate 1 is prepared in which a gate structure 3 and source / drain regions 7 formed on both sides of the gate structure 3 in the gate length direction are formed. Here, a substrate having an SOI structure may be used as the substrate as in the first embodiment. The source / drain region 7 is assumed to be activated by an annealing process after introducing P by ion implantation to form an n-type diffusion layer. In addition to P, this ion-implanted element may be As (arsenic) or In (indium), which is an n-type impurity. In addition, the n-type diffusion layer of the source / drain region 7 may be formed by the process of the first embodiment in addition to a known process.

Next, as shown in FIG. 5B, the ³⁰ Si layer 23 is selected to a thickness of up to 20 nm by using the silane isotope gas ³⁰ SiH ₄ as the source gas by the CVD method on the source / drain region 7. Epitaxially grow. In order to make ³¹ P generated in the ³⁰ Si layer 23 in a later step a predetermined concentration, the concentration of the silane isotope gas ³⁰ SiH ₄ in the source gas is changed with respect to ²⁸ SiH ₄ . May be. However, the selection of the concentration of the isotope gas ³⁰ SiH ₄ is determined by the rate of conversion in the processing step of changing ³⁰ Si to ³¹ P. Further, when the ³⁰ Si layer 23 is selectively epitaxially grown on the source / drain region 7 by the CVD method, an amorphous ³⁰ Si layer 23α is also deposited on the gate structure 3.

Next, as shown in FIG. 5C, a neutron beam 50 from a thermal neutron source is irradiated under a predetermined condition from a direction perpendicular to the surface of the silicon substrate 1. At this time, in order to obtain a uniform irradiation amount of the neutron beam 50, it is desirable to irradiate the silicon substrate 1 while rotating in the in-plane direction around the normal line of the center of the substrate surface. By the irradiation of the neutron beam 50, as shown in FIG. 5-4, the nuclear reaction shown by the equation (1) of the background art is performed, and the ³⁰ Si layer 23 formed on the source / drain region 7 ³⁰ Si changes to ³¹ P. As a result, a lifted source / drain layer 8 having a desired surface resistivity is obtained.

The surface resistivity of the lifted source / drain layer 8 is changed by appropriately adjusting the film thickness for selective epitaxial growth of the ³⁰ Si layer 23, the concentration of ³⁰ Si in the film for selective epitaxial growth, the thermal neutron flux, and the irradiation time. be able to.

Thereafter, the amorphous ³⁰ Si layer 23α on the gate structure 3 is removed, an interlayer insulating film 11 is formed on the silicon substrate 1 by a known method, and the contact plug 12 connected to the lifted source / drain layer 8 is connected to the interlayer insulating film. 4 and forming the upper wiring layer 13 patterned into a predetermined shape on the interlayer insulating film 11, the semiconductor device shown in FIG. 4 is obtained.

According to the second embodiment, when a high concentration of impurity atoms cannot be doped in a shallow region of the source / drain region 7 by a method such as ion implantation, a neutron beam is applied to the source / drain region 7. The surface resistance of the source / drain region 7 can be lowered by employing an elevated structure in which the lifted source / drain layer 8 having a high impurity ( ³¹ P) concentration obtained from ³⁰ Si is formed by irradiation. It has the effect.

(Third embodiment)
In the first embodiment, the gate structure 3 is formed on the silicon substrate 1 and then the source / drain regions 7 are formed on both sides of the gate structure 3 in the gate length direction. In the third embodiment, a case will be described in which the n-type source / drain region 7 formed by nuclear conversion using neutron irradiation is formed before the gate insulating film 4 is deposited.

6A to 6D are diagrams schematically illustrating an example of a manufacturing procedure of the semiconductor device according to the present invention. First, as shown in FIG. 6A, a p-type silicon substrate 1 is prepared. Next, as shown in FIG. 6B, by using the silane isotope gas ³⁰ SiH ₄ as a source gas by the CVD method, the ³⁰ Si layer 25 is 20 nm corresponding to the depth of the source / drain region 7 of the shallow junction. Selective epitaxial growth with thickness up to It should be noted that the concentration of silane isotope gas ³⁰ SiH ₄ in the source gas is changed with respect to ²⁸ SiH ₄ so that ³¹ P generated in the ³⁰ Si layer 25 in a later step has a predetermined concentration. May be. However, the selection of the concentration of the isotope gas ³⁰ SiH ₄ is determined by the rate of conversion in the processing step of changing ³⁰ Si to ³¹ P. Further, as the substrate, a substrate having an SOI structure may be used as in the first embodiment.

Next, as shown in FIG. 6C, a glass mask 31 in which a pattern is formed with a neutron absorber 32 is placed on the epitaxially grown ³⁰ Si layer 25. As the neutron absorber 32, a substance that absorbs neutrons such as Hf (hafnium) is used. Further, when the mask 31 is installed, alignment is performed so that the neutron absorber 32 is located in the vicinity of the center in the element formation region defined by the element isolation insulating film (not shown). Thereafter, the neutron beam 50 from the thermal neutron source is irradiated onto the silicon substrate 1 having the ³⁰ Si layer 25 through the mask 31.

Next, as shown in FIG. 6-4, in the region of the ³⁰ Si layer 25 in which neutrons are transmitted without being absorbed by the mask 31, nuclear conversion is induced to convert ³⁰ Si into ³¹ P. A source / drain region 7 having a predetermined P concentration is formed. Further, in the region patterned with the neutron absorber 32 in the ³⁰ Si layer 25, neutrons do not pass through the mask 31 and are not irradiated to the ³⁰ Si layer 25, and therefore, the ³⁰ Si layer (channel region) 9 that is not doped with impurities. Remains as it is.

Thereafter, the gate insulating film 4, the gate electrode 5 and the gate structure 3 in which the side walls 6 are formed on both sides in the gate length direction after forming the gate insulating film 4 and the gate electrode 5 in a predetermined shape on the channel region 9 are formed. To do. Then, an interlayer insulating film 11 is formed on the silicon substrate 1 by a known method, contact plugs 12 connected to the source / drain regions 7 are formed in the interlayer insulating film 11, and a predetermined shape is formed on the interlayer insulating film 11. By forming the upper wiring layer 13 having the semiconductor device, the semiconductor device shown in FIG. 1 is obtained. Before forming the gate insulating film 4, for example, a region other than the channel region 9 is masked with a photoresist or the like and the channel region 9 of the ³⁰ Si layer between the source / drain regions 7 is formed by ion implantation. Type impurities may be introduced.

According to the third embodiment, it is not necessary to etch the region where the ³⁰ Si layer is selectively epitaxially grown as in the first embodiment, and the region where the shallow junction is formed is more accurate than etching. ³⁰ The film thickness of the Si layer 25 can be controlled.

  As described above, the method for manufacturing a semiconductor device according to the present invention is useful for a semiconductor device having a MISFET structure in which an element size is miniaturized.

It is a partial sectional view showing typically an example of the structure of the semiconductor device to which the present invention is applied. It is a figure which shows typically an example of the manufacturing procedure of the semiconductor device by this invention (the 1). It is a figure which shows typically an example of the manufacturing procedure of the semiconductor device by this invention (the 2). It is a figure which shows typically an example of the manufacturing procedure of the semiconductor device by this invention (the 3). FIG. 10 is a diagram schematically showing an example of a manufacturing procedure of the semiconductor device according to the present invention (part 4); It is a figure which shows typically an example of the manufacturing procedure of the semiconductor device by this invention (the 5). It is a figure which shows typically the profile of the density | concentration of the impurity atom from the silicon substrate surface in a source / drain area | region. It is a partial sectional view showing typically an example of the structure of the semiconductor device to which the present invention is applied. It is a figure which shows typically an example of the manufacturing procedure of the semiconductor device by this invention (the 1). It is a figure which shows typically an example of the manufacturing procedure of the semiconductor device by this invention (the 2). It is a figure which shows typically an example of the manufacturing procedure of the semiconductor device by this invention (the 3). FIG. 10 is a diagram schematically showing an example of a manufacturing procedure of the semiconductor device according to the present invention (part 4). It is a figure which shows typically an example of the manufacturing procedure of the semiconductor device by this invention (the 1). It is a figure which shows typically an example of the manufacturing procedure of the semiconductor device by this invention (the 2). It is a figure which shows typically an example of the manufacturing procedure of the semiconductor device by this invention (the 3). FIG. 10 is a diagram schematically showing an example of a manufacturing procedure of the semiconductor device according to the present invention (part 4);

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 p-type semiconductor substrate 2 Element isolation insulating film 3 Gate structure 4 Gate insulating film 5 Gate electrode 6 Side wall 7 Source / drain region 7a Low concentration impurity region 8 Lifting source / drain layer 9 Channel region 11 Interlayer insulating film 12 Contact plug 13 Upper wiring layers 21, 23, 25 ³⁰ Si layer 21α, 23α Amorphous ³⁰ Si layer 22 Projection 31 Mask 32 Neutron absorber 50 Neutron beam

Claims (5)

A method of manufacturing a semiconductor device, wherein shallow junction source / drain regions are formed on both sides in a gate length direction of a gate structure including a gate insulating film and a gate electrode having a predetermined shape formed at a predetermined position on a p-type silicon substrate. ,
An etching step of etching the source / drain region formation region to a predetermined depth;
The p-type silicon was on the substrate is deposited a ³⁰ Si layer of a predetermined composition, and ³⁰ Si layer formation step of selective epitaxial growth of the ³⁰ Si layer formation region of the source / drain regions,
Irradiating the p-type silicon substrate with a neutron beam to form a predetermined concentration of ³¹ P in the ³⁰ Si layer; and
A method for manufacturing a semiconductor device, comprising: A semiconductor device having a gate structure formed at a predetermined position on a p-type silicon substrate, source / drain regions formed on both sides of the gate structure in the gate length direction, and an elevated structure on the source / drain region. A manufacturing method comprising:
A ³⁰ Si layer forming step of depositing a ³⁰ Si layer having a predetermined composition on the p-type silicon substrate and selectively epitaxially growing the ³⁰ Si layer in the source / drain regions;
Irradiating the p-type silicon substrate with a neutron beam to form a lifted source / drain layer having a predetermined concentration of ³¹ P in the ³⁰ Si layer;
A method for manufacturing a semiconductor device, comprising: A method of manufacturing a semiconductor device, wherein p-type source / drain regions are formed on both sides of a gate structure in a gate length direction of a gate structure including a gate insulating film having a predetermined shape and a gate electrode formed at a predetermined position on a silicon substrate,
Before forming the gate structure, a ³⁰ Si layer having a predetermined thickness is deposited in a region including the formation region of the gate structure, and the ³⁰ Si layer is irradiated with neutron beams, so that a channel containing ³¹ P having a predetermined concentration is formed. A method for manufacturing a semiconductor device, comprising forming a region. a ³⁰ Si layer forming step of epitaxially growing a ³⁰ Si layer having a predetermined composition on a p-type silicon substrate;
A mask placement step in which a mask in which a neutron absorber is disposed at a predetermined position is aligned on the p-type silicon substrate by aligning the neutron absorber with the gate structure formation region on the p-type silicon substrate. When,
A neutron beam irradiation step of irradiating the p-type silicon substrate with a neutron beam from above the mask and converting it into a predetermined concentration of ³¹ P in the ³⁰ Si layer to form a source / drain region;
And a gate structure is formed in the gate structure formation region corresponding to the position where the neutron absorber is disposed. A semiconductor device manufactured using the method for manufacturing a semiconductor device according to claim 1.

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