CN1280891C - Non-volatile storage structure and its manufacturing method - Google Patents
Non-volatile storage structure and its manufacturing method Download PDFInfo
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- CN1280891C CN1280891C CN 01145049 CN01145049A CN1280891C CN 1280891 C CN1280891 C CN 1280891C CN 01145049 CN01145049 CN 01145049 CN 01145049 A CN01145049 A CN 01145049A CN 1280891 C CN1280891 C CN 1280891C
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Abstract
In a nonvolatile memory of the present invention, a selection gate is a self-aligned partition wall of the upper side of a side wall stacked on a floating/control gate. The steps, such as removing a selection gate layer from the upper side of a source electrode line (144), etching a groove insulating layer in the area of the source electrode line, adulterating the source electrode line, etc., can be carried out by utilizing the same shadow mask (1710). The memory can be formed in an independent base plate area or on the upper side of the independent base plate area; before the groove insulating layer is etched, the source electrode line can be at least adulterated partially; short circuit can be avoided by isolating the base plate area and a low side structure. The memory can realize sector erasing or execute chip erasing operation to erase all cell elements in parallel; a periphery electric crystal gate electrode and the selection gate can be formed by the same layer; the partition wall of the selection gate is provided with extension objects, and low resistance contact can be made from a wire of the upper side; when a machine or a chemical machine grinds the insulating layer of the upper side, circuit elements of the upper side of a semiconductor base plate can be protected by utilizing an adjacent virtual arrangement structure.
Description
Technical field
The invention relates to a kind of semiconductor technology, refer to a kind of non-volatile memory structure and manufacture method thereof especially.
Background technology
In the past when making the Nonvolatile flash memory; regular meeting uses a kind of very typical processing procedure-local silicon oxidation (local oxidation of Silicon; LOCOS) processing procedure; to isolate and to come each element (as the bit line) on the wafer; but the processing procedure of local silicon oxidation tends to generate the oxide layer of beak shape; we must headspace to the structure of this protrusion; but the size of this projective structure has accounted for sizable ratio in the bit distance between centers of tracks; make interelement distance further to dwindle, the misalignment step becomes the principal element of limiting element size.In view of this, a kind of so-called shallow trench isolation from (shallowtrench isolation, STI) technology in response to and give birth to, effectively improve this situation in self aligned mode.
Fig. 1 illustrates the U.S. Patent number 6,013,551 of people such as J.Chen at bulletin on January 11st, 2000, the traditional non-volatile manufacture method of piling up the lock flash memory of content description to Fig. 8.Growth silicon layer 108 above P doping silicon substrate 150 (also can be described as tunnel oxide (tunnel oxidelayer), can abbreviate oxide layer as in the following description), deposit a doping polysilicon layer 124 again at oxide layer 108 end faces, this polysilicon layer 124 will form the floating gate (floating gate) of memory cell electric crystal.
Then, form mask 106,, cause and in substrate 150, form a plurality of grooves 910 (as shown in Figure 2) via the downward etching polysilicon of mask open layer 124, oxide layer 108 and substrate 150 on the surface of structure.
As shown in Figure 3, insert dielectric material in the groove 910 and cover total, its details step is: earlier with hot evaporating method growth silicon layer 90, strengthen chemical vapour deposition technique (plasma enhanced chemical vapor deposion with the electricity slurry then, PECVD) deposition one silicon layer 94, the following again atmospheric chemical vapor deposition (subatomspheric chemical vapordeposition, SACVD) the thicker silicon layer 96 of deposition one layer thickness.
Then to structure carry out cmp (chemical mechanical polishing, CMP) step, as shown in Figure 4, to expose polysilicon layer 124.
About cmp, we are in this explanation especially a little.Under patterned insulation layer maybe will deposit before one deck, the upper surface that needs planarization insulating layer, because so do the requirement that to relax the little shadow equipment depth of focus that is used for patterned insulation layer or upper layers, if the upper surface of insulating barrier is smooth, then we can accept the depth of focus bigger variability, and this is to being particular importances with little shadow device fabrication small size article.
And chemical mechanical milling method is widely used in the planarization processing procedure, because chemical mechanical milling method is very quick, does not also need at high temperature to carry out.
Handle insulating barrier with chemical mechanical milling method and normally stop at the harder one deck in insulating barrier below, give an example, when handling the silicon layer with chemical mechanical milling method, can before forming the silicon layer, deposit one deck silicon oxide layer earlier, as stopping layer, see also in the U.S. Patent number 5,909,628 " REDUCING NON-UNIFORMITY IN A REFILL LAYER THICKNESSFOR A SEMICONDUCTOR DEVICE " of bulletin on June 1st, 1999.
Then as shown in Figure 5, structurally form an ONO (oxidation silicon, silicon nitride, oxidation silicon) layer 98, deposit a silicon layer 99 then up, then deposit a silicon tungsten layer 100.
Form mask (not drawing) then, and above-mentioned 100,99,98,124 each layers (as shown in Figure 6) of patterning, polysilicon layer 124 will become floating gate at this moment, and silicon layer 99 and silicon tungsten layer 100 will become control sluice (control gate) and character line (wordline) respectively.
As shown in Figure 8, then structurally form mask 101, utilize mask 101 etchings to remove the oxide layer 90,94,96 (as shown in Figure 7) of part, after the etching, keep mask 101, be used to implant alloy to form source electrode line 103.
The implantation step of carrying out other then is with suitable doped source zone and drain region.
Though said method can dwindle the size of memory,, still need dwindle the size of memory again along with the evolution of processing procedure and the restriction of live width.
Summary of the invention
The object of the present invention is to provide a kind of manufacturing to comprise the method for the integrated circuit of non-volatility memorizer, utilize autoregistration step repeatedly to form polysilicon layer (floating gate, control sluice, selection lock), autoregistration and mutual arrangement mode by three's lock, can further reduce bit cable brake distance, the size of dwindling memory more significantly.
According to above-mentioned purpose, the method that the embodiment of the invention provides a kind of manufacturing to comprise the integrated circuit of non-volatility memorizer, this method may further comprise the steps:
(a) form first insulating barrier and ground floor on the first area of semiconductor, wherein this integrated circuit comprises a plurality of non-volatile memory cell unit, and each those memory cell includes one by the formed floating gate of this ground floor of part;
(b) opening via this ground floor forms a plurality of grooves in this semiconductor first area, and with those grooves of filling insulating material;
(C) form a second layer on this semiconductor first area, wherein each those cell element includes one by the formed conduction lock of this second layer of part, and this floating gate of this conduction lock and those cell elements is isolated with one second insulating barrier;
(d) this second layer of patterning stretches to the rectangular of a predetermined direction with formation, each this rectangular across a plurality of those grooves;
(e) remove not this ground floor of part on this semiconductor first area that is covered by this second layer, to form a plurality of first structures, it is one formed rectangular by this second layer that each those first structure comprises, and comprising this ground floor of part of this rectangular below, each those first structure has a first side wall;
(f) on this ground floor and this second layer, form one the 3rd layer, and with the processing procedure that comprises anisotropic etching remove the part the 3rd layer, what make in each those first structures forms a partition to this first side wall of small part, wherein this ground floor in corresponding first structure with this of each this partition and the material of this second layer are isolated with an isolated material;
(g) use little shadow to form a little shadow mask pattern, this little shadow mask pattern covers this partition on this first structure the first side wall;
(h) serve as the cover curtain with this little shadow mask pattern, to remove this partition that is not covered by little shadow mask pattern, therefore, each those cell element includes one by the formed conduction lock of the partition on this first side wall of this first structure; And
(i) utilize this little shadow mask pattern in this semiconductor first area, to mix alloy for the cover curtain.
Before forming this second layer, this ground floor forms and is the rectangular of an angle with this predetermined direction and those grooves pass a row non-volatile memory cell unit to be same as this rectangular direction.
The method that forms this ground floor more comprises:
Little shadow mask pattern on little this ground floor of shadow patterning, rectangular to define this of this ground floor; And
Utilize above-mentioned this little shadow mask pattern to define those grooves.
In the above-mentioned method:
Each this first structure includes one second sidewall;
This little shadow mask pattern processing procedure comprises deposition and little shadow patterning one little shadow mask pattern, with on this first side wall that covers this first structure to this partition of small part, and cover one first semiconductor substrate, zone between this first side wall of adjacent this first structure.
Each this second semiconductor substrate zone extends between two adjacent these first structures, and the source/drain areas of all memory cells between two adjacent these first structures of bound fraction is provided, and wherein this source/drain areas is electrically connected to each other.
Above-mentioned method more comprises uses this little shadow mask pattern to remove insulating material in the groove in this second semiconductor substrate zone with etching wholly or in part.
Remove in this groove after the insulating material in etching wholly or in part, more comprise removing this little shadow mask pattern, and in this first and second semiconductor substrates zone, mix alloy.
This ground floor comprises a polysilicon layer, and this second layer comprises a polysilicon layer and a metal silicon compounds layer.
In the above-mentioned method:
Before forming this second layer, this ground floor has a plurality of oblong openings, but the zone that will form source electrode line is then by this ground floor covering;
The formation of this groove is to form from this semiconductor first area of the downward etching of this oblong openings; And
Step (e) comprises on this source electrode line zone and removes this ground floor.
Above-mentioned method more comprises following steps to form second MOS (metal-oxide-semiconductor) transistor:
Also form first insulating barrier and ground floor simultaneously on this semi-conductive second area when on semi-conductive first area, forming first insulating barrier and ground floor:
Remove this ground floor and this first insulating barrier of this integrated circuit second area;
When carrying out (c) step, also on this second area, form second insulating barrier simultaneously;
When carrying out (c) step, also on second insulating barrier of this second area, form the second layer simultaneously to form second MOS (metal-oxide-semiconductor) transistor.
Described second insulating barrier is different with first thickness of insulating layer.
Above-mentioned method more comprises following steps the 3rd MOS (metal-oxide-semiconductor) transistor:
In this first area and this second area when forming this first insulating barrier, also form this first insulating barrier in the 3rd zone simultaneously;
Before forming this ground floor, remove this first insulating barrier from this second and third zone, and form one the 3rd insulating barrier in this second and third zone; And
When this second area removes this ground floor, patterning is positioned at this ground floor in this first and the 3rd zone simultaneously, so that the conduction lock as this first and the 3rd MOS (metal-oxide-semiconductor) transistor to be provided.
After forming this layer second layer, this first insulating barrier, this second insulating barrier, and the thickness of the 3rd insulating barrier all inequality.
When forming the 3rd insulating barrier, the thickness that is positioned at this first insulating barrier of this first area can increase.
This integrated circuit comprises a non-volatile memory cell unit, and this cell element comprises (a) by the formed conduction lock of this ground floor of part and (b) by the formed conduction lock of this second layer.
Before forming this first insulating barrier step, more comprise:
Form a gate insulation layer on this semiconductor substrate, this memory cell will be formed in the zone of this integrated circuit;
Form a conductor layer on this gate insulation layer, so that a floating gate of this memory cell to be provided; And
Remove this conductor layer and this gate insulation layer from this first and second zone.
Above-mentioned method more is included in this conductor layer top and forms an insulating barrier, to isolate this conductor layer and this ground floor.
The method that the present invention provides a kind of manufacturing to comprise the non-volatility memorizer integrated circuit in addition, this method comprises:
Form an insulating barrier, wherein this integrated circuit comprises a plurality of non-volatile memory cell unit, and this insulating barrier (108) is the gate insulation layer as those non-volatile memory cell units;
Form a ground floor, with floating gate as those non-volatile memory cell units;
Insulating barrier is on the ground floor of those memory cells on the formation floating gate;
Remove insulating barrier on this floating gate, ground floor and this insulating barrier in regular turn from high-voltage region, high-speed region, I/O (output is gone into) zone of the periphery of this integrated circuit non-volatile memory cell unit, in order to respectively to form at least one peripheral MOS (metal-oxide-semiconductor) transistor on the zone at this high-voltage region, high-speed region, I/O (output is gone into);
Form one first gate insulation layer in this high-voltage region, high-speed region, I/O zone;
Remove this first gate insulation layer from this high-speed region, I/O zone;
Form one second gate insulation layer in this high-speed region, I/O zone;
Form a second layer on insulating barrier, this first gate insulation layer, this second gate insulation layer on this floating gate, this MOS (metal-oxide-semiconductor) transistor that wherein is positioned at this high-voltage region has by the formed conduction lock of this second layer of part;
Remove this second layer and second gate insulation layer from this I/O zone;
Form one the 3rd gate insulation layer in this I/O zone; And
The ground floor and the second layer on this memory cell sidewall of high-temperature oxydation;
Form one the 3rd layer on the MOS (metal-oxide-semiconductor) transistor of those memory cells and this high-voltage region and this high-speed region comprehensively;
Form a little shadow mask pattern in this I/O zone with the definition MOS (metal-oxide-semiconductor) transistor;
Impose anisotropic etching so that the 3rd layer of formation partition on the sidewall of the MOS (metal-oxide-semiconductor) transistor of the MOS (metal-oxide-semiconductor) transistor of those memory cells, this high-voltage region and high-speed region;
Form another little shadow mask pattern to protect the respectively partition an of side of those memory cells;
Remove all this not by the 3rd layer of little shadow mask pattern, be used to form MOS (metal-oxide-semiconductor) transistor on this I/O zone;
This first gate insulation layer that wherein is positioned at this high-voltage region is thicker than this second gate insulation layer, and is also thick than the 3rd gate insulation layer, and the 3rd gate insulation layer is then thick than this second gate insulation layer.
The periphery that said method more is included in this I/O zone forms an empty interposed structure; this void interposed structure is identical with the MOS (metal-oxide-semiconductor) transistor of high-speed region; and after second layer step forms; before removing this second layer and the second gate insulation layer step from this I/O zone; form a protective layer in the MOS (metal-oxide-semiconductor) transistor of this high-voltage region, high-speed region and the top of those memory cells, with the 3rd layer of protection I/O zone MOS (metal-oxide-semiconductor) transistor.
Description of drawings
Fig. 1 to Fig. 7 is the processing procedure profile of known flash memory;
Fig. 8 is the vertical view of Fig. 1 to Fig. 7 memory;
Fig. 9 A is the vertical view of the memory embodiment according to the present invention;
Fig. 9 B and Fig. 9 C are the profile of Fig. 9 A memory;
Figure 10 A is the circuit diagram of Fig. 9 A memory;
Figure 10 B is the vertical view of Fig. 9 A memory;
Figure 11 and Figure 12 A are the processing procedure profile of Fig. 9 A memory;
Figure 12 B is the vertical view of Figure 12 A structure;
Figure 13 to Figure 15 is the processing procedure profile of Fig. 9 A memory;
Figure 16 is the perspective view of Fig. 9 A memory in processing procedure;
Figure 17 A to Figure 22 B is the processing procedure profile of Fig. 9 A memory;
Figure 22 C is the vertical view of Figure 22 A and Figure 22 B structure;
Figure 23 A to Figure 24 C is the profile of memory embodiment of the present invention in processing procedure;
Figure 25 to Figure 26 C is the profile of memory embodiment of the present invention;
Figure 27 to Figure 29 is the vertical view of memory embodiment of the present invention;
Figure 30 A and Figure 30 B are the profile of memory embodiment of the present invention;
Figure 30 C shows the mask layout of memory embodiment of the present invention;
Figure 31 A to Figure 33 B is the profile of memory embodiment of the present invention;
Figure 34 is the vertical view of memory embodiment of the present invention;
Figure 35 and Figure 36 are the processing procedure profile of Figure 34 memory;
Figure 37 and Figure 38 are the vertical view of Figure 34 memory in processing procedure
Figure 39 to Figure 41 is the processing procedure profile of Figure 34 memory;
Figure 42 is the vertical view of memory embodiment of the present invention in processing procedure;
Figure 43 is the calcspar that is used for the voltage generator of memory embodiment of the present invention;
Figure 44 to Figure 61 is the processing procedure profile of memory embodiment of the present invention.
98,1010,1810,2901,2903,3003: insulating barrier
98.1,98.3,1510,1810,2710,4408,4410: the silicon layer
98.2,720,903,1203,2607: the silicon nitride layer
103: source electrode line
108: tunnel oxide (can be the silicon layer)
110: semiconductor structure
113: dielectric layer
120: memory cell
120S: select electric crystal
120F: floating gate electric crystal
124: floating gate (form by polysilicon, for cooperation illustrates, some the time can be called the polysilicon layer, or unsteady brake cable)
128: control sluice (illustrate for cooperating, some the time be called the control brake cable)
128.1: the polysilicon layer
128.2: the silicon tungsten layer
128A: part
130: the bit line
133: regions and source
134,312: bit line zone
138: bit line contact area
141: empty interposed structure
144: source electrode line
144C, 29003C: contact openings
150: substrate regions
520: the character line (form by polysilicon, for cooperation illustrates, some the time can be called the polysilicon layer, or select lock)
520E: lateral projection
710: the stacked structure (or being called array structure) that comprises floating gate and control sluice
901: memory array
904,1014,1710,2501,2810,4501,4601,4801: photo-resistive mask
905: substrate
910: isolated groove
1103,1105:N-zone
1107,2709: the zone
1603: the neighboring area
1810: grid oxic horizon
2110,2401: implant
2605: electric conducting material
2701,3010: the gap
2703.1,2703.2: the memory array section
2903: metal tape
3301: petrificating layer
4201: voltage generator
4402,4404,4406,4404D: active area
Embodiment
The narration of relevant preferred embodiment is to illustrate and unrestricted usefulness, unless Wen Zhongyou indicates especially, not so the present invention is not limited to any special size, material, program step, alloy, doping content, crystallization position to, each layer thickness, layout or other element characteristics.
Fig. 9 A is the vertical view of the fast-flash memory display of autoregistration three lock memory cells 120, Fig. 9 B is the profile along the line 9B-9B incision of Fig. 9 A, Fig. 9 C is that Figure 10 A is the circuit diagram of array along the profile of the line 9C-9C incision of Fig. 9 A, and Figure 10 B is the vertical view of other newly-increased features of explanation.
Bit line among the figure (bit lines) the 130th, horizontal expansion, bit line 130 is (as aluminium or tungsten by the conductive layer that is positioned at memory cell 120 tops, do not draw) form, bit line 130 contacts in bit line contact area 138 with the bit line zone 134 of memory cell 120, source electrode line (sourcelines) the 144th extends longitudinally in 710 of adjacent array structures, each array structure 710 comprises one and controls brake cable (control gate Line) 128 longitudinally, control sluice as each row memory cell, control brake cable 128 in the present embodiment is made up of polysilicon layer 128.1 and silicon tungsten layer 128.2, polysilicon floating gate 124 is positioned at the below of control sluice 128, each floating gate is positioned at adjacent isolated groove 910 locks, and 910 of grooves are laterally to be positioned at 130 on bit line.
Each array structure 710 all is that autoregistration is piled up.
Character line 520 (as doping polysilicon layer) and bit line 130 vertical (or being a special angle), each bar character line 520 can be as the selection lock of a row memory cell, each character line 520 is the autoregistration partitions that form on the sidewall of corresponding stacked structure 710, character line 520 separates by oxidation silicon partition 903 and silicon layer 1510 and adjacent control sluice 128 and floating gate 124, and 903 and 1510 layers only do not need mask to generate.
Shown in Figure 10 A, the memory cell of each row has two cell elements 120 at 130 adjacent on two bit lines, wherein a control brake cable 128 and a character line 520 are shown in each memory, two adjacent memory row are shared a source electrode line 144, in each memory cell 120, a NMOS selects electric crystal 120s and a floating gate electric crystal 120F polyphone, select the grid of electric crystal 120s to be provided by character line 520, the control sluice of floating gate electric crystal 120F is then provided by control brake cable 128.
We can by from floating gate 124 through silicon layer 108 to the Fowler-Nordheim electrons tunnel of source electrode line 144 or substrate regions 150 with each cell element of erasing (zone 150 comprises the passage area of memory cell), and cell element is stylized by the hot electron injection of source terminal, this noun " injection of source terminal hot electron " is that the bit line zone 134 of hypothesis cell element is " source electrode ", in another case, if this zone is drain electrode, then source electrode line zone 144 is exactly a source electrode, the zone 134 and 144 can be called as regions and source, we especially term limit the present invention.
Memory is inside and the top (as shown in figure 11) that is formed at the independent p type island region territory 150 of silicon substrate 905, silicon substrate 905 is formed by monocrystalline silicon or other semi-conducting materials, in certain embodiments, the end face of substrate 905 has a crystal orientation＜100 〉, this substrate mixes with boron, and concentration is that 2E15 is to 2E16atom/cm
3
The generation method of above-mentioned zone 150 is as follows: in substrate 905, implant N type alloy via mask open with ionic-implantation, and forming N-zone 1103, can area of isolation 150 and following square structure, give an example, with energy and the 1.0E13atom/cm of 1.5MeV
2Dosage implant phosphorus.
In an independent ion implantation step or a series of ion implantation step, use other mask (not drawing) to implant N type alloy to form N-zone 1105, N-zone 1105 is surrounded zone 150 fully, in certain embodiments, this step can produce N well (not drawing) simultaneously, will form the periphery P MOS electric crystal of peripheral circuit within it, this class circuit has sensing amplifier, input/output driver, decoder, voltage generator or the like, in the CMOS technology, producing this class N well is known technology.
When memory operates, N-zone 1103 is identical or higher with the voltage of substrate regions 150 with 1105 voltage, the reference voltage of following table 1 viewing area 150, the voltage in the zone 1107 of the substrate 905 then voltage with zone 1103 and 1105 is identical or lower, in certain embodiments, make zone 150,1103, the 1105 formation short circuits that are connected together, make regional 1107 ground connection in addition.
The present invention is not particularly limited the isolation technology in zone 150, and also not limiting is the memory with separate substrates zone.
Shown in Figure 12 A, generate silicon layer (or be called tunnel oxide, below abbreviate oxide layer sometimes as) 108 at the end face of substrate regions 150 with thermal oxidation method, in certain embodiments, be the grow up oxide layer of thick 9um of about 800 ℃ dry type oxidation process.
Then, form polysilicon layer 124 at oxide layer 108 end faces, in certain embodiments, be with Low Pressure Chemical Vapor Deposition (low pressure chemical vapor deposition, LPCVD) the polysilicon layer 124 of deposition one bed thickness 120um slightly mixed by (N type) at that time or afterwards in deposition, and above-mentioned polysilicon layer 124 can be as floating gate, perhaps can be as other circuit elements of peripheral circuit, this class component has intraconnections, electric crystal grid, resistor, capacitor board or the like.
End face at polysilicon layer 124 continues deposition one silicon nitride layer 1203, in certain embodiments, it is the nitride that deposits a bed thickness 120nm with Low Pressure Chemical Vapor Deposition, if necessary, also can above polysilicon layer 124, form one deck silicon layer (not drawing) and so can lower stress in elder generation before the depositing nitride.
Above silicon nitride layer 1203, form photo-resistive mask 904 then with little shadow technology, and from mask open etching silicon nitride layer 1203 and polysilicon layer 124, form and equidirectional rectangular (strip) that passes memory array of bit line whereby, in the vertical view of Figure 12 B, " BL " axle points to the direction of bit line, and " WL " axle points to the direction of character line, in certain embodiments, be with reactive ion-etching (reactiveion etching process, RIE) etching polysilicon layer 124 and silicon nitride layer 1203.
Can not influence the cell element geometry even if photo-resistive mask 904 is aimed at yet,, only need be adjusted at the part in array edges and neighboring area (zone at peripheral circuit place) yet even need to adjust.
After the etching polysilicon layer 124, opening etching oxide layer 108 and substrate regions 150 from photo-resistive mask 904, to form isolated groove 910 (as shown in figure 13), the isolated groove of peripheral circuit (not drawing) also is to form in this step, etching mode then can be selected reactive ion-etching, and gash depth is about 0.25nm.
Remove photo-resistive mask 904 then.
Utilize mask etching two-layer or sandwich construction as long as mention here, unless mention especially, otherwise be to utilize this mask only to understand the etching the superiors, after the superiors are etched, remove mask, and then with the superiors that retain as mask, the layer that etching is remaining, or do not need mask, for instance, behind the etching silicon nitride layer 1203, remove resistance mask 904 earlier, be used as mask with silicon nitride layer 1203 then, the polysilicon layer 124 under the etching, oxide layer 108, substrate 150, the silicon nitride layer 1203 that has part is simultaneously etched, but is not to remove fully.
With trench dielectric material filling groove 910 to form an insulating barrier 1010 and to cover wafer (as shown in figure 13), in certain embodiments, insulating barrier 1010 can be generated by following method: above the exposed surface of groove 910 with known rapid thermal oxidation method (rapid termal oxide, RTO) silicon oxide layer of generation one bed thickness 13.5um, and then use high-density electric slurry (high density plasma, HDP) chemical vapour deposition technique (chemical vapor deposition, CVD) the silicon layer of deposition one bed thickness 480nm.
Then utilize chemical mechanical milling method (CMP) and/or some comprehensive etch process (blanketetch process) etching to remove partial insulative layer 1010, till exposing silicon nitride layer 1203 (as shown in figure 14), wherein silicon nitride layer 1203 is as etching stopping layer in this step.Remove silicon nitride layer 1203 (as in the wet etching mode) then, or insulating barrier 1010 also etched away, this can utilize regularly wet etching (timed wet etch), last structure can be as shown in figure 15, one smooth superstructure is arranged, or be the sidewall that etching isolation layer 1010 can expose polysilicon layer 124, this can improve the efficient of memory cell, and we will be in hereinafter explanation.
Then, form insulating barrier 98 (shown in Fig. 9 B and Fig. 9 C) in certain embodiments, insulating barrier 98 is oxygen nitrogen oxide (oxide-nitride-oxide, ONO) structure, its formation method is: at first, under 800 ℃ or lower temperature, adding thermosetting silicon layer 98.1 (as shown in figure 16) with dry type oxidation process above the polysilicon layer 124, the reference thickness of silicon layer 98.1 is 6um, deposit the silicon nitride layer 98.2 of a bed thickness 4um then with Low Pressure Chemical Vapor Deposition, then add thermosetting silicon oxide layer 98.3 being lower than under 850 ℃ the temperature with wet oxidation process.
In Figure 16,98.3 while of silicon layer are as the gate insulator of peripheral electric crystal, before forming silicon layer 98.3, on memory array, form earlier photo-resistive mask (not drawing), mask does not cover neighboring area 1603, etch away 98.2 of neighboring area 1603,98.1,124,108 each layers are to expose substrate 905, remove mask then, the oxidation wafer is to generate silicon layer 98.3, the reference thickness of 1603 silicon layer 98.3 is 24nm in the neighboring area, silicon oxide layer 98.3 above memory area silicon nitride layer 98.2 then is that 1nm is thick, silicon oxide layer 98.3 on silicon nitride layer 98.2 is thinner, and this is because the growth speed ratio of silicon on nitride wants slow on silicon substrate 905.
Above insulating barrier 98, form polysilicon layer 128.1, in certain embodiments, deposit the polysilicon layer 128.1 of a bed thickness 80um with Low Pressure Chemical Vapor Deposition, mixed with N+ or P+ at that time or afterwards in deposition, and deposited silicon tungsten layer 128.2 then, its reference thickness is 50nm, silicon tungsten layer 128.2 can form by chemical vapour deposition technique, then deposit ammonification silicon layer 720 above wafer, nitration case 720 can be formed by Low Pressure Chemical Vapor Deposition, and thickness is about 160um.
In certain embodiments, wherein one deck of polysilicon layer 128.1 and silicon tungsten layer 128.2 can omit, or is replaced by other materials.
Then, form photoresistance on silicon nitride layer 720 surface, little shadow patterning photoresistance forms rectangular, character line on itself and the memory array in the same way, this photo-resistive mask 1014 will be used for forming stacked structure 710, photo-resistive mask 1014 also can patterning neighboring area 1603 peripheral electric crystal grid 128.1,128.2, silicon nitride layer 720, photo-resistive mask 1014 do not have to aim at a geometry that can't change memory cell, the border and the neighboring area that only need to adjust memory array get final product.
Etching 720; 128 (promptly 128.1 and 128.2); 98 each layers are with definition stacked structure 710; available etching mode has non-grade to reactive ion-etching; remove resistance mask 1014 earlier then; above neighboring area 1603, form another photo-resistive mask (not drawing) again; with silicon nitride layer 720 be under the mask etching polysilicon layer 124 and oxide layer 108; photoresistance can be protected the silicon substrate 905 of peripheral active area; divest photoresistance then; Figure 17 A and Figure 17 B show the memory array profile that generates; its section and bit line parallel; these sections are obtained along arrow 17A and the 17B of Figure 16 respectively; section among Figure 17 B is to downcut along groove 910, and the section of Figure 17 A then is to downcut along the position between adjacent trenches.
Similarly, the section of Figure 18 A, Figure 19 A, Figure 20 A, Figure 21 A, Figure 22 A, Figure 23 A, Figure 24 A, Figure 31 A, Figure 32 A, Figure 33 A is to downcut along the position between adjacent trenches, and the section of Figure 18 B, Figure 19 B, Figure 20 B, Figure 21 B, Figure 22 B, Figure 23 B, Figure 24 B, Figure 31 B, Figure 32 B, Figure 33 B then is to downcut along groove 910.
In certain embodiments, do not form peripheral electric crystal grid with polysilicon layer 128.1 and silicon tungsten layer 128.2, peripheral electric crystal grid is formed by the polysilicon layer that deposits afterwards, and the character line also is formed by the polysilicon layer.This embodiment has omitted first etching 98.2 before forming silicon layer 98.3; 98.1; 124; the step of 108 each layers; and the step with the mask protection memory array has also been omitted when etching; when forming photo-resistive mask 1014; periphery active area top existing 108; 124; 98; 128; 720 each layers; cover those layers of memory array active area exactly; be etched in these layers in neighboring area and memory array zone simultaneously; so do not need to divest photo-resistive mask 1014 after the intact silicon layer 98.3 of etching, above-mentionedly when etching polysilicon layer 124, be used to protect the mask of peripheral active area then can omit.
Oxidation structure (as under 1080 ℃ oxygen atmosphere, carrying out) with the rapid thermal oxidation method, so, can form the silicon layer 1510 (shown in Figure 18 A and Figure 18 B) of thick 5um at the exposed surface of substrate regions 150, the polysilicon layer 124 and 128.1 that this step can allow oxidation expose simultaneously has the horizontal breadth of 8nm at a silicon oxide layer 1510 of polysilicon sidewall.
Deposit the thin silicon nitride layer 903 (shown in Figure 19 A and Figure 19 B) of a bed thickness 20um with Low Pressure Chemical Vapor Deposition, do not need mask, the above-mentioned silicon nitride layer 903 of anisotropic etching promptly can form partition on the sidewall of stacked structure 710.
This etching step can remove simultaneously and be exposed to outer silicon layer 1510, be lower than the silicon layer 1810 of above substrate regions 150, growing up again under 800 ℃ the temperature with dry type oxidation process, this is designated as 1810 silicon layer in Figure 19 A will provide the gate insulator of selecting electric crystal, and the reference thickness of this silicon layer 1810 is 5nm.
In certain embodiments, can omit the step that forms silicon nitride layer 903 or silicon layer 1510.
Then, form polysilicon layer 520 (shown in Figure 20 A, Figure 20 B, Figure 21 A, Figure 21 B), in certain embodiments, deposit the polysilicon layer 520 of a bed thickness 300um with Low Pressure Chemical Vapor Deposition, deposition was carried out severe doping (N+ or P+) at that time or afterwards, above-mentioned polysilicon layer 520 is carried out comprehensive anisotropic etching (as reactive ion-etching), fortunately form partition on the sidewall of stacked structure 710, we can control the width of formed polysilicon partition by the vertical thickness of adjusting silicon nitride layer 720 and polysilicon layer 520.
On the stacked structure 710 two ends sidewalls among the embodiment polysilicon partition 520 is arranged all, in certain embodiments, source electrode line 144 is very narrow, so that polysilicon layer 520 can fill up the gap of 710 of source electrode line top stacked structures, and can not form partition on the sidewall near piling up of that end of source electrode line.
Except grid alternatively, polysilicon layer 520 can also be as the circuit element of other peripheral circuits such as intraconnections, electric crystal grid, for this purpose, before etching polysilicon layer 520, can form mask earlier in the neighboring area, above memory cell, then not need this mask.
Above part polysilicon layer 520, utilize little shadow to form photo-resistive mask 1710 (shown in Figure 21 A and Figure 21 B), the polysilicon layer 520 of this part will form the character line, photo-resistive mask 1710 also can cover part or whole neighboring areas, form the rectangular of character line direction, two adjacent stacks structures 710 that each rectangular and adjacent source polar curve is 144 are overlapping, and covering bit line zone 134, source electrode line 144 is not then covered by photo-resistive mask 1710.
The longitudinal edge of photo-resistive mask 1710 can be situated in the arbitrary position on the stacked structure 710, therefore if the error of mask alignment less than half of stacked structure 710 width, we are for the strictness so of requirement of position.In certain embodiments, minimum characteristic size is 0.14mm, and the admissible error of mask alignment is 0.07mm, and the width of each stacked structure 710 is 0.14mm, i.e. the alignment tolerance of twice.
Each stacked structure 710 of etching keeps the polysilicon partition 520 of each stacked structure 710 near that side of bit line near the polysilicon layer 520 (shown in Figure 22 A and Figure 22 B) of that side of source electrode line.
Etch away after the polysilicon layer 520, keep photo-resistive mask 1710, implant the usefulness of wafer as N type alloy (as phosphorus), direction as 2110 ratios of arrow among Figure 22 A, severe doping (N+) source electrode line 144, this is to allow source electrode line have high voltage for erasing and/or " deeply " of the operating voltage that stylizes implants, and when alloy spreads to side, dark implantation can be suitable overlapping of 124 formation of doped source polar curve and floating gate.
In certain embodiments, alloy can not penetrate insulating barrier 1010, (shown in Figure 22 B) do not take place so this step does not have the situation of the bottom of doping groove 910, this step impure source line zone is labeled as " 144.0 " in Figure 22 C, no matter whether alloy can penetrate insulating barrier 1010, insulating barrier 1010 all can avoid alloy near or arrive 1103 (as shown in figure 11) of N-zone, therefore can avoid having high leakage current or situation of short circuit to take place at source electrode line 144 and 1103 in N-zone.In certain embodiments, finish back (after being heating steps) at processing procedure, substrate 905 upper surfaces in the territory, upper surface abscission zone 150 in N-zone 1103 are approximately 1mm, and groove 910 degree of depth are 0.25mm.
After the implantation; stay photo-resistive mask 1710; and the insulating barrier 1010 that exposes has removed (shown in Figure 23 B) from the groove 910 that is positioned at source electrode line 144 wholly or in part; silicon nitride layer 903 and dioxide layer 1510 can protect for 124 and 128 two-layer unlikely exposing of sidewall; etching mode can be an anisotropic etching, as reactive ion etching.Remove the silicon layer 1810 (shown in Figure 23 A) that is positioned at source electrode line 144 end faces in an etching simultaneously in this step.
Remove mask 1710 then, and carry out comprehensive N+ and implant 2401 with doping bit line zone 134 and source electrode line 144 (shown in Figure 24 A, Figure 24 B, Fig. 9 B, Fig. 9 C), stacked structure 710 and polysilicon layer 520 cover substrate when implanting.In certain embodiments, the implant procedure step is included in the non-zero angle direction of vertical axis (axle of vertical wafer) and carries out the ion implantation, and with the doping trenched side-wall, in certain embodiments, angle is 7 °, 8 ° or 30 °, and alloy can be an arsenic.
Above-mentioned this implantation can't penetrate the insulating barrier 1010 near bit line zone 134, so bit line zone can not form short circuit.
Next can utilize known technology to finish the manufacturing of memory, similarly being can depositing insulating layer (not drawing), form contact openings 138 (shown in Fig. 9 A), deposition and patterning conductive material to be to form the bit line and other must part.
Explanation as the relevant Figure 15 in front, after grinding insulating barrier 1010, it can be etched with the sidewall that exposes polysilicon layer 124, Figure 24 C illustrates this embodiment, this figure is memory passes control sluice 128 along the character line a memory array profile, control sluice 128 comprises the part 128A near floating gate 124 sidewalls, so can improve the capacitive coupling of 124 of control sluice 128 and floating gates.In certain embodiments.Polysilicon layer 124 thick 120nm, wide 140nm, if the upper surface of polysilicon layer 124 greatly about the top 60um of insulating barrier 1010 upper surfaces, just can the be greatly improved coupling situation of 124 of control sluice 128 and floating gates that is petty.
It should be noted that the floating gate 124 autoregistration active area of bit line direction among the present invention especially, 128 autoregistration floating gates 124 of the control sluice of character line direction are selected 520 autoregistration control sluice 128 of lock (character line) then.Its implementation method is utilized the shallow trench isolation technology exactly, opens 124 definition active area (or directly defining floating gate 124 and active area simultaneously with the active area mask) to float, and so floating gate 124 is the autoregistration active area; Then utilize the control sluice 128 definition floating gates 124 when the thick dielectric layer of definition control sluice 128 tops (or also and then define simultaneously floating gate 124 and control sluice 128) of floating gate 124 tops, control sluice 128 like this and autoregistration floating gate 124; Lock 520 (partition) is selected in generation at last, because select lock 520 to generate along the thick dielectric layer of control sluice 128 tops, that is the control sluice 128 of 520 while of the selection lock also autoregistration thick dielectric layer below of character line direction.
Utilize autoregistration step repeatedly, not only can effectively reduce the size of memory, can also guarantee the electrical conductivity of each cell element, though select the misalignment of 128 of lock 520 and control sluice can't change the electrical conductivity of memory cell, but determined the electrical conductivity of memory cell because of the passage length of selecting 124 of lock 520 and floating gates, so selecting the misalignment of 124 of lock 520 and floating gates is the electrical conductivity that can have influence on memory cell, change design element electrically, utilize processing procedure of the present invention can effectively improve this class deviation.
In certain embodiments, the grid of periphery electric crystal is to be formed by 520 on polysilicon layer, rather than by 128 layers form, the part of the relevant Figure 16 in front was carried, so need before deposition control sluice layer 128, not cover memory array earlier, and 1603 remove polysilicon layer 124 and 98.2,98.1,108 each layers from the neighboring area.Forming among the embodiment of peripheral electric crystal grid with polysilicon layer 520, photo-resistive mask 1014 can't cover neighboring area 1603, or can not cover the zone that peripheral electric crystal grid will form at least, therefore, when definition stacked structure 710, can etch away 108,124,98,128,720 each layers of neighboring area or peripheral at least electric crystal area of grid, expose the substrate 905 of peripheral active area.
Handle wafer (shown in Figure 17 A to Figure 19 B) as above-mentioned mode then, silicon layer 1810 will form the gate insulator of peripheral electric crystal.
In certain embodiments, can reduce the resistance of peripheral electric crystal grid by the following step, after deposition polysilicon layer 520 (as shown in figure 25), above polysilicon layer 520, form one deck silicon tungsten or other layer of low resistance material (not drawing), above the neighboring area, form photo-resistive mask 2501 then, silicon tungsten or the other materials layer that is not covered by photo-resistive mask 2501 on the polysilicon layer 520 removed in etching, then polysilicon layer 520 is carried out anisotropic etching, to form partition (shown in Figure 20 A and Figure 20 B), and define peripheral electric crystal grid and other peripheral elements, remove photo-resistive mask 2501 then, so silicon tungsten or other electric conducting materials 2605 will cover the polysilicon layer 520 (shown in Figure 26 B) of neighboring area, if electric conducting material 2605 and polysilicon layer are by the while etching, then polysilicon layer 520 top of memory array also may stay some electric conducting materials 2605.
In certain embodiments, before forming photo-resistive mask 2501, above polysilicon layer 520, deposit one deck silicon nitride layer 2607 (shown in Figure 26 C) earlier, if electric conducting material 2605 is the resistance that is used to reduce peripheral electric crystal grid, then silicon nitride layer 2607 is deposited on electric conducting material 2605 tops, above peripheral electric crystal grid, form photo-resistive mask 2501 then as mentioned above, etching is the silicon nitride layer of coated region not, mode according to Figure 25, Figure 26 A, Figure 26 B is handled wafer, and Figure 26 C is the profile that the neighboring area has the embodiment of electric conducting material 2605.When after a while structure being carried out cmp, silicon nitride layer 720 and 2607 can be as etching stopping layer, when the stage of Figure 24 A and Figure 24 B (after doped source polar curve and the bit line), when structure is insulated material (as vapour deposition oxide (vapordeposited oxide (vapox), do not draw) cover after, carrying out cmp can the planarization wafer.In certain embodiments; insulating barrier is as the last layer protective layer before wafer cutting or the encapsulation; and in certain embodiments; the material of insulating barrier can be to mix or the silicon layer that do not mix; as boron phosphorus silicon glass (borophosphosilicate glass; BPSG), can also use other material.
In certain embodiments, some peripheral electric crystal grids or other elements be by 128 layers form, other periphery gates or element then are to be formed by 520 on polysilicon layer, the back will illustrate a this embodiment according to Figure 44 to Figure 50.
Reduce the resistance of polysilicon layer (character line) 520, can utilize metal tape, each strip metal band is positioned on the character line, and with certain all period interval contact with the character line (as per 128 the row), because character line 520 is narrow partitions, still have low resistance even there is small embossment to contact with metal tape, photo-resistive mask 2501 can be used for forming this projection.Figure 27 is the vertical view of this embodiment, show and utilize anisotropic etching polysilicon layer 520 to form after the partition, memory array is blocked and a gap 2701 is arranged, gap 2701 and bit line are in the same way, so produce and to form the space of character line projection, gap 2701 can be used for groove 910, memory array section 2703.1 is positioned at a side (it seems that Figure 27 be to be positioned at the top, gap) in gap, memory array section 2703.2 then depends on the below, gap, character line 520 and stacked structure 710 be continual to stride across section 2703.1 and 2703.2 and the gap, part polysilicon layer 520 before carrying out etching formation partition in formed mask 2501 coverage gap 2701, Figure 28 shows the vertical view that removes photo-resistive mask 2501 and form photo-resistive mask 1710 post gaps 2701 zones.
In Figure 27, photo-resistive mask 2501 comprises extend along the gap rectangular, photo-resistive mask 2501 is blocked in the zone 2709 of 520 on adjacent character line, but the polysilicon layer 520 of etching character cable brake like this, therefore can avoid forming short circuit between adjacent character line, one can break can be continuous above source electrode line 144 for photo-resistive mask 2501, and the photo-resistive mask above source electrode line need not interrupted, this be stranded for the polysilicon layer 520 in etching source electrode line zone be to utilize photo-resistive mask 1710 (as shown in figure 28).
Photo-resistive mask 2501 also can cover peripheral electric crystal grid and other peripheral elements, as the narration of top relevant Figure 25.
Photo-resistive mask 1710 (as shown in figure 28) can have identical geometry external form with the photo-resistive mask that top relevant Figure 21 A is narrated to Figure 23 B, above-mentioned same purposes also can be arranged, be etching source electrode line 144 polysilicon layer 520, to source electrode line implant 2110 deeply, the insulating barrier 1010 of etched trench, Figure 29 shows the polysilicon layer 520 of etching source electrode line, and each polysilicon (character line) 520 has lateral projection 520E in gap 2701.
Handle wafer with reference to previous Figure 22 A to Figure 26 C then, if insulating barrier 1010 is to carry out etching with reference to the mode of figure 23B, then remove the insulating barrier 1010 in the gap 2701 that is positioned at source electrode line 144 wholly or in part, channel bottom and sidewall in the memory array intermediate gap simultaneously mix, so, source electrode line 144 can pass the gap and uninterrupted.
Figure 30 A shows the profile that is positioned at than gap of storage 2701 inside of back-end process, above memory cell, formed insulating barrier 2901, each metal tape 2903 is positioned at the top of corresponding character line 520, and the opening 2903C via insulating barrier 2901 contacts with character line 520 in lock crack 2701.In Figure 30 A, the upper surface of polysilicon layer 520 is high together with the upper surface of control control lock 128 top silicon nitride layers 720, and this is because polysilicon layer 520 is handled through chemical mechanical milling method, stops when running into the silicon nitride layer.Particularly, insulating barrier 2901 is made up of plural layer, and some layer is to deposit after the step of Figure 24 A and Figure 24 B, handles through cmp again, then forms other layers to finish a complete insulating barrier 2901.Polysilicon layer 520 and silicon nitride ply in other embodiments.
In certain embodiments, the do not use up width (be Figure 28 and Figure 29 heavy ruler cun) in whole gap 2701 of isolated groove 910, the composite bed isolated groove can be positioned at the gap, or also can be without any groove in the gap.
Figure 30 B and Figure 30 C are respectively memory section and the mask distribution patterns of another embodiment, Figure 30 c shows photo- resistive mask 904,1014,2501 (please also refer to Figure 12 A, Figure 12 B, Figure 16, Figure 27), bit line contact 138 can with the contact openings 290C etching simultaneously of polysilicon layer 520, also can be not simultaneously, the contact openings 144C of source electrode line 144 also can contact 138 or polysilicon contact 2903C etching simultaneously with the bit line.In certain embodiments, the contact openings (not drawing) of contact openings 138,2903C, 144C and control sluice 128 is to use same photo-resistive mask to carry out etching synchronously, from the downward etching silicon nitride of mask open layer 720 to expose control sluice, the contact openings 2903C of polysilicon layer 520 does not link to each other with control sluice 128, forms short circuit to avoid character line 520 and control sluice 128.
Contact openings 138 can use known technology to fill up with N+ doping polysilicon connector, if because the contact mask not have to aim at make contact openings 138 etch effects the interior insulating barrier 1010 of groove 910, the insulating barrier 1010 that then is removed in the groove will be received in the N+ polysilicon when forming connector, the polysilicon connector can avoid Metal Contact and 150 in P doped substrate zone to form short circuit.
In certain embodiments, can form short circuit between the adjacent source electrode line 144, for example, source electrode line can four is one group, four source electrode lines of each group can with the metal tape 2903 formation short circuit of joining, metal tape 2903 can contact with source electrode line via the 3010 inner opening 144C of the gap between the memory array adjacent lines, the source electrode line short circuit can be reduced needs to connect the zone of source electrode line to higher metal layers (not drawing), only need a contact openings (not drawing) because four source electrode line contacts with higher metal layers, the resistance that also can be used for reducing source electrode line that contacts with higher metal layers, can be formed at the source electrode line top by the formed metal tape of higher metal layers, contact at interval with metal tape 2903,3010 inner opening 144C contact metal tape 2903 in the gap with source electrode line, and memory array can have a plurality of gaps 3010.For four source electrode lines of each group, the formation short circuit that also can be connected together of eight of being followed control brake cable 128.
By photo-resistive mask 1014 defined control brake cables 128 along source electrode line contact openings 144C bending, if it is very close in the bit line zone 312 of adjacent control brake cable 128 in gap 3010, polysilicon layer 520 may be inserted in the above-mentioned zone 312, cause character line 520 to form the short circuit of trouble in these zones, for fear of short circuit, can use photo-resistive mask 1710 (Figure 28) to remove polysilicon layer 520 in the gap 3010, this can make that character line partition 520 is blocked in gap 3010, the particular character line in 3010 in lockage crack can not be electrically connected with metal tape 2903 (shown in Figure 30 B), and 2903 of metal tapes contact with the character line in gap 2701.
It is similar with Figure 24 B to Figure 24 A with 2703.2 section with 3010 memory array section 2703.1 to be positioned at lock crack 2701, and metal tape 2903 is positioned on the character line, but is not in contact with it in memory array section 2703.1 and 2703.2.
In certain embodiments, can be by silicon source electrode line 144 to reduce its resistance, for example, deposit cobalt or other suitable metals on the structure in stage (before or after the bit line zone 134 of promptly mixing) of Figure 24 A and Figure 24 B, heating wafer feasible exposed silicon and cobalt or other metal reactions, and the silicon compounds of formation conduction, remove unreacted cobalt or other metals then, this silicon compounds just can be stayed source electrode line 144 and character line 520 tops, above-mentioned silicon step therewith in the field known silicon processing procedure (being the autoregistration silicon compounds) identical.
In certain embodiments, insulating barrier 1810 may be not enough to avoid cobalt or other metals and 134 in bit line zone to form short circuit, therefore, character line 520 is to form short circuit with bit line zone 134, we can utilize following method to avoid this situation: after wafer is through Figure 20 A and the processing in Figure 20 B stage, just the deposition photo-resistive mask 1710 before, first depositing insulating layer 3003 (as Figure 31 A and Figure 31 B), the material of above-mentioned insulating barrier 3003 can be a silicon.Aforesaid then method, form photo-resistive mask 1710 in regular turn, then remove the insulating barrier 3003 that exposes in photo-resistive mask 1710 outsides, again with the processing of wafer through Figure 21 A to Figure 23 B step, particularly be exactly etching polysilicon layer 520 and doped source polar curve 144 (promptly implanting 2110), remove photo-resistive mask 1710 then, just the structure of generation is shown in Figure 32 A and Figure 32 B.
And then deposition layer of metal (as cobalt), the heating wafer makes the silicon in metal and the source electrode line zone react, and removes unreacted metal, and is last, just forms petrificating layer 3301 (shown in Figure 33 A and Figure 33 B) above source electrode line.
Under certain conditions, if there is not complete etching to remove the insulating barrier 1010 (shown in Figure 23 B) that is positioned at groove 910, then the silicon compounds 3301 in the groove 910 can be blocked.
Then, continue etching isolation layer 3003, implant 2401 (shown in Figure 24 A and Figure 24 B) in bit line zone 134 and source electrode line, or can pass insulating barrier 3003 and implant, insulating barrier 3003 also can be selected to be retained in the memory certainly.
And source electrode line silicon technology can be used with the embodiment (being that peripheral electric crystal grid is to be formed by 128 on control sluice layer) of Figure 16, also can use with the embodiment (being that peripheral electric crystal grid is to be formed by 520 on polysilicon layer) of Figure 25, Figure 26 A, Figure 26 B, Figure 26 C, or use with the embodiment ( polysilicon layer 128 and 520 all is used for as peripheral electric crystal grid) of Figure 44 to Figure 50, this part will illustrate that the silicon technology also can combine with protruding 520E (extremely shown in Figure 30 as Figure 27) in the back.
Figure 34 explanation is according to another fast-flash memory array of the present invention, and each isolated groove 910 protrudes between the adjacent source electrode line 144, but does not intersect with source electrode line, and we are denoted as 910B to the border of isolated groove.
The processing procedure of above-mentioned sort memory is as follows: doped substrate 905 forms area of isolation 150 (as shown in figure 11), form tunnel oxide 108, polysilicon layer 124, silicon nitride layer 1203, photo-resistive mask 904 (shown in Figure 12 A and Figure 12 B) then in regular turn, patterning silicon nitride layer 1203 and polysilicon layer 124, but, this step does not have etching substrates zone 150, whether 108 of tunnel oxides can be decided in its sole discretion and will etch away, then remove photo-resistive mask 904, the structure that obtains just as shown in figure 35.
Then, deposit the silicon oxide layer 2710 (as shown in figure 36) of the 300nm of a bed thickness with chemical vapour deposition technique, as boron phosphorus silicon glass, little then shadow patterning photo-resistive mask 2810 (as shown in figure 37), making becomes the rectangular of character line direction, each is rectangular to be positioned at the zone that source electrode line 144 will form, other elements of photo-resistive mask 2810 and memory (as control sluice 128) relevant (as shown in figure 38), and this step does not also form control sluice 128.
By the selection of photo-resistive mask 2810 and silicon nitride layer 1203 is removed the dioxide layer 2710 and 108 that photo-resistive mask and silicon nitride layer 1203 are surrounded than etching, remove photo-resistive mask 2810 then, with dioxide layer 2710 and silicon nitride layer 1203 is mask etching substrates zone 150, forms rectangle groove 910; Or in etching substrates zone 150 o'clock, photo-resistive mask 2810 can be kept, under this situation, do not need to deposit dioxide layer 2710.Figure 39 shows the section of the embodiment that uses dioxide layer 2710, and this section is the resultant plane by groove of line 39-39 cutting-out along Figure 37, and the plane section by groove is then not the same with Figure 36.
And then deposit an insulating barrier 1010 (as shown in figure 13), and remove partial insulative layer 1010 (as shown in figure 14) with chemical mechanical milling method, then removing silicon nitride layer 1203, selective etch insulating barrier 1010 causes upper surface to become a flat surfaces.Figure 40 B is a resulting structures at parallel character line and the section plan by groove, and Figure 40 A then is by the section plan between adjacent trenches, and some insulating barrier 1010 may cover the substrate regions 150 of source electrode line 144 parts.Source electrode line does not stride across groove (some dioxide layer 2710 can be stayed on the sidewall of polysilicon rectangular 124, and at this moment oxide layer seems can similarly to be the part of insulating barrier 1010).
In certain embodiments, can etching remove partial insulative layer 1010,, improve the capacitive coupling (shown in Figure 24 C) of 124 of control sluice 128 and floating gates whereby to expose the sidewall of polysilicon layer 124.
Remaining fabrication steps can be identical with aforementioned Figure 16 to Figure 33 B, as form steps such as insulating barrier (material can be oxygen nitrogen oxide layer, ONO layer) 98, control sluice layer 128, silicon nitride layer 720, photo-resistive mask 1014 (being that peripheral electric crystal grid can be formed by 128 layers or 520 on character line layer).
Form silicon layer 1510 (shown in Figure 18 A) then, silicon nitride partition 903 and silicon layer 1810 (shown in Figure 19 A).
Deposition and anisotropic etching polysilicon layer 520 (shown in Figure 20 A), form photo-resistive mask 1710 (shown in Figure 21 A) then, the polysilicon layer 520 at etching source electrode line 144 places (shown in Figure 22 A), but can not etching as for insulating barrier 1010 etchings at source electrode line 144 places, implant 2110 then, because source electrode line does not intersect with groove 910, the current implantation whole rectangular source electrode line that mixes, the structure that generates is identical with Figure 22 A, and Figure 41 shows the section (being that this profile is to suppose the insulating barrier 1010 at etching source electrode line place) along groove.
Explanation as the relevant Figure 24 A in front and Figure 24 B, remove photoresistance and invite cover 1710, carry out the N type and implant 2401 doping bit lines zone 134 and source electrode line 144, insulating barrier 1010 that can first etching source electrode line place before implanting 2410 steps, or between implantation 2110 and 2410 steps, carry out etching, or after implanting 2410 steps, carry out, or not etching.
In certain embodiments, the bossing 520E of Figure 27 to Figure 30 is taken as character line 520; In certain embodiments, shown in Figure 24 A, Figure 31 A to Figure 33 B, meeting silicon source electrode line 144 is to reduce its resistance.
In Figure 42, we have omitted dioxide layer 2710 and photo-resistive mask 2810, isolated groove 910 shown in Figure 12 A be by photo-resistive mask 904 definition, but because groove 910 is rectangular (as shown in figure 37), therefore silicon nitride layer 1203 and polysilicon layer 124 have same profile with the composite bed of Figure 37, groove 910 has same profile with the groove of Figure 34 to Figure 41, remove the insulating barrier 1010 (as shown in figure 15) of source electrode line 144 tops with chemical mechanical milling method, remaining fabrication steps is just the same with Figure 37 to Figure 41, when definition stacked structure 710, and the polysilicon layer 124 and the dioxide layer 108 of the source electrode line of etching simultaneously 144 tops, this step can expose source electrode line 144.
At Fig. 9 A in the embodiment of Figure 43, be to utilize source terminal hot electron injection method (make the become non-conductive) memory cell that stylizes, see also " the NonvolatileSemiconductor Memory Technology " the 21st to 23 page that people such as W.D.Brown delivered in 1998, following table 1 is listed the memory reference voltage that drives with 1.8V external power source supply (VCC), oblique line is to be used for representing selecting/voltage of non-selection memory column or row, give an example, table 1 " stylizing " OK, " bit line zone 134 " row, it is 0V that the bit line is selected in project " 0V/V3 " expression, and not selected bit line is voltage V3, and we do not list all non-selection voltages.
The erasing of memory cell can use from floating gate 124 to source electrode line 144 " via the source electrode line sector of erasing " of table 1 (please refer to OK) or wear tunnel to the Fowler-Nordheim of substrate regions 150 (" via the substrate sector of erasing "), the latter is than preferable technology, because reduced band and interband (band-to-band) electric current.In the fast-flash memory array of Figure 10 B and Figure 34, the whole zone (sector) of can only erasing, and other cell element of can not erasing, a zone is meant row or an ordered series of numbers, the source electrode line 144 of their correspondence is connected to form short circuit via circuit, and corresponding control brake cable 128 also is connected to form short circuit via circuit.
Some embodiment provide the erase a plurality of zones or the selection of whole memory array in the single operation step, the cell element that wherein utilizes from floating gate 124 to substrate regions 150 Fowler-Nordheim electrons tunnel to be remained to be erased to erase synchronously, " wafer is erased " of Here it is table 1, zone 150 is a forward bias with respect to all control sluice, array is erased the speed that adopts the wafer erase mode can be faster than what come by the row erase mode, and this is particularly useful when testing memory.
Table 1
| Stylize | Via the source electrode line whole zone of erasing | Via the substrate whole zone of erasing | Wafer is erased | | |
| Control sluice | |||||
| 128 | +10V/0V | -10V | -10V | -10V | 1.8V |
| | 0V/V3 ** (VCC＝1.8V) | V4 *** (VCC＝1.8V) | Float | Float | 1.5 |
| | 6V | 5V | Float | Float | |
| Select gate | |||||
| 520 | VTN+ΔV 1 * | 0V | 0V | 0V | VCC+ΔV 2 * (VCC＝1.8V ) |
| | 0V | 0V | 6V | 6V | 0V |
Annotate:
* in an embodiment, VTN=0.6V, Δ V
1=0.9V, Δ V
2=1.4V.
* V3 is greater than 0V
1Voltage.
* * V4 voltage range 0＜V4＜VCC.
Article one, memory can have a plurality of memory arrays, and each memory array all has bit line and the character line of oneself, and different arrays can be placed on identical substrate regions 150 or be placed on the different isolated substrates zone 150 of same integrated circuit." wafer is erased " operates the memory cell that can erase on some substrate regions 150, and can not erase at the cell element of other substrate regions 150.
Voltage generator and decoder block 4201 (as shown in figure 43) can use known technology in response to power supply supply voltage VCC, address signal " ADDR ", other the necessary voltages of generation such as order/controlling signal.
Figure 44 explanation is according to the thickness of the golden oxygen half electric crystal of the resultant difference of the memory embodiment gate insulator of Fig. 9 A to Figure 43, the gate insulator that need approach during high speed operation, on the contrary, the electric crystal that is exposed under the high voltage then needs thicker gate insulator, simultaneously, tunnel oxide 108 also will have enough thickness to remember long data.
In will narrating below among the embodiment at once, all gate insulators all are the silicon layers, but this is not certain, and the thickness of relevant gate insulator is hypothesis VCC=1.8V, and operating voltage as above table 1 is listed, these voltages only for the explanation but not be used for limiting the present invention.
In Figure 44, tunnel oxide 108 thick about 9um select 1810 of electric crystal grid oxic horizons will relatively approach (as 5nm), and are still also enough thick so that quick computing to be provided, and just withstand voltage 3.2V (the VCC+ Δ V in the example that is used as read operation in the table 1
2=3.2V).
Neighboring area 1603 comprises active area 4402,4404,4406, high voltage active area 4402 is to use to the electric crystal under-10V voltage (seeing also table 1) and other high voltages to being exposed to 10V, these electric crystals may be voltage generator 4201 parts of (as shown in figure 43), thicker on the grid oxic horizon 4408 in zone 4402, about 22 to 25nm is thick.
High speed active area 4404 is to use to being exposed to the electric crystal that is lower than under the VCC voltage, these electric crystals may be the parts of address decoder, sensing amplifier, time pulse signal generator, voltage generator, address and data buffer and other circuit, their grid oxic horizon 4410 is quite thin, and about 3.5nm is thick.
I/O active area 4406 is to using as the electric crystal that cuts off the wafer circuit interface, cutting off wafer circuit may operate under higher power supply supply voltage, as 2.5V or 3.3V, so the I/O electric crystal must have thicker grid oxic horizon to bear so high voltage, in Figure 44, I/O electric crystal grid oxic horizon 1810 is same one decks with selecting electric crystal grid oxic horizon 1810, and it is thick to be about 5um.
In Figure 44, the electric crystal grid in zone 4402 and 4404 is to be formed by 128 on control sluice layer, the I/O electric crystal grid in zone 4406 and the selection lock 520 (being the character line) of memory cell are to be formed by 520 on polysilicon layer, explanation as Figure 26 B and Figure 26 C, selecting can have metal level and/or silicon nitride layer on the lock 520, and control sluice 128 is formed by polysilicon polysilicon metal or other conductive layers.
The processing procedure of above-mentioned formation gate insulator is as follows: the tunnel oxide 108 (shown in Figure 12 A) that generates thick 9nm, above-mentioned oxide layer 108 is to be created on the entire wafer (to comprise neighboring area 1603), deposit then and patterning polysilicon layer 124, then form isolated groove 910, and fill up groove 910 with insulating material 1010, see also Figure 12 A to Figure 15, Figure 37, Figure 42 and relevant explanatory note.
Form silicon layer 98.1 and silicon nitride layer 98.2 (as shown in figure 16), the reference thickness of above-mentioned these layers is respectively 1nm and 5nm.
Deposition and little shadow patterning photo-resistive mask 4501 make it cover memory array (as shown in figure 45) then, and 98.2,98.1,124,108 each layers of etching neighboring area 1603 are to expose substrate 905.
Then, remove photo-resistive mask 4501, oxidation wafer under 850 ℃ or lower temperature, so can generate the silicon layer 4408 (as shown in figure 46) of thick 24um in active area 4402,4404,4406, simultaneously, above the silicon nitride layer 98.2 of memory array active area 901, then form the silicon layer 98.3 of thick 1nm to 1.5nm.
Deposition and patterning photo-resistive mask 4601 make it cover whole memory array and high voltage active area 4402 then, and active area 4404 and 4406 is not covered, and therefore are able to the silicon layer 4408 of etching active area 4404 and 4406.
Remove photo-resistive mask 4601 then, generally speaking, remove photoresistance step afterwards and normally clean wafer, the dioxide layer 4408 that cleaning not too can failure area 4402 in this embodiment, this is because dioxide layer 4408 is very thick, and thin oxide layer 4410 (as shown in figure 44) is because of can contacting with photoresistance, so also can be because of removing the cleaning behind the photoresistance and cause damage.
Oxidation wafer then, generate the silicon layer 4410 (as shown in figure 47) of thick 3.5nm in active area 4404 and 4406, but serviceability temperature is lower than 850 ℃ dry type oxidation process here, and this step makes the thickness of dioxide layer 4408 (promptly in the zone 4402) be increased to about 25um.
On wafer, deposit control sluice layer 128 and silicon oxide layer 720 then, form photo-resistive mask 1014, and the electric crystal grid that utilizes this photo-resistive mask 1014 to define stacked structures 710 and be positioned at high-voltage region 4402 and high-speed region 4404, photo-resistive mask 1014 does not cover I/O active area 44406, and etching photo-resistive mask in regular turn 1014 is with the silicon nitride layer 720 under exposing, control sluice layer 128, and 98.3,98.2,98.1,4408,4410 each layers are as long as wherein run into the polysilicon layer 124 of array active area 901 and the substrate 905 of peripheral active area promptly stops in etching process.
Remove photo-resistive mask 1014 then; form another photo-resistive mask 4801 (as shown in figure 48) and cover all neighboring areas 1603 (have the zone that forms silicon nitride layer 720 can be) without photo-resistive mask 4801; on the etched wafer not by the polysilicon layer 124 and the silicon layer 108 of 720 protection of photo-resistive mask 4801 and silicon nitride layer; so form stacked structure 710; remove photo-resistive mask 4801 then, the structure that is generated as shown in figure 49.
Then; continue to form silicon layer 1510 and silicon nitride layer 903 (shown in Figure 19 A and Figure 19 B); sidewall with protection stacked structure 710; oxidation wafer then; above the exposed substrate 905 of the exposed substrate regions 150 of memory array active area 901 and I/O active area 4406, form the silicon layer 1810 (as Figure 20 A and shown in Figure 44) of thick 5um; then deposition and patterning polysilicon layer 520 are with as I/O periphery electric crystal grid (shown in Figure 25, Figure 26 A, Figure 26 B, Figure 26 C).
As mentioned above; when carrying out cmp; the silicon nitride layer 2607 (shown in Figure 26 C) of active area 4406 polysilicon layers 520 top can be protected polysilicon layer 520; if if but do not form above-mentioned silicon nitride layer 2607; also can protect polysilicon layer 520 in the mode of Figure 50; its method is: form empty interposed structure at " void is put (dummy) " the regional 4404D near electric crystal active area 4406 earlier; void is put the treatment step and high-speed region 4404 identical (Figure 44) in zone; so can form silicon nitride layer 720 at regional 4404D; the upper surface of silicon nitride layer 720 is than the upper surface height of regional 4406 polysilicon layers 520; when covering brilliant figure and carrying out cmp with silicon (not drawing) after a while; the silicon nitride layer 720 of zone 4404D can not allow the silicon of regional 4406 polysilicon layers 520 top be removed, and so can protect polysilicon layer 520.
In addition, void is put regional treatment step also can be identical with high-voltage region 4402, perhaps, available different void is put the zone and is surrounded each I/O electric crystal active area 4406, some is a mode of utilizing zone 4402, some then utilizes the mode in zone 4404, or is provided in the single disposal structure that arbitrary side surrounds element.Some regional 4404D can not be that void is put the zone, promptly can form electric crystal in these zones.Can utilize isolated groove 910 that regional 4404D is separated with zone 4406, perhaps regional 4404D may be partly overlapping with isolated groove, or be positioned at the top of isolated groove fully.
Below we at mode with empty interposed structure protective circuit element, be described further again.
Figure 51 is the profile of semiconductor structure 110, and this structure comprises that semiconductor substrate 905, polysilicon layer 128 and 520, protective layer 720 its materials can be silicon nitride), dielectric layer 113.Circuit structure 121.1 comprises by polysilicon layer 128 formed circuit element 128.1 and by polysilicon layer 520 formed circuit element 520.1, in one embodiment, said elements 128.1 can be the grid of capacitor board or membrane transistor, and element 520.1 can be source electrode, drain electrode and/or the passage area of capacitor board, electric crystal, both can be different devices, for example, element 128.1 can be the electric crystal grid, and element 520.1 can be resistor, capacitor board, intraconnections etc.
The protection feature 720.1 and 720.2 be by 720 layers form, can protection component 128.1,520.1,520.2 when cmp dielectric layer 113.
The element 128.3 of at least a portion does not have protected seam 720 to cover.
Form empty interposed structure 141 in place near element 128.3; can when cmp dielectric layer 113, protect this circuit element; each empty interposed structure comprises by polysilicon layer 520 formed part 520.3; can cover other part 520.3 by protective layer 720 formed feature member 720.3; feature 520.3 can be as any circuit element; any electrical functionality is not provided yet, can be connected to a fixed voltage or allows it float.
Field area of isolation 1010 is formed by the shallow trench isolation technology, or can utilize local silicon oxidation (local oxidation of silicon, LOCOS) technology or other technologies formation; Empty interposed structure 141 is positioned at an area of isolation 1010 tops, but this not necessarily.
Because the non-flat forms influencing profiles of each element; make that the upper surface of dielectric layer 113 is also uneven; we carry out cmp to dielectric layer 113; stop when running into protective layer 720; reach the purpose of planarization whereby; the structure that generates is shown in Figure 52; the upper surface of structure may be fully smooth; or also leave some non-flat forms zones; a reason that forms non-flat forms is each feature member 720.1; 720.2; 720.3 it is and uneven; wherein element 720.2 and 720.3 upper surface are lower than the upper surface of element 720.1; also have; dielectric layer 113 upper surfaces of element 128.3 tops also can be lower; this is because the below does not have the structure of protective layer 720; the not good reason of another flatness may be that element is lower in some partial density of integrated circuit; see also in the U.S. Patent number 5 of bulletin on June 1st, 1999; 909; 628 " REDUCING NON-UNIFORMITY IN A REFILL LAYER THICKNESS FOR ASEMICONDUCTOR DEVICE "; but; through after the cmp; the upper surface of structure 110 is more smooth, belongs to substantive smooth.
In certain embodiments; gap is less than 15nm between the low spot of the height point of protective layer 720 and dielectric layer 113; the degree of known non-flat forms is relevant with thickness, milling time, the cmp parameter (as pressure) of dielectric layer 113; the degree of non-flat forms is also relevant with specific cmp technology (as using mud or low mud fixed abrasive), and the present invention does not limit any specific cmp processing procedure or non-flat forms degree.
In certain embodiments, not every protective layer 720 all is subjected to grinding influence, such as has only higher feature member 720.1 can be subjected to grinding influence, and lower feature member 720.2 then can not.
Empty interposed structure 141 meeting protection components 128.3 are unaffected, in certain embodiments, adjacent structure 141 spacings of element 128.3 two opposite sides are about 5mm, and layer 720 be the silicon nitride of thick 160nm, and void is put upper surface about 0.21mm above element 128.3 of feature member 720.3; In other embodiments, empty interposed structure 141 spacings of element 128.3 two opposite sides surpass 10mm, and maximum can allow spacing to follow the quality of the material of use, layer thickness, cmp that relation is all arranged.
Can only provide empty interposed structure on one side of structure 121.3.
If the dielectric layer 113 above element 128.3 is thick inadequately, so that required isolation can't be provided, then can structurally deposit another layer insulating (not drawing), this one deck has the substantive smooth upper surface of comparison, because the dielectric layer of below 113 has more smooth structure through after the cmp.
Provide one below with reference to processing procedure: according to each one demand treatment substrate 905 (as forming complementary metal oxide semiconductor (complementary metal oxide semiconductor, CMOS) well, but the present invention is not limited only to complementary metal oxide semiconductor), form then insulating barrier 4410 or 1810 and other the layer, deposition and patterning 128,520,720 each layers, depositing insulating layer 113 then, and, can form other layer or steps of mixing certainly some stage in processing procedure with the chemical mechanical milling method processing.
In Figure 53, empty interposed structure 141 is to use polysilicon layer 128, the integrated circuit of Figure 53 comprises a fast-flash memory array 901, silicon layer 124 is as the floating gate of memory cell, polysilicon layer 128 is as control sluice, polysilicon layer 520 is grid alternatively, insulating barrier 108 (" tunnel oxide ") is to be formed by silicon, enough thickness is arranged so that suitable data memory to be provided, in certain embodiments, oxide layer 108 thick 9nm select electric crystal grid oxic horizon 1810 thick 5nm, the material of mentioning here and thickness only the confession explanation with but not be used for limiting the present invention.
The bit line of memory cell zone 134 is connected with top bit line (not drawing), and it stretches to the direction of bit line " BL ", and the direction of character line is stretched in source electrode line zone 144, and is vertical with the bit line.
Wherein neighboring area 1603 comprises active area 4402,4404,4406 (shown in Figure 53), form electric crystal in it, high voltage active area 4402 is to use for the electric crystal that is arranged in high voltage environment, electric crystal then is used to erase and the memory cell of the array 901 that stylizes, this regional electric crystal grid is formed by 128 on polysilicon layer, and gate insulator 4408 is silicon layers of thick about 20nm.
High-speed region 4404 comprises the electric crystal that has than thin grid oxide layer 4410, under low-voltage, operate, oxide layer 4410 thick 3.5nm, electric crystal grid be by 128 layers form.
I/O active area 4406 is for using as the electric crystal that cuts off the wafer circuit interface, cutting off wafer circuit can operate under higher power supply supply voltage, so electric crystal has thicker grid oxic horizon, to bear this voltage, gate insulator is with identical as memory array 901 1810 layers of selection electric crystal gate insulators.
Relevant manufacturing step is summarized as follows:
On substrate 905, form the tunnel oxide 108 (Figure 54) of thick 9nm with thermal oxidation method, deposit polysilicon layer 124, silicon layer 98.1, silicon nitride layer 98.2 then in regular turn, then above memory array 901, form photo-resistive mask 4501,98.2,98.1,124 each layers in the etching area 4402,4404,4406 are to expose substrate 905.
Before deposition silicon layer 98.1, first patterning polysilicon layer 124 and substrate 905 form isolated groove, fill up groove with silicon 1010.
After the etching oxide layer 108, remove photo-resistive mask 4501, heating generates the oxide layer 4408 (Figure 55) of thick 19nm on substrate 905, at this moment can form very thin silicon layer 98.3 above silicon nitride layer 98.2.
Generate photo-resistive mask 4601, the silicon layer 4408 in the etching area 4404 and 4406 on the substrate at memory array 901 and high-voltage region 4402 little shadows.
Remove photo-resistive mask 4601 then, the oxidation wafer, the silicon layer 4410 (the 56th figure) of the thick 3.5nm of generation above the substrate 905 in zone 4404 and 4406, in this step, the thickness of the oxide layer 4408 in the zone 4402 has a little to be increased.
On wafer, deposit polysilicon layer 128 and silicon nitride layer 720 then, form photo-resistive mask 1014 with the floating gate of definition (i) memory array and control sluice (ii) the electric crystal grid in the zone 4402 and 4404, the (iii) empty interposed structure 141 in the zone 4406, etching is by 720,128,98.3,98.2,98.1,4408,4410 each layers of mask overlay area, and etching will stop at polysilicon layer 124 in the memory array zone and the substrate 905 (Figure 57) in other zones.
Remove photoresistance 1014 then, when cleanup step, polysilicon layer 128 and silicon nitride layer 720 can be protected the thin grid oxide layer 4410 of high-speed region 4404.
4402,4404,4406 form another photo-resistive mask 4801 in the zone; there is the place of silicon nitride layer 720 can; except the zone of photo- resistive mask 4801 and 720 protection of silicon nitride layer; the polysilicon layer 1124 of etched wafer and silicon layer 108 remove photo-resistive mask 4801 (Figure 58) then.
124 and 128 layers expose sidewall and substrate 905 above oxidation structure generate thin silicon layer 1510 (Figure 59), deposition and anisotropic etching approach silicon nitride layer 903 then, so can form partition at electric crystal grid structure and empty interposed structure, when etching, the silicon layer 1510 that exposes because of etching silicon nitride layer 903 may be removed.
Above the exposed surface of substrate 905, generate the silicon layer 1810 (Figure 60) of thick 5nm with thermal oxidation.
Structurally deposit polysilicon layer 520, form the electric crystal grid of photo-resistive mask 2501 then, the partition that anisotropic etching polysilicon layer 520 forms on electric crystal grid structure and the empty interposed structure sidewall with definition I/O zone 4406.
Remove resistance mask 2501 earlier, above the selection grid of the grid of I/O electric crystal and memory array, form photoresist layer 1710 (Figure 61), the polysilicon layer 520 in the remaining zone of etching.
The doping step that the suitable stage in processing procedure suits forms the source electrode of electric crystal and drain region, bit line and source electrode line are regional and other doped regions.
In certain embodiments, memory cell is multistage cell element (multilevel cells, MLC), be that each memory cell can store the information that surpasses a bit, each floating gate 124 can store three or more charge energy rank, corresponds to three or more different control sluice 128 threshold voltage, sees also the United States Patent (USP) 5 of Lee in bulletin on September 4th, 1999,953,255.
The present invention is not limited to the above embodiments, the present invention not only be defined in specific erase or the mechanism that stylizes (as Fowler-Nordheim, or hot electron injects), non-flash electronic type programmable read-only memory (the electrically eraseable programmable read onlymemory that can erase is contained in the present invention, EEPROM) and other known or not the invention memories, the present invention also is not limited only to above-mentioned material, such as control sluice, selecting the material of lock and other conducting elements can be metal, the metal silicon compounds, polysilicon metal and other electric conducting materials or compound, perhaps also can comprise conductor and conductor part simultaneously, polysilicon layer as the part doping, silicon or silicon nitride also can replace with other insulating material, P type and N type conduction pattern can exchange, the present invention is not subject to any specific program step or sequence of steps, give an example, in certain embodiments, the thermal oxidation of silicon can change into chemical vapour deposition technique or other technologies deposition one deck silicon or other insulating material, in certain embodiments, dark implantation 2110 can be carried out behind etching insulating material 1010, the invention is not restricted to the silicon integrated circuit, the claim scope definition other meet the embodiment and the variation of category of the present invention.
Claims (19)
1, a kind of manufacturing comprises the method for the integrated circuit of non-volatility memorizer, it is characterized in that, this method comprises at least:
(a) form first insulating barrier (108) and ground floor (124) on the first area of semiconductor, wherein this integrated circuit comprises a plurality of non-volatile memory cell unit, and each those memory cell includes one by the formed floating gate of part this ground floor (124);
(b) opening via this ground floor forms a plurality of grooves (910) in this semiconductor first area, and fills those grooves (910) with insulating material (1010);
(c) on this semiconductor first area, form a second layer (128), wherein each those cell element includes one by the formed conduction lock of part this second layer (128), and this floating gate (124) of this conduction lock and those cell elements is isolated with one second insulating barrier (98);
(d) this second layer of patterning (128) stretches to the rectangular of a predetermined direction with formation, each this rectangular across a plurality of those grooves (910);
(e) remove not by this ground floor of part (124) on this semiconductor first area of this second layer (128) covering, to form a plurality of first structures, it is one formed rectangular by this second layer that each those first structure comprises, and comprising this ground floor of part of this rectangular below, each those first structure has a first side wall;
(f) on this ground floor and this second layer, form one the 3rd layer (520), and with the processing procedure that comprises anisotropic etching remove the part the 3rd layer (520), what make in each those first structures forms a partition (520) to this first side wall of small part, wherein this ground floor (124) in corresponding first structure with this of each this partition (520) and the material of this second layer (128) are isolated with an isolated material;
(g) use little shadow to form a little shadow mask pattern (1710), this little shadow mask pattern covers this partition on this first structure the first side wall;
(h) serve as the cover curtain with this little shadow mask pattern (1710), to remove this partition (520) that is not covered by little shadow mask pattern, therefore, each those cell element includes one by the formed conduction lock of partition (520) on this first side wall of this first structure; And
(i) utilize this little shadow mask pattern (1710) in this semiconductor first area, to mix alloy for the cover curtain.
2, the method for claim 1, it is characterized in that, in forming this second layer (128) before, this ground floor (124) forms and is the rectangular of an angle with this predetermined direction and those grooves pass a row non-volatile memory cell unit to be same as this rectangular direction.
3, method as claimed in claim 2 is characterized in that, the method that forms this ground floor (124) more comprises:
Little shadow mask pattern on little this ground floor of shadow patterning, rectangular to define this of this ground floor; And
Utilize above-mentioned this little shadow mask pattern to define those grooves (910).
4, the method for claim 1 is characterized in that, wherein:
Each this first structure includes one second sidewall;
This little shadow mask pattern processing procedure comprises deposition and little shadow patterning one little shadow mask pattern, with on this first side wall that covers this first structure to this partition of small part, and cover one first semiconductor substrate, zone between this first side wall of adjacent this first structure.
5, method as claimed in claim 4, it is characterized in that, each this second semiconductor substrate zone extends between two adjacent these first structures, and the source/drain areas (1810) of all memory cells between two adjacent these first structures of bound fraction is provided, wherein this source/drain areas (1810) is electrically connected to each other.
6, method as claimed in claim 4 is characterized in that, more comprises using this little shadow mask pattern to remove insulating material in the groove in this second semiconductor substrate zone with etching wholly or in part.
7, method as claimed in claim 6 is characterized in that, removes in this groove after the insulating material in etching wholly or in part, more comprises removing this little shadow mask pattern, and mix alloy in this first and second semiconductor substrates zone.
8, the method for claim 1 is characterized in that, this ground floor (124) comprises a polysilicon layer, and this second layer (128) comprises a polysilicon layer and a metal silicon compounds layer.
9, the method for claim 1 is characterized in that, wherein:
Before forming this second layer, this ground floor has a plurality of oblong openings, but the zone that will form source electrode line is then by this ground floor covering;
The formation of this groove is to form from this semiconductor first area of the downward etching of this oblong openings; And
Step (e) comprises on this source electrode line zone and removes this ground floor.
10, the method for claim 1 is characterized in that, more comprises following steps to form second MOS (metal-oxide-semiconductor) transistor:
Also form first insulating barrier (108) and ground floor (124) when on semi-conductive first area, forming first insulating barrier (108) and ground floor (124) simultaneously on this semi-conductive second area;
Remove this ground floor (124) and this first insulating barrier (108) of this integrated circuit second area;
When carrying out (c) step, also on this second area, form second insulating barrier (98) simultaneously;
When carrying out (c) step, also go up simultaneously and form the second layer (128) to form second MOS (metal-oxide-semiconductor) transistor at second insulating barrier (98) of this second area.
11, method as claimed in claim 10 is characterized in that, described second insulating barrier (98) is different with first insulating barrier (108) thickness.
12, the method for claim 1 is characterized in that, more comprises following steps the 3rd MOS (metal-oxide-semiconductor) transistor:
In this first area and this second area when forming this first insulating barrier (108), also form this first insulating barrier (108) in the 3rd zone simultaneously;
In forming this ground floor (124) before, remove this first insulating barrier (108) from this second and third zone, and form one the 3rd insulating barrier in this second and third zone; And
When removing this ground floor (124) from this second area, patterning is positioned at this ground floor (124) in this first and the 3rd zone simultaneously, so that the conduction lock as this first and the 3rd MOS (metal-oxide-semiconductor) transistor to be provided.
13, method as claimed in claim 12 is characterized in that, wherein in forming this layer second layer (128) afterwards, this first insulating barrier, this second insulating barrier, and the thickness of the 3rd insulating barrier all inequality.
14, method as claimed in claim 12 is characterized in that, when forming the 3rd insulating barrier, the thickness that is positioned at this first insulating barrier of this first area can increase.
15, the method for claim 1, it is characterized in that, this integrated circuit comprises a non-volatile memory cell unit, and this cell element comprises (a) by the formed conduction lock of this ground floor of part (124) and (b) by the formed conduction lock of this second layer (128).
16, method as claimed in claim 15 is characterized in that, more comprises before forming this first insulating barrier (108) step:
Form a gate insulation layer on this semiconductor substrate, this memory cell will be formed in the zone of this integrated circuit;
Form a conductor layer on this gate insulation layer, so that a floating gate of this memory cell to be provided; And
Remove this conductor layer and this gate insulation layer from this first and second zone.
17, method as claimed in claim 16 is characterized in that, more is included in this conductor layer top and forms an insulating barrier, to isolate this conductor layer and this ground floor.
18, a kind of manufacturing comprises the method for the integrated circuit of non-volatility memorizer, it is characterized in that, this method comprises:
Form an insulating barrier (108), wherein this integrated circuit comprises a plurality of non-volatile memory cell unit, and this insulating barrier (108) is the gate insulation layer as those non-volatile memory cell units;
Form a ground floor (124), with floating gate as those non-volatile memory cell units;
Insulating barrier (98) is on the ground floor (124) of those memory cells on the formation floating gate;
Remove insulating barrier on this floating gate (98), ground floor and this insulating barrier (108) in regular turn from high-voltage region, high-speed region, the I/O zone of the periphery of this integrated circuit non-volatile memory cell unit, in order on this high-voltage region, high-speed region, I/O zone, respectively to form at least one peripheral MOS (metal-oxide-semiconductor) transistor;
Form one first gate insulation layer (4408) in this high-voltage region, high-speed region, I/O zone;
Remove this first gate insulation layer (4408) from this high-speed region, I/O zone;
Form one second gate insulation layer (4410) in this high-speed region, I/O zone;
Form a second layer (128) on insulating barrier (98), this first gate insulation layer (4408), this second gate insulation layer (4410) on this floating gate, this MOS (metal-oxide-semiconductor) transistor that wherein is positioned at this high-voltage region has by the formed conduction lock of this second layer of part;
Remove this second layer (128) and second gate insulation layer (4410) from this I/O zone;
Form one the 3rd gate insulation layer (1810) in this I/O zone; And
The ground floor and the second layer on this memory cell sidewall of high-temperature oxydation;
Form one the 3rd layer (520) on the MOS (metal-oxide-semiconductor) transistor of those memory cells and this high-voltage region and this high-speed region comprehensively;
Form a little shadow mask pattern in this I/O zone with the definition MOS (metal-oxide-semiconductor) transistor;
Impose anisotropic etching so that the 3rd layer (520) form partition on the sidewall of the MOS (metal-oxide-semiconductor) transistor of the MOS (metal-oxide-semiconductor) transistor of those memory cells, this high-voltage region and high-speed region;
Form another little shadow mask pattern to protect the respectively partition an of side of those memory cells;
Remove all this not by the 3rd layer of little shadow mask pattern, be used to form MOS (metal-oxide-semiconductor) transistor on this I/O zone;
This first gate insulation layer that wherein is positioned at this high-voltage region is thicker than this second gate insulation layer, and is also thick than the 3rd gate insulation layer, and the 3rd gate insulation layer (1810) is then thick than this second gate insulation layer (4410).
19, method as claimed in claim 18; it is characterized in that; the periphery that more is included in this I/O zone forms an empty interposed structure; this void interposed structure is identical with the MOS (metal-oxide-semiconductor) transistor of high-speed region; and after second layer step forms; before removing this second layer (128) and second gate insulation layer (4410) step from this I/O zone; form a protective layer (720) in the MOS (metal-oxide-semiconductor) transistor of this high-voltage region, high-speed region and the top of those memory cells, with the 3rd layer of protection I/O zone MOS (metal-oxide-semiconductor) transistor.
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| CN100385646C (en) * | 2005-08-19 | 2008-04-30 | 力晶半导体股份有限公司 | Semiconductor component of preventing breakdown, and manufacturing method |
| CN100452355C (en) * | 2005-08-19 | 2009-01-14 | 力晶半导体股份有限公司 | Nonvolatile memory, and manufacturing method |
| US8125051B2 (en) * | 2008-07-03 | 2012-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device layout for gate last process |
| US7981801B2 (en) | 2008-09-12 | 2011-07-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chemical mechanical polishing (CMP) method for gate last process |
| KR20100108715A (en) * | 2009-03-30 | 2010-10-08 | 주식회사 하이닉스반도체 | Method for manufacturing of non-volatile memory device |
| CN102931143B (en) * | 2011-08-10 | 2015-04-29 | 无锡华润上华科技有限公司 | Method for manufacturing NOR flash device |
| CN103021855B (en) * | 2011-09-27 | 2015-04-01 | 中芯国际集成电路制造(上海)有限公司 | Separate gate flash memory active region manufacturing method |
| CN103151458B (en) * | 2013-03-22 | 2015-04-29 | 厦门博佳琴电子科技有限公司 | Embedded phase change memory array and manufacturing method |
| CN105723501B (en) * | 2013-12-18 | 2020-02-21 | 英特尔公司 | Heterogeneous layer device |
| US10043672B2 (en) * | 2016-03-29 | 2018-08-07 | Lam Research Corporation | Selective self-aligned patterning of silicon germanium, germanium and type III/V materials using a sulfur-containing mask |
| WO2018030666A1 (en) * | 2016-08-11 | 2018-02-15 | 에스케이실트론 주식회사 | Wafer and manufacturing method therefor |
| CN107845634B (en) * | 2016-09-19 | 2020-04-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN108091658B (en) * | 2017-11-16 | 2021-04-13 | 上海华力微电子有限公司 | Process integration structure and method of flash memory |
| CN114678370B (en) * | 2022-05-30 | 2022-08-02 | 广州粤芯半导体技术有限公司 | Flash structure and preparation method thereof |
| CN115274676B (en) * | 2022-09-29 | 2022-12-13 | 广州粤芯半导体技术有限公司 | Flash memory structure and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2732070B2 (en) * | 1988-07-12 | 1998-03-25 | 三菱電機株式会社 | Writing method for nonvolatile semiconductor memory device |
| US5280446A (en) * | 1990-09-20 | 1994-01-18 | Bright Microelectronics, Inc. | Flash eprom memory circuit having source side programming |
| US5912842A (en) * | 1995-11-14 | 1999-06-15 | Programmable Microelectronics Corp. | Nonvolatile PMOS two transistor memory cell and array |
| JP3850136B2 (en) * | 1998-04-03 | 2006-11-29 | 株式会社リコー | Nonvolatile semiconductor memory device |
-
2001
- 2001-12-31 CN CNB2004100965896A patent/CN100533740C/en not_active Expired - Lifetime
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Also Published As
| Publication number | Publication date |
|---|---|
| CN100533740C (en) | 2009-08-26 |
| CN1632945A (en) | 2005-06-29 |
| CN1430264A (en) | 2003-07-16 |
| CN1632952A (en) | 2005-06-29 |
| CN100390960C (en) | 2008-05-28 |
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