CN1142586C - Semiconductor integrated circuit device and process for manufacturing the same - Google Patents

Semiconductor integrated circuit device and process for manufacturing the same Download PDF

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Publication number
CN1142586C
CN1142586C CNB991040155A CN99104015A CN1142586C CN 1142586 C CN1142586 C CN 1142586C CN B991040155 A CNB991040155 A CN B991040155A CN 99104015 A CN99104015 A CN 99104015A CN 1142586 C CN1142586 C CN 1142586C
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district
mentioned
trap
conduction type
forms
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CN1238557A (en
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谷口泰弘
宿利章二
����һ
黑田谦一
池田修二
桥本孝司
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Desella Advanced Technology Co
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Hitachi Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L

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  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

A photoresist pattern through which a first well forming region and a second well forming region are exposed is formed over a semiconductor substrate, used as the mask to dope the semiconductor substrate with an impurity thereby to form buried n-wells, and further used as the mask to dope the same with an impurity thereby to form shallow p-wells in a self-alignment manner over the buried n-wells. Subsequently, the photoresist pattern is removed. After this, a photoresist pattern through which the outer peripheral region of the first well forming region and a third well forming region are exposed is formed over the major surface of the semiconductor substrate, and used as the mask to dope the semiconductor substrate with an impurity thereby to form shallow p-wells.

Description

The method of semiconductor device and manufacturing semiconductor device
Technical field
The present invention relates to make the technology of semiconductor device, relate to a kind of otherwise effective technique when being applied to the trap isolation technology in more detail, for electricity is isolated in trap (well) (semiconductor regions) and the Semiconductor substrate that forms in the Semiconductor substrate, in the bottom of original trap branch and lateral parts, form another trap so that surround original trap by this technology.
Background technology
Above-mentioned trap isolation technology can be supplied with the desirable voltage that is different from the voltage that is added on Semiconductor substrate to first trap that forms by first trap and second trap electricity isolation that forms in Semiconductor substrate around it.
Above-mentioned technology be applied to various semiconductor device pictures for example in first trap, form memory cell for instance and the MISFET in memory cell (metal-insulator-semiconductor field effect transistor) apply the DRAM (dynamic random access memory) of reverse bias voltage, electric erasable and programmable program ROM) and so on or first trap is applied the fast storage (EEPROM: semiconductor device of tribute voltage.
The semiconductor device of trap isolation structure that description is had our research here.
More precisely, the second conduction type shallow well that is formed with the first conduction type deep trap on the trap isolated area in the second conductive type semiconductor substrate and in the zone of deep trap, forms.By from of the deep position diffusion impurity of Semiconductor substrate first type surface, form the periphery that surrounds shallow well and make shallow well and the above-mentioned deep trap of Semiconductor substrate electricity isolation to Semiconductor substrate.Therefore, can supply with the voltage different to shallow well with the voltage that puts on Semiconductor substrate.
In another zone of Semiconductor substrate, be formed with first conventional conductive type of trap and the second conventional conductive type of trap.By form the trap of these first conduction types and second conduction type from the predetermined position diffusion impurity of Semiconductor substrate first type surface to Semiconductor substrate.
Forming in the technology of above-mentioned well structure with two masks, obtaining above-mentioned well structure is with two masks: be used to form the common mask of the first conduction type deep trap and the doping step of first conductive type of trap of routine and be used to form the second conduction type shallow well and the shared mask of the doping step of second conductive type of trap of routine.
Yet, form with mask relevant that we have found following point in two kinds of described so far technology of trap.
Specifically, from producing first problem the actual conditions that second conductive type impurity and first conductive type impurity form the second conduction type shallow well by compensating.That is to say, the valid density of second conductive type impurity increases to about two times of the second conductive type impurity concentration in routine second conductive type of trap that does not have trap to isolate, therefore the transistor that forms on the Semiconductor substrate first type surface has the characteristic that differs widely, and the spy is threshold voltage in addition.Need new mask to adjust threshold voltage.
The total impurities concentration that second problem is the second conduction type shallow well increases to about three times that place the impurity concentration that do not have routine second conductive type of trap of trap under isolating.Therefore, carrier mobility is reduced to the characteristics of transistor that damage forms in the Semiconductor substrate first type surface on first type surface, particularly reduces leakage current.
When along with transistorized further miniaturization, trap density big on the rise in owing to disturb the transistorized factor of high-performance, two above-mentioned problems become serious.
Summary of the invention
The purpose of this invention is to provide and need under situation about increasing to some extent on the number of steps of making semiconductor device, can not make the optimized technology of impurity concentration of the trap of trap and the routine in the trap isolated area.
Another object of the present invention provides the technology that can improve the characteristic of the element that forms in the trap of the routine in trap and trap isolated area on the number of steps of making semiconductor device under the situation that any increase need not arranged.
According to describing below of carrying out with reference to the accompanying drawings, the above-mentioned purpose and the new characteristics with other of invention will be conspicuous.
To be summarized in the representational situation of disclosed the present invention in the specification hereinafter tout court.
According to an aspect of the present invention, the method for the manufacturing semiconductor device that provides comprises step:
A) making makes first trap form first mask that Qu Hezai exposes to the open air from second trap formation district of first trap formation district a distance formation on the Semiconductor substrate first type surface;
B) make doping mask with the first above-mentioned mask the dark position that impurity mixes above-mentioned Semiconductor substrate so that the Semiconductor substrate in above-mentioned first trap formation district and second trap formation district is formed the embedding well region of first conduction type;
C) making doping mask with the first above-mentioned mask mixes impurity above-mentioned Semiconductor substrate so that forms district and the second above-mentioned trap at above-mentioned first trap and form the formation second conduction type shallow well district on the above-mentioned embedding well region of first conduction type in the district;
D) on the Semiconductor substrate first type surface, form to make and surround first trap and form triple-well that peripheral and first trap of the embedding well region of first conduction type in the district forms periphery, the second conduction type shallow well district in the district and form the district and forming from above-mentioned first trap that the 4th trap that a distance, district forms forms that the district exposes to the open air and by second mask thinner than above-mentioned first mask; With
E) making doping mask with the second above-mentioned mask mixes above-mentioned Semiconductor substrate to impurity so that forms in above-mentioned triple-well forms district and surround the first above-mentioned trap and form the periphery in the second conduction type shallow well district in district and be shallower than the first trap and form in district the first embedding trap of conduction type and with the first trap, form the shallow well district that the first embedding well region of conduction type in distinguishing is electrically connected to; And so that form in above-mentioned the 4th trap forms district be shallower than the first trap form district in the first conduction type shallow well district of the first embedding trap of conduction type
Wherein, in above-mentioned first trap forms the district, form the second conduction type shallow well district in the district at the first above-mentioned trap and formed the first conduction type shallow well district of the formation in the district at above-mentioned triple-well and form the embedding well region of first conduction type in the district and surround and isolate with the Semiconductor substrate electricity at the first above-mentioned trap.
In addition, mix step (e) in the present invention so that the impurity concentration at least a portion first conduction type shallow well district in triple-well forms the district is higher than the impurity concentration in the second conduction type shallow well district in first trap forms the district.
In addition, the step that further comprises of the present invention is:
On the Semiconductor substrate first type surface, form the 5th trap formation that makes from a distance formation of first trap formation district by the formation figure and distinguish the 3rd mask that exposes to the open air;
Making doping mask with the 3rd mask mixes impurity Semiconductor substrate so that form the first conduction type shallow well district in the 5th trap forms the district;
On the Semiconductor substrate first type surface, forms to make and formed the 6th trap that encloses along bread in the district by the 5th trap and form and distinguish the 4th mask that exposes to the open air by forming figure;
Making doping mask with the 4th mask mixes Semiconductor substrate to impurity so that form the second conduction type shallow well district in the 6th well region;
On the Semiconductor substrate first type surface, forms and the 5th trap is formed distinguish by forming figure; The 6th trap forms the district and surrounds a part of element isolation zone that the 5th trap forms the district and expose to the open air and have the 5th mask that it is placed in the open end on the element isolation zone; With
Making doping mask with the 5th mask mixes impurity Semiconductor substrate so that forms that the first conduction type shallow well district in the district and the 6th trap form the embedding well region of formation first conduction type below the second conduction type shallow well district in the district so that embedding well region and the 5th trap form district and the 6th trap forms the first conduction type shallow well district in the district and is electrically connected and extends at the 5th trap below the element isolation zone that the formation of encirclement the 5th trap is distinguished
Wherein, in the 6th trap forms the district, the 6th trap form that the second conduction type shallow well district in the district is formed by the 5th trap that the first conduction type shallow well district in the district and the 5th trap form that district and the 6th trap form that the embedding well region of first conduction type in the district surrounds and with the isolation of Semiconductor substrate electricity.
In addition, the step that further comprises of the present invention is:
In first trap forms the district, on the Semiconductor substrate first type surface, form the 6th mask that the first conduction type shallow well district is exposed to the open air; With
Make doping mask with the 6th mask and impurity is mixed first trap form the district so that compensate first trap and form the conduction type in the second conduction type shallow well district in the district and form first trap and form the first conduction type shallow well district in the district,
In step, in first trap forms the district, form the first conduction type shallow well district and the second conduction type shallow well district, and the second conduction type shallow well district by the first conduction type well region, triple-well form the first conduction type shallow well district that forms in the district and first trap form that the embedding well region of first conduction type in the district surrounds and with the isolation of Semiconductor substrate electricity.
In addition, according to a further aspect of the invention, provide the method for making semiconductor integrated device device, comprise step:
(a) making makes first trap form first mask that Qu Hezai exposes to the open air from second trap formation district of first trap formation district a distance formation on the Semiconductor substrate first type surface;
(b) making doping mask with the first above-mentioned mask mixes impurity above-mentioned Semiconductor substrate so that forms the dark position that district and the second above-mentioned trap form the Semiconductor substrate in distinguishing at above-mentioned first trap and form the embedding well region of first conduction type;
(c) making doping mask with the first above-mentioned mask mixes impurity above-mentioned Semiconductor substrate so that forms district and the second above-mentioned trap at above-mentioned first trap and form the formation second conduction type well region on the above-mentioned embedding well region of first conduction type in the district;
(d) on the Semiconductor substrate first type surface, form make surround that first trap forms that the 3rd well region that encloses outside the well region of the embedding well region of first conduction type in the district and second conduction type exposes and than on the second thin mask of first mask; With
(e) making doping mask with the second above-mentioned mask mixes Semiconductor substrate to impurity so that forms in above-mentioned triple-well forms the district and surround the first above-mentioned trap and form the peripheral of the second conduction type well region in the district and be shallower than first trap and form embedding well region of first conduction type in distinguishing and the first conduction type well region that is electrically connected with this embedding well region
Wherein, in above-mentioned first trap forms the district, form the second conduction type well region in the district at the first above-mentioned trap and formed the first conduction type well region that forms in the district at above-mentioned triple-well and form the embedding trap of first conduction type in the district and surround and isolate with the Semiconductor substrate electricity at the first above-mentioned trap.
In addition,, provide the method for making semiconductor device, comprise step according to another aspect of the invention:
(a) on the Semiconductor substrate first type surface, make first mask that makes first semiconductor regions and expose to the open air by forming figure at second semiconductor regions that forms from first semiconductor regions a distance;
(b) make doping mask with the first above-mentioned mask the dark position that impurity mixes above-mentioned Semiconductor substrate so that the Semiconductor substrate in the first and second above-mentioned semiconductor regions is formed the embedding semiconductor regions of first conduction type;
(c) making doping mask with the first above-mentioned mask mixes impurity on above-mentioned Semiconductor substrate so that the above-mentioned embedding semiconductor regions of first conduction type in the first above-mentioned semiconductor regions and above-mentioned second semiconductor regions and forms the shallow semiconductor regions of second conduction type;
(d) on the Semiconductor substrate first type surface, forms the 3rd semiconductor regions of periphery of the embedding semiconductor regions of first conduction type that makes in encirclement first semiconductor regions and the shallow semiconductor regions of second conduction type in first semiconductor regions and second mask that the 4th semiconductor regions from first semiconductor regions a distance exposes to the open air by forming figure; With
(e) making doping mask with the second above-mentioned mask mixes above-mentioned Semiconductor substrate to impurity so that form to surround the peripheral of the shallow semiconductor regions of second conduction type in the first above-mentioned semiconductor regions and the shallow semiconductor regions of first conduction type that is electrically connected with the embedding semiconductor regions of first conduction type in the first above-mentioned semiconductor regions and the shallow semiconductor regions of formation first conduction type in the 4th above-mentioned semiconductor regions in the 3rd above-mentioned semiconductor regions
Wherein, in the first above-mentioned semiconductor regions, the embedding semiconductor regions of shallow semiconductor regions of first conduction type that the shallow semiconductor regions of second conduction type in the first above-mentioned semiconductor regions is formed in the 3rd above-mentioned semiconductor regions and first conduction type in the first above-mentioned semiconductor regions surround and isolate with the Semiconductor substrate electricity and
Wherein, in the second above-mentioned semiconductor regions, the above-mentioned shallow semiconductor regions of second conduction type is electrically connected with above-mentioned Semiconductor substrate.
Hereinafter the representational overview of additive method will be described tout court.
According to a further aspect of the present invention, provide a kind of semiconductor device, comprising:
In first trap of Semiconductor substrate forms the district and second trap that forms at the position that forms the district with a certain distance from first trap form in the district at the embedding well region of first conduction type with a certain distance from the dark position formation of Semiconductor substrate first type surface;
Above-mentioned first trap form district and the second above-mentioned trap form on the above-mentioned embedding well region of first conduction type in the district with the method for irrespectively setting impurity concentration with the above-mentioned embedding well region of first conduction type with the second conduction type shallow well district of the embedding well region self-aligned manner formation of first conduction type;
Form and surround the first above-mentioned trap in the district and form the second conduction type shallow well district in the district and form the first conduction type shallow well district that the embedding well region of first conduction type in distinguishing is electrically connected forming triple-well that the district forms around above-mentioned first trap with first trap; With
Form the first conduction type shallow well district that forms in the 4th trap formation district that forms on the position of distinguishing at the arbitrary trap that forms the district with a certain distance from the first above-mentioned trap, above-mentioned second trap formation is distinguished and above-mentioned triple-well forms in the district,
Wherein, above-mentioned first trap forms the second conduction type shallow well district in the district and is formed the embedding well region of first conduction type in the district and above-mentioned triple-well by the first above-mentioned trap and form the first conduction type shallow well district in the district and surround and isolate with the Semiconductor substrate electricity.
Description of drawings
Fig. 1 is the sectional view of major part of the semiconductor device of explanation the technology of the present invention thought;
Fig. 2 (a) and Fig. 2 (b) are the illustrative curve charts of the impurities concentration distribution of the various piece among Fig. 1;
Fig. 3 is the illustrative curve chart of the impurities concentration distribution of the various piece among Fig. 1;
Fig. 4 is the sectional view of major part in the method for the semiconductor device in shop drawings 1;
Fig. 5 is the top plan view of mask layout that is used for the semiconductor device manufacture method of Fig. 1;
Fig. 6 is the sectional view of major part in the method for the semiconductor device in shop drawings 1;
Fig. 7 is the top plan view of mask layout that is used for the semiconductor device manufacture method of Fig. 1;
Fig. 8 is the sectional view of major part in the method for the semiconductor device of making one embodiment of the invention;
Fig. 9 is the sectional view of major part in the semiconductor device manufacture method after Fig. 8;
Figure 10 is the sectional view of major part in the semiconductor device manufacture method after Fig. 9;
Figure 11 is the sectional view of major part in the semiconductor device manufacture method after Figure 10;
Figure 12 is the sectional view of major part in the semiconductor device manufacture method after Figure 11;
Figure 13 is the sectional view of major part in the semiconductor device manufacture method after Figure 12;
Figure 14 is the sectional view of major part in the semiconductor device manufacture method after Figure 13;
Figure 15 is the circuit diagram of the memory cell in the semiconductor device of Figure 14;
Figure 16 is the top plan view of semiconductor chip that forms the semiconductor device of another embodiment of the present invention;
Figure 17 is the sectional view of major part in the method for the semiconductor device of making Figure 16;
Figure 18 is the sectional view of major part in the semiconductor device manufacture method after Figure 17;
Figure 19 is the sectional view of major part in the semiconductor device manufacture method after Figure 18;
Figure 20 is the sectional view of major part in the semiconductor device manufacture method after Figure 19;
Figure 21 is the sectional view of major part in the semiconductor device manufacture method after Figure 20;
Figure 22 is the sectional view of major part in the semiconductor device manufacture method after Figure 21;
Figure 23 is the sectional view of major part in the semiconductor device manufacture method after Figure 22;
Figure 24 is the top plan view of semiconductor chip that forms the semiconductor device of another embodiment of the present invention;
Figure 25 is the sectional view of major part in the method for the semiconductor device of making Figure 24;
Figure 26 is the sectional view of major part in the semiconductor device manufacture method after Figure 25;
Figure 27 is the sectional view of major part in the semiconductor device manufacture method after Figure 26;
Figure 28 is the sectional view of major part in the semiconductor device manufacture method after Figure 27;
Figure 29 is the sectional view of major part in the semiconductor device manufacture method after Figure 28;
Figure 30 is the sectional view of major part in the semiconductor device manufacture method after Figure 29;
Figure 31 is the sectional view of major part in the semiconductor device manufacture method after Figure 30;
Figure 32 is the top plan view of the semiconductor chip of the expression semiconductor device that forms another embodiment of the present invention
Figure 33 is the sectional view of major part in the method for the semiconductor device of making Figure 32;
Figure 34 is the sectional view of major part in the semiconductor device manufacture method after Figure 33;
Figure 35 is the sectional view of major part in the semiconductor device manufacture method after Figure 33;
Figure 36 is the sectional view of major part in the semiconductor device manufacture method after Figure 33;
Figure 37 is the sectional view of major part in the semiconductor device manufacture method after Figure 33;
Figure 38 is the sectional view of major part in the semiconductor device manufacture method after Figure 33;
Figure 39 is the sectional view of major part in the semiconductor device manufacture method after Figure 33;
Figure 40 is the circuit diagram of memory cell in the fast storage (EEPROM);
Figure 41 is a sectional view of making major part in the method for semiconductor integrated circuit of another embodiment of the present invention;
Figure 42 is the sectional view of major part in the semiconductor device manufacture method after Figure 41;
Figure 43 is the sectional view of major part in the semiconductor device manufacture method after Figure 42;
Figure 44 is the sectional view of major part in the semiconductor device manufacture method after Figure 43;
Figure 45 is the sectional view of major part in the semiconductor device manufacture method after Figure 44;
Figure 46 is the top plan view of component placement in the cache in the semiconductor device of embodiment 5;
Figure 47 is the storage unit circuit figure in the cache of embodiment 5;
Figure 48 is the sectional view of major part in the method for the semiconductor device of making one embodiment of the invention;
Figure 49 is the sectional view of major part in the semiconductor device manufacture method after Figure 48;
Figure 50 is the sectional view of major part in the semiconductor device manufacture method after Figure 48;
Figure 51 is the sectional view of major part in the semiconductor device manufacture method after Figure 48;
Figure 52 is the sectional view of major part in the semiconductor device manufacture method after Figure 48;
Figure 53 is the sectional view of major part in the semiconductor device manufacture method after Figure 48;
Figure 54 is the fragmentary sectional view of semiconductor device with trap isolation structure of our research;
Figure 55 is the fragmentary sectional view of semiconductor device with trap isolation structure of our research;
Figure 56 is the illustrative curve chart of the impurities concentration distribution of the various piece among explanation Figure 55;
Figure 57 is the partial section of Semiconductor substrate of problem of the semiconductor device of our research of explanation; With
Figure 58 is the partial section of Semiconductor substrate of problem of the semiconductor device of our research of explanation.
Embodiment
To link embodiments of the invention with reference to the accompanying drawings and describe the present invention's (run through the accompanying drawing of all explanation embodiment, have the part of identical function with identical tag mark mark, and omit the description of its repetition) in detail.
(embodiment 1)
Fig. 1 is the sectional view of major part of the semiconductor device of explanation technological thought of the present invention; Fig. 2 (a), Fig. 2 (b) and Fig. 3 are the illustrative curve charts of the impurities concentration distribution of the various piece among Fig. 1; Fig. 4 and 6 is sectional views of major part in the method for the semiconductor device of shop drawings 1; Fig. 5 and 7 is the top plan views of mask layout of method that are used for the semiconductor device of shop drawings 1; Fig. 8 to 14 is sectional views of major part in the method for the semiconductor device of making one embodiment of the invention; Figure 15 is the circuit diagram of the memory cell in the semiconductor device in Figure 14; Figure 54 and 55 is the partial cross section figure of semiconductor device with trap isolation structure of our research; And Figure 56 is the illustrative curve chart of the impurities concentration distribution of the various piece among explanation Figure 55.
The trap isolation technology of our research at first, here will be described before describing embodiment 1.
Figure 54 explanation has the trap isolation structure of two traps of our research.Make Semiconductor substrate 50 with p type monocrystalline, and form an insulation film 51 in the element isolation zone in the first type surface of Semiconductor substrate 50.
N type Impurity Distribution extends to the position, deep so forms dark n trap 52 from the first type surface of Semiconductor substrate 50.N type Impurity Distribution extends to the position more shallow than dark n trap from the master meter of Semiconductor substrate 50 and therefore forms shallow n trap 53.
Form the first type surface extension of common p trap 54 and p type Impurity Distribution in insulation film 51 area surrounded on the scene from Semiconductor substrate 50.In addition, form p trap 55 so that dark n trap 52 encirclements of (its bottom and lateral parts) quilt around it.
Here when the running of routine, though Semiconductor substrate 50 is to be in earthing potential therefore common p trap 54 not to be applied voltage except that 0V, but p trap 55 is surrounded by dark n trap 52 and isolates with Semiconductor substrate 50 electricity, so can supply with the desirable voltage that is different from the voltage that Semiconductor substrate 50 is applied, for example negative voltage to p trap 55.
Here will describe by using two masks to form the process problem of above-mentioned well structure.Figure 55 represents the cross section structure of trap, is formed with n trap 57a and 57b and than n trap 57a and shallow p trap 58a and the 58b of 57b in cross section structure in p N-type semiconductor N substrate 56.
(bottom and lateral parts) surrounded by n trap 57b around the shallow p trap 58b, so shallow p trap 58b and Semiconductor substrate 56 electricity are isolated.Therefore, can supply with the desirable voltage that is different from the voltage that Semiconductor substrate 56 is applied, for example negative voltage to p trap 58b.
In this process,, realize above-mentioned well structure with two masks by the doping step that forms n trap 57a and 57b being adopted same mask and the doping step that forms p trap 58a and 58b being adopted same mask.
Here, Figure 56 (a) and Figure 56 (b) illustrate that in Figure 55 position A, B and C are in the impurities concentration distribution on the depth direction.Shown in Figure 56 (a), with boron (B) CONCENTRATION DISTRIBUTION at n-MISFET place, position in p trap 58a relatively, A place, position phosphorus (p) CONCENTRATION DISTRIBUTION in n trap 57a must be low and must be high at the position dark from the surface near surface.
This is because form p trap 58a and 58b with shared mask when the doping step, therefore must optimization at position B and C two place's Impurity Distribution.Shown in Figure 56 (b), more precisely, the p trap in the zone at position C place, must in the near surface place, form the differentiated effective p trap 58b of boron concentration and phosphorus concentration, and must consider to form effective n trap 57b at the position dark from the surface.
Yet we have found that this process involves following problem.First problem is that p trap 58b forms by the compensation between boron and the phosphorus, so p type impurity valid density generally is reduced to half of least concentration of p trap 58a.Therefore, the characteristics of transistor that on the Semiconductor substrate first type surface, forms, specifically, threshold voltage is widely different.Need another mask to adjust threshold voltage.
The total impurities concentration that second problem is the p trap increases to about three times up to the impurity concentration of common p trap 58 (a).Therefore, the carrier mobility step-down in the first type surface zone of Semiconductor substrate, so that the characteristics of transistor that on first type surface, forms, specifically, leakage current is step-down correspondingly.
Owing to reduce the factor of high-performance transistor quality, so along with transistor becomes more little, along with trap concentration becomes high more, described so far these two problems become more and more serious.
So the present invention proposes can adjust the well structure of the impurity concentration of each trap under the situation that does not increase mask count.Fig. 1 is the sectional view of the major part in the Semiconductor substrate 1 of explanation the technology of the present invention thought.
Make Semiconductor substrate 1 and in the first type surface of Semiconductor substrate 1, form ditch type element isolation zone 2 with for example boron-doping p type silicon (si) monocrystalline.By being embedded in, isolated film 2b forms isolated area 2 among the ditch 2a that constitutes in the first type surface of Semiconductor substrate 1.Above-mentioned isolated film 2b for example is a silicon oxide film, so that top surface planeization is consequently flushed substantially with the first type surface of Semiconductor substrate 1.
Between these interregional in abutting connection with between the isolated area 2, be formed with trap isolated area (first trap forms the district), second trap forms the district and the 4th trap forms the district.
In the trap isolated area, shallow p trap (the second conduction type shallow well district) 4a that be provided with embedding n trap (the embedding trap of first conduction type) 3a, above n trap 3a, forms and serve as shallow n trap (the first conduction type shallow well district) 5a that surrounds the periphery formation of shallow p trap 4a with self-aligned manner.
By the ion implantation of making the ion injecting mask with shared mask various impurity are mixed Semiconductor substrate 1, form these embedding n trap 3a and shallow p trap 4a.Therefore, form embedding n trap 3a and shallow p trap 4a at position, same plane with in same plane domain.
Here, embedding n trap 3a is mixed with for example phosphorus, though this is not specifically limited.In addition, shallow p trap 4a is mixed with for example boron.
Make shallow n trap 5a form the frontier district between cross-over connection shallow p trap 4a lateral parts and the Semiconductor substrate 1 and extend from the bottom of isolated area 2 and overlapping with embedding n trap 3a.Therefore, shallow p trap 4a is surrounded along its circumference by shallow n trap 5a and embedding n trap 3a fully, so shallow p trap 4a and Semiconductor substrate 1 electricity are isolated.Above-mentioned shallow n trap 5a is mixed with for example phosphorus.
In second trap forms the district, be provided with at embedding n trap (the embedding well region of first conduction type) 3b that forms from the dark position of the first type surface of Semiconductor substrate 1 and shallow p trap (the second conduction type shallow well district) 4b that above embedding n trap 3b, forms with self-aligned manner.
By the ion implantation of making the ion injecting mask with common mask various impurity are mixed Semiconductor substrate 1 and form these embedding n trap 3b and shallow p trap 4b.Therefore, in position, same plane and same plane domain, form embedding n trap 3b and shallow p trap 4b.
Ion implantation by making the ion injecting mask with same mask is mixed Semiconductor substrate 1 simultaneously to the impurity of the embedding n trap 3a in the impurity of embedding n trap 3b and the above-mentioned trap isolated area.Therefore, the impurity of embedding n trap 3b and the Impurity Distribution on depth direction (for example, the degree of depth and zone) are the same with the Impurity Distribution on depth direction (for example, the degree of depth and zone) with the impurity of embedding n trap 3a.
Ion implantation by making the ion injecting mask with same mask is mixed Semiconductor substrate 1 simultaneously to the impurity of the shallow p trap 4a in the impurity of shallow p trap 4b and the above-mentioned trap isolated area.Therefore, the impurity of shallow p trap 4b and the Impurity Distribution on depth direction (for example, the degree of depth and zone) are the same with the Impurity Distribution on depth direction (for example, the degree of depth and zone) with the impurity of shallow p trap 4a.
Form in the district at the 4th trap, be formed with shallow n trap (the first conduction type shallow well district) 5b.Ion implantation by making the ion injecting mask with same mask is mixed Semiconductor substrate 1 to the impurity of the shallow n trap 5a in the impurity of above-mentioned shallow n trap 5b and the above-mentioned trap isolated area.Therefore, the impurity of shallow n trap 5b and the Impurity Distribution on depth direction (for example, the degree of depth and zone) are the same with the Impurity Distribution on depth direction (for example degree of depth and zone) with the impurity of shallow n trap 5a.
Explanation is in the impurities concentration distribution at the position of Fig. 1 D, E, F and G place in Fig. 2 (a) and Fig. 2 (b).
Make the impurities concentration distribution that forms the shallow n trap 5b in the district (at position D place) at the 4th trap extend to the predetermined degree of depth so that the transistorized optimized performance of the p-that above first type surface, forms from the first type surface of Semiconductor substrate 1.
The impurity depth distribution that second trap forms district (at position E place) be included among near the first type surface the shallow p trap 4b distribution and away from the distribution among the embedding n trap 3b in the Semiconductor substrate of first type surface.The distribution of semiconductor first type surface vicinity is adjusted to the concentration that makes the transistorized optimized performance of n-that on first type surface, forms.Make distribution in Semiconductor substrate adjust to electric best isolation of semiconductor substrate and at the shallow p trap of first type surface vicinity.
Is the same in the impurities concentration distribution in the trap isolated area (at position F place) fully with the above-mentioned impurities concentration distribution that second trap forms in the district (at position E place), so omit the description to it.Yet, as shown in Figure 1, form shallow n trap 5a in the periphery of the shallow p trap in the trap isolated area, therefore the impurities concentration distribution at position G place is different with the impurity concentration that second trap forms in the district in this zone.The impurities concentration distribution at the position G place of Fig. 3 explanation in Fig. 1.
In above-mentioned zone, though shallow p trap 4a and n trap 5a form and overlap each other, but the impurities concentration distribution that makes n trap 5a is adjusted to the impurities concentration distribution dark (as shown in figs. 1 and 3) than p well region 4a, therefore as the isolation of the n type among Fig. 3 spacing is illustrated, can make the electricity isolation fully mutually of shallow p trap 4a and Semiconductor substrate 1.
In whole embodiment, this structure example is as putting on predetermined voltage the trap of each trap or appointment by the wiring that forms on the Semiconductor substrate first type surface.
Then, consult the method that Fig. 4 to 7 will describe the semiconductor device in the shop drawings 1.
Fig. 4 is the sectional view of major part in the method for the semiconductor device of shop drawings 1.At first, in the first type surface of Semiconductor substrate 1, make raceway groove 2, then the insulation film of just on the first type surface of Semiconductor substrate 1, forming by silica with CVD (chemical vapor deposition) method or method like that deposition.Make insulation film polishing and complanation and insulation film is only imbedded in the raceway groove 2a with CMP (chemico-mechanical polishing) method or method like that and form element isolation zone 2 thus to form isolated film.
Then, make Semiconductor substrate 1 oxidation, form the insulation film of forming by silicon oxide film or film like that on the zone of exposing in the first type surface of Semiconductor substrate 1.After this, formation exposes trap isolated area (first trap forms the district) and second trap formation district to the open air and covers other regional photoresist figures (first mask) on the first type surface of Semiconductor substrate 1.At this moment, the open end of photoresist figure 7a partly is placed on the isolated area 2.
Fig. 5 represents an example of the plane figure of above-mentioned photoresist figure 7a.Two rectangular graph 7a1 of expression and 7a2 in Fig. 5.Rectangular graph 7a1 is the mask graph that is used for forming trap on trap isolated area side, and its inside is the exposed areas of Semiconductor substrate 1.Rectangular graph 7a2 is used for forming the mask graph that forms trap on district's side at second trap, and its inside is the exposed areas of Semiconductor substrate 1.
After this, as shown in Figure 4, make mask with photoresist figure 7a phosphonium ion is mixed Semiconductor substrate 1 so that can form embedding n trap 3a and 3b at the dark position of Semiconductor substrate 1.At this time, can make embedding n trap 3a and the impurity concentration of 3b adjust to optimum value.
After this, for example carry out the boron ion as mask and inject, therefore can on embedding n trap 3a and 3b, form shallow p trap 4a and 4b in self aligned mode with same photoresist figure 7a.The acceleration energy that is given for the ion injection that forms p trap 4a and 4b is lower than the acceleration energy of the ion injection that is used to form n trap 3a and 3b.Say exactly, form than the dark embedding n well region 3a of the peak region of the impurity concentration among shallow p well region 4a and the 4b and the peak region of the impurity concentration among the 3b.
At this time, according to technological thought of the present invention, not according to adjusting the impurity concentration of shallow p trap 4a and 4b but can irrespectively make the impurity concentration of shallow p trap 4a and 4b adjust to best impurity concentration with embedding n trap with the difference of the impurity concentration of embedding n trap 3a and 3b.As described in inciting somebody to action hereinafter, the above makes the characteristic of improving the element that forms in shallow p trap 4a and the 4b is to realize, for example improves threshold voltage so or leakage current is to realize if element is MOSFET (Metal-oxide-semicondutor FET) or MISFET (metal-insulator semiconductor FET).
Because photoresist figure that need not be discrete but form embedding n trap 3a and 3b and shallow p trap 4a and 4b with single photoresist figure is so can make manufacturing cost far below the manufacturing cost in the situation that forms each trap with discrete photoresist figure.Can reduce because foreign substance causes the incidence of defective, to improve the rate of finished products and the reliability of semiconductor device.
At this moment, can turn the order of the doping of the doping of embedding n trap 3a and 3b and shallow p trap 4a and 4b around.
Next step, as shown in Figure 6, remove photoresist figure 7a shown in Figure 4, just on the first type surface of Semiconductor substrate 1, form the external zones (triple-well forms the district) make in the trap isolated area and the 4th trap then and form to distinguish and expose to the open air and cover other regional photoresist figures (second mask) 7b.At this moment, the open end of photoresist figure 7b part also is placed on the isolated area 2.
Fig. 7 represents an example of the plane figure of above-mentioned photoresist figure 7b.Fig. 7 represents picture frame diagram shape 7b1 and rectangular graph 7b2.In the drawings, dot rectangular graph 7a1 among the photoresist figure 7b and 7a2 so that clearly illustrate that position relation (seeing Figure 4 and 5) with photoresist figure 7a.
Picture frame figure 7b1 is the figure that is used for forming the n trap on the trap isolated area, and the exposed areas of its internal representation Semiconductor substrate 1.Rectangular graph 7b2 is used to form the figure that the 4th trap forms the n trap in the district, and its inside is the exposed areas of Semiconductor substrate 1.
After this, as shown in Figure 6, make mask with photoresist figure 7b phosphonium ion is mixed Semiconductor substrate 1 to form shallow n trap 5a and 5b.At this time, can make the impurity concentration of trap 5a and 5b adjust to optimum value.This just makes the characteristic of improving the element that forms among the shallow n trap 5b realize, if element is MISFET, for example then improves threshold voltage or leakage current and can realize.
Therefore, according to technological thought of the present invention, can irrespectively make the impurity concentration among shallow p trap 4a and 4b and the shallow n trap 5b adjust to optimum value each other, therefore make the electrical characteristics optimization of the element that forms in the zone in shallow p trap 4a and 4b and shallow n trap 5b all the time, when above-mentioned element is MISFET, make for example threshold voltage or leakage current optimization all the time.
In addition, owing to only can form embedding n trap 3a and 3b, shallow p trap 4a and 4b and shallow n trap 5a and 5b with two photoresist figure 7a and 7b, so compare with the process of making the photoresist figure for each trap, can reduce the number that forms photoresist figure step.Specifically, it is possible saving a succession of step for the formation compulsory whirl coating of photoresist figure, exposure, development, cleaning and an oven dry photoresist.This can realize with regard to making the cost that reduces the manufacturing semiconductor device.In addition, owing to can reduce, can realize so improve the rate of finished products of semiconductor device because foreign substance causes the incidence of defective.
Mix so that the shallow n trap 5a of at least a portion in embedding n trap 3a vicinity (promptly, Fig. 6 than lower part) impurity concentration be higher than part impurity concentration among the shallow p trap 4a of (that is, lower corner part of the Fig. 6) in embedding n trap 3a vicinity and in the vicinity of shallow n trap 5a.
Therefore, in the doping step situation that forms shallow well 5a,, also can keep the pn knot among the shallow well 5a even the position of shallow well 5a, is left shallow p trap 4a along the face displacement.Thereby this just makes the puncture voltage that guarantees shallow well 5a guarantee that shallow well district 4a in the trap isolated area and the electric isolating power between the Semiconductor substrate 1 can realize.
Therefore, can provide work semiconductor device very reliably to cause low price to the strong influence of semi-conductor industry.
Then, will consult Fig. 8 to 14 here and describe the situation that technological thought of the present invention is used for DRAM (dynamic random access memory).
Fig. 8 is illustrated in that memory cell in the method for making DRAM forms district (first trap forms the district and triple-well forms the district) and peripheral circuit forms district's (second trap forms the district and the formation of the 4th trap is distinguished).
At first, has the weld zone film 8 that silicon oxide film that thickness is 20nm or film like that are formed by having on the first type surface that resistivity for example is the Semiconductor substrate 1 formed of the p type silicon single crystal of 10 Ω .cm with thermal oxidation method or method like that growth.After this, on weld zone film 8, has the insulation film 9 that silicon nitride film that thickness is 200nm or film like that are formed with chemical vapor deposition method (CVD method) deposition.
Then, formation makes element isolation zone expose the also photoresist figure in cladding element district to the open air on insulation film 9.After this, make etching mask, make insulation film 9 below constitute figure with dry ecthing method with the photoresist figure.
After this, the figure of insulation film 9 forms the raceway groove 2a that is used as isolated area as etching mask in Semiconductor substrate 1 with dry ecthing method.After this, be that 50KeV and dosage are 5 * 10 at for example acceleration energy 12/ cm 2Condition under mix in raceway groove 2a surface in the Semiconductor substrate 1 so that the element isolation zone in Semiconductor substrate 1 with boron ion or suchlike ion and to form raceway groove blocking layer 10.
Secondly, as shown in Figure 9, deposit thickness for example is the silicon oxide film of 400nm or film like that on the first type surface of the Semiconductor substrate 1 that comprises raceway groove 2a surface.After this, make silicon oxide film be planarized to the degree that only is retained among the raceway groove 2a, so that in raceway groove 2a, can form isolated film 2b and element isolated area 2 with CMP method or method like that.Above-mentioned element isolation zone 2 delimited the active area boundary.
Then, as shown in figure 10, for example memory cell forms the district and peripheral circuit forms photoresist figure (first mask) 7c that thickness is about 5 μ m that has that the district exposes and cover other zones to the open air to form the zone that makes n raceway groove MISFEF place on the first type surface of Semiconductor substrate 1.
Figure 11 represents a kind of example of the plane figure of above-mentioned photoresist figure 7c.Figure 11 represents two rectangular graph 7c1 and 7c2.Rectangular graph 7c1 is used for forming the mask graph that district's side forms trap in memory cell, and the exposed areas of its internal representation Semiconductor substrate 1.On the other hand, rectangular graph 7c2 is used for forming the mask graph that forms trap on the edge of distinguishing side at peripheral circuit, and its inside is the exposed areas of Semiconductor substrate 1.
After this, as shown in figure 10, making mask with photoresist figure 7c is 2 at acceleration energy, and 500KeV and dosage are 1 * 10 13/ cm 2Following phosphonium ion of condition or ion like that mix Semiconductor substrate 1 up to dark position so that form embedding n trap 3a and 3b.At this time, can make the impurity concentration of embedding n trap 3a and 3b adjust to optimum value.
After this, make mask three kinds of conditions with same photoresist figure 7c: for example, acceleration energy is that 500KeV and dosage are 7 * 10 12/ cm 2Condition, acceleration energy be that 150KeV and dosage are 5 * 10 12/ cm 2Condition and acceleration energy be that 50KeV and dosage are 1 * 10 12/ cm 2Condition under carry out the boron ion and inject so that on embedding n trap 3a and 3b, form shallow p trap 4a and 4b with self-aligned manner.Therefore, be used to form acceleration energy that the ion of shallow p trap 4a and 4b injects and be lower than the acceleration energy that the ion that is used to form embedding n trap 3a and 3b injects.Say that exactly the impurity concentration peak region of embedding n trap 3a and 3b is darker than the impurity concentration peak region of shallow p trap 4a and 4b.
At this time, in the present embodiment can be not according to the difference of the impurity concentration of embedding n trap 3a and 3b but irrespectively the impurity concentration of shallow p trap 4a and 4b is adjusted to optimum value with embedding n trap 3a and 3b.This just makes the characteristic of the element that improvement forms in shallow p trap 4a and 4b be to realize, if element is MISFET, for example then improving threshold voltage or leakage current is to realize.
In addition, because photoresist figure that need not be discrete but form embedding n trap 3a and 3b and shallow p trap 4a and 4b, so can make manufacturing cost far below with the manufacturing cost in the situation of discrete photoresist figure formation trap with single photoresist figure 7c.Can reduce because foreign substance causes the incidence of defective to improve rate of finished products and the reliability of DRAM.
Can make impurity be incorporated into the order that embedding n trap 3a and 3b and impurity be incorporated into shallow p trap 4a and 4b here, turns around.
Secondly, remove photoresist figure 7c shown in Figure 10, then just as shown in figure 12, on the first type surface of Semiconductor substrate 1, form and make memory cell form peripheral region in the district and peripheral circuit to form p raceway groove MISFET in the district and form the district and expose and cover photoresist figure (second mask) 7d that other regional thickness are about 3 μ m to the open air.
Figure 10 represents the plane figure of above-mentioned photoresist figure 7d.Figure 13 represents picture frame diagram shape 7d1 and rectangle 7d2., in Figure 13, dot rectangular graph 7c1 and 7c2 among the photoresist figure 7c here, so that clearly illustrate that and the position of photoresist figure 7c relation (should consult) along with Figure 10 and 11.
Picture frame figure 7d1 is used for forming the figure that district's side forms the n trap in memory cell, and the exposed areas of its internal representation Semiconductor substrate 1.Rectangular graph 7d2 is used to form the figure that peripheral circuit forms the n trap in the district, and its inside is the exposed areas of Semiconductor substrate 1.
After this, as shown in figure 12, make mask three kinds of conditions with photoresist figure 7d: acceleration energy is 1, and 100KeV and dosage are 1.5 * 10 13/ cm 2Condition, acceleration energy be that 500KeV and dosage are 3 * 10 12/ cm 2Condition and acceleration energy be that 180KeV and dosage are 5 * 10 11/ cm 2Following phosphonium ion of condition or ion like that mix Semiconductor substrate 1 to form shallow n trap 5a and 5b.After this, be that 70KeV and dosage are 2 * 10 at acceleration energy 12/ cm 2Following boron difluoride (BF of condition 2) ion mix Semiconductor substrate 1.Carry out BF for the threshold voltage that is adjusted at the P-MISFET that forms in the peripheral circuit formation district here, 2Ion inject.
At this time, can make n trap 5a and 5b adjust to best impurity concentration in the present embodiment.This just makes the characteristic of the element that improvement forms in shallow n trap 5b realize, if with the example of MISFET as element, for example improves threshold voltage or leakage current so and can realize.
Therefore, can make the impurity concentration among shallow p trap 4a and 4b and the shallow n trap 5b irrespectively adjust to optimum value each other in the present embodiment, therefore make the electrical characteristics optimization of the element that forms in the zone in shallow p trap 4a and 4b and shallow n trap 5b all the time, when above-mentioned element is MOSFET, make for example threshold voltage and the leakage current optimization of element all the time.
In addition, owing to can only form embedding n trap 3a and 3b, shallow p trap 4a and 4b and shallow n trap 5a and 5b with two photoresist figure 7a and 7b, so compare with the process of making the photoresist figure for each trap, can reduce the number that forms photoresist figure step.Specifically, it is possible reducing a succession of step for the formation compulsory whirl coating of photoresist figure, exposure, development, cleaning and an oven dry photoresist.This can realize with regard to making the cost that reduces manufacturing DRAM.In addition, owing to can reduce, can realize so improve the rate of finished products of DRAM because foreign substance causes the incidence of defective.
Therefore, can provide work DRAM very reliably to cause low price to the strong influence of semi-conductor industry.
Then, as shown in figure 14, form the memory cell that forms selection MISFET Q in the district in memory cell, and in peripheral circuit formation district, form P-MISFET Q pWith n-MISFET Q n
Select the memory cell of MISFETQ mainly to be included in a pair of n N-type semiconductor N zone 11a and the 11b that p trap 4a upward forms disconnected from each otherly; Form grid insulating film 11i on the active area in Semiconductor substrate 1; With the grid 11g that on grid insulating film 11i, forms.At this moment, select MISFET Q memory cell to have threshold voltage or the threshold voltage like that of 1v.
Form the shallow p trap of selecting MISFET Q memory cell and surrounded by embedding n trap 3a and shallow n trap 5a fully, therefore, shallow p trap 4a and Semiconductor substrate 1 electricity are isolated.Therefore, can supply with the voltage different to shallow p trap 4a with the voltage that puts on Semiconductor substrate 1.At this moment, the lead-in wire that is connected by the upper surface with shallow p trap 4a is supplied with the voltage that puts on shallow p trap 4a.Make shallow n trap or trap like that have similar structure at trap power supply face.
Semiconductor regions 11a and 11b be form to select in the MISFET Q memory cell source/leakage and with arsenic (As) doped regions.Between these semiconductor regions 11a and 11b and just below gate electrode 11g, form the channel region of selecting MISFET Q memory cell.
For example depositing by the order by down narration, n type low-resistance polysilicon membrane, titanium nitride (TiN) film and tungsten (W) film form the gate electrode 11g. that is made up of a part of word line WL
Titanium nitride membrane among the gate electrode 11g is to prevent in order directly to be deposited on the low-resistance polysilicon membrane at W film because the heat treatment in the manufacture method generates the barrier metal film of silicide on contact portion.
The barrier metal film should not be limited to titanium nitride, but conversion in many ways.For example, tungsten nitride also is a kind of excellent materials that is used for the barrier metal film.
W film in the gate electrode 11g that selects MISFET Q memory cell has the effect that reduces lead resistance, thus the sheet resistance of gate electrode 11g (that is word line WL) can be lowered to about 2 to 2.5 Ω/ Such numerical value approximately be tungsten silicide 15 to 10 Ω 2cm resistivity 1/10.
Therefore, the access speed of improvement DRAM is possible.In addition, owing to can increase along the number of the memory cell of a word line WL arrangement, so can reduce the shared area of whole storage area, thereby reduce semiconductor chip size.
In the present embodiment, can arrange for example 512 memory cell along word line WL.Above-mentioned arrangement is compared with the situation that can arrange 256 memory cell along word line WL, can make semiconductor chip size reduce about 6%.In the semiconductor chip of further miniaturization grade, reach make semiconductor chip size reduce 10% or more effect be possible.Therefore, can increase the quantity of the semiconductor chip of each method manufacturing, impel the cost of DRAM to descend.If do not change semiconductor chip size, then improve the element integrated level and can realize.
Grid insulating film 11i for example is a silicon oxide film, and its thickness for example can be adjusted to about 7nm.Grid insulating film 11i also can be oxynitrides (a SiON film).Therefore, can eliminate the interface state in the grid insulating film, and can reduce the electron trap in the grid insulating film, therefore can improve the hot carrier resistance among the grid insulating film 11i.This improves as thin as a wafer with regard to making that the reliability of grid insulating film can realize.
The method of grid insulating film 11i oxynitriding is comprised makes the grid insulating film 11i that is formed by oxidation at NH 3Or NO 2Atmosphere in stand high-temperature heat treatment so that nitrogen is incorporated the method for grid insulating film 11i into; On the face of the grid insulating film 11i that silica or oxide like that are formed, form the method for nitride film; With the nitrogen ion mix the Semiconductor substrate first type surface and then oxidation be doped the method for the Semiconductor substrate that forms grid insulating film 11i; Perhaps mix the polysilicon membrane that forms gate electrode with the nitrogen ion and then the polysilicon membrane that is doped of heat treatment so that nitrogen retention in the method for grid insulating film.
P-MISFET Q in peripheral circuit formation district pMainly be included in a pair of p N-type semiconductor N zone 12a and the 12b that form on the Semiconductor substrate 1 disconnected from each otherly; The grid insulating film 12i that on Semiconductor substrate 1, forms; With the gate electrode 12g that on grid insulating film 12i, forms.At this moment, above-mentioned MISFET Q pHave the 0.3V threshold voltage or such as threshold voltage.
Semiconductor regions 12a and 12b form p-MISFET Q pThe zone of source/leakage.Between these semiconductor regions 12a and 12b and just below gate electrode 12g, form P-MISFET Q pChannel region.
Make these semiconductor regions 12a and 12b have LDD (lightly doped drain) structure.More precisely, in semiconductor regions 12a and 12b, can form low concentration region (p with lower impurity concentration -) and have high concentration region (p than higher impurity concentration +).In the middle of the above-mentioned zone, on edge, channel region outside, form high concentration region forming low concentration region on the channel region edge.In other words, between channel region and high concentration region, form low concentration region.
The gate electrode 11g (word line WL) that gate electrode 12g and memory cell form in the district is configured figure simultaneously and for example forms gate electrode 12g by order deposition n type low-resistance polysilicon membrane, titanium nitride membrane and W film by down narration.
Grid insulating film 11i in grid insulating film 12i and the memory cell formation district forms simultaneously and for example is made up of silica for example has the grid insulating film 12i that thickness is about 7nm.Grid insulating film 12i also can be oxynitrides film (that is a SiON film).This makes and improves as thin as a wafer the hot carrier resistance of grid insulating film and can realize.
On the other hand, in forming the shallow p trap 4b that distinguishes in (right-hand side in Figure 14), peripheral circuit forms n-MISFET Qn.Just forming n-MISFET Q here, n Shallow p trap 4b below form embedding n trap 3b, yet the lower lateral parts that is not surrounded by n N-type semiconductor N zone among the shallow p trap 4b is to be electrically connected with Semiconductor substrate 1, thereby can not hindered to shallow p trap 4b service voltage from Semiconductor substrate 1.
N-MISFET Qn mainly is included in p trap 4b and goes up a pair of semiconductor regions 13a and the 13b that forms disconnected from each otherly; The grid insulating film 13i that on Semiconductor substrate 1, forms; With the gate electrode 13g that on grid insulating film 13i, forms.At this moment, above-mentioned MISFET Qn has threshold voltage or the threshold voltage like that of 0.3V.
Semiconductor regions 13a and 13b are the zones that forms source/leakage of n-MISFET Qn.Between these semiconductor regions 13a and 13b and just below gate electrode 13g, form the channel region of n-MISFET Qn.
Make these semiconductor regions 13a and 13b have LDD (lightly doped drain) structure.More precisely, in semiconductor regions 13a and 13b, can form low concentration region with lower impurity concentration and the high concentration region that has than higher impurity concentration.In the middle of the above-mentioned zone, form high concentration region on the edge, channel region outside forming low concentration region on the channel region edge.In other words, between channel region and high concentration region, form low concentration region.
Form and form gate electrode 13g simultaneously when gate electrode 11g (word line WL) in the district and peripheral circuit form gate electrode 12g in the district and forming memory cell for example by order deposition n type low-resistance polysilicon membrane, titanium nitride membrane and W film formation gate electrode 13g by down narration.
Form and form grid insulating film 13i simultaneously when grid insulating film 11i in the district and peripheral circuit form grid insulating film 12i in the district and grid insulating film 13i is for example silicon oxide film with for example about 7nm thickness forming memory cell.Grid insulating film 13i also can be oxide/nitride film (a SiON film).As mentioned above, this makes and improves as thin as a wafer the hot carrier resistance of grid insulating film and can realize.
On the first type surface of Semiconductor substrate 1, deposit the layer insulation film 14a that silicon oxide film for example or film like that are formed, so that cover and select MISFETQ memory cell P-MISFETQ pWith n-MISFET Qn.Form the connecting hole 15a that exposes Semiconductor substrate 1 first type surface with photoetching process and dry ecthing method in the predetermined locations of layer insulation film 14a.
Then, electric conductor membrane is imbedded memory cell and form connecting hole 15a in the district to form plug 16.After this, make ground floor lead-in wire 17a and bit line BL by make electric conductor membrane constitute figure with photoetching process and dry ecthing method then by the electric conductor membrane that on layer insulation film 14a, deposits the alloy composition of aluminium, silicon and copper for example.
After this, on layer insulation film 14a, deposit layer insulation film 14b that silica for example forms so that cover ground floor lead-in wire 17a and bit line BL.After this, in predetermined position, form the connecting hole 15b of the upper surface that exposes plug 16 with photoetching process and dry ecthing method.
Secondly, electric conductor membrane is imbedded memory cell and form connecting hole 15b in the district to form plug 18.After this, formation for example is the capacitor 19 that convex is used for storage on layer insulation film 14b.As shown in figure 15, above-mentioned capacitor 19 comprises storage utmost point 19a, the plate 19b that forms separately on capacitor insulation film that forms on the surface of storage utmost point 19a and the surface at capacitor insulation film, and with selecting MISFET Q memory cell to constitute memory cell.
Then, the layer insulation film 14c that deposition for example is made up of silicon oxide film on layer insulation film 14b is with covering capacitor 19.After this, in layer insulation film 14c and 14b, form the connecting hole 15c that exposes ground floor lead-in wire 17a.
After this, deposition for example constitutes electric conductor membrane to form the go between figure of 17b of the second layer with photoetching process and dry ecthing method then by the electric conductor membrane of the alloy composition of aluminium, silicon and copper on layer insulation film 14c.
After this step, by forming the subsequent step manufacturing DRAM that goes between and form the routine of surface protective film.In the semiconductor device of making like this, when semiconductor device is in operating state, supplies with 0V for example and form shallow p trap in the district to memory cell and for example-1 supply with-3.3V to Semiconductor substrate 1.
Can reach following effect according to the embodiment 1 that describes till now: (1) can make the impurity concentration of shallow p trap 4a and 4b and shallow n trap 5b irrespectively adjust to optimum value each other respectively, and the electrical characteristics that therefore can make the MISFET Q, the Qn that form and Qp all the time in the zone of trap 4a and 4b are threshold voltage and leakage current optimization for example.(2) only just can form embedding n trap 3a and 3b, shallow p trap 4a and 4b and shallow n trap 5a and 5b with two photoresist figure 7a and 7b, therefore compare with the process that forms the photoresist figure for each trap, can reduce the number that forms photoresist figure step.(3), can realize so reduce the cost of making semiconductor device owing to effect (2).(4) because effect (2) so can reduce the incidence that causes defective owing to foreign substance because form the decreased number of photoresist figure step, therefore can improve the rate of finished products of semiconductor device.(5) increase than the impurity concentration height of the shallow p trap 4a of at least a portion (following turning) by the impurity concentration that makes the shallow n trap of at least a portion (lower part) 5b, depart from along face even when forming the doping step of shallow well 5b, form the position of shallow well 5b, also can guarantee the puncture voltage of shallow well 5b.Therefore, guarantee that the electric isolating power between the shallow well 4a and Semiconductor substrate 1 is possible in the trap isolated area.(6) owing to effect (3), (4) and (5), so provide semiconductor device to realize with high workload reliability with low price.
(embodiment 2)
Figure 16 is the top plan view of the semiconductor chip of the expression semiconductor device that forms another embodiment of the present invention, and Figure 17 to 30 is the sectional views that are illustrated in major part in the method for the semiconductor device that is used for making Figure 16.
With adopting the present invention to be applied to have gate length for example is that the situation of CMIS (complementary mis) logical circuit of 0.25 μ m is described embodiment 2.
Figure 16 is the top plan view of the semiconductor chip IC that is made up of the semiconductor device of embodiment 2 of expression.Above-mentioned semiconductor chip IC is little chip and the rectangular shape that belongs to p type silicon single crystal.On the first type surface of semiconductor chip IC, be equipped with voltage for example be higher than 1.8V 3.3V supply voltage driving element region D 1 and with the region D 2 of the supply voltage driving element of 1.8V.
In installing zone D1, input/output circuitry I/O, many logic components, phase-locked loop PLL and clock pulse generator CPG are installed.In installing zone D2, be provided with logical circuit 20E.
To consult Figure 17 to 23 here and describe semiconductor device among the embodiment 2.
At first, the same with aforesaid embodiment, as shown in figure 17,, form isolated area 2 then with thermal oxidation method or the method like that weld zone film 8 of on the first type surface of Semiconductor substrate 1, growing.Then, on the first type surface of Semiconductor substrate 1, form photoresist figure (first mask) 7e that makes formation expose and cover the about 5 μ m thickness of having of other zones to the open air by for example 3.3V-N zone of the n-MISFET of 3.3V supply voltage driving (first trap forms the district and second trap forms the district).
Then, in order to form embedding n trap 3a and 3b, be 2 at acceleration energy, 300KeV and dosage are 1 * 10 13/ cm 2Condition under do phosphonium ion or ion like that are mixed the mask that Semiconductor substrate 1 arrives dark position with photoresist figure 7e.At this time, can make the impurity concentration of embedding n trap 3a and 3b adjust to optimum value.
After this, in order to form shallow p trap 4a and 4b with self-aligned manner on embedding n trap 3a and 3b, three kinds of conditions: acceleration energy is that 450KeV and dosage are 1 * 10 13/ cm 2Condition, acceleration energy be that 200KeV and dosage are 3 * 10 12/ cm 2Condition and acceleration energy be that 50KeV and dosage are 1.2 * 10 12/ cm 2Condition under mix the mask of boron ion with same photoresist figure 7e.
At this time, in the present embodiment, not according to the difference of the impurity concentration of embedding n trap 3a and 3b but irrespectively can make the impurity concentration of shallow p trap 4a and 4b adjust to optimum value with embedding n trap 3a and 3b.These electrical characteristics that just make the MISFET that improvement forms in shallow p trap 4a and 4b for example threshold voltage and leakage current can realize.
In addition, owing to not using discrete photoresist figure to be to use single photoresist figure 7e to form embedding n trap 3a and 3b and shallow p trap 4a and 4b, so can make manufacturing cost far below the manufacturing cost in the situation that forms each trap with discrete photoresist figure.Can reduce because foreign substance causes the incidence of defective to improve the rate of finished products and the reliability of semiconductor device.
At this moment, impurity mixes the order that embedding n trap 3a and 3b and impurity mix shallow p trap 4a and 4b and can turn around.
Secondly, as shown in figure 18, remove photoresist figure 7e shown in Figure 17, just on the first type surface of Semiconductor substrate 1, form the peripheral 3.3V-N zone (triple-well forms the district and the formation of the 4th trap is distinguished) in the zone of exposing the n-MISFET that is positioned at the driving of formation 3.3V supply voltage to the open air then and cover photoresist figure (second mask) 7f that other regional thickness that form at that time are about 3 μ m on the first type surface of Semiconductor substrate 1.
Then, three kinds of conditions: acceleration energy is 1, and 300KeV and dosage are 1 * 10 13/ cm 2Condition, acceleration energy be that 600KeV and dosage are 5 * 10 12/ cm 2Condition and acceleration energy be that 200KeV and dosage are 2 * 10 12/ cm 2Condition under, make mask with photoresist figure 7f phosphonium ion or ion like that mixed Semiconductor substrate 1 so that form shallow n trap 5c and 5d.After this, be that 70KeV and dosage are 2 * 10 at acceleration energy 12/ cm 2Following boron difluoride (BF of condition 2) mix Semiconductor substrate 1.Here, be to carry out BF for the threshold voltage of adjusting the P-MISFET that the 3.3V supply voltage drives 2Ion inject.
Form these shallow N trap 5c and 5d so that surround the side of shallow p trap 4a and its lower part is overlapping with the upper part of embedding n trap and be electrically connected with embedding n trap 3a.Say that exactly shallow p trap 4a is by shallow n trap 5c and 5d and embedding n trap 3a surrounds and isolate with Semiconductor substrate 1 electricity.This just makes supplies with to shallow p trap 4a that to be different from the voltage that is applied to the voltage on the Semiconductor substrate 1 be can be practicable.Supply with 3.3V to shallow n trap, and make the voltage of Semiconductor substrate 1 be set in 0V (GND).
Therefore, in present embodiment 2, can make the impurity concentration of shallow p trap 4a and 4b and shallow n trap 5d irrespectively adjust to optimum value each other, thereby make electrical characteristics for example threshold voltage and the leakage current optimization of the MISFETQ of formation in the zone of shallow p trap 4a and 4b and shallow n trap 5d all the time.
Only just can form embedding n trap 3a and 3b, shallow p trap 4a and 4b and shallow n trap 5c and 5d with two photoresist figure 7e and 7f, therefore be the process of each trap formation photoresist figure number of specific energy minimizing formation photoresist figure step mutually.Therefore, with the same among the embodiment 1, reduce the cost of making semiconductor device and the rate of finished products that improves semiconductor device and can realize.
Mix so that at least a portion near embedding n trap 3a (promptly, press close to the turning below among Figure 18) shallow n trap 5c and the impurity concentration of the 5d impurity concentration that is higher than a near part shallow p trap 4a at (that is the following turning among Figure 18) embedding n trap 3a and shallow n trap 5c and 5d.Therefore, described the same with relevant embodiment 1, guarantee that shallow well 4a in the trap isolated area and the electric isolating power between the Semiconductor substrate 1 are possible.
Therefore, can provide the semiconductor device that has CMIS (complementary mis) logical circuit very reliably with the price that semi-conductor industry is caused strong influence.
Secondly, as shown in figure 19, remove the photoresist figure 7f shown in Figure 18, just on the first type surface of Semiconductor substrate 1, form exterior domain and the n trap power supply supply area of the P-MISFET that exposes the driving of 1.8V supply voltage to the open air then and cover photoresist figure (the 3rd mask) 7g that thickness is about 1.5 μ m that has in other zones.
Then, 7g makes mask with the photoresist figure, is that 400KeV and dosage are 1.5 * 10 at acceleration energy 13/ cm 2Condition and acceleration energy be that 200KeV and dosage are 1 * 10 12/ cm 2Following phosphonium ion of condition or ion like that mix Semiconductor substrate 1 so that form by for there being the 1.8V of 1.8V to organize shallow n trap 5e and 5f.In addition, be that 70KeV and dosage are 2 * 10 at acceleration energy 12/ cm 2Following boron difluoride (BF of condition 2) ion or ion like that mix Semiconductor substrate 1.
At this time, in present embodiment 2, can make the impurity concentration of n trap 5e and 5f irrespectively adjust to optimum value each other.These electrical characteristics that just make the MISFET that improvement forms in shallow n trap 5e and 5f for example threshold voltage and leakage current are possible all the time.
After this, as shown in figure 20, remove photoresist figure 7g shown in Figure 19, just forming the photoresist figure 7h that thickness is about 1.5 μ m that has expose the zone that forms the n-MISFET that 1.8V supply voltage for example drives and predetermined isolated area to the open air and to cover other zones of on the first type surface of Semiconductor substrate 1, forming at that time on the first type surface of Semiconductor substrate 1 then.
Secondly, making mask with photoresist figure 7h (the 4th mask), is that 200KeV and dosage are 1.5 * 10 at acceleration energy 13/ cm 2Condition and acceleration energy be that 60KeV and dosage are 1 * 10 12/ cm 2Following boron ion of condition or ion like that mix Semiconductor substrate 1 so that form 1.8V and organize shallow p trap 4c and raceway groove blocking layer 10a.After this, be that 40KeV and dosage are 3 * 10 at acceleration energy 12/ cm 2Following boron difluoride (BF of condition 2) ion or ion like that mix Semiconductor substrate 1.
At this time, in present embodiment 2, can make the impurity concentration of p trap 4c adjust to optimum value individually.These electrical characteristics that just make the MISFET that improvement forms in shallow p trap 4c for example threshold voltage and leakage current are possible all the time.
In addition, in present embodiment 2, form n trap 4c and raceway groove blocking layer 10a simultaneously with single photoresist figure 7h.Therefore, can make manufacturing cost far below by the manufacturing cost in the situation that forms n trap 4c and raceway groove blocking layer 10a with discrete photoresist figure.Can reduce because foreign substance causes the incidence of defective to improve the cost rate and the reliability of CMOS logical circuit.
Above-mentioned shallow n trap 4c surrounds at shallow n trap 5e that is formed on this side on its side and 5f.Here, so because shallow in some cases n trap 5d and shallow n trap 5e are close to mutually and above-mentioned raceway groove blocking layer 10a is set isolates with the electricity that the guarantor levies between two shallow n trap 5d and the 5e.
Then, as shown in figure 20, remove photoresist 7h, just remove weld zone film 8 then from the first type surface of Semiconductor substrate 1.After this, as shown in figure 21, make the Semiconductor substrate thermal oxidation have the grid insulating film 21i that thickness is about 8nm on the first type surface of Semiconductor substrate 1, to form.Here, above-mentioned grid insulating film 21i plays the grid insulating film effect of the MISFET that the 3.3V supply voltage drives.
After this, on the first type surface of Semiconductor substrate 1, form and expose the zone that forms the MISFET that the 1.8V supply voltage drives to the open air and be used for to the zone of trap power supply and cover photoresist figure (the 5th mask) 7i that thickness is about 2.5 μ m that has in other zones.Form photoresist figure 7i so that its open end partly is placed on the isolated area 2 here.
Secondly, organize embedding n trap 3c in order to form 1.8V, 7i makes mask with photoresist, is 1 at acceleration energy, and 000KeV and dosage are 1 * 10 13/ cm 2Following phosphonium ion of condition or ion like that mix Semiconductor substrate 1.
Just below shallow n trap 5e and 5f and shallow p trap 4c, form above-mentioned embedding n trap 3c so that all extend in formation 1.8V and organize on the zone of MISFET.The upper part of embedding n trap 3c is overlapping with the lower part of n trap 5e and 5f and be electrically connected with shallow n trap 5e and 5f.Therefore, shallow p trap 4c is by shallow n trap 5e and 5f and embedding n trap 3c encirclement, and therefore shallow p trap 4c and Semiconductor substrate 1 electricity are isolated.This just makes that it is possible supplying with the voltage different with the voltage that is applied to Semiconductor substrate 1 to shallow p trap 4c.
Then, as shown in figure 22, during trap forms, be used as the etching mask of wet etching Semiconductor substrate 1, from the zone that forms the MISFET that the 1.8V supply voltage drives, remove grid insulating film 21i thus as the photoresist figure 7i of mask.
At this moment, in present embodiment 2, the photoresist figure 7i that is used to form trap makes etching mask, removes grid insulating film 21i.Therefore, can make manufacturing cost far below the manufacturing cost in the situation that adopts discrete photoresist figure for these methods.Can reduce because foreign substance causes the incidence of defective to improve the rate of finished products and the reliability of semiconductor device.
After this, as shown in figure 23, remove photoresist figure 7i, just in the zone of the MISFET that forms the driving of 1.8V supply voltage, form the grid insulating film 22i that forms by silicon oxide film or film like that then.Yet, because driving voltage is low in the above-mentioned zone, so grid insulating film 22i has for example thickness of about 5nm, and thinner than above-mentioned grid insulating film 21i.
Secondly, the predetermined electric conductor membrane of deposition on Semiconductor substrate 1 just constitutes figure so that form gate electrode 12g and 13g on grid insulating film 21i and 22i with photoetching process and dry ecthing method then.
Then, be formed for P-MISFETQ with conventional ion implantation or method like that pWith n-MISFET Q nSource/ leakage semiconductor regions 12a, 12b, 13a and 13b and be used for semiconductor regions 23a and the 23b that trap electric power is supplied with.Here, semiconductor regions 23a and 23b that trap electric power is supplied with are mixed with for example phosphorus, are higher than the impurity concentration of shallow n trap 5d and 5e on impurity concentration.
Therefore, form P-MISFET Q pWith N-MISFET Q nAt this moment, just forming the n-MISFET Q that the 3.3V supply voltage drives nAnd surrounded by n N-type semiconductor N zone but below the shallow p trap 4b that its lateral parts is electrically connected with Semiconductor substrate 1 the embedding n trap 3b of formation, so not overslaugh of embedding n trap 3b from Semiconductor substrate 1 to shallow p trap 4b service voltage.
In the middle of these MISFET, the P-MISFET Q that the 3.3V supply voltage drives pWith n-MISFET Q nBe formed in the circuit in the installing zone D1 among Figure 16, and the P-MISFET Q that the 1.8V supply voltage drives pWith n-MISFET Q nBe formed in the circuit in the installing zone D2 among Figure 16.
After this, on the first type surface of Semiconductor substrate 1, form the layer insulation film 14a that forms by silica or oxide like that and consequently cover P-MISFET Q pAnd n-MISFETQ nAfter this, form the connecting hole 15a of the first type surface that exposes Semiconductor substrate 1 with photoetching process and the dry ecthing method predetermined position in layer insulation film 14a.
Then, be deposited over layer insulation film 14a by for example electric conductor membrane of the alloy composition of aluminium, silicon and copper and upward and then just constitute the figure that forms ground floor lead-in wire 7a with photoetching process and dry ecthing method.
After this; the layer insulation film 14b that deposition is made up of for example silica on layer insulation film 14a so that cover ground floor lead-in wire 17a, just for example the wiring step by routine, surface protective film formation step or the like are made the semiconductor device with CMOS logical circuit then.
Present embodiment 2 can also reach following effect except that the effect of aforesaid embodiment 1.(1)-1 only putting on the 3.3V that is added with 3.3V to the reverse biased of-3.3V organizes the 3.3V that shallow n trap 5c and 5d surround and organizes shallow p trap 4a, and-0.5 to-1.8V reverse biased puts on the 1.8V that is added with 1.8V specially and organizes the 1.8V that shallow n trap 5e and 5f surround and organize shallow p trap 4C, therefore can control threshold voltage and the leakage current of the MISFET that corresponding supply voltage drives satisfactorily.Here, reverse biased can be used to reduce leakage current in auxiliary mode.In action, p trap 4a and 4c are applied for example 0V, MISFET just can working at high speed.(2) the photoresist figure 7i that is used to form trap by use makes mask, removes grid insulating film 21i.Therefore, manufacturing cost is lower than and is the manufacturing cost in the situation of the discrete photoresist figure of these method employings.(3) the photoresist figure 7i that is used to form trap by use makes mask and removes grid insulating film 21i.Therefore, can reduce because foreign substance causes the reliability of the incidence of defective with the rate of finished products of raising semiconductor device.
(embodiment 3)
Figure 24 is the top plan view of the semiconductor chip of the expression semiconductor device that forms another embodiment of the present invention, and Figure 25 to 31 is the sectional views that are illustrated in major part in the method for making the semiconductor device among Figure 24.
With adopting the present invention to be applied to 64 megabit DRAM being housed on the common semiconductor chip and having gate length is that the situation of semiconductor device of the high speed logic circuit of 0.25 μ m is described embodiment 3.
Figure 24 is the top plan view of the semiconductor chip IC of the semiconductor device among the expression embodiment 3.Little chip by the p type silicon single crystal of rectangular shape is formed above-mentioned semiconductor chip IC.In the first type surface of semiconductor chip IC, arrange region D 1 and have the region D 2 of the installation elements that drives with the 1.8V supply voltage with the installation elements that drives with for example high 2.5V supply voltage than 1.8V supply voltage.
In installing zone D1, input/output circuitry I/O, many logic components 20A, DRAM, phase-locked loop PLL and clock pulse generator CPG are installed.In installing zone D2, logical circuit 20E is installed.
To method that make semiconductor device according to embodiment 3 be described with reference to Figure 25 to 31 here.
At first, the same with aforesaid embodiment 1 and 2, as shown in figure 25,, just form isolated area 2 then with thermal oxidation method or the method like that weld zone film 8 of on the first type surface of Semiconductor substrate 1, growing.Then, on the first type surface of Semiconductor substrate 1, make zone exposure that makes the n-MISFET that forms for example 2.5V supply voltage driving and the photoresist figure 7e that thickness is about 5 μ m that has that covers other zones.
After this, in order to form embedding n trap 3a and 3b, 7e makes mask with photoresist, with aforesaid embodiment 2 in dosage and inject the same dosage of energy and inject energy phosphonium ion or ion like that are mixed Semiconductor substrate 1 to its dark position.At this time, can make the impurity concentration of embedding n trap 3a and 3b adjust to optimum value.
Secondly,, make mask with same photoresist figure 7e in order on embedding n trap 3a and 3b, to form shallow p trap 4a and 4b with self-aligned manner, with aforesaid embodiment 1 in dosage and inject the same dosage of energy and the injection energy mixes the boron ion.
At this time, in present embodiment 3, so owing to aforesaid embodiment 1 and 2 in same reason can improve the electrical characteristics of the MISFET that in shallow p trap 4a and 4b, forms, for example threshold voltage and leakage current.In addition, because picture in embodiment 1 and 2, forms many traps by using photoresist figure 7e, can realize so reduce rate of finished products and the reliability of manufacturing cost and raising semiconductor device significantly.
Secondly, remove the photoresist figure 7e shown in Figure 25, then just as shown in Figure 28, on the first type surface of Semiconductor substrate 1, form with embodiment 2 in the same photoresist figure 7f.In order to form shallow n trap 5c and 5d, 7f makes mask with the photoresist figure, with embodiment 2 in dosage and inject the same dosage of energy and inject energy and carry out ion and inject.After this, with embodiment 2 in dosage and inject the same dosage of energy and inject energy and carry out boron difluoride (BF 2) ion inject.Here, be to carry out BF for the threshold voltage of adjusting the P-MISFET that the 2.5V supply voltage drives 2Ion inject.Supply with 2.5V to these shallow n trap 5c and 5d.
Thereby, can cause strong influence thus with low-cost production 64 megabit DRAM with to have gate length be that the high speed logic circuit of 0.25 μ m is assemblied in the semiconductor device with high reliability in the common semiconductor chip to semi-conductor industry.
Secondly, as shown in figure 27, as relevant embodiment 2 is described, remove the photoresist figure 7f as shown in Figure 26, just form then and have the photoresist figure 7g that thickness is about 2.5 μ m.
Then, in order to form shallow n trap 5e and 5f, 7f makes mask with the photoresist figure, with embodiment 2 in dosage and inject the same dosage of energy and inject the ion that energy carries out phosphorus or element like that and inject.After this, with embodiment 2 in dosage and inject the same dosage of energy and inject energy and carry out boron difluoride (BF 2) or the ion of fluoride like that inject.Therefore, the same with embodiment 2, the electrical characteristics that can make the MIS.FET that forms all the time in shallow n trap 5e and 5f are threshold voltage and leakage current optimization for example.
After this, the same with enforcement 2 as shown in figure 28, remove the photoresist figure 7g shown in Figure 27, just formation has the photoresist figure 7h that thickness is about 2.5 μ m then.
Secondly, the same with embodiment 2 in order to form raceway groove blocking layer 10a and shallow well 4c, 7h makes mask with the photoresist figure, and the ion that carries out boron or element like that injects.After this, with embodiment 2 in dosage and inject the same dosage of energy and inject energy and carry out boron difluoride (BF 2) ion inject.
At this time, in present embodiment 3, owing to embodiment 2 in the same reason the electrical characteristics for example threshold voltage and the leakage current optimization that can make the MISFET that in the zone of shallow p trap 4c, forms all the time.In addition, owing to, can realize so reduce the rate of finished products and the reliability of manufacturing cost and raising semiconductor device significantly by using single photoresist figure 7h to form n trap and raceway groove blocking layer 10a simultaneously.
Then, the same with aforesaid embodiment 2, remove photoresist figure 7h shown in Figure 28, remove weld zone film 8 then.As shown in figure 29, thermal oxidation Semiconductor substrate 1 has the grid insulating film 21i that thickness is about 7nm to form on the first type surface of Semiconductor substrate 1.Here, above-mentioned grid insulating film 21i is a grid insulating film of using the MISFET of 2.5V supply voltage driving.
After this, on the first type surface of Semiconductor substrate 1, form and the same photoresist figure 7i of photoresist figure 7i among the embodiment 2.After this, in order to form embedding trap 3c, 7i makes mask with the photoresist figure, with embodiment 2 in dosage and inject the same dosage of energy and inject the ion that energy carries out phosphorus or element like that and inject.
Then, the same with embodiment 2, as shown in figure 30,7i carries out wet etch process as mask with the photoresist figure, the grid insulating film 21i in the zone of the MISFET that removal formation 1.8V supply voltage drives.Therefore, in the present embodiment, the rate of finished products and the reliability that reduce manufacturing cost and raising semiconductor device significantly can realize.
After this, as shown in figure 31, remove photoresist figure 7i, then just in the zone that forms the MISFET that the 1.8V supply voltage drives formation have a thin grid insulating film 22i that thickness is about 2.5nm by what silica or oxide like that were formed.After this, the same with among the embodiment 2 forms gate electrode 12g and 13g on grid insulating film 21i and 22i.
Then, be formed for P-MISFETQ with conventional ion implantation or method like that pWith n-MISFET Q nSource/ leakage semiconductor regions 11a, 11b, 12a, 12b, 13a and 13b and be used for semiconductor regions 23a and the 23b that trap electric power is supplied with, form memory cell, the p-MISFET Q that selects MISFET Q thus pWith n-MISFET Q n
At this moment, just forming the n-MISFET Q that the 2.5V supply voltage drives nAnd do not surrounded but the embedding n trap 3b of formation below the shallow p trap 4b that its lateral parts is electrically connected with Semiconductor substrate 1 by n N-type semiconductor N zone, thus not overslaugh of embedding n trap 3b from Semiconductor substrate 1 to shallow p trap 4b service voltage.
In the middle of these MISFET, memory cell, the P-MISFET Q of the selection MISFET Q that the 2.5V supply voltage drives pWith n-MISFET Q nThe P-MISFET Q that forming circuit in the installing zone D1 in Figure 24 and 1.8V supply voltage drive pWith n-MISFET Q nForming circuit in the installing zone D2 in Figure 24.
Except that the effect of aforesaid embodiment 1, present embodiment 3 can reach following effect.(1)-1 only putting on the 2.5V that is added with 2.5V to the reverse biased of-3.3V organizes the 2.5V that shallow n trap 5c and 5d surround and organizes shallow p trap 4a, and-0.5 to-1.8V reverse biased puts on the 1.8V that is added with 1.8V specially and organizes the 1.8V group shallow well 4c that shallow n trap 5e and 5f surround, and therefore can control threshold voltage and the leakage current of the MISFET that corresponding supply voltage drives satisfactorily.In addition, the connection of the memory cell among the DRAM (ON) electric current have fully with common 2.5V group p trap in form the same numerical value of numerical value in the situation of memory cell.Here, reverse biased can be used for reducing leakage current in auxiliary mode.In running, p trap 4a and 4c are applied for example 0V, MISFET just can working at high speed.(2) the photoresist figure 7i that is used to form trap by use makes mask, removes grid insulating film 21i.Therefore, manufacturing cost is lower than and is the manufacturing cost in the situation of the discrete photoresist figure of these method employings.(3) the photoresist figure 7i that is used to form trap by use makes mask, removes grid insulating film 21i.Therefore can reduce because foreign substance causes the incidence of defective to improve the rate of finished products and the reliability of semiconductor device.
(embodiment 4)
Figure 32 is the top plan view of the semiconductor chip of the expression semiconductor device that forms another embodiment of the present invention; Figure 33 to 39 is the sectional views that are illustrated in major part in the method for making semiconductor device; And Figure 40 is the circuit diagram of the memory cell in fast storage (EEPROM).
To adopt the present invention to be applied in 8 megabit fast storages (EEPROM) are housed on the common semiconductor chip and have gate length is that the situation of semiconductor device of the high speed logic circuit of 0.25 μ m is described embodiment 4.
Figure 32 is the top plan view of the semiconductor device IC of expression embodiment 4.The little chip of p type silicon single crystal by rectangular shape is formed above-mentioned semiconductor chip IC.In the first type surface of semiconductor chip IC, arrange region D 1 and have the region D 2 of the installation elements of 1.8V supply voltage driving with installation elements of using the driven higher than 1.8V supply voltage.
In installing zone D1, input/output circuitry I/O, many logic components 20A, fast storage (EEPROM), phase-locked loop PLL and clock pulse generator CPG are installed.In installing zone D2, logical circuit 20E is installed.
The method of the semiconductor device of making embodiment 4 will be described here with reference to Figure 33 to 40.
At first, the same with aforesaid embodiment 1,2 and 3, as shown in figure 33,, just form isolated area 2 then with thermal oxidation method or the method like that weld zone film 8 of on the first type surface of Semiconductor substrate 1, growing.Then, on the first type surface of Semiconductor substrate 1, make the photoresist figure 7e that thickness is about 5 μ m that has that other zones are exposed and covered in the zone that makes memory cell formation district and form the n-MISFET that drives with for example 10V supply voltage to the open air.
After this, in order to form embedding n trap 3a and the 3b in the high-breakdown-voltage group, 7e makes mask with the photoresist figure, with aforesaid embodiment 2 and 3 in dosage and inject the same dosage of energy and inject energy phosphonium ion or ion like that are mixed Semiconductor substrate 1 to its dark position.At this time, can make the impurity concentration of embedding n trap 3a and 3b adjust to optimum value.
Secondly, in order on embedding n trap 3a and 3b, to form shallow p trap 4a and 4b in the high-breakdown-voltage group with self-aligned manner, with same photoresist figure 7e do mask with aforesaid embodiment 2 and 3 in dosage and inject the same dosage of energy and the injection energy mixes the boron ion.
At this time, in the present embodiment, can make shallow p trap 4a in the high-breakdown-voltage group and the impurity concentration of 4b and embedding n trap 3a and the 3b in the high-breakdown-voltage group irrespectively adjust to optimum value.Therefore, owing to the same, so the electrical characteristics that can improve the MISFET that forms in shallow p trap 4a in the high-breakdown-voltage group and the 4b for example threshold voltage and leakage current with reason in aforesaid embodiment 1 and 2.In addition, owing to form embedding n trap 3a and 3b and shallow p trap 4a and 4b, can realize so reduce the rate of finished products and the reliability of manufacturing cost and raising semiconductor device significantly with photoresist figure 7e.
Secondly, as shown in figure 34, remove the photoresist figure 7e shown in Figure 33, just form to make then and form the photoresist figure 7f that thickness is about 4 μ m that has that the outer peripheral areas in the zone of the MISFET of 10V supply voltage driving for example exposes to the open air at the first type surface of Semiconductor substrate 1.
Then, in order on Semiconductor substrate 1, to form shallow well 5c and the 5d in the high-breakdown-voltage group, 7f makes mask with the photoresist figure, with embodiment 2 and 3 in dosage and inject the same dosage of energy and inject the ion that energy carries out phosphorus or element like that and inject.After this, with embodiment 2 and 3 in dosage and inject the same dosage of energy and inject energy and carry out boron difluoride (BF 2) ion inject.Here, be to carry out BF for the threshold voltage of adjusting the P-MISFET that the 10V supply voltage drives 2Ion inject.
In present embodiment 4, the electrical characteristics that also can make the MISFET of formation in the zone in shallow p trap 4a and 4b and shallow n trap 5a and 5b all the time owing to the reason the same with reason in aforesaid embodiment 2 and 3 are threshold voltage and leakage current optimization for example.
In addition, owing to only just can form embedding n trap 3a and 3b, shallow p trap 4a and 4b and shallow n trap 5c and 5d, therefore can reduce the number that forms photoresist figure step with two photoresist figure 7e and 7f.This just makes that reducing the cost of making semiconductor device and the rate of finished products that improves semiconductor device can realize.
In present embodiment 4, owing to the same with reason in aforesaid embodiment 2 and 3, thus also can guarantee the puncture voltage of shallow well 5a, thereby guarantee the electric isolation performance of shallow well 4a and Semiconductor substrate 1 in the trap isolated area.
Secondly, as shown in figure 35, remove the photoresist figure 7f shown in Figure 34, then just formation and the same photoresist figure 7g of photoresist figure 7g among the embodiment 2 on the first type surface of Semiconductor substrate 1.Then, in order in Semiconductor substrate 1, to form for there being the 1.8V of 1.8V to organize shallow n trap 5e and 5f, 7g makes mask with the photoresist figure, with embodiment 2 and 3 in dosage and inject the same dosage of energy and inject the ion that energy carries out phosphorus or element like that and inject.After this, with embodiment 2 and 3 in dosage and inject the same dosage of energy and inject energy and carry out for example boron difluoride (BF 2) or the ion of compound like that inject.
After this, as shown in figure 36, remove the photoresist figure 7g shown in Figure 35, then just formation and the same photoresist figure 7h of photoresist figure 7h among the embodiment 2 on the first type surface of Semiconductor substrate 1.Then, in order to form raceway groove blocked-off region 10a and shallow n trap 4c, with photoresist figure 7h do mask with embodiment 2 and 3 in dosage and inject the same dosage of energy and inject energy carry out boron or so the ion of dvielement inject.After this, with embodiment 2 and 3 in dosage and inject the same dosage of energy and inject energy and carry out for example boron difluoride (BF 2) ion inject.
Then, as shown in figure 37, remove the photoresist figure 7h among Figure 36.After this, remove weld zone film 8, have the grid insulating film 24i that thickness for example is about 20nm with regard to the above-mentioned Semiconductor substrate 1 of thermal oxidation on the first type surface of Semiconductor substrate 1, to form then from the first type surface of Semiconductor substrate 1.Here, above-mentioned grid insulating film 24i is the grid insulating film of the MISFET of the 10V supply voltage driving in the high-breakdown-voltage group.
After this, on the first type surface of Semiconductor substrate 1, form and the same photoresist figure 7i of photoresist figure 7i among the aforesaid embodiment 2.After this, in order to form embedding trap 3c, with embodiment 2 and 3 in dosage and inject the same dosage of energy and inject the ion that energy carries out phosphorus or element like that and inject.
Then, as shown in figure 38, during trap forms, make mask, make Semiconductor substrate 1 stand wet etch process, from forming the zone removal grid insulating film 24i of the MISFET that the 1.8V supply voltage drives with photoresist figure 7i.So in present embodiment 4, the rate of finished products and the reliability that reduce manufacturing cost and raising semiconductor device significantly can realize.
After this, as shown in figure 39,, remove photoresist figure 7i, just on the zone of the MISFET that forms the driving of 1.8V supply voltage, form the thin grid insulating film 22i that thickness is about 5nm then as in embodiment 2 and 3.
Secondly, etch away grid insulating film 24i, just on memory cell areas, form the tunnel insulation film 25i that the thickness of being made up of silica or compound like that is about 11nm then from memory cell areas.
Then, the predetermined electric conductor membrane of deposition on Semiconductor substrate 1, just make predetermined electric conductor membrane constitute figure then, on tunnel insulation film 25i, form floating gate electrodes 25fg thus on grid insulating film 21i and 22i, to form gate electrode 12g and 13g with photoetching process and dry ecthing method.
Then, be formed on semiconductor regions 25a and 25b in the memory cell areas, be used for P-MISFET Q with conventional ion implantation or method like that pWith n-MISFET Q nSource/ leakage semiconductor regions 12a, 12b, 13a and 13b and be used for semiconductor regions 23a and the 23b that trap electric power is supplied with.
After this, after forming interlayer film 25Li on the floating gate electrodes 25fg, just on interlayer film 25Li, form control grid electrode 25cg to form the memory cell MC of the double-deck grid structure in the fast storage (EEPROM).The circuit diagram of representing above-mentioned memory cell MC here, among Figure 40.Above-mentioned memory cell MC is set at the intersection point vicinity of bit line BL and word line WL.Memory cell MC is electrically connected with word line WL at its control grid electrode place, is electrically connected with bit line BL at its place, drain region and is electrically connected with source line SL at its place, source region.
Therefore, form memory cell p-MISFET Q pWith n-MISFET Q nForming the n-MISFET Q that the 10V supply voltage drives here, n Shallow p trap 4b below form embedding n trap 3b, and shallow p trap 4b is electrically connected with Semiconductor substrate 1, so can be from Semiconductor substrate 1 to shallow p trap 4b service voltage.
In the middle of these MISFET, memory cell, P-MISFETQ that the 10V supply voltage drives pWith n-MISFET Q nBe formed in the circuit in the installing zone D1 among Figure 32, and the P-MISFET Q that drives with the 1.8V supply voltage pWith n-MISFET Q nBe formed in the circuit in the installing zone D2 among Figure 32.
After this, the wiring step of the routine of the semiconductor device by fast storage (EEPROM) is housed and surface protective film form step and make semiconductor device.
Present embodiment 4 can reach following effect except that the effect of aforesaid embodiment 1.(1)-reverse biased of 13V only puts on the shallow p trap 4a in the high-breakdown-voltage group of being surrounded by the shallow n trap 5c in the high-breakdown-voltage group and 5d, and-reverse biased of 1.8V puts on the shallow p trap 4c in the 1.8V group of being surrounded by the shallow n trap 5e in the 1.8V group and 5f specially.Yet, problem is not taking place aspect the trap puncture voltage.(2) the photoresist figure 7i that is used to form trap by use makes mask, removes grid insulating film 21i.Therefore, cost of manufacture is lower than the manufacturing cost in the situation of the discrete photoresist figure of these method employings.(3) the photoresist figure 7i that is used to form trap by use makes mask, removes grid insulating film 21i.Therefore, can reduce because foreign substance causes the incidence of defective to improve the rate of finished products and the reliability of semiconductor device.
(embodiment 5)
Figure 41 to 45 is sectional views of major part in the method for the semiconductor device of making one embodiment of the invention; Figure 46 is the top plan view of element assembling in the cache in the semiconductor device of present embodiment 5; Figure 47 is the circuit diagram of the memory cell in the cache; And Figure 57 and 58 is partial sections of the Semiconductor substrate of the problem in our semiconductor device found of explanation.
Before describing present embodiment 5, problem in the trap formation process that we have found will be described at this.
As our research, Figure 57 schematically is illustrated in the partial section in the method for making semiconductor device.Form Semiconductor substrate 60 with p type silicon single crystal, and form ditch type isolated area 61 in the element isolation zone in the first type surface of Semiconductor substrate 60.Above-mentioned formation should not be confined to ditch type isolated area 61 and can be the isolated area that an insulation film is formed.
In Figure 57, the left-hand side of isolated area 61 is the zones that form P-MISFET, and the right-hand side of isolated area 61 is the zones that form n-MISFET.
In such a case, in order to form p trap and n trap in the zone that in Semiconductor substrate 1, forms N-MISFET by application the present invention, as relevant aforesaid embodiment 1 or the like is described, on the first type surface of Semiconductor substrate 60, make the zone that forms n-MISFET is exposed to the open air and cover the photoresist figure 62 in the zone that forms P-MISFET.At this moment the end portion that shows photoresist figure 62 in Figure 57 is given prominence to above isolated area 61.
Here, shown in Figure 57, the side surface of photoresist Figure 62 end portion can be (the anti-taper among Figure 57) of taper.For example when the position of impurity being mixed Semiconductor substrate 60 was dark more, photoresist figure 62 was just done thickly more, and it is remarkable especially that above-mentioned state just becomes.
Shown in Figure 58, when under above-mentioned situation, making mask the impurity that is used to form trap mixed Semiconductor substrate 60 with photoresist figure 62, form in the district at n-MISFET, the Impurity Distribution on the end portion below isolated area 61 sides between p trap 63 and embedding n trap 64 is not inconsistent with the impurity concentration of being scheduled to, but the Impurity Distribution of the end portion of embedding n trap 64 is lifted to the main surface side of Semiconductor substrate 60.Therefore, bad puncture voltage or the problem of sewing appear in trap in research process.Along with the isolated area that is equivalent to frontier district between P-MISFET and the n-MISFET narrows down, above-mentioned problem is even more serious.
In addition, when photoresist figure 62 is made into normal taper, similar problem appears.More precisely, mix the impurity that forms p trap 63 and be incorporated into the zone that forms P-MISFET yet, the Impurity Distribution that therefore is formed on the zone of the P-MISFET below the isolated area 61 is not the Impurity Distribution of being scheduled to.
So in present embodiment 5, in above-mentioned situation, form and not only make n-MISFET form the district but also make P-MISFET form the photoresist figure that the district exposes to the open air, therefore the end portion of photoresist figure can not be set in place in n-MISFET and form on the isolated area 2 of borderline region between district and the p-MISFET formation district, the foreign ion that forms p trap and embedding n trap is injected into n-MISFET forms two zones in district and P-MISFET formation district, after this, n type impurity is injected into p-MISFET and forms the district, thereby form the n trap.
A kind of special example here will be described.With adopting the present invention for example to be applied to have the situation of the semiconductor device of cache technological thought of the present invention is described.
Figure 41 is the sectional view of major part in the method for the semiconductor device of making present embodiment 5.Cache zone (first trap form district) is arranged, do not need embedding trap and the zone (3.3V-NB) that drives with the 3.3V supply voltage and the embedding trap of needs and form zone (formation of first trap is distinguished) what Figure 41 saw there with the 1.8/3.3VMISFET that 1.8V or 3.3V supply voltage drive.
At first, the same with aforesaid embodiment 1 to 4, for example be about the weld zone film 8 of 20nm so that form isolated area 2 with thermal oxidation method or the method like that thickness of forming by silica or oxide like that of on the first type surface of Semiconductor substrate 1, growing.
In the cache zone in isolated area, the width that forms the isolated area 2 of boundary between district and the n-MISFET formation district at P-MISFET is that 0.9 μ m is to 1.5 μ m, its width is narrower than the width of other regional isolated areas 2, therefore can reduce and get over the area that cache memory occupies.
Then, as shown in figure 42, on the first type surface of Semiconductor substrate 1, form and make cache zone (first trap forms the district) and n-MISFET form zone (second trap forms and distinguishes) to expose and cover photoresist figure (first mask) 7j that other regional thickness are about 5 μ m to the open air.
At this moment in present embodiment 5, the P-MISFET in the cache forms the district and is not covered by photoresist figure 7j but expose to the open air.Reason is if the P-MISFET that the end portion of photoresist figure 7i is placed cover the cache district forms the position that district and n-MISFET form the P-MISFET on the isolated area in the frontier district between the district, because it is as indicated above, isolated area is narrow, so can cause above-mentioned problem under different situations.
After this, in order to form embedding n trap 3a and 3b, making mask with photoresist figure 7i is 2 at acceleration energy, and 300KeV and dosage are 1 * 10 13/ cm 2Following phosphonium ion of condition or ion like that mix Semiconductor substrate 1 to its position, deep.At this time, can make the impurity concentration of embedding n trap 3a and 3b adjust to optimum value.
Secondly, in order to form shallow p trap 4a and 4b with self-aligned manner on embedding n trap 3a and 3b, make mask three kinds of conditions with same photoresist figure 7j: acceleration energy is that 450KeV and dosage are 1 * 10 13/ cm 2Condition, acceleration energy be that 200KeV and dosage are 3 * 10 12/ cm 2Condition and acceleration energy be that 50KeV and dosage are 1.2 * 10 12/ cm 2Condition under carry out boron ion inject.
At this time, in present embodiment 5, can make the impurity concentration of shallow p trap 4a and 4b and embedding n trap 3a and 3b irrespectively adjust to optimum value.Therefore, the electrical characteristics of improving the MISFET form in shallow p trap 4a and 4b for example can realize by threshold voltage and leakage current.
In addition, photoresist figure that need not be discrete but form embedding n trap 3a and 3b and shallow p trap 4a and 4b with single photoresist figure 7j.Therefore, rate of finished products and the reliability that reduces manufacturing cost and raising semiconductor device significantly can realize.
In above-mentioned step, p trap 4a also forms in the district at the P-MISFET of cache and forms.To avoid above-mentioned impurities concentration distribution problem takes place in n-MISFET forms shallow p trap 4a in the district be possible with regard to making for this.
Secondly, remove photoresist figure 7j shown in Figure 42.As shown in figure 43, the external zones (triple-well forms the district) of the shallow p trap 4a in the zone that on the first type surface of Semiconductor substrate 1, make external zones (triple-well forms the district) that the P-MISFET make in the cache forms the shallow p trap 4a in district, the cache, needs embedding trap and need the P-MISFET in the zone of embedding trap to form photoresist figure (second mask) 7k that thickness is about 4 μ m that has that district (the 4th trap forms and distinguishes) exposes and cover other zones to the open air.
Then, in order to form shallow n trap 5g to 5k in Semiconductor substrate 1, make mask two kinds of conditions with photoresist figure 7k: for example acceleration energy is that 360KeV and dosage are 1.3 * 10 13/ cm 2Condition and acceleration energy be that 70KeV and dosage are 1 * 10 12/ cm 2Following phosphonium ion of condition or ion like that mix above-mentioned Semiconductor substrate 1, be that 70KeV and dosage are 2 * 10 at acceleration energy then 12/ cm 2Condition under with boron difluoride (BF 2) mix.At this moment, use BF 2Carrying out ion injects in order that adjust the threshold voltage of P-MISFET.
Make ion implantation energy at this time adjust to the intensity that the bottom that makes shallow well 5k reaches embedding n trap 3a.Therefore, in the cache district, can form shallow n trap 5k and shallow p trap 4a.In addition, above-mentioned shallow p trap 4a is by shallow n trap 5k and 5g and embedding n trap 3a encirclement, so that shallow p trap 4a and Semiconductor substrate 1 electricity isolation.Therefore, can supply with the voltage different to above-mentioned shallow p trap 4a with the voltage that puts on Semiconductor substrate 1.For example supply with 0 to 1.8V voltage to above-mentioned shallow p trap 4a.
Embedding n trap 3a and shallow n trap 5g and shallow n trap 5k electricity are isolated, and therefore can supply with different voltage to them.Specifically, can supply with about 3.3V and supply with the voltage that for example is about 1.8V to shallow n trap 5k to embedding n trap 3a and shallow n trap 5g.
It is overlapping with the upper part of embedding n trap 3a and be electrically connected with embedding n trap 3a to form the lower part of above-mentioned shallow n trap 5g above-mentioned shallow n trap 5g with the side that is enclosed in the shallow p trap 4a in the cache district.The width of shallow n trap 5g for example is about 4 μ m, though this is not particularly limited.
Form that these shallow n trap 5i and 5j form the side of the shallow p trap 4a in the district with the MISFET that surround to need embedding trap and the lower face of shallow n trap 5i and 5j and overlapping with the upper part of embedding n trap 3a and be electrically connected with embedding n trap 3a.Say that exactly above-mentioned shallow p trap 4a is by shallow n trap 5i and 5j and embedding n trap 3a surrounds and isolate with Semiconductor substrate 1 electricity.Yet, supply with routine 0V voltage (GND) to above-mentioned shallow p trap 4a as Semiconductor substrate 1.Though the voltage that puts on shallow p trap 4a equals to put on the voltage of Semiconductor substrate 1, shallow p trap 4a isolates with Semiconductor substrate 1 electricity, does not therefore accept the noise from Semiconductor substrate 1.Therefore, the functional reliability of improving the element that forms in shallow p trap 4a can realize.
In shallow n trap 5K, form the P-MISFET in the cache.More precisely, form in the district, when forming other shallow n trap 5g, can make the conduction type transoid of shallow p trap 4a to 5j at the P-MISFET of cache.
In present embodiment 5, owing to the same with the reason of aforesaid embodiment 1 to 4, the electrical characteristics that make the MISFET that forms in the 5k at shallow p trap 4a and 4b and shallow n trap 5g all the time for example threshold voltage and leakage current optimization also can realize.
In addition, only just can form embedding n trap 3a and 3b, shallow p trap 4a and 4b and shallow n trap 5g to 5k with two photoresist figure 7j and 7k.This just makes that the rate of finished products of the manufacturing cost that reduces semiconductor device and raising semiconductor device is the same with aforesaid embodiment 1 to 4, can realize.
When carrying out next step, further improvement adjustment of the impurity concentration of n trap 5k in cache is feasible.More precisely, after removing photoresist figure 7k shown in Figure 43, as shown in figure 44, formation exposes the P-MISFET formation district in the cache to the open air and covers other regional photoresist figure 7m.
In addition, in order to form shallow n trap 5k, make mask with photoresist figure 7m phosphonium ion or ion like that are mixed Semiconductor substrate 1.At this moment, regulate the dosage of foreign ion to correct conduction type.Regulate ion implantation energy so that the lower part of shallow n trap 5k reaches embedding n trap 3a.This just makes in the cache district and to form shallow n trap 5k and shallow p trap 4a can realize.
After this, remove photoresist figure 7k shown in Figure 43 or photoresist figure 7m shown in Figure 44.Then, as shown in figure 45, form grid insulating film 12i and 13i simultaneously so that in the zone of shallow p trap 4a and 4b, form n-MISFET Q nIn the zone of 5k, form P-MISFET Q with Qnd and at shallow n trap 5h pAnd Qpr.
After this, the wiring step of the routine of the semiconductor device by cache is housed and conventional surface protective film form step and make semiconductor device.
Figure 46 represents so to be manufactured on the component placement top plan view of the memory cell of the cache in the semiconductor device.Figure 47 represents the circuit diagram of above-mentioned memory cell.
N-MISFET Q NdWork the MISFET effect that drives memory cell.
P-MISFET Q PrPlay load MISFET effect.Make these MISFET Q by shared electric conductor membrane NdWith MISFET Q PrGate electrode 13g and 12g integrally constitute figure.
MISFET Q at the left-hand side of Figure 46 NdIn gate electrode 13g with at the MISFET of right-hand side Q NdSemiconductor regions 13a be electrically connected, and at the MISFET Q of the right-hand side of Figure 46 NdIn gate electrode 13g and load MISFET Q PrSemiconductor regions 12a be electrically connected.
MISFET Q NdSemiconductor regions 13a serve as and transmit n-MISFET Q tWhole semiconductor regions and by MISFET Q tWith bit line BL 1And BL 2Be electrically connected.Here, a part of word line WL forms MISFET Q tGate electrode.In addition, bit line BL 1And BL 2Can transmit anti-phase signal mutually.
Except that the effect of aforesaid embodiment 1, present embodiment 5 can reach following effect.(1) in the borderline region between the formation of the n-MISFET in cache zone district and the p-MISFET formation district, can prevent that the impurities concentration distribution of shallow p trap 4a and embedding n trap 3a from lifting to the first type surface of Semiconductor substrate 1.Therefore, avoid since this lift can under different situations, cause bad trap puncture voltage and the problem sewed be possible.
(embodiment 6)
Figure 48 to 53 is sectional views of major part in the method for the semiconductor device of making one embodiment of the invention.
With adopting technological thought of the present invention to be applied to the MISFET of cache and high-breakdown-voltage group is assemblied in the situation of the semiconductor device in the shared semiconductor chip embodiment 6 is described.
Figure 48 is the sectional view of the major part in the semiconductor device of present embodiment 6.In Figure 48, the zone (first trap forms the district) that having of expressing forms cache, the zone that does not need embedding trap (3.3V-NB) that forms the MISFET that the 3.3V supply voltage drives, the zone (1.8/3.3V-B) that forms the embedding trap of needs of the MISFET that 1.8V or 3.3V supply voltage drive, the memory cell that forms the zone (HV) of MISFET in the high-breakdown-voltage group that the 12V supply voltage drives and the embedding trap of needs and form aforesaid fast storage (EEPROM), DRAM or memory like that form and distinguish.
At first, the same with aforesaid embodiment 1 to 5, grow on the first type surface of Semiconductor substrate 1 with thermal oxidation method and to weld film 8, just form isolated area 2 then.In the cache zone in above-mentioned isolated area 2, the width that forms borderline isolated area 2 between district and the n-MISFET formation district at P-MISFET for example is about 0.9 μ m to 1.5 μ m, the same with embodiment 5, its width is narrower than the width of other isolated areas 2 in regional.
Then, as shown in figure 49, on the first type surface of Semiconductor substrate 1, form photoresist figure 7j.In present embodiment 6, the P-MISFET formation district in the cache zone is also covered by photoresist figure 7j and is exposed to the open air.
After this, in order to form embedding n trap 3a and 3b, 7j makes mask with the photoresist figure, with aforesaid embodiment 5 in dosage and inject the same dosage of energy and inject energy phosphonium ion or ion like that are mixed Semiconductor substrate 1 to its position, deep.At this time, can make the impurity concentration of embedding trap 3a and 3b adjust to optimum value.
Secondly, in order on embedding n trap 3a and 3b, to form shallow p trap 4a and 4b with self-aligned manner, with same photoresist figure 7j do mask with embodiment 5 in dosage and inject the same dosage of energy and inject the ion injection that energy carries out boron.
At this time, present embodiment 6 is the same with embodiment 5, can make the impurity concentration of shallow p trap 4a and 4b and embedding n trap 3a and 3b irrespectively adjust to optimum value, improves the electrical characteristics of the MISFET in shallow p trap 4a and 4b thus.
In addition, owing to just can form embedding n trap 3a and 3b and shallow p trap 4a and 4b with single photoresist figure 7j, so the same with embodiment 5, the rate of finished products and the reliability that reduce manufacturing cost and raising semiconductor device significantly can realize.
Secondly, as shown in figure 50, remove photoresist figure 7j shown in Figure 49, just on the first type surface of Semiconductor substrate 1, form photoresist figure 7k then.Form above-mentioned photoresist figure 7k to expose for example p-MISFET of shallow p trap 4a formation district in cache to the open air, the external zones of shallow p trap 4a, form the zone that does not need embedding trap (3.3V-NB) of the P-MISFET in the 3.3V group, form the zone of the embedding trap of needs of the p-MISFET in 1.8V or the 3.3V group, 1.8v or the outer peripheral areas of the embedding trap of needs of the shallow p trap 4a in the 3.3v group, the p-MISFET that forms in the district (HV) at the MISFET of high-breakdown-voltage group forms district (HV), the external zones of shallow p trap 4a in the MISFET of high-breakdown-voltage group forms district (HV) and form the external zones of the shallow p trap 4a in distinguishing and cover other zones in memory cell.
Then, in order to form shallow n trap 5g to 5j, 5m, 5n, 5p and 5q and shallow well 5k1 in Semiconductor substrate 1, make mask three kinds of conditions with photoresist figure 7k: acceleration energy is 1, and 300KeV and dosage are 1 * 10 13/ cm 2Condition, acceleration energy be that 600KeV and dosage are 5 * 10 11/ cm 2Condition and acceleration energy be that 200KeV and dosage are 5 * 10 11/ cm 2Following phosphonium ion of condition or ion like that mix above-mentioned Semiconductor substrate 1, then, be that 70KeV and dosage are 2 * 10 at acceleration energy 12/ cm 2Following boron difluoride (BF of condition 2) mix above-mentioned Semiconductor substrate 1.Carry out BF 2Ion inject in order that adjust the threshold voltage of P-MISFET.
Form these shallow n trap 5i and 5j so that be enclosed in the side that the MISFET that needs embedding trap forms the shallow p trap 4a in the district, the lower part of shallow n trap 5i and 5j and shallow n trap 5i overlapping with the upper part of embedding n trap 3a and 5j are electrically connected with shallow n trap 3a.In other words, shallow p trap 4a is by shallow n trap 5i and 5j and embedding n trap 3a encirclement, so that shallow p trap 4a and Semiconductor substrate 1 electricity isolation.Therefore, can supply with the voltage different to shallow p trap 4a with the voltage that puts on Semiconductor substrate 1.For example apply 0 to-3.3V voltage to above-mentioned shallow p trap 4a.
The MISFET that forms shallow n trap 5n and 5m so that be enclosed in the high-breakdown-voltage group forms the side of the shallow p trap 4a in the district (HV), and the upper part of the lower part of shallow n trap 5m and 5n and embedding n trap 3a is overlapping, and shallow n trap 5m and 5n are electrically connected with embedding n trap 3a.Shallow p trap 4a is by shallow n trap 5m and 5n and embedding n trap 3a surrounds and isolate with Semiconductor substrate 1 electricity.Therefore, can supply with the voltage different to shallow p trap 4a with the voltage that puts on Semiconductor substrate 1.For example supply with 0 to-12V voltage to above-mentioned shallow p trap.
Form shallow n trap 5p and 5q so that be enclosed in the side of the shallow p trap 4a in the memory cell of high-breakdown-voltage group, the lower part of shallow n trap 5p and 5q and shallow n trap 5p overlapping with the upper part of embedding n trap 3a and 5q are electrically connected with embedding n trap 3a.Shallow p trap 4a is by shallow n trap 5q and 5q and embedding n trap 3a surrounds and isolate with Semiconductor substrate 1 electricity.Therefore, can supply with the voltage different to above-mentioned shallow p trap 4a with the voltage that puts on Semiconductor substrate 1.For example supply with 0 to-12V voltage to above-mentioned shallow p trap 4a.
In addition, in shallow well 5k1, be formed with the P-MISFET of cache.Yet in present embodiment 6, undoping is to be not enough to finish the complete transoid of conduction type.When such state, the same with aforesaid embodiment 5, can mix fully.
In present embodiment 6, can make shallow p trap 4a and 4b, shallow n trap 5g adjust to optimum value independently one by one to the impurity concentration of 5j, 5m, 5n, 5p and 5q and shallow well 5k1, so that the electrical characteristics that make the MISFET that forms in the zone of 5j, 5m, 5n, 5p and 5q at trap 4a and 4b and shallow n trap 5g all the time for example threshold voltage and leakage current optimization.
In addition, owing to only just can form embedding n trap 3a and 3b, shallow p trap 4a and 4b and shallow n trap 5g to 5j, 5m, 5n, 5p and 5q with two photoresist figure 7j and 7k, so the same with aforesaid embodiment 1 to 5, the rate of finished products that reduces the manufacturing cost of semiconductor device and improve semiconductor device can realize.
Therefore, can be equipped with the semiconductor device of cache and high-breakdown-voltage MISFET, thereby semi-conductor industry is produced strong influence with low-cost production with high reliability.
Secondly, remove photoresist figure 7k shown in Figure 50.After this, shown in Figure 51, the zone that makes the zone of the embedding trap of needs make the zone that forms the P-MISFET in the cache, to form the P-MISFET in the 3.3V group and form the embedding trap of needs of the P-MISFET in the 1.8V/3.3V group is exposed and is covered other regional photoresist figure 7m.
Then, in order to form impurity concentration or the optimized semiconductor regions 26a of conduction type that makes shallow n trap 5k1 and shallow n trap 5h and 5i, making mask with photoresist figure 7m is that 360KeV and dosage are 1.3 * 10 at for example acceleration energy 13/ cm 2Following phosphonium ion of condition or ion like that mix Semiconductor substrate 1.
The dosage of adjustment foreign ion in the P-MISFET of cache forms the district so that the conduction type of Semiconductor substrate 1 (shallow p trap 4a) from p type transoid to the n type.In addition, make the optimized adjustment of impurity concentration of shallow n trap 5h and 5i.
Therefore, can in the cache zone, form shallow n trap 5k and shallow p trap 4a.Shallow n trap 5k becomes the overall area of shallow well 5k1 and semiconductor regions 26a in above-mentioned situation.Shallow p trap 4a is surrounded by shallow n trap 5k and 5g, isolates with Semiconductor substrate 1 electricity, therefore can supply with the voltage different with the voltage that puts on Semiconductor substrate 1 by shallow p trap 4a.For example shallow well is applied 0 to-1.8V voltage.
Because high-breakdown-voltage MISFET is set, carry out simultaneously so adjust the doping that doping step and stage afterwards of the conduction type of the shallow well 5k among the P-MISFET of cache require in other zones.This just makes the occurrence rate of being avoided increasing the quantity of mask and reducing foreign substance is possible, thereby improves rate of finished products.
After this, remove the photoresist figure 7m shown in Figure 51.Shown in Figure 52,, in shallow p trap 4a and 4b, form p N-type semiconductor N zone 26b with photoetching process and ion implantation then in order to make the impurity concentration optimization.Semiconductor regions 26b is mixed with for example boron.
The reason that forms semiconductor regions 26a or 26b will be described below.Though the MISFET of MISFET, the 1.8V of 3.3V group group and the trap impurity concentration of the MISFET in the cache be substantially equate mutually with the trap impurity concentration of MISFET in the high-breakdown-voltage group be inequality, so they must be than the trap impurity concentration height of high-breakdown-voltage group.
After this, shown in Figure 53, on the first type surface of Semiconductor substrate 1, form grid insulating film 12i, 13i and 21i simultaneously.Then, in shallow p trap 4a and 4b zone, form n-MISFET Q n, Q NdAnd Q, and form p-MISFET Q in the zone of 5k at shallow n trap 5h pAnd Q Pr
The same with embodiment 1 to 5, in the zone that does not need embedding trap, form n-MISFET and below the shallow p trap 4b that is electrically connected with Semiconductor substrate 1, form embedding n trap 3b, therefore can be from Semiconductor substrate 1 to shallow p trap 4b service voltage.
After this, wiring step and the conventional surface protective film by routine forms step manufacturing semiconductor device.Omit the description of the circuit diagram of component placement top plan view in the relevant cache stored unit and relevant memory cell here.Because the same, so omit the relevant description that is included in the cross section structure aspect of the capacitor 19 among the DRAM equally with the description among the aforesaid embodiment 5.
Present embodiment can reach following effect except that the effect of aforesaid embodiment 1.(1) when technological thought of the present invention is applied to make the method for the semiconductor device with the MISFET in the high-breakdown-voltage group, except forming n type or p N-type semiconductor N district 26a and 26b in the trap of the external MISFET of MISFET in the high-breakdown-voltage group so that can compensating impurity concentration deficiency in the trap.(2) when cache, high-breakdown-voltage group MISFET, common MISFET and another memory cell be not go wrong when in shared semiconductor chip, forming.Can simplify manufacture method by the predetermined method of carrying out many zones simultaneously.Therefore, can be by the always synthetic method of making semiconductor device of the method that forms each element be made semiconductor device.
Though described the present invention particularly aspect embodiments of the invention, the present invention should not be limited to aforesaid embodiment 1 to 6 but can be easily with various mode conversion under the situation that does not break away from main points of the present invention.
For example, adopting isolated area is that the situation of ditch type has been described embodiment 1 to 6.But the present invention should not be confined to this but can come conversion in various mode, and for example the field insulation film that forms with the selective oxidation method is formed isolation structure.
Semiconductor substrate comprises the what is called " epitaxial wafer " that forms epitaxial loayer on Semiconductor substrate.In this conversion, on the surface of the Semiconductor substrate that for example monocrystalline silicon is formed, form for example epitaxial loayer of silicon single crystal with epitaxy.Though be not that this is done special restriction, thickness is that the epitaxial loayer of 5 μ m is best.
The data storage capacitor that adopts DRAM is that the situation of convex has been described aforesaid embodiment 1,3 and 6.Yet the present invention should not be limited to this but can come conversion in various mode of blade type that for example comprises.
The situation that adopts common insulation film to form the capacitor insulative film of the data storage capacitor among the DRAM has been described aforesaid embodiment 1,3 and 6.Yet the present invention should not be so limited but can conversion, so that for example by constituting ferroelectric storage with ferroelectric material as the material that pZT and so on makes the capacitor insulation film in the data holding capacitor.
As mentioned below, can conversion embodiment 2,3 and 4.At first, make the photoresist figure (the photoresist figure 7i or the photoresist figure like that are equivalent to Figure 22) that exposes to the open air in the logical circuit zone make in Figure 16 or the 1.8V group MISFET zone (having back bias) in the zone like that and mix Semiconductor substrate with phosphonium ion or ion like that as mask.Under for the condition that forms the dark n trap that extends to position, Semiconductor substrate deep from the Semiconductor substrate first type surface, carry out the ion injection.Then, remove the photoresist figure, just form the 1.8V that makes in the logical circuit zone then and organize the photoresist figure (the photoresist figure 7j or the photoresist figure like that are equivalent to Figure 20) that expose to the open air in MISFET zone (having back bias).After this, this photoresist figure is used as mask so that boron ion or ion like that are mixed Semiconductor substrate.Under the condition that forms the shallow well that extends to semiconductor superficial part position from the Semiconductor substrate first type surface and have the conduction type opposite, carry out ion and inject, thereby form the shallow p trap that is surrounded by dark n trap with deep trap.Above-mentioned shallow p trap is surrounded by dark n trap and isolates with the Semiconductor substrate electricity.The subsequent step that forms element is the same with the subsequent step of aforesaid embodiment 2,3 and 4.
To the effect that reach by disclosing representational aspect of the present invention in this specification be described briefly hereinafter. (1) according to the present invention, the first trap forms and distinguishes, the second trap forms district, triple-well forms district and the impurity concentration in the 4th trap formation district can be individually adjusted optimum value. Therefore can make all the time at trap and form the transistorized electrical characteristics of MIS that form in district for example starting voltage and leakage current optimization. (2) according to the present invention, only with two masks, just can form the first trap forms district and the second trap and forms the first embedding trap of conduction type, the first trap in district and form the second conduction type shallow well, triple-well in district and form the first conduction type shallow well in district and the 4th trap and form the first conduction type shallow well in distinguishing, so that compare with the process of making a mask for each trap, reduce the number of making masks. (3) due to above-mentioned effect (1) and (2), in the semiconductor device with trap isolation structure,, in the situation that do not increase the number of making the semiconductor device step, can make the impurity concentration optimization of well region and the common well region in the trap isolated area. (4) due to above-mentioned effect (1) and (2),, in the situation that do not increase the number of making the semiconductor device step with trap isolation structure, can improve the electrical characteristics of the element that forms in well region and the common well region in the trap isolated area. (5), due to above-mentioned effect (2), reduce the cost of making semiconductor device and can realize. (6) due to above-mentioned effect (2), the minimizing on the number of mask formation step correspondingly can reduce to cause due to foreign substance the incidence of defect, therefore improves the yield rate of semiconductor device. (7), due to above-mentioned effect (1), (2), (3), (4) and (5), provide the semiconductor device with high workload reliability to realize. (8) according to the present invention, make impurity concentration that at least a portion forms the first conduction type shallow well district in district at triple-well higher than form the impurity concentration in the second conduction type shallow well district in district at the first trap, therefore can make knot space out between the second conduction type shallow well district and Semiconductor substrate to improve electric isolation performance therebetween. , even form position that triple-well forms the first conduction type shallow well district in district by along the face displacement when forming the Impurity injection step in shallow well district, can guarantee that also breakdown voltage that triple-well forms the first conduction type shallow well district in district levies at the first trap and form the second conduction type shallow well district in district and the electric isolation performance between Semiconductor substrate with the guarantor. (9) due to above-mentioned effect (8), the yield rate and the reliability that improve semiconductor device can realize. (10) according to the present invention, can make the 5th trap form the impurity concentration that district and the 6th trap form district and adjust to independently optimum value, therefore can make all the time in the transistorized electrical characteristics of MIS of well region formation for example starting voltage and leakage current optimization. (11) according to the present invention, form below district while forming embedding well region and use the 5th mask to make etching mask to remove the grid insulating film that exposes by the 5th mask when just at the 5th trap, forming district and the 6th trap, therefore can make the number of mask formation step be less than the number of removing the mask formation step in the situation of step with different masks. (12), due to above-mentioned effect (11), reduce the cost of making semiconductor device and can realize. (13) due to above-mentioned effect (11), the minimizing on the number of mask formation step correspondingly can reduce to cause due to foreign substance the incidence of defect, therefore improves the yield rate of semiconductor device. (14), due to above-mentioned effect (10), (11), (12) and (13), with low cost, provide the semiconductor device with high workload reliability to realize. (15) according to the present invention, mix the first conductive type impurity with the 6th mask that expose to the open air in the zone that makes the shallow well district that forms conduction type as doping mask and form the conduction type in the second conduction type shallow well district in distinguishing to compensate the first trap, therefore be formed on the first trap and form the first interior conduction type shallow well district of district. In the first trap forms district during the stage of the doping step in formation the second conduction type shallow well district, the impurities concentration distribution that can prevent the second conduction type shallow well district forms the first conduction type shallow well district in district and the borderline region place between the second conduction type shallow well district lifts to the Semiconductor substrate first type surface at the first trap, therefore can avoid the problem that can cause under different situations such as trap breakdown voltage fault and leakage current of lifting due to impurities concentration distribution. (16) when technological thought of the present invention is applied to make the method with the transistorized semiconductor device of high-breakdown-voltage group MIS, according to the present invention, can to compensate the impurity concentration of the well region in MIS transistor except high-breakdown-voltage group MIS transistor not enough by mixing in addition impurity with well region conduction type identical conduction type.

Claims (42)

1. method of making semiconductor device comprises step:
A) making makes first trap form first mask that Qu Hezai exposes to the open air from second trap formation district of first trap formation district a distance formation on the Semiconductor substrate first type surface;
B) make doping mask with the first above-mentioned mask the dark position that impurity mixes above-mentioned Semiconductor substrate so that the Semiconductor substrate in above-mentioned first trap formation district and second trap formation district is formed the embedding well region of first conduction type;
C) making doping mask with the first above-mentioned mask mixes impurity above-mentioned Semiconductor substrate so that forms district and the second above-mentioned trap at above-mentioned first trap and form the formation second conduction type shallow well district on the above-mentioned embedding well region of first conduction type in the district;
D) on the Semiconductor substrate first type surface, form to make and surround first trap and form triple-well that peripheral and first trap of the embedding well region of first conduction type in the district forms periphery, the second conduction type shallow well district in the district and form the district and forming from above-mentioned first trap that the 4th trap that a distance, district forms forms that the district exposes to the open air and by second mask thinner than above-mentioned first mask; With
E) making doping mask with the second above-mentioned mask mixes above-mentioned Semiconductor substrate to impurity so that forms in above-mentioned triple-well forms district and surround the first above-mentioned trap and form the periphery in the second conduction type shallow well district in district and be shallower than the first trap and form in district the first embedding trap of conduction type and with the first trap, form the shallow well district that the first embedding well region of conduction type in distinguishing is electrically connected to; And so that form in above-mentioned the 4th trap forms district be shallower than the first trap form district in the first conduction type shallow well district of the first embedding trap of conduction type
Wherein, in above-mentioned first trap forms the district, form the second conduction type shallow well district in the district at the first above-mentioned trap and formed the first conduction type shallow well district of the formation in the district at above-mentioned triple-well and form the embedding well region of first conduction type in the district and surround and isolate with the Semiconductor substrate electricity at the first above-mentioned trap.
2. according to the method for claim 1,
Wherein, mix impurity so that the impurity concentration peak region of the embedding trap of first conduction type in above-mentioned first trap formation district is darker than the impurity concentration peak region that forms the second conduction type shallow well district in district and above-mentioned second trap formation district at the first above-mentioned trap.
3. according to the method for claim 1, further comprise step:
Form the MIS transistor in the zone in the first conduction type shallow well district in above-mentioned first trap forms the district.
4. according to the method for claim 1, further comprise step:
On above-mentioned Semiconductor substrate first type surface, form grid insulating film;
On above-mentioned grid insulating film, form gate electrode; With
Make mask with above-mentioned gate electrode predetermined impurity mixed Semiconductor substrate,
Wherein, above-mentioned first trap form district and the second above-mentioned trap form in the district the second conduction type shallow well district and above-mentioned triple-well form district and the 4th above-mentioned trap form in the first conduction type shallow well district in distinguishing each regional in formation MIS transistor.
5. according to the method for claim 1,
Wherein, carry out the doping of above-mentioned step (e) so that the second conduction type shallow well district that part of impurity concentration height of impurity concentration ratio in the first above-mentioned trap forms the district of at least a portion in the first conduction type shallow well district in above-mentioned triple-well forms the district.
6. according to the method for claim 5,
Wherein, carry out above-mentioned step (e) doping so that near the impurity concentration the above-mentioned embedding well region in the first conduction type shallow well district in above-mentioned triple-well forms the district than near the embedding well region in the embedding shallow well of second conduction type district that forms at the first above-mentioned trap in distinguishing and near the impurity concentration height the first conduction type shallow well district.
7. according to the method for claim 1, further comprise step:
On the first type surface of above-mentioned Semiconductor substrate, form element isolation zone,
Wherein, in the first above-mentioned trap forms the district, by the active area in the second above-mentioned conduction type shallow well district of above-mentioned element isolation zone delimitation,
Wherein, at least a portion in the first conduction type shallow well district in above-mentioned triple-well forms the district extends in below the above-mentioned element isolation zone.
8. according to the method for claim 7, further comprise step:
The second conduction type raceway groove blocked-off region extends in below the above-mentioned element isolation zone.
9. method according to Claim 8,
In method, below above-mentioned triple-well formed the element isolation zone of distinguishing, the impurity concentration in the first above-mentioned conduction type shallow well district was higher than the impurity concentration of above-mentioned raceway groove blocked-off region.
10. according to the method for claim 7,
Wherein, by in above-mentioned Semiconductor substrate, forming isolating trenches then by forming above-mentioned element isolation zone at above-mentioned isolating trenches embedded set isolated film.
11., further comprise step according to the method for claim 1:
On the Semiconductor substrate first type surface, form the 5th trap that makes form the formation of a distance, district from the first above-mentioned trap and form the 3rd mask that the district exposes to the open air;
Make doping mask with the 3rd above-mentioned mask and impurity mixed Semiconductor substrate so that in the 5th above-mentioned trap forms the district, form the first conduction type shallow well district,
On the Semiconductor substrate first type surface, form to make and form the 4th mask that the district exposes to the open air along the 6th trap formation district that bread encloses by the 5th above-mentioned trap; With
Making doping mask with the 4th above-mentioned mask mixes impurity Semiconductor substrate so that form the second conduction type shallow well district in above-mentioned the 6th trap forms the district.
12., further comprise step according to the method for claim 11:
The 5th mask that formation is distinguished above-mentioned the 5th trap formation on the Semiconductor substrate first type surface, the 6th above-mentioned trap forms the district and the element isolation zone in a part of encirclement the 5th trap formation district exposes and have its open end that constitutes to the open air on element isolation zone; With
With the 5th above-mentioned mask do doping mask impurity mix below Semiconductor substrate so that the first conduction type shallow well district in above-mentioned the 5th trap forms district and the 6th trap the second conduction type shallow well district in forming district form the first embedding well region of conduction type so that above-mentioned embedding well region and above-mentioned the 5th trap form district and the 6th above-mentioned trap the first conduction type shallow well district in forming district is electrically connected to and can extend in element isolation zone that the 5th above-mentioned trap formation of part encirclement distinguishes below;
Wherein, form in the district at above-mentioned the 6th trap, the second conduction type shallow well district in the 6th trap forms the district formed by the 5th above-mentioned trap that the first conduction type shallow well district in the district and the 5th above-mentioned trap form that district and the 6th above-mentioned trap form that the embedding well region of first conduction type in the district surrounds and with the electric isolation of Semiconductor substrate.
13., further comprise step according to the method for claim 12:
Make etching mask with the 5th above-mentioned mask and remove grid insulating film from the Semiconductor substrate first type surface that above-mentioned the 5th mask exposes; With
After the 5th above-mentioned mask is removed step, form grid insulating film at the Semiconductor substrate first type surface that exposes from the 5th above-mentioned mask with thickness different with other regional grid insulating film thickness.
14. according to the method for claim 13,
Wherein, it is lower than the transistorized driving voltage of the MIS with other regional grid insulating films to have a transistorized driving voltage of MIS of grid insulating film of different-thickness.
15., further comprise step according to the method for claim 1:
On the Semiconductor substrate first type surface, form to make and distinguishing the 5th trap formation district of a distance formation and the 3rd mask that a part of element isolation zone exposes to the open air from above-mentioned first trap formation;
Making doping mask with the 3rd above-mentioned mask mixes impurity Semiconductor substrate so that form the first conduction type shallow well district in the 5th above-mentioned trap forms the district;
On the Semiconductor substrate first type surface, form to make and form the 4th mask that the formation of the 6th trap is distinguished and a part of element isolation zone exposes to the open air that the district encloses along bread by the 5th above-mentioned trap;
Making doping mask with the 4th above-mentioned mask mixes Semiconductor substrate to impurity so that is formed on above-mentioned the 6th trap and form the second conduction type shallow well district in the district and the second conduction type raceway groove blocked-off region below above-mentioned element isolation zone;
The 5th mask that formation is distinguished above-mentioned the 5th trap formation on the Semiconductor substrate first type surface, the 6th above-mentioned trap forms the district and the element isolation zone in a part of encirclement the 5th trap formation district exposes and have its open end that constitutes to the open air on element isolation zone; With
Making doping mask with the 5th above-mentioned mask mixes impurity Semiconductor substrate so that forms the first conduction type shallow well district in the district and the 6th trap at above-mentioned the 5th trap and form and form the embedding well region of first conduction type below the second conduction type shallow well district in the district so that above-mentioned embedding well region and above-mentioned the 5th trap form the first conduction type shallow well district in the district is electrically connected and extends in a part and surround below the element isolation zone that above-mentioned the 5th trap formation distinguishes;
Wherein, form in the district at above-mentioned the 6th trap, the second conduction type shallow well district in the 6th trap forms the district formed by the 5th above-mentioned trap that the first conduction type shallow well district in the district and the 5th above-mentioned trap form that district and the 6th above-mentioned trap form that the embedding well region of first conduction type in the district surrounds and with the electric isolation of Semiconductor substrate.
16., further comprise step according to the method for claim 1:
In above-mentioned first trap forms the district, on the Semiconductor substrate first type surface, be formed for exposing to the open air the 6th mask of the part in the zone that forms the second conduction type shallow well district; With
Making doping mask with the 6th above-mentioned mask mixes above-mentioned first trap to impurity and forms district so that compensation and form the conduction type in the second conduction type shallow well district in the district and be formed on the first above-mentioned trap at the first above-mentioned trap and form the first conduction type shallow well district in the district
Wherein, form at above-mentioned first trap and to form the first conduction type shallow well district and the second conduction type shallow well district in the district, and the second above-mentioned conduction type shallow well district forms the first conduction type shallow well district that forms in the district and forms the embedding trap of first conduction type in the district at first trap by the first conduction type well region, at above-mentioned triple-well and surrounds and isolate with the Semiconductor substrate electricity.
17. according to the method for claim 16,
Wherein, the element isolation zone that forms between the first conduction type shallow well in above-mentioned first trap formation district and the second conduction type shallow well district has the width narrower than the element isolation zone in other zone.
18. according to the method for claim 16,
Wherein, form the MIS transistor in the first conduction type shallow well district in the first above-mentioned trap forms the district and the second conduction type shallow well district.
19. according to the method for claim 1,
Mix with impurity in addition when wherein, in above-mentioned Semiconductor substrate, forming the MIS transistor of high-breakdown-voltage and remove outer shallow well district, the transistorized high-breakdown-voltage shallow well of the MIS district that forms high-breakdown-voltage with the increase impurity concentration.
20. the method according to claim 1 further comprises:
On the Semiconductor substrate first type surface, form and expose the 7th mask that the 7th trap forms the district to the open air;
Make doping mask with the 7th above-mentioned mask and impurity is mixed above-mentioned the 7th trap form the district, so that formation extends to the first conduction type deep-well region of above-mentioned position, Semiconductor substrate deep from above-mentioned Semiconductor substrate first type surface in the 7th above-mentioned trap forms the district;
Make etching mask with the 7th above-mentioned mask and remove grid insulating film from the first type surface of the Semiconductor substrate exposed by above-mentioned the 7th mask; With
After the 7th above-mentioned mask is removed step, form grid insulating film at the Semiconductor substrate first type surface that exposes from the 7th above-mentioned mask with thickness different with the thickness of other regional grid insulating films.
21., further comprise step according to the method for claim 20:
Make the 8th mask that exposes in the 8th trap formation district that is formed by the 7th above-mentioned trap in district's area surrounded in formation on the Semiconductor substrate first type surface by forming figure;
Make doping mask with the 8th above-mentioned mask and with the method for the conduction type that compensates above-mentioned deep-well region impurity mixed Semiconductor substrate so that in the 8th above-mentioned trap forms the district, form by the second conduction type shallow well district of above-mentioned deep-well region encirclement,
Wherein, in the 8th above-mentioned trap formed the district, the second conduction type shallow well district was surrounded by the first conduction type deep-well region and isolates with the Semiconductor substrate electricity.
22. according to the method for claim 20,
Wherein, it is lower than the voltage of the transistorized driving of MIS with other regional grid insulating films to have a transistorized driving voltage of MIS of above-mentioned grid insulating film of different-thickness.
23. according to the method for claim 20,
Wherein, the end of the 7th above-mentioned mask be placed on the element isolation zone and
Wherein, the end face of the deep-well region in the 7th above-mentioned trap forms the district terminates at below the element isolation zone.
24., further comprise step according to the method for claim 20:
Below above-mentioned element isolation zone, form the second conduction type raceway groove blocked-off region.
25. a method of making semiconductor device comprises step:
(a) making makes first trap form first mask that Qu Hezai exposes to the open air from second trap formation district of first trap formation district a distance formation on the Semiconductor substrate first type surface;
(b) making doping mask with the first above-mentioned mask mixes impurity above-mentioned Semiconductor substrate so that forms the dark position that district and the second above-mentioned trap form the Semiconductor substrate in distinguishing at above-mentioned first trap and form the embedding well region of first conduction type;
(c) making doping mask with the first above-mentioned mask mixes impurity above-mentioned Semiconductor substrate so that forms district and the second above-mentioned trap at above-mentioned first trap and form the formation second conduction type well region on the above-mentioned embedding well region of first conduction type in the district;
(d) on the Semiconductor substrate first type surface, form make surround that first trap forms that the 3rd well region that encloses outside the well region of the embedding well region of first conduction type in the district and second conduction type exposes and than on the second thin mask of first mask; With
(e) making doping mask with the second above-mentioned mask mixes Semiconductor substrate to impurity so that forms in above-mentioned triple-well forms the district and surround the first above-mentioned trap and form the peripheral of the second conduction type well region in the district and be shallower than first trap and form embedding well region of first conduction type in distinguishing and the first conduction type well region that is electrically connected with this embedding well region
Wherein, in above-mentioned first trap forms the district, form the second conduction type well region in the district at the first above-mentioned trap and formed the first conduction type well region that forms in the district at above-mentioned triple-well and form the embedding trap of first conduction type in the district and surround and isolate with the Semiconductor substrate electricity at the first above-mentioned trap.
26. according to the method for claim 25,
Wherein, mix impurity so that the impurity concentration peak region of the embedding trap of first conduction type in above-mentioned first trap formation district is darker than the impurity concentration peak region that forms the second conduction type well region in the district at the first above-mentioned trap.
27. according to the method for claim 25, the step that further comprises is:
Form the MIS transistor in the zone in the first conduction type well region in above-mentioned triple-well forms the district.
28. according to the method for claim 25, the step that further comprises is:
On above-mentioned Semiconductor substrate first type surface, form grid insulating film;
On above-mentioned gate insulating film, form gate electrode; With
Make mask with above-mentioned gate electrode predetermined impurity mixed Semiconductor substrate,
Wherein, above-mentioned first trap form district and the second above-mentioned trap form the second conduction type well region in the district and in the first conduction type well region in above-mentioned triple-well forms the district each regional in formation MIS transistor.
29. according to the method for claim 25,
Wherein, carry out the doping of above-mentioned step (e) so that the impurity concentration height of the second conduction type well region of impurity concentration ratio in the first above-mentioned trap forms the district of at least a portion of the first conduction type well region in above-mentioned triple-well forms the district.
30. according to the method for claim 25,
Wherein, carry out the doping of above-mentioned step (e) so that near the impurity concentration the above-mentioned embedding well region in the first conduction type well region in above-mentioned triple-well forms the district compares near the embedding well region above-mentioned in the second conduction type well region and near the impurity concentration height the first above-mentioned conduction type well region.
31. the method according to claim 25 further comprises:
Form in the district at the first above-mentioned trap, on semiconductor substrate surface, form the 6th mask that the second conduction type well region is exposed to the open air; With
Make doping mask with the 6th above-mentioned mask and impurity is mixed above-mentioned first trap form district so that compensation and form the conduction type of the second conduction type well region in the district and be formed on the first above-mentioned trap at the first above-mentioned trap and form the first conduction type well region in the district,
Wherein, form at above-mentioned first trap and to form the first conduction type well region and the second conduction type well region in the district, and the second above-mentioned conduction type well region forms the first conduction type well region that forms in the district and forms the embedding well region of first conduction type in the district at first trap by the first conduction type well region, at above-mentioned triple-well and surrounds and isolate with the Semiconductor substrate electricity.
32. according to the method for claim 31,
Wherein, the element isolation zone that forms between the first conduction type well region in above-mentioned first trap formation district and the second conduction type well region has the width narrower than the element isolation zone in other zone.
33. according to the method for claim 31,
Wherein, form the MIS transistor in the first conduction type well region in the first above-mentioned trap forms the district and the second conduction type well region.
34. a method of making semiconductor device comprises step:
(a) on the Semiconductor substrate first type surface, make first mask that makes first semiconductor regions and expose to the open air by forming figure at second semiconductor regions that forms from first semiconductor regions a distance;
(b) make doping mask with the first above-mentioned mask the dark position that impurity mixes above-mentioned Semiconductor substrate so that the Semiconductor substrate in the first and second above-mentioned semiconductor regions is formed the embedding semiconductor regions of first conduction type;
(c) making doping mask with the first above-mentioned mask mixes impurity on above-mentioned Semiconductor substrate so that the above-mentioned embedding semiconductor regions of first conduction type in the first above-mentioned semiconductor regions and above-mentioned second semiconductor regions and forms the shallow semiconductor regions of second conduction type;
(d) on the Semiconductor substrate first type surface, forms the 3rd semiconductor regions of periphery of the embedding semiconductor regions of first conduction type that makes in encirclement first semiconductor regions and the shallow semiconductor regions of second conduction type in first semiconductor regions and second mask that the 4th semiconductor regions from first semiconductor regions a distance exposes to the open air by forming figure; With
(e) making doping mask with the second above-mentioned mask mixes above-mentioned Semiconductor substrate to impurity so that form to surround the peripheral of the shallow semiconductor regions of second conduction type in the first above-mentioned semiconductor regions and the shallow semiconductor regions of first conduction type that is electrically connected with the embedding semiconductor regions of first conduction type in the first above-mentioned semiconductor regions and the shallow semiconductor regions of formation first conduction type in the 4th above-mentioned semiconductor regions in the 3rd above-mentioned semiconductor regions
Wherein, in the first above-mentioned semiconductor regions, the embedding semiconductor regions of shallow semiconductor regions of first conduction type that the shallow semiconductor regions of second conduction type in the first above-mentioned semiconductor regions is formed in the 3rd above-mentioned semiconductor regions and first conduction type in the first above-mentioned semiconductor regions surround and isolate with the Semiconductor substrate electricity and
Wherein, in the second above-mentioned semiconductor regions, the above-mentioned shallow semiconductor regions of second conduction type is electrically connected with above-mentioned Semiconductor substrate.
35. a semiconductor device comprises:
In first trap of Semiconductor substrate forms the district and second trap that forms at the position that forms the district with a certain distance from first trap form in the district at the embedding well region of first conduction type with a certain distance from the dark position formation of Semiconductor substrate first type surface;
Above-mentioned first trap form district and the second above-mentioned trap form on the above-mentioned embedding well region of first conduction type in the district with the method for irrespectively setting impurity concentration with the above-mentioned embedding well region of first conduction type with the second conduction type shallow well district of the embedding well region self-aligned manner formation of first conduction type;
Form and surround the first above-mentioned trap in the district and form the second conduction type shallow well district in the district and form the first conduction type shallow well district that the embedding well region of first conduction type in distinguishing is electrically connected forming triple-well that the district forms around above-mentioned first trap with first trap; With
Form the first conduction type shallow well district that forms in the 4th trap formation district that forms on the position of distinguishing at the arbitrary trap that forms the district with a certain distance from the first above-mentioned trap, above-mentioned second trap formation is distinguished and above-mentioned triple-well forms in the district,
Wherein, above-mentioned first trap forms the second conduction type shallow well district in the district and is formed the embedding well region of first conduction type in the district and above-mentioned triple-well by the first above-mentioned trap and form the first conduction type shallow well district in the district and surround and isolate with the Semiconductor substrate electricity.
36. according to the semiconductor device of claim 35,
Wherein, forming the second above-mentioned conduction type shallow well district than the shallow position of the embedding well region of first conduction type.
37. according to the semiconductor device of claim 35,
Wherein, the second conduction type shallow well district that above-mentioned first trap formation district and the second above-mentioned trap are formed in the district has equal impurity concentration on depth direction,
Wherein, make above-mentioned first trap form district and the second above-mentioned trap form the embedding well region of first conduction type in distinguishing on depth direction, have equal impurity concentration and
Wherein, the first conduction type shallow well district that above-mentioned triple-well formation district and the 4th above-mentioned trap are formed in the district has equal impurity concentration on depth direction.
38. according to the semiconductor device of claim 35,
Wherein, mix so that the impurity concentration of at least a portion in the first conduction type shallow well district in above-mentioned triple-well forms the district is higher than the impurity concentration in the second conduction type shallow well district.
39. according to the semiconductor device of claim 38,
Wherein, mix so that near the impurity concentration the above-mentioned embedding well region in the first conduction type shallow well district in above-mentioned triple-well forms the district be higher than the first above-mentioned trap form distinguish near the embedding well region of first conduction type in the second conduction type shallow well district and near the impurity concentration the shallow well district.
40. according to the semiconductor device of claim 35,
Wherein, constitute the MIS transistor in the first conduction type shallow well district in above-mentioned triple-well forms the district.
41. according to the semiconductor device of claim 35,
Wherein, in above-mentioned first trap forms the second conduction type shallow well district in the district, in the second above-mentioned trap forms the second conduction type shallow well district in the district, in above-mentioned triple-well forms the first conduction type shallow well district in the district and in the 4th above-mentioned trap forms the first conduction type shallow well district in the district, constitute the MIS transistor.
42. according to the semiconductor device of claim 35,
Wherein, in the first type surface of above-mentioned Semiconductor substrate, form element isolation zone;
Wherein, in forming the district, the first above-mentioned trap delimit the active area in the second above-mentioned conduction type shallow well district by above-mentioned element isolation zone; With
Wherein, at least a portion in the first conduction type shallow well district in above-mentioned triple-well forms the district is extended below above-mentioned element isolation zone.
CNB991040155A 1998-03-16 1999-03-16 Semiconductor integrated circuit device and process for manufacturing the same Expired - Lifetime CN1142586C (en)

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US6211003B1 (en) 2001-04-03
US20010021551A1 (en) 2001-09-13

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