CN1691354A

CN1691354A - Semiconductor device and image display device

Info

Publication number: CN1691354A
Application number: CN 200510065700
Authority: CN
Inventors: 丰田吉彦; 坂本孝雄; 須贺原和之; 中川直纪
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 2004-04-21
Filing date: 2005-04-21
Publication date: 2005-11-02
Anticipated expiration: 2025-04-21
Also published as: CN100505310C

Abstract

The objective is to provide a semiconductor device improved in source/drain withstand voltage and AC stress resistance, which thus achieves desired current properties, as well as its manufacturing method. A silicon nitride film 2 and a silicon oxide film 3 are formed on a glass substrate 1. Formed on the silicon oxide film 3 are a source region 45, a drain region 46, a channel region 40 having a specified channel length, a GOLD region 41 and a LDD region 43 each having impurities whose concentration is lower than that of the source region, a GOLD region 42 and a LDD region 44 each having impurities whose concentration is lower than that of the drain region, and a thin-film transistor T that includes a gate insulating film 5 and a gate electrode 6a. The gate electrode 6a is overlapped such that it is faced with the channel region 40 and COLD regions 41 and 42.

Description

Semiconductor device and image display device

Technical field

The present invention relates to semiconductor device and image display device, relate in particular to semiconductor device that in the display of LCD and organic EL (electroluminescence) display etc., uses and image display device with image displaying circuit portion.

Background technology

In display, use thin-film transistor.As an example of such thin-film transistor, the thin-film transistor of GOLD (the overlapping lightly doped drain of the grid) structure of putting down in writing is described in patent documentation TOHKEMY 2002-076351.The n type thin-film transistor of GOLD structure has source region, drain region, channel region, GOLD district, gate insulating film and gate electrode, forms on glass substrate.

The GOLD district on the zone between channel region and the drain region, especially is positioned on the zone under the gate electrode and forms, with gate electrode overlaid in the plane.The impurity concentration in this GOLD district is set for than the impurity concentration height in the channel region, and is lower than the impurity concentration in the drain region.

Below, the action of for example n type thin-film transistor of this GOLD structure is described.If on grid, apply the positive voltage of regulation, then on channel region, form raceway groove, the resistance between source region and the drain region reduces, and becomes the state that can flow through electric current between source region and drain region.

On the other hand, if apply negative voltage on grid, then do not form raceway groove on channel region, the resistance between source region and the drain region increases, and becoming does not have electric current to flow the state that has only small Leakage Current to flow through between source region and drain region in fact.

This Leakage Current is owing to the electronics of the hole that forms in raceway groove and a large amount of existence between source region and drain region are located at the junction surface again in conjunction with forming.If the electric field at junction surface increases, then the probability of combination also increases again, and Leakage Current increases.

In display, must remain on the voltage that applies on the liquid crystal in the image duration before rewriting picture.At this moment, keeping in the employed pixel transistor Leakage Current for a long time for this voltage, the voltage that applies on liquid crystal descends in time, the display characteristic deterioration.Therefore, in pixel transistor, require Leakage Current extremely low.

Below, as another example of the thin-film transistor that uses at display, the thin-film transistor of LDD (lightly doped drain) structure of putting down in writing is described in patent documentation TOHKEMY 2001-3554448.The n type thin-film transistor of LDD structure has source region, drain region, channel region, LDD district, gate insulating film and gate electrode etc. and forms on glass substrate.

On the zone between source region and the drain region, form the LDD district.In addition, the impurity concentration in LDD district is set for higher and lower than the impurity concentration in drain region than the impurity concentration of channel region.

In the thin-film transistor of LDD structure, if apply negative voltage, then on channel region, form accumulating layer, but leak near electric field because the LDD district has relaxed the source as gate voltage, can suppress Leakage Current.

But existing thin-film transistor has following problem.As mentioned above, in the thin-film transistor that uses as pixel transistor, require Leakage Current minimum.In thin-film transistor,, near impurity concentration source region higher and drain region, produce high electric field than the GOLD district if apply negative voltage as gate voltage then in the GOLD district, form accumulating layer as the GOLD structure of an example of thin-film transistor.Therefore, can not suppress Leakage Current, influential to the characteristic of the OFF electric current in the thin-film transistor.

In addition, by higher voltage on leaking, applying, on the junction surface of leaking side, produce bigger electric field than grid.Collide ionic phenomenon by the electron production that this electric field quickens, generate the right of electronics and hole.This phenomenon occurs repeatedly, electronics and hole to increasing, leakage current increases, until ablative degradation.The drain voltage of this moment is called the source and leaks withstand voltage.

In the thin-film transistor of above-mentioned GOLD structure,, can suppress to collide ionic phenomenon to a certain extent because near the electric field the drain region is relaxed at the place, junction surface in channel region and GOLD district.But the length (GOLD length) that exists in the GOLD district of realistic scale can not obtain sufficient source down and leak withstand voltage problem.

In addition, if on grid, apply positive and negative AC (alternating current) pulse, observed the deterioration in characteristics of thin-film transistor.The reliability at AC stress like this is to use distinctive phenomenon in the multicrystal thin-film transistor.The following describes this phenomenon.If on grid, apply negative voltage, produce big electric field on the junction surface between leak in grid and source, and locate captive charge carrier at multicrystal crystal boundary etc. and slowly emitted.The highfield at the place, electronics joint that is emitted quickens, and causes and collides the ionization phenomenon.

Owing to have high energy by the electron hole pair that collides the ionization generation, enter in the oxide-film above the potential barrier between gate oxidation films and the semiconductor.The high-octane electron hole pair that has like this is called hot carrier, enters and forms fixed charge in the oxide-film, locates to generate defective at the interface etc., makes the mobilance deterioration, makes the deterioration in characteristics of thin-film transistor.

Because near the electric field the drain region is relaxed by the junction surface in channel region and GOLD district in the thin-film transistor of existing GOLD structure, can suppress the generation of hot carrier to a certain extent.But it is low to exist under the GOLD length of realistic scale the reliability at AC stress, can not obtain the problem of sufficient hot carrier patience.

On the other hand, in another routine thin-film transistor, same problem is arranged also.That is,, can suppress the generation of hot carrier to a certain extent because near the electric field the drain region is relaxed by the junction surface in channel region and LDD district.But the LDD length (length in LDD district) that exists in realistic scale can not obtain down sufficient source and leak withstand voltage and at the reliability problems of AC stress.

In addition, form raceway groove if apply positive voltage as gate voltage on channel region, then the resistance in LDD district and channel resistance are connected in series.Because the impurity concentration in LDD district is lower than source region and drain region, exist the resistance value in LDD district to increase the problem that the ON electric current is low.

Like this, in existing thin-film transistor, exist and to obtain withstand voltage, the AC stress patience of sufficient source leakage, and can not get the problem of desirable OFF current characteristics or ON current characteristics (current characteristics).

Summary of the invention

The present invention proposes in order to address the above problem a little just, a purpose is to provide and can leaks semiconductor device withstand voltage and AC stress patience, the desirable current characteristics of acquisition in the raising source, and another purpose is to provide the image display device with the image displaying circuit portion that comprises such semiconductor device.

According to semiconductor device of the present invention, comprise have semiconductor layer, dielectric film and electrode and the semiconductor element that on the substrate of regulation, forms, wherein:

Above-mentioned semiconductor element has the 1st element, and the 1st element has:

The 1st impurity range that on above-mentioned semiconductor layer, forms;

Be separated with distance and the 2nd impurity range that on above-mentioned semiconductor layer, forms with above-mentioned the 1st impurity range;

Above-mentioned semiconductor layer on the part between above-mentioned the 1st impurity range and above-mentioned the 2nd impurity range, be separated with the channel region of raceway groove that conduct that distance forms has the channel length of regulation respectively with above-mentioned the 1st impurity range and above-mentioned the 2nd impurity range;

Above-mentioned semiconductor layer on the part between above-mentioned the 1st impurity range and the above-mentioned channel region, the 3rd impurity range that forms with above-mentioned channel region with joining;

Above-mentioned semiconductor layer on the part between above-mentioned the 2nd impurity range and the above-mentioned channel region, the 4th impurity range that forms with above-mentioned channel region with joining;

The 5th impurity range that on the part between above-mentioned the 1st impurity range and above-mentioned the 3rd impurity range, forms at above-mentioned semiconductor layer; And

The 6th impurity range that on the part between above-mentioned the 2nd impurity range and above-mentioned the 4th impurity range, forms at above-mentioned semiconductor layer;

In above-mentioned the 1st element,

Above-mentioned electrode has an opposed sidepiece and another sidepiece mutually,

The junction surface of above-mentioned the 3rd impurity range and above-mentioned the 5th impurity range and an above-mentioned sidepiece are positioned on the roughly same plane, and the junction surface of above-mentioned the 4th impurity range and above-mentioned the 6th impurity range and above-mentioned another sidepiece are in the same plane,

Above-mentioned electrode forms, and is mutually opposed and stacked with above-mentioned channel region, above-mentioned the 3rd impurity range and above-mentioned the 4th impurity range integral body separately,

Above-mentioned dielectric film forms respectively between above-mentioned semiconductor layer and above-mentioned electrode and joins with above-mentioned semiconductor layer and above-mentioned electrode,

That above-mentioned the 3rd impurity range to above-mentioned the 6th impurity range impurity concentration is separately set for is lower than above-mentioned the 1st impurity range and above-mentioned the 2nd impurity range impurity concentration separately, than the impurity concentration height of above-mentioned channel region, and

Above-mentioned the 3rd impurity range is set for different with the impurity concentration of above-mentioned the 5th impurity range and above-mentioned the 6th impurity range with the impurity concentration of above-mentioned the 4th impurity range.

According to this structure, in the zone between channel region and the 1st impurity range and on the zone between channel region and the 2nd impurity range, mutually opposedly form the 3rd impurity range and the 4th impurity range (GOLD district) with electrode, the impurity concentration of the 3rd impurity range and the 4th impurity range is lower than the impurity concentration of impurity concentration height, ratio the 1st impurity range (source) and the 2nd impurity range (leakage) of channel region; And, in the zone between the 1st impurity range and the 2nd impurity range and on the zone between the 2nd impurity range and the 4th impurity range, form the 5th impurity range and the 6th impurity range (LDD structure), the impurity concentration of the 5th impurity range and the 6th impurity range is lower than the impurity concentration of the 1st impurity range and the 2nd impurity range, than the impurity concentration height of channel region, thus, compare with the element of existing LDD structure, can obtain higher source and leak withstand voltage and AC stress patience, and obtain low OFF current characteristics.

According to image display device of the present invention, have the image displaying circuit portion of display image of being used for, wherein:

Above-mentioned image displaying circuit portion has the 1st element and the 2nd element,

The 1st element has:

The 1st impurity range that on above-mentioned semiconductor layer, forms;

The 2nd element comprises:

The 7th impurity range that on above-mentioned semiconductor layer, forms;

Be separated with distance and the 8th impurity range that on above-mentioned semiconductor layer, forms with above-mentioned the 7th impurity range;

Above-mentioned semiconductor layer on the part between above-mentioned the 7th impurity range and above-mentioned the 8th impurity range, be separated with the channel region of raceway groove that conduct that distance forms has the channel length of regulation respectively with above-mentioned the 7th impurity range and above-mentioned the 8th impurity range;

Above-mentioned semiconductor layer on the part between above-mentioned the 7th impurity range and the above-mentioned channel region, the 9th impurity range that forms with above-mentioned channel region with joining;

Above-mentioned semiconductor layer on the part between above-mentioned the 8th impurity range and the above-mentioned channel region, the 10th impurity range that forms with above-mentioned channel region with joining;

In above-mentioned the 1st element,

Above-mentioned the 3rd impurity range is set for different with the impurity concentration of above-mentioned the 5th impurity range and above-mentioned the 6th impurity range with the impurity concentration of above-mentioned the 4th impurity range;

In above-mentioned the 2nd element,

The junction surface of above-mentioned channel region and above-mentioned the 9th impurity range and an above-mentioned sidepiece are positioned on the roughly same plane, and the junction surface of above-mentioned channel region and above-mentioned the 10th impurity range and above-mentioned another sidepiece are in the same plane,

Above-mentioned electrode forms, and is mutually opposed and stacked with the integral body of above-mentioned channel region,

That above-mentioned the 9th impurity range and above-mentioned the 10th impurity range impurity concentration are separately set for is lower than above-mentioned the 7th impurity range and above-mentioned the 8th impurity range impurity concentration separately, than the impurity concentration height of above-mentioned channel region.

According to this structure, can obtain the source higher and leak withstand voltage and AC stress patience than the 1st element, and can obtain low OFF current characteristics, and, by using, compare the increase of the occupied area that can suppress image displaying circuit portion when only using the 1st element than the 2nd little element of the 1st element occupied area.

According to the manufacture method of semiconductor device of the present invention, comprise following operation:

Has formation the 1st electrode on the substrate of first type surface;

On substrate, form the 1st semiconductor layer of regulation;

In the operation that forms the 1st electrode with form between the operation of the 1st semiconductor layer, on substrate, form dielectric film;

Mode with crosscut the 1st semiconductor layer forms the 1st mask parts that comprises part 1 on the 1st semiconductor layer,

By inject the foreign ion of regulation conduction type to the 1st semiconductor layer as mask with the 1st mask parts, as channel region, form a pair of 1st impurity range (1st injection process) with regulation impurity concentration clipping the mode that the 1st mask parts is positioned on the part of the 1st semiconductor layer of a side and opposite side to join with channel region with the part that is positioned at the 1st semiconductor layer under the 1st mask parts;

Cover the each several part of whole channel region and a pair of the 1st impurity range, on the 1st semiconductor layer, form the 2nd mask parts that comprises part 1;

By with the 2nd mask parts as mask, inject the foreign ion of regulation conduction type to the 1st semiconductor layer, be positioned on the part of the 1st semiconductor layer of a side and opposite side clipping channel region, distinguish the distance ground that roller is separated with regulation with raceway groove and form other a pair of 2nd impurity range (2nd injection process) higher than the impurity concentration of the 1st impurity range;

In the operation that forms the 1st electrode with form in the operation of the 1st impurity range, each integral body and the 1st electrode that forms channel region and a pair of the 1st impurity range is overlapping and opposed.

According to this manufacture method and since with the 1st mask parts as mask with the 1st injection process formation a pair of the 1st impurity range as the GOLD district, just can easily form semiconductor device by only increasing a mask parts with GOLD district.And, by adjusting the size of the 1st mask parts, can easily adapt to variation of the length on the orientation of the 1st impurity range etc.

Above-mentioned purpose, feature, aspect and advantage with other of the present invention can more be expressly understood by the following detailed description that carries out in conjunction with the accompanying drawings.

Description of drawings

Fig. 1 is the profile of 1 semiconductor device according to the embodiment of the present invention;

Fig. 2 is a profile of showing an operation of the manufacture method of semiconductor device shown in Figure 1 in this execution mode;

Fig. 3 shows the profile of following the operation of operation shown in Figure 2 in this execution mode;

Fig. 4 shows the profile of following the operation of operation shown in Figure 3 in this execution mode;

Fig. 5 shows the profile of following the operation of operation shown in Figure 4 in this execution mode;

Fig. 6 shows the profile of following the operation of operation shown in Figure 5 in this execution mode;

Fig. 7 shows the profile of following the operation of operation shown in Figure 6 in this execution mode;

Fig. 8 shows the profile of following the operation of operation shown in Figure 7 in this execution mode;

Fig. 9 shows the profile of following the operation of operation shown in Figure 8 in this execution mode;

Figure 10 is that withstand voltage result's figure is leaked in the source of thin-film transistor in this execution mode of displaying;

Figure 11 is the figure that shows the result of the ON electric current of thin-film transistor in this execution mode;

Figure 12 is the figure that shows the result of the OFF electric current of thin-film transistor in this execution mode;

Figure 13 is the figure that shows the result of the AC stress patience of thin-film transistor in this execution mode;

Figure 14 shows in this execution mode the figure that the etching work procedure in the thin-film transistor of the thin-film transistor of GOLD structure according to the present invention and existing GOLD structure is compared;

Figure 15 is the profile of an operation of showing according to the embodiment of the present invention the manufacture method of 2 semiconductor device;

Figure 16 shows the profile of following the operation of operation shown in Figure 15 among this figure;

Figure 17 shows the profile of following the operation of operation shown in Figure 16 among this figure;

Figure 18 shows the profile of following the operation of operation shown in Figure 17 among this figure;

Figure 19 shows the profile of following the operation of operation shown in Figure 180 among this figure;

Figure 20 shows the profile of following the operation of operation shown in Figure 19 among this figure;

Figure 21 is that withstand voltage result's figure is leaked in the source of thin-film transistor in this execution mode of displaying;

Figure 22 is the figure that shows the result of the ON electric current of thin-film transistor in this execution mode;

Figure 23 is the figure that shows the result of the OFF electric current of thin-film transistor in this execution mode;

Figure 24 is the figure that shows the result of the AC stress patience of thin-film transistor in this execution mode;

Figure 25 is the profile of an operation of showing according to the embodiment of the present invention the manufacture method of 3 semiconductor device;

Figure 26 shows the profile of following the operation of operation shown in Figure 25 in this execution mode;

Figure 27 shows the profile of following the operation of operation shown in Figure 26 in this execution mode;

Figure 28 shows the profile of following the operation of operation shown in Figure 27 in this execution mode;

Figure 29 shows the profile of following the operation of operation shown in Figure 28 in this execution mode;

Figure 30 is a curve of showing according to the embodiment of the present invention the dependence of the impurity concentration of saturated deterioration rate and GOLD district in 4;

Figure 31 is a curve of showing according to the embodiment of the present invention the dependence of saturated deterioration rate and GOLD length in 5;

Figure 32 is a curve of showing according to the embodiment of the present invention the dependence of AC stress life and LDD length in 6;

Figure 33 is the curve of dependence of difference of showing according to the embodiment of the present invention the LDD length of ON electric current and source in 7 and leaking the LDD length of side;

Figure 34 is the profile of an operation of showing according to the embodiment of the present invention the manufacture method of 8 semiconductor device;

Figure 35 shows the profile of following the operation of operation shown in Figure 34 in this execution mode;

Figure 36 shows the profile of following the operation of operation shown in Figure 35 in this execution mode;

Figure 37 shows the profile of following the operation of operation shown in Figure 36 in this execution mode;

Figure 38 shows the profile of following the operation of operation shown in Figure 37 in this execution mode;

Figure 39 is that withstand voltage result's figure is leaked in the source of thin-film transistor in this execution mode of displaying;

Figure 40 is the figure that shows the result of the ON electric current of thin-film transistor in this execution mode;

Figure 41 is the figure that shows the result of the OFF electric current of thin-film transistor in this execution mode;

Figure 42 shows that according to the embodiment of the present invention source in 9 leaks the curve of dependence of the impurity concentration in withstand voltage and GOLD district;

Figure 43 is a curve of showing the dependence of the impurity concentration of AC stress life and GOLD district in this execution mode;

Figure 44 shows that according to the embodiment of the present invention source in 10 leaks the curve of dependence of the impurity concentration in withstand voltage and LDD district;

Figure 45 is a curve of showing the dependence of the impurity concentration of AC stress life and LDD district in this execution mode;

Figure 46 is a curve of showing the dependence of the impurity concentration of OFF electric current and LDD district in this execution mode;

Figure 47 shows that according to the embodiment of the present invention the curve of the dependence of withstand voltage and GOLD length is leaked in the source in 11;

Figure 48 is a curve of showing the dependence of AC stress life and GOLD length in this execution mode;

Figure 49 shows that according to the embodiment of the present invention the curve of the dependence of withstand voltage and LDD length is leaked in the source in 12;

Figure 50 is a curve of showing the dependence of AC stress life and LDD length in this execution mode;

Figure 51 is a curve of showing the dependence of OFF electric current and LDD length in this execution mode;

Figure 52 is a curve of showing the dependence of ON electric current and LDD length in this execution mode;

Figure 53 shows according to the embodiment of the present invention the profile of estimating in 13 with an operation of the manufacture method of semiconductor device;

Figure 54 shows the profile of following the operation of operation shown in Figure 53 in this execution mode;

Figure 55 shows the profile of following the operation of operation shown in Figure 54 in this execution mode;

Figure 56 shows ON electric current and the LDD length of source and the curve of the dependence of the difference of the LDD length of leaking side in this execution mode;

Figure 57 is a curve of showing the dependence of the difference of OFF electric current and LDD length in this execution mode;

Figure 58 is the plane graph of 14 semiconductor device according to the embodiment of the present invention;

Figure 59 is along the profile of the LIX-LIX of hatching shown in Figure 58 in this execution mode;

Figure 60 is the figure that shows the measurement result of OFF electric current in this execution mode;

Figure 61 is the profile of an operation of showing according to the embodiment of the present invention the manufacture method of 15 semiconductor device;

Figure 62 shows the profile of following the operation of operation shown in Figure 61 in this execution mode;

Figure 63 shows the profile of following the operation of operation shown in Figure 62 in this execution mode;

Figure 64 shows the profile of following the operation of operation shown in Figure 63 in this execution mode;

Figure 65 shows the profile of following the operation of operation shown in Figure 64 in this execution mode;

Figure 66 shows the profile of following the operation of operation shown in Figure 65 in this execution mode;

Figure 67 shows the profile of following the operation of operation shown in Figure 66 in this execution mode;

Figure 68 is the profile of an operation of showing according to the embodiment of the present invention the manufacture method of 15 semiconductor device;

Figure 69 shows the profile of following the operation of operation shown in Figure 61 in this execution mode;

Figure 70 shows the profile of following the operation of operation shown in Figure 69 in this execution mode;

Figure 71 shows the profile of following the operation of operation shown in Figure 70 in this execution mode;

Figure 72 shows the profile of following the operation of operation shown in Figure 71 in this execution mode;

Figure 73 shows the profile of following the operation of operation shown in Figure 72 in this execution mode;

Figure 74 shows the profile of following the operation of operation shown in Figure 73 in this execution mode;

Figure 75 shows the profile of following the operation of operation shown in Figure 74 in this execution mode;

Figure 76 is a block diagram of showing according to the embodiment of the present invention the structure of 17 liquid crystal indicator;

Figure 77 shows in this execution mode, according to the area of the occupied area of the thin-film transistor of GOLD structure of the present invention and the occupied area of the thin-film transistor of existing LDD structure than and the curve of the dependence of gate length;

Figure 78 is a block diagram of showing according to the embodiment of the present invention the structure of 18 liquid crystal indicator;

Figure 79 is a block diagram of showing according to the embodiment of the present invention the structure of 19 liquid crystal indicator;

Figure 80 is a block diagram of showing according to the embodiment of the present invention the structure of 20 liquid crystal indicator;

Figure 81 shows in this execution mode, according to the area of the occupied area of the thin-film transistor of GOLD structure of the present invention and the occupied area of the thin-film transistor of existing LDD structure than and the curve of the dependence of gate electrode number.

Embodiment

(execution mode 1)

1 semiconductor device according to the embodiment of the present invention is described.As shown in Figure 1, on glass substrate 1, form silicon nitride film 2, on this silicon nitride film 2, form silicon oxide layer 3.On this silicon oxide layer 3, form the polysilicon film of island.In this polysilicon film, form the source region 45 of impurity concentration and be separated with the drain region 46 of the impurity concentration with regulation of distance with this source region 45 with regulation.

On the zone between source region and drain region 45 and 46, be separated with the channel region 40 that distance forms the gate length with regulation respectively with source region and drain region 45 and 46.

On the zone between source region 45 and the channel region 40,45 sides form LDD district 43 in the source region, form GOLD district 41 in channel region 40 sides.In addition, on the zone between drain region 46 and the channel region 40,46 sides form LDD district 44 in the drain region, form GOLD district 42 in channel region 40 sides.

LDD district 43,44 and GOLD district 41,42 impurity concentration are separately all set impurity concentration height than channel region 40, lower than the impurity concentration in source region 45 and drain region 46 for.And the impurity concentration in LDD district 43,44 is set the impurity concentration height than GOLD district 41,42 for.

Formation makes it cover the polysilicon film of this island by the gate insulating film 5 that silicon oxide layer constitutes.On this gate insulating film 5, form gate electrode 6a.The interlayer dielectric 7 that formation is made of for example silicon oxide layer makes its covering grid electrode 6a.

Form the contact hole 7a on the surface of exposing source region 45 respectively and expose the contact hole 7b on the surface in drain region 46 at this interlayer dielectric 7, formation source electrode 8a and drain electrode 8b make it fill this

contact hole

7a, 7b on interlayer dielectric 7.

Thin-film transistor T comprises gate electrode 6a, source region 45, drain region 46, LDD district 43 and 44, GOLD district 41 and 42, channel region 40 and constitutes.Especially, form gate electrode 6a and cover whole channel region 40, and form GOLD district 41 and GOLD district 42 overlaid in the plane.

That is, the sidepiece of a side GOLD district 41 and the junction surface in LDD district 43 and gate electrode 6a is positioned on the roughly same plane H1, and another sidepiece of the junction surface in the opposing party's GOLD district 42 and LDD district 44 and gate electrode 6a is positioned on the same plane H2.

Below, an example of the manufacture method of above-mentioned semiconductor device is described.As shown in Figure 2, at first, on first type surface, form the silicon nitride film 2 of the about 100nm of thickness with for example plasma CVD (chemical vapor deposition) method as the glass substrate 1 of 1737 models of making by healthy and free from worry (Corning) company of substrate.On this silicon nitride film 2, form the silicon oxide layer 3 of the about 100nm of thickness.On this silicon oxide layer 3, form the amorphous state silicon fiml of the about 50nm of thickness then.

In addition,, the impurity that prevents to contain in the glass substrate 1 forms silicon nitride film 2 for spreading upward.As the film that is used for stoping this diffusion of impurities, except silicon nitride film, can also use SiON, SiC, AlN, Al ₂O ₃Deng material.In addition, be the double-decker of silicon nitride film 2 and silicon oxide layer 3 as the counterdie of amorphous state silicon fiml, but be not limited to double-layer structure, also can omit these films or stacked more film.

Then, by in specified vacuum, the amorphous state silicon fiml being implemented heat treatment, remove the unnecessary hydrogen that exists in the amorphous state silicon fiml.Then, by shining the laser that sends by for example XeCl laser, as shown in Figure 2,, become polysilicon film 4 amorphous state silicon fiml polycrystallization to the amorphous state silicon fiml.The particle diameter of polysilicon film 4 is about 0.5 μ m.

In addition, except the XeCl laser, can also use for example YAG laser, CW laser.Also can carry out the polycrystallization of amorphous state silicon fiml with thermal annealing.Particularly, when implementing thermal annealing, can obtain the bigger polysilicon film of particle diameter by the catalyst that uses nickel etc.On this polysilicon film 4, form photoresist pattern 61.

Then, as shown in Figure 3,, form the polysilicon film 4a of island by as mask polysilicon film 4 being carried out anisotropic etching with this photoresist pattern 61.Remove photoresist pattern 61 by carrying out the processing of ashing and soup afterwards.

Then, as shown in Figure 4, form the gate insulating film 5 that constitutes by silicon oxide layer of the about 100nm of thickness with plasma CVD method for example.At this moment, use the TEOS (tetraethylorthosilicise) of liquid as the raw material of silicon oxide layer.

Then, for the threshold value of control TFT, with for example dosage 1 * 10 ¹²Atom/cm ³, acceleration energy 60KeV injects boron to polysilicon film 4a.In addition, this injection process gets final product as required, also can omit.

Then, as shown in Figure 5, handle formation photoresist pattern 62 by the photomechanical process of implementing regulation.Pass through then with photoresist pattern 62 as for example dosage 5 * 10 of mask ¹²Atom/cm ³, acceleration energy 80KeV injects phosphorus to polysilicon film 4, forms impurity range 4ab, 4ac.

This injection rate becomes the injection rate (impurity concentration) in the GOLD district.Between impurity range 4ab and impurity range 4ac, form impurity range 4aa as raceway groove.Remove photoresist pattern 62 by carrying out the processing of ashing and soup afterwards.

Then, as shown in Figure 6, on the whole surface of gate insulating film 5, form the chromium film 6 of the about 400nm of thickness with sputtering method.Handle formation photoresist pattern 63 by carrying out photomechanical process then.

By as mask chromium film 6 being carried out wet etching, as shown in Figure 7, form gate electrode 6a with photoresist pattern 63.Gate electrode 6a forms, and clips the overlaid in the plane as the impurity range 4ab of the impurity range 4aa of raceway groove and impurity range 4ac.In impurity range 4ab, 4ac with the equitant in the plane zone of gate electrode 6a as the GOLD district.

In addition, though when carrying out wet etching, lateral erosion quarter has been carried out in the side of the chromium film 6 that exposes, can carry out the overetched time by control and control this etched amount.

Then, by with photoresist pattern 63 as mask, with dosage 1 * 10 for example ¹⁴Atom/cm ³, acceleration energy 80KeV injects phosphorus to impurity range 4ab, 4ac, forms impurity range 4ab, 4ac as source region and drain region.Remove photoresist pattern 63 by carrying out the processing of ashing and soup afterwards.

Then, as shown in Figure 8, by being mask, with for example dosage 1 * 10 with gate electrode 6a ¹³Atom/cm ³, acceleration energy 80KeV injects phosphorus, forms impurity range 4af, 4ag as the LDD district on remaining impurities district 4ab, 4ac respectively.As the impurity concentration of impurity range 4af, the 4ag in LDD district by the injection rate of this phosphorus be used for forming the injection rate decision of the phosphorus in GOLD district.

Like this, by forming impurity range 4af, 4ag, make impurity concentration as impurity range 4ab, the 4ac in GOLD district liken to into the impurity concentration of impurity range 4af, the 4ag in LDD district low.

Then, as shown in Figure 9, form the interlayer dielectric 7 that constitutes by silicon oxide layer of the about 400nm of thickness with plasma CVD method for example, with covering grid electrode 6a.By handling, form the photoresist pattern (not shown) that is used for forming contact hole then in the fixed photomechanical process of these interlayer dielectric 7 enterprising professional etiquettes.By as mask interlayer dielectric 7 and gate insulating film 5 being carried out anisotropic etching, form the contact hole 7a on the surface of exposing impurity range 4ad and expose the contact hole 7b on the surface of impurity range 4ae with this photoresist pattern.

Then, on interlayer dielectric 7, form the stacked film (not shown) of chromium film and aluminium film, with filling contact hole 7a, 7b.By handling, be formed for forming the photoresist pattern (not shown) of electrode in the fixed photomechanical process of the enterprising professional etiquette of this stacked film.By carrying out wet etching as mask, form source electrode 8a and drain electrode 8b then with this photoresist pattern.

Be formed as described above the major part of semiconductor device with thin-film transistor T.In this thin-film transistor T, impurity range 4ad is as source region 45, and impurity range 4ae is as drain region 46, and impurity range 4af, 4ag are as LDD district 43,44, and impurity range 4ab, 4ac are as GOLD district 41,42, and impurity range 4aa is as channel region 40.

This LDD district 43,44 has length L 1, the L2 on the orientation of regulation respectively, and GOLD district 41,42 has length G1, the G2 on the orientation of regulation respectively.The LDD length L 1 and the L2 in LDD district 43,44 are roughly the same, and the GOLD section length G1 and the G2 in GOLD district 41,42 are roughly the same.

The following describes in above-mentioned thin-film transistor T the withstand voltage result who obtains that measures is leaked in the source.Having used grid width in mensuration is 10 μ m, and effectively gate length is that the length on the orientation of 5 μ m, GOLD district 41 and 42 is that length on the orientation of 1 μ m, LDD district 43 and 44 is that length on the orientation of 0.5 μ m, gate electrode 6a is the thin-film transistor of 7 μ m.

On the other hand, in order to compare, as the thin-film transistor of existing LDD structure and the thin-film transistor of GOLD structure, having used grid width respectively is that 10 μ m, gate length are that length on the orientation in 5 μ m, LDD district is that the thin-film transistor of LDD structure of 0.5 μ m and grid width are that 10 μ m, gate length are that length on the orientation in 5 μ m, GOLD district is that length on the orientation of 1 μ m, gate electrode is the thin-film transistor of the GOLD structure of 7 μ m.

Showed leakage withstand voltage measurement result in source among Figure 10.Gate voltage is set 0V for during mensuration, source ground connection.And the drain voltage when leakage current is 0.1 μ A is defined as the source and leaks withstand voltage.As shown in figure 10, confirmed, realized that according to the thin-film transistor of the GOLD structure of execution mode 1 leaking withstand voltage higher source than the source of the thin-film transistor of the thin-film transistor of existing GOLD structure and LDD structure leaks withstand voltage.

The following describes the measurement result of ON electric current.During mensuration, source ground connection applies 8V respectively on grid, applies 5V on leaking.And the leakage current of measuring this moment as the ON electric current.The measurement result of this ON electric current is shown in Figure 11.As shown in figure 11, confirmed, in thin-film transistor, obtained the roughly the same ON electric current of ON electric current with the thin-film transistor of the existing LDD structure that has equal length as the LDD district according to the GOLD structure of execution mode 1.

The following describes the measurement result of OFF electric current.During mensuration, source ground connection applies 5V respectively on leaking, apply on grid-5V.And the leakage current of measuring this moment as the OFF electric current.The measurement result of this OFF electric current is shown in Figure 12.As shown in figure 12, confirmed, in thin-film transistor, obtained the low OFF electric current of OFF electric current than the thin-film transistor of existing GOLD structure according to the GOLD structure of execution mode 1.

The following describes the evaluation result of AC stress life.As the AC stress condition, gate voltage is ± 15V, and source voltage is 0V, and drain voltage is 0V, reaches stress time before 80% as the AC stress life with the ON electric current.This AC stress life the results are shown in Figure 13.

At this, each AC stress life is to represent as 1 o'clock relative value (ratio) according to the AC stress life of the thin-film transistor of execution mode 1 with handle.As shown in figure 13, confirmed, compared significantly prolongation with the thin-film transistor of LDD structure, distinguished the reliability that can improve thus at AC stress according to the AC stress life and the thin-film transistor of existing GOLD structure of execution mode 1.

Below, the evaluation of the impurity injection rate (impurity concentration) in the GOLD district of the thin-film transistor that forms with above-mentioned manufacture method and LDD district is described.At first, similarly made the evaluation sample with the occasion that forms thin-film transistor.That is, on glass substrate, form the silicon nitride film of the about 100nm of thickness, the silicon oxide layer of the about 100nm of thickness and the amorphous state silicon fiml of the about 50nm of thickness successively, this amorphous state silicon fiml has been carried out the laser annealing of regulation and handled.

Then, form the silicon oxide layer of the about 100nm of thickness, the ion that has carried out being used to form the phosphorus in GOLD district injects and is used to form the ion injection of the phosphorus in LDD district, has measured the amount of the impurity of injection with SIMS (ion microprobe).The result is that the amount of the impurity corresponding with the GOLD district is 5 * 10 ¹⁷Atom/cm ³, the amount of the impurity corresponding with the LDD district is 1.5 * 10 ¹⁸Atom/cm ³

This GOLD district is by forming as the foreign ion that mask injects with the photoresist pattern 62 that forms on gate insulating film 5.Different therewith, in the prior art, be that gate electrode is a double-layer structure, form the method in GOLD district by the underclad portion implanting impurity ion that clips taper as mask with top section.

But, in the method, when the etching of the top section that is used to form gate electrode, underclad portion also having been carried out etching, the bed thickness of underclad portion becomes inhomogeneous.Therefore, clip underclad portion carry out foreign ion when injecting the deviation of injection rate increase.In addition, owing to clip the metal material implanting impurity ion that constitutes gate electrode, injecting energy must be higher, the main cause that this deviation that becomes the injection rate of foreign ion further increases.

On the other hand, in above-mentioned method, by after forming gate insulating film, being used to form the injection of the foreign ion in GOLD district immediately, to the influential deviation of having only the thickness of gate insulating film of the injection rate of foreign ion.As a result, compare the deviation of the injection rate that can suppress foreign ion with existing occasion.

In addition, in existing method, the cone angle control of the length on the orientation in GOLD district (GOLD length) when forming upper electrode by etching.But, in the method,,, have the problem that is difficult to control GOLD length because of the deviation of cone angle and etching speed causes the variation of GOLD length big in the little occasion of cone angle.If the problem that reduces cone angle then also exist GOLD length to be restricted.

And, for gate electrode is formed taper, must react the deposit of the etching reaction of etched part and product in dry etching device inner equilibrium and carry out, exist the extremely difficult problem of control of etch process.

On the other hand, in said method,, have and freely to set GOLD length, improve the advantage of the size Control of GOLD length by being used to form the injection of the foreign ion in GOLD district as mask with the photoresist pattern.

Like this, in above-mentioned method of manufacturing thin film transistor, by after forming gate insulating film, be used for the injection of the foreign ion in GOLD district as mask with the photoresist pattern, injection rate controlled good, and can improve the controlled of GOLD length, improve the degree of freedom to GOLD length technology.

In addition, in above-mentioned thin-film transistor, become single layer structure, compare, can reduce the number of times that has comprised the etched etch process that is used to form gate electrode with existing occasion by making gate electrode.This is shown in Figure 14.As shown in figure 14, in thin-film transistor according to present embodiment, essential four etchings before finishing thin-film transistor, and essential six etchings in existing method.

Owing to be easy to generate particle (foreign matter) in etch process, this becomes the productivity ratio main reasons for decrease, by reducing the number of times of etch process, can boost productivity and manufacturing cost.

(execution mode 2)

At this, illustrate the impurity concentration occasion higher in GOLD district than the impurity concentration in LDD district.Its manufacture method at first is described.Up to formation gate insulating film 5 shown in Figure 15, inject and to be used for before the operation of impurity of regulation of threshold value of control TFT, all with identical up to above-mentioned operation shown in Figure 4.

Then, as shown in figure 16, handle formation photoresist pattern 64 on gate insulating film 5 by the photomechanical process of implementing regulation.Pass through then with photoresist pattern 64 as for example dosage 1 * 10 of mask ¹³Atom/cm ³, acceleration energy 80KeV injects phosphorus, forms impurity range 4ab, 4ac.This injection rate becomes the injection rate in the GOLD district.Remove photoresist pattern 64 by carrying out the processing of ashing and soup afterwards.

Then, as shown in figure 17, on the whole surface of gate insulating film 5, form the chromium film 6 of the about 400nm of thickness with sputtering method.Handle by the photomechanical process of on chromium film 6, implementing regulation then and form photoresist pattern 63.Photoresist pattern 63 forms and impurity range 4ab, 4ac overlaid.In impurity range 4ab, 4ac with photoresist pattern 63 equitant parts as the GOLD district.

Then, as shown in figure 18,, form gate electrode 6a by as mask chromium film 6 being carried out wet etching with photoresist pattern 63.Though when carrying out wet etching, lateral erosion quarter has been carried out in the side of the chromium film 6 that exposes, can carry out the overetched time by control and control this etched amount.

Then, by with photoresist pattern 63 as mask, with dosage 1 * 10 for example ¹⁴Atom/cm ³, acceleration energy 80KeV injects phosphorus, forms impurity range 4ad, 4ae as source region and drain region.Remove photoresist pattern 63 by carrying out the processing of ashing and soup afterwards.

Then, as shown in figure 19, by being mask, with for example dosage 5 * 10 with gate electrode 6a ¹²Atom/cm ³, acceleration energy 80KeV injects phosphorus, forms impurity range 4af, 4ag as the LDD district.This injection rate becomes the injection rate in the LDD district.At this moment, the impurity concentration in GOLD district is set for, than the impurity concentration height in LDD district, lower than the impurity concentration in source region and drain region.

Then, process and the identical operation of aforesaid operation shown in Figure 9 as shown in figure 20, form the thin-film transistor of the GOLD structure of n channel-type.

The following describes in above-mentioned thin-film transistor T the withstand voltage result who obtains that measures is leaked in the source.Having used grid width in mensuration is 10 μ m, and gate length is that the length on the orientation of 5 μ m, GOLD district 41 and 42 is that length on the orientation of 1 μ m, LDD district 43 and 44 is that length on the orientation of 0.5 μ m, gate electrode 6a is the thin-film transistor of 7 μ m.

Showed leakage withstand voltage measurement result in source among Figure 21.Condition determination is identical with aforesaid condition.As shown in figure 21, confirmed, realized that according to the thin-film transistor of the GOLD structure of execution mode 2 leaking withstand voltage higher source than the source of the thin-film transistor of the thin-film transistor of existing GOLD structure and LDD structure leaks withstand voltage.

The following describes the measurement result of ON electric current.Condition determination is identical with aforesaid condition.The measurement result of ON electric current is shown in Figure 22.As shown in figure 22, confirmed, in thin-film transistor, obtained the roughly the same ON electric current of ON electric current with the thin-film transistor of the existing LDD structure that has equal length as the LDD district according to the GOLD structure of execution mode 2.

The following describes the measurement result of OFF electric current.Condition determination is with aforesaid identical.The measurement result of OFF electric current is shown in Figure 23.As shown in figure 23, confirmed, in thin-film transistor, obtained the low OFF electric current of OFF electric current than the thin-film transistor of existing GOLD structure according to the GOLD structure of execution mode 2.

The following describes the evaluation result of AC stress life.Condition determination is identical with aforesaid condition.The AC stress life the results are shown in Figure 24.As shown in figure 24, confirmed, compared significantly prolongation with the thin-film transistor of LDD structure, distinguished the reliability that can improve thus at AC stress according to the AC stress life and the thin-film transistor of existing GOLD structure of execution mode 2.

Measured the GOLD district of the thin-film transistor that forms with above-mentioned manufacture method and the impurity injection rate (impurity concentration) in LDD district with the method identical with said method, the result is that the amount of the impurity corresponding with the GOLD district is 1 * 10 ¹⁸Atom/cm ³, the amount of the impurity corresponding with the LDD district is 5 * 10 ¹⁷Atom/cm ³

(execution mode 3)

At this, another example of the method for manufacturing thin film transistor that illustrated is described in execution mode 2.Up to formation gate insulating film 5 shown in Figure 25, inject and to be used for before the operation of impurity of regulation of threshold value of control TFT, all with identical up to above-mentioned operation shown in Figure 4.

Then, as shown in figure 26, handle formation photoresist pattern 62 on gate insulating film 5 by the photomechanical process of implementing regulation.Pass through then with photoresist pattern 62 as for example dosage 1 * 10 of mask ¹³Atom/cm ³, acceleration energy 80KeV injects phosphorus, forms impurity range 4ab, 4ac as the GOLD district.This injection rate becomes the injection rate in the GOLD district.Remove photoresist pattern 62 by carrying out the processing of ashing and soup afterwards.

Then, through the operation identical with operation shown in Figure 7, form photoresist pattern 63 and gate electrode 63a with aforesaid Fig. 6.Then, as shown in figure 27, by with photoresist pattern 63 as mask, with dosage 1 * 10 for example ¹⁴Atom/cm ³, acceleration energy 80KeV injects phosphorus, forms impurity range 4ad, 4ae as source region and drain region.Remove photoresist pattern 63 by carrying out the processing of ashing and soup afterwards.

Then, as shown in figure 28, by being mask, with for example dosage 4 * 10 with gate electrode 6a ¹²Atom/cm ³, acceleration energy 60KeV injects boron, forms impurity range 4af, 4ag as the LDD district.

At this moment, injecting n type impurity range 4ab, the 4ac of phosphorus, the part that has been injected into the boron of p type descends owing to the injection of p type impurity (boron) makes carrier concentration, thereby effectively impurity concentration descends.Thus, make as the impurity concentration of impurity range 4af, the 4ag in LDD district liken to for the impurity concentration of impurity range 4ab, the 4ac in GOLD district low.

That is, effective impurity concentration in LDD district by the ion injection rate that is used for forming the LDD district and the difference that is used for forming the ion injection rate in GOLD district determine.Thus, make the impurity concentration in GOLD district higher and lower than the impurity concentration in source region and drain region than the impurity concentration in LDD district.

Then, use and the identical operation of aforesaid operation shown in Figure 9, as shown in figure 29, form the thin-film transistor of the GOLD structure of n channel-type.Discovery with the thin-film transistor of said method manufacturing also can obtain with execution mode 2 in the identical characteristic of thin-film transistor of explanation.

The above-mentioned impurity concentration of setting the GOLD district for than the high semiconductor device of the impurity concentration in LDD district in, near leaking electric field is relaxed with the LDD district lower than GOLD district impurity concentration because of the junction surface in channel region and GOLD district, can obtain the leakage of sufficient source withstand voltage with AC stress patience.Deterioration rate when having applied stress depends on stress time, and the long more deterioration rate of stress time is also big more, but under certain deterioration rate value deterioration be saturated.The inventor is higher by the impurity concentration that makes the GOLD district, finds that deterioration is saturated under the few deterioration rate of deterioration.Thus, can make the characteristics of transistor long-term stability.In addition, because GOLD district and gate electrode also form raceway groove when forming raceway groove in the GOLD district, so the GOLD district can not produce harmful effect to the ON electric current.And when channel cutoff (OFF), near the electric field leak in the source can reduce the OFF electric current owing to the LDD district relaxes.

(definition) deterioration rate and saturated deterioration rate are described below successively.At first, by apply AC stress on thin-film transistor, the ON electric current reduces.So-called deterioration rate is exactly the slip of this ON electric current, if ON electric current reduction (deterioration amount) is Δ I, the initial value of electric current is I _o, the ON electric current after AC stress applies is I, then deterioration rate (Δ I/I _o) can be by AI/I _o=(I _o-I) I _oTry to achieve.If prolong the time that applies AC stress on thin-film transistor, then the carrying out of deterioration (minimizing of ON electric current) is saturated.So-called saturated deterioration rate is defined as the deterioration rate of this deterioration rate when saturated.In this manual, the deterioration rate is used to refer to the deterioration rate of the ON electric current under certain stress time.And saturated deterioration rate is the deterioration rate during with respect to stress time ON current saturation as mentioned above, and this value is a value intrinsic in the semiconductor device.In each evaluation result described later, showed this saturated deterioration rate and GOLD district impurity concentration dependence or with the dependence of GOLD length.

Below, the length on the orientation of length, source and leakage side on the orientation in the scope of impurity concentration when the impurity concentration that is described in detail in GOLD district in the semiconductor device in execution mode 4～7 is higher than the impurity concentration in LDD district, the GOLD district and the length on the orientation, LDD district poor.

(execution mode 4)

At this, the impurity concentration in the GOLD district in the thin-film transistor is described.In order to try to achieve the scope of impurity concentration, made all thin-film transistors of the impurity concentration variation in GOLD district, estimated its electrical characteristic.The grid width of this thin-film transistor is that 10 μ m, gate length are that length on the orientation in 5 μ m, GOLD district is that length on the orientation in 1 μ m, LDD district is that length on the orientation of 0.5 μ m, gate electrode is 7 μ m, and the impurity concentration in LDD district is half of impurity concentration in GOLD district, uses the method identical with the method that illustrated in the execution mode 2 to make.

Figure 30 has showed the curve of dependence of the impurity concentration in saturated deterioration rate when applying AC stress and GOLD district.As shown in figure 30, by the impurity concentration in GOLD district is set for 〉=1 * 10 ¹⁷Atom/cm ³And≤1 * 10 ¹⁹Atom/cm ³, can suppress saturated deterioration amount.Especially, the impurity concentration in GOLD district is 〉=5 * 10 ¹⁷And≤5 * 10 ¹⁸Atom/cm ³Scope in the time can suppress saturated deterioration amount.

(execution mode 5)

At this, the length on the orientation in the GOLD district in the thin-film transistor is described.For the scope of the length on the orientation of asking the GOLD district (GOLD length), make all thin-film transistors of GOLD length variations, estimated its electrical characteristic.

The grid width of this thin-film transistor is that 10 μ m, gate length are that length on the orientation in 5 μ m, LDD district is that length on the orientation in length on 0.5 μ m and the orientation that makes gate electrode and GOLD district correspondingly changes, and uses the method identical with the method for explanation in the execution mode 1 to make.In addition, the impurity concentration in GOLD district is 1 * 10 ¹⁸Atom/cm ³, the impurity concentration in LDD district is 5 * 10 ¹⁷Atom/cm ³

Figure 31 has showed the curve of the dependence of the length (GOLD length) on the orientation in saturated deterioration rate when applying AC stress and GOLD district.As shown in figure 31, if GOLD is shorter in length than 0.5 μ m, then can reduces saturated deterioration rate, suppress saturated deterioration amount.Because saturated deterioration amount has the tendency that reduces along with GOLD length prolongs, and wishes that GOLD length is longer, if but GOLD length surpasses 2 μ m, and saturated deterioration rate has saturated tendency.In addition, if because GOLD length increases, and transistorized size strengthens, so wish the GOLD length setting to be≤2 μ m.Like this, from the viewpoint of saturated deterioration amount and transistorized occupied area, wish GOLD length setting one-tenth 〉=0.5 μ m and≤2 μ m.

(execution mode 6)

At this, the length on the orientation in the LDD district in the thin-film transistor is described.For the scope of the length on the orientation of asking the LDD district (LDD length), make all thin-film transistors of LDD length variations, estimated its electrical characteristic.

The grid width of this thin-film transistor is that 10 μ m, gate length are that length on the orientation in 5 μ m, GOLD district is that length on 1 μ m and the orientation that makes gate electrode is 7 μ m, uses the method identical with the method for explanation in the execution mode 1 to make.In addition, the impurity concentration in GOLD district is 1 * 10 ¹⁸Atom/cm ³, the impurity concentration in LDD district is 5 * 10 ¹⁷Atom/cm ³

Figure 32 has showed the curve of the dependence of the length (LDD length) on the orientation in AC stress life and LDD district.Shown in figure 32, if LDD is shorter in length than 0.5 μ m, the AC stress life has the tendency that shortens.On the other hand, also can not change very much even LDD length surpasses 1.5 μ m AC stress life, the AC stress life has saturated tendency.In addition, the problem that the ON electric current reduces if existence LDD length prolongs wishes that the LDD length setting is≤1.5 μ m.Like this, from the viewpoint of AC stress life and ON electric current wish the LDD length setting be 〉=0.5 μ m and≤1.5 μ m.

(execution mode 7)

At this, the length on the orientation in LDD district of the source in the thin-film transistor is described and leaks the poor of length on the orientation in LDD district of side.If the length on the orientation in LDD district is different, then influential to the ON electric current with the leakage side at source.

Apply the voltage of regulation in source and leakage, during the ground connection of source, because the voltage drop that the LDD district of source causes, the voltage that the voltage ratio between grid and the source applies on grid is low.Cause because this voltage drop is the resistance by the LDD district of source, if the LDD length of source is longer than the LDD length in the LDD district of leakage side, then leakage current also descends.On this point, the difference of the LDD length of the LDD length of source and leakage side is little better.

So, for the LDD length of asking source with leak the scope of difference of the LDD length of side, make LDD length and leak side LDD length and certain, make all thin-film transistors of the LDD length variations of source, estimated its electrical characteristic.

The grid width of the thin-film transistor that uses in the evaluation is that 10 μ m, gate length are that length on the orientation in 5 μ m, GOLD district is that length on 1 μ m and the orientation that makes gate electrode is 7 μ m.In addition, the impurity concentration in GOLD district is 1 * 10 ¹⁸Atom/cm ³, the impurity concentration in LDD district is 5 * 10 ¹⁷Atom/cm ³

In addition, as method of manufacturing thin film transistor, in the manufacture method of the semiconductor device that in execution mode 2, illustrated, by injecting ion as mask with the photoresist pattern that is used for forming gate electrode, impurity range 4ad, 4ae (with reference to Figure 18) have been formed, in this following formation as source region and drain region.That is, after having formed gate electrode, remove the photoresist pattern, form the photoresist pattern that is used for forming source region and drain region.Then, carry out ion with this photoresist pattern as mask and inject, formed source region and drain region.Remove the photoresist pattern afterwards, be infused in by the ion that is used for forming the LDD district on whole of semiconductor layer and formed the LDD district.

Below, the result who measures the ON electric current in the thin-film transistor of making is in this wise described.Show the LDD length of ON electric current and source among Figure 33 and leaked the curve of dependence of poor (LDD length poor) of the LDD length of side.As shown in figure 33, if the difference of LDD length surpasses 0.3 μ m, then the tendency of ON electric current minimizing is remarkable, and it is big that the inclination angle of curve becomes.On this point, in order to ensure the ON electric current of regulation, the poor≤0.3 μ m of LDD length is preferred.

(execution mode 8)

At this, illustrate the thin-film transistor of p type.Up to formation gate insulating film 5 shown in Figure 34, inject and to be used for before the operation of impurity of regulation of threshold value of control TFT, all with identical up to above-mentioned operation shown in Figure 4.

Then, as shown in figure 35, handle formation photoresist pattern 62 on gate insulating film 5 by the photomechanical process of implementing regulation.Pass through then with photoresist pattern 62 as for example dosage 1 * 10 of mask ¹³Atom/cm ³, acceleration energy 60KeV injects boron, forms impurity range 4ab, 4ac as the GOLD district.This injection rate becomes the injection rate in the GOLD district.Remove photoresist pattern 62 by carrying out the processing of ashing and soup afterwards.

Then, through the operation identical with operation shown in Figure 7, form photoresist pattern 63 and gate electrode 6a with aforesaid Fig. 6.Then, as shown in figure 36, by with photoresist pattern 63 as mask, with dosage 1 * 10 for example ¹⁵Atom/cm ³, acceleration energy 60KeV injects boron, forms impurity range 4ad, 4ae as source region and drain region.Remove photoresist pattern 63 by carrying out the processing of ashing and soup afterwards.

Then, as shown in figure 37, by being mask, with for example dosage 5 * 10 with gate electrode 6a ¹³Atom/cm ³, acceleration energy 60KeV injects boron, forms impurity range 4af, 4ag as the LDD district.Thus, make the impurity concentration height of likening to for impurity range 4ab, the 4ac in GOLD district as the impurity concentration of impurity range 4af, the 4ag in LDD district, and liken to into the impurity concentration of impurity range 4ad, the 4ae in source region and drain region low.

Then, use and the identical operation of aforesaid operation shown in Figure 9, as shown in figure 38, form the thin-film transistor of the GOLD structure of p channel-type.

The following describes in above-mentioned thin-film transistor the withstand voltage result who obtains that measures is leaked in the source.Having used grid width in mensuration is 20 μ m, and effectively gate length is that the length on the orientation of 5 μ m, GOLD district 41 and 42 is that length on the orientation of 1 μ m, LDD district 43 and 44 is that length on the orientation of 0.5 μ m, gate electrode 6a is the thin-film transistor of 7 μ m.

On the other hand, in order to compare, as the thin-film transistor of existing LDD structure and the thin-film transistor of GOLD structure, having used grid width respectively is that 20 μ m, gate length are that length on the orientation in 5 μ m, LDD district is that the thin-film transistor of LDD structure of 0.5 μ m and grid width are that 20 μ m, gate length are that length on the orientation in 5 μ m, GOLD district is that length on the orientation of 1 μ m, gate electrode is the thin-film transistor of the GOLD structure of 7 μ m.

Showed leakage withstand voltage measurement result in source among Figure 39.Condition determination is identical with aforesaid condition.As shown in figure 39, confirmed, realized that according to the thin-film transistor of the GOLD structure of execution mode 8 leaking withstand voltage higher source than the source of the thin-film transistor of the thin-film transistor of existing GOLD structure and LDD structure leaks withstand voltage.

The following describes the measurement result of ON electric current.Condition determination is identical with aforesaid condition.The measurement result of ON electric current is shown in Figure 40.As shown in figure 40, confirmed, in thin-film transistor, obtained the roughly the same ON electric current of ON electric current with the thin-film transistor of the existing LDD structure that has equal length as the LDD district according to the GOLD structure of execution mode 8.

The following describes the measurement result of OFF electric current.Condition determination is with aforesaid identical.The measurement result of OFF electric current is shown in Figure 41.As shown in figure 41, confirmed, in thin-film transistor, obtained the low OFF electric current of OFF electric current than the thin-film transistor of existing GOLD structure according to the GOLD structure of execution mode 8.

Below, when the impurity concentration that is described in detail in GOLD district in the semiconductor device in execution mode 9～13 is lower than the impurity concentration in LDD district, the length on the orientation in the LDD district of length, source and leakage side on the scope of the length on the orientation in the scope of the impurity concentration in GOLD district, GOLD district, the impurity concentration in LDD district, the orientation in LDD district poor.

(execution mode 9)

At this, the impurity concentration in the GOLD district in the thin-film transistor is described.In order to try to achieve the scope of impurity concentration, made all thin-film transistors of the impurity concentration variation in GOLD district, estimated its electrical characteristic.The grid width of this thin-film transistor is that 10 μ m, gate length are that length on the orientation in 5 μ m, GOLD district is that length on the orientation in 1 μ m, LDD district is that length on the orientation of 0.5 μ m, gate electrode is 7 μ m.Make of the method identical with the method that illustrated in the execution mode 1.

In addition, the injection condition that is used for forming the foreign ion in LDD district is a dosage 1 * 10 ¹³Atom/cm ³, acceleration energy 80KeV.GOLD district and LDD district impurity concentration separately be resemble illustrated in the execution mode 1 measure and to obtain by carrying out SIMS, estimate based on the injection rate of foreign ion and the relation of impurity concentration.

Figure 42 has showed that the source leaks the curve of dependence of the impurity concentration in withstand voltage and GOLD district.As shown in figure 42, if the impurity concentration in GOLD district is higher than 1 * 10 ¹⁹Atom/cm ³, withstand voltage reduction is leaked in the source, leaks withstand voltage also low than the source in the thin-film transistor of existing GOLD structure.

On this point, as the impurity concentration in GOLD district, set for≤1 * 10 ¹⁹Atom/cm ³Be preferred, in order to ensure more stable withstand voltage, set for 〉=1 * 10 ¹⁷Atom/cm ³And≤1 * 10 ¹⁸Atom/cm ³Be preferred.

Below, in Figure 43, showed the curve of dependence of the impurity concentration in AC stress life and GOLD district.As shown in figure 43, as the impurity concentration in GOLD district, 〉=1 * 10 ¹⁷Atom/cm ³And≤1 * 10 ¹⁹Atom/cm ³Scope in obtained reasonable AC stress life.And, 〉=5 * 10 ¹⁷Atom/cm ³And≤1 * 10 ¹⁸Atom/cm ³Scope obtained better AC stress life.

Like this, leak the viewpoint of withstand voltage and AC stress life from the source, as the impurity concentration in GOLD district, set for 〉=1 * 10 ¹⁷Atom/cm ³And≤1 * 10 ¹⁹Atom/cm ³Be preferred.

(execution mode 10)

At this, the impurity concentration in the LDD district in the thin-film transistor is described.In order to try to achieve the scope of impurity concentration, made all thin-film transistors of the impurity concentration variation in LDD district, estimated its electrical characteristic.The grid width of this thin-film transistor is that 10 μ m, gate length are that length on the orientation in 5 μ m, GOLD district is that length on the orientation in 1 μ m, LDD district is that length on the orientation of 0.5 μ m, gate electrode is 7 μ m.Make of the method identical with the method that illustrated in the execution mode 1.

In addition, the injection condition that is used for forming the foreign ion in GOLD district is a dosage 5 * 10 ¹²Atom/cm ³, acceleration energy 80KeV.GOLD district and LDD district impurity concentration separately be resemble illustrated in the execution mode 1 measure and to obtain by carrying out SIMS, estimate based on the injection rate of foreign ion and the relation of impurity concentration.

Figure 44 has showed that the source leaks the curve of dependence of the impurity concentration in withstand voltage and LDD district.As shown in figure 44, if the impurity concentration in LDD district is higher than 5 * 10 ¹⁹Atom/cm ³, withstand voltage reduction is leaked in the source.

Like this, leak withstand voltage viewpoint from the source, as the impurity concentration in LDD district, set for≤5 * 10 ¹⁹Atom/cm ³Be preferred, in order to ensure more stable withstand voltage, set for≤1 * 10 ¹⁹Atom/cm ³Be preferred.

Below, in Figure 45, showed the curve of dependence of the impurity concentration in AC stress life and LDD district.As shown in figure 45, as the impurity concentration in LDD district ,≤5 * 10 ¹⁹Atom/cm ³Scope in obtained reasonable AC stress life.And, 1 * 10 ¹⁹Atom/cm ³Obtained better AC stress life.

Then, the curve of dependence of in Figure 46, having showed the impurity concentration in OFF electric current and LDD district.As shown in figure 46, the OFF electric current increases with the increase of the impurity concentration in LDD district, and from reducing the viewpoint of OFF electric current, the impurity concentration in LDD district is low to be preferred.From with last, as the impurity concentration in LDD district, set for≤5 * 10 ¹⁹Atom/cm ³Be preferred.

(execution mode 11)

The grid width of this thin-film transistor is that 10 μ m, gate length are that length on the orientation in 5 μ m, LDD district is that length on the orientation in length on 0.5 μ m and the orientation that makes gate electrode and GOLD district correspondingly changes, and uses the method identical with the method for explanation in the execution mode 1 to make.In addition, the impurity concentration in GOLD district is 5 * 10 ¹⁷Atom/cm ³, the impurity concentration in LDD district is 1.5 * 10 ¹⁸Atom/cm ³

Figure 47 has showed that the source leaks the curve of the dependence of withstand voltage and GOLD length.As shown in figure 47, if GOLD is shorter in length than 0.5 μ m, then withstand voltage rapid decline is leaked in the source.On the other hand, even GOLD length surpasses 2 μ m, withstand voltage also not too big variation is leaked in the source, and the withstand voltage saturated tendency that has is leaked in the source.

Then, the curve of having showed the dependence of AC stress life and GOLD length at Figure 48.As shown in figure 48, if GOLD is shorter in length than 0.5 μ m, then the AC stress life sharply descends.On the other hand, even GOLD length surpasses 2 μ m, the AC stress life is not too big variation also, and the AC stress life has saturated tendency.

Like this, leak the viewpoint of withstand voltage and AC stress life from the source, it is preferred that the GOLD length setting becomes 〉=0.5 μ m.On the other hand, if GOLD length surpasses 2 μ m, then the source leakage is withstand voltage all has saturated tendency with the AC stress life.And if GOLD length surpasses 2 μ m, big, occupied area increase that the size of thin-film transistor becomes becomes the main cause that hinders the semiconductor device miniaturization.From with last, the GOLD length setting become 〉=0.5 μ m and≤2 μ m are preferred.

(execution mode 12)

The grid width of this thin-film transistor is that 10 μ m, gate length are that length on the orientation in 5 μ m, GOLD district is that length on the orientation of 1 μ m, gate electrode is 7 μ m, uses the method identical with the method for explanation in the execution mode 1 to make.In addition, the impurity concentration in GOLD district is 5 * 10 ¹⁷Atom/cm ³, the impurity concentration in LDD district is 1.5 * 10 ¹⁸Atom/cm ³

Figure 49 has showed that the source leaks the curve of the dependence of withstand voltage and LDD length.As shown in figure 49, if LDD is shorter in length than 0.5 μ m, then the withstand voltage tendency that decline is arranged is leaked in the source.On the other hand, even LDD length surpasses 1.5 μ m, withstand voltage also not too big variation is leaked in the source, and the withstand voltage saturated tendency that has is leaked in the source.

Then, the curve of having showed the dependence of AC stress life and LDD length at Figure 50.As shown in figure 50, if LDD is shorter in length than 0.5 μ m, then the AC stress life has the tendency of decline.On the other hand, even LDD length surpasses 1.5 μ m, the AC stress life is not too big variation also, and the AC stress life has saturated tendency.

Then, the curve of having showed the dependence of OFF electric current and LDD length at Figure 51.Shown in Figure 51, if LDD is shorter in length than 0.5 μ m, then the OFF electric current has the tendency of increase.On the other hand, along with LDD length prolongs, the OFF electric current has the tendency that slowly reduces.

Then, the curve of in Figure 52, having showed the dependence of ON electric current and LDD length.Shown in Figure 52, along with LDD length prolongs, the ON electric current has the tendency that slowly reduces.If consider the tendency of OFF electric current, then in order to ensure the ON electric current of regulation and suppress the OFF electric current, it is preferred that the LDD length setting is become≤1.5 μ m.

Like this, leak the viewpoint of withstand voltage, AC stress life and OFF electric current from the source, it is preferred that the LDD length setting becomes 〉=0.5 μ m.On the other hand, from the viewpoint of ON electric current and OFF electric current, it is preferred that the LDD length setting becomes≤1.5 μ m.From with last, the LDD length setting become 〉=0.5 μ m and≤1.5 μ m are preferred.

(execution mode 13)

The grid width of the thin-film transistor that uses in the evaluation is that 10 μ m, gate length are that length on the orientation in 5 μ m, GOLD district is that length on 1 μ m and the orientation that makes gate electrode is 7 μ m.In addition, the impurity concentration in GOLD district is 5 * 10 ¹⁷Atom/cm ³, the impurity concentration in LDD district is 1.5 * 10 ¹⁸Atom/cm ³

At first, process and the identical operation of operation shown in Fig. 2 that illustrated at execution mode 1-7 shown in Figure 53, form gate electrode 6a with photoresist pattern 63 as mask.Just do not remove photoresist pattern 63 as the ion injection that mask is used to form source region and drain region afterwards with the photoresist pattern.

Then, shown in Figure 54, be pre-formed the photoresist pattern 65 that is used to form source region and drain region.This photoresist pattern 65 is patterned into, form the LDD length (L1) of source and leak side length (L2) and be 1 μ m (with reference to Figure 55), and the LDD length that makes source from 0.5 μ m to 0.05 μ m with the LDD district of the scale variation of 0.05 μ m.

As mask, form impurity range 4ad, 4ae with this photoresist pattern 65 as source region and drain region by injecting phosphorus.Remove photoresist pattern 65 afterwards.Then shown in Figure 55 again gate electrode 6a form impurity range 4af, 4ag as mask by injecting phosphorus as the LDD district.

Like this, formed as the LDD length L 1 of the impurity range 4af in the LDD district of source respectively and be 1 μ m as LDD length L 2 sums of the impurity range 4ag in the LDD district of leaking side, and the LDD length of impurity range 4af from 0.5 μ m to 0.05 μ m with the thin-film transistor of the evaluation usefulness of the scale variation of 0.05 μ m.

Below, the result who measures the ON electric current in the thin-film transistor of making is in this wise described.In addition, condition determination is identical with aforesaid condition.As the measurement result of ON electric current, showed the LDD length of ON electric current and source among Figure 56 and leaked the curve of dependence of poor (LDD length poor) of the LDD length of side.Shown in Figure 56, if the difference of LDD length surpasses 0.3 μ m, then the tendency of ON electric current minimizing is remarkable, and it is big that the inclination angle of curve becomes.On this point, in order to ensure the ON electric current of regulation, the poor≤0.3 μ m of LDD length is preferred.

Then, the curve of dependence of in Figure 57, having showed the difference of OFF electric current and LDD length.Shown in Figure 57, the OFF electric current does not have dependence with the difference of LDD length basically.From with last, poor as LDD length, set for≤0.3 μ m is preferred.

(execution mode 14)

At this, illustrate thin-film transistor as thin-film transistor with two gate electrodes.Two thin-film transistors have been formed in fact by having two gate electrodes, but the leakage by making a thin-film transistor and the source of another thin-film transistor are electrically connected, and one and another gate electrode are electrically connected, identical functions when on function, realizing with a thin-film transistor.

Structurally, on the polysilicon film of an island, form two thin-film transistor T for example shown in Figure 1.Promptly, shown in Figure 58 and 59, form two groups comprise impurity range 4ad respectively as the source region, as the impurity range 4ae in drain region, as the impurity range 4af in LDD district and 4ag, as the impurity range 4ab in GOLD district and 4ac, as the impurity range 4aa of channel region and the thin-film transistor of gate electrode 6a.Because structure in addition is identical with structure shown in Figure 1, so same parts is given identical Reference numeral and omitted its explanation.

In addition, above-mentioned thin-film transistor can be by only changing the pattern of the part corresponding with gate electrode, use with execution mode 1 in the identical manufacture method manufacturing of manufacture method that illustrated.

The following describes in above-mentioned thin-film transistor T the OFF electric current is measured the result who obtains.Having used grid width in mensuration is 10 μ m, and the gate length of each gate electrode is that the length on the orientation of 5 μ m, GOLD district 41 and 42 is that length on the orientation of 1 μ m, LDD district 43 and 44 is that length on the orientation of 0.5 μ m, each gate electrode is the thin-film transistor of 7 μ m.In addition, the impurity concentration in GOLD district is 5 * 10 ¹⁷Atom/cm ³, the impurity concentration in LDD district is 1.5 * 10 ¹⁸Atom/cm ³

Figure 60 has showed the measurement result of OFF electric current.Shown in Figure 60, compare according to the thin-film transistor that illustrated in the thin-film transistor of execution mode 14 and the execution mode 1, can further reduce the OFF electric current.Except the OFF electric current, the source leak withstand voltage and AC stress life all can reach with execution mode 1 in the identical level of thin-film transistor that illustrated.

In addition, in above-mentioned thin-film transistor illustrated the situation of two gate electrode 6a, but be not limited in this, in the zone that forms thin-film transistor,, can reduce the OFF electric current more by increasing the size that allows and the number of gate electrode.

(execution mode 15)

At this, illustrate the thin-film transistor of thin-film transistor with GOLD structure, LDD structure and the semiconductor device of common thin-film transistor.Its manufacture method at first is described.

At first, use with execution mode 1 in the identical method of method that illustrated, shown in Figure 61, on glass substrate 1, form silicon nitride film 2 and silicon oxide layer 3.On the silicon oxide layer 2 on the region R 1～R3 that is positioned at the regulation that will form thin-film transistor on the glass substrate 1, form the polysilicon film of island respectively.On region R 1～R3, form diverse thin-film transistor respectively.

Formation makes it cover this polysilicon film by the gate insulating film 5 that silicon oxide layer constitutes.Then, for the threshold value of control TFT, with for example dosage 1 * 10 ¹²Atom/cm ³, acceleration energy 60KeV injects boron to polysilicon film, forms the impurity range 4aa of island.

Then, shown in Figure 62, handle the photoresist pattern 62a that on region R 1, forms the thin-film transistor that is used for forming n type GOLD structure by the photomechanical process of implementing regulation, and in the region R 2 of the thin-film transistor that forms n type LDD structure with form on the region R 3 of common p type thin-film transistor and form the photoresist pattern 62b that covers these region R 2, R3.

By with photoresist pattern 62a, 62b as mask, with dosage 5 * 10 for example ¹²Atom/cm ³, acceleration energy 80KeV injects phosphorus to impurity range 4aa, forms impurity range 4ab, 4ac on region R 1.This injection rate becomes the injection rate in the GOLD district.Remove photoresist pattern 62a, 62b by carrying out the processing of ashing and soup afterwards.

Then, on the whole surface of gate insulating film 5, form the chromium film (not shown) of the about 400nm of thickness with sputtering method.Handle by the photomechanical process of implementing regulation then, on region R 3, form the photoresist pattern 63b that is used for to the gate electrode composition, and on region R 1 and R2, form the photoresist pattern 63a (with reference to Figure 63) that covers it.

Then, shown in Figure 63,, on region R 3, form gate electrode 6a by as mask the chromium film being carried out wet etching with this photoresist pattern 63a, 63b.In addition, their chromium film 6b of residual covering on region R 1 and R2.Remove photoresist pattern 63a, 63b by advancing the processing of ashing and soup afterwards.

Then, shown in Figure 64, by with residual chromium film 6b and gate electrode 6a as mask, with for example dosage 1 * 10 ¹⁵Atom/cm ³, acceleration energy 60KeV injects boron, forms impurity range 4ad, 4ae as the source region and the drain region of p type thin-film transistor on the impurity range 4aa that is positioned on the region R 3.At this moment, because region R 1 and R2 are covered by chromium film 6b, boron is not injected among these region R 1, the R2.

Handle by the photomechanical process of implementing regulation then, on region R 1 and R2, form photoresist pattern 66a, the 66b that is used for to the gate electrode composition, and on region R 3, form the photoresist pattern 66c (with reference to Figure 65) that covers this region R 3.

At this moment, the photoresist pattern 66a in the region R 1 and impurity range 4ab, 4ac form on overlaid ground in the plane.The equitant in the plane part of this photoresist pattern 66a and impurity range 4ab, 4ac is as the GOLD district.

Then, shown in Figure 65,, on region R 1 and region R 2, form gate electrode 6a respectively by as mask chromium film 66b being carried out etching with

photoresist pattern

66a, 66b, 66c.At this moment, the gate electrode 6a that on region R 1, forms and impurity range 4ab, 4ac overlaid in the plane.And the gate electrode 6a that forms on region R 3 is not because by photoresist pattern 66c covering, this gate electrode 6a has etched.

In addition, though when carrying out wet etching to carried out lateral erosion quarter as the side of the chromium film of gate electrode, can carry out the overetched time by control and control this etched amount.

Then, under the state of

residual photoresist pattern

66a, 66b, 66c, by with

photoresist pattern

66a, 66b, 66c as mask, with for example dosage 1 * 10 ¹⁴Atom/cm ³, acceleration energy 80KeV injects phosphorus, on the impurity range 4ab, the 4ac that are positioned on the region R 1, form respectively n type GOLD structure thin-film transistor as the impurity range 4ad in source region with as the impurity range 4ae in drain region.

In addition, on the impurity range 4aa that is positioned on the region R 2, form respectively n type LDD structure thin-film transistor as the impurity range 4ad in source region with as the impurity range 4ae in drain region.In addition, because region R 3 is covered by photoresist pattern 66c, do not inject phosphorus to region R 3.Remove

photoresist pattern

66a, 66b, 66c by carrying out the processing of ashing and soup afterwards.

Then, shown in Figure 66, by being mask, with for example dosage 1 * 10 with gate electrode 6a ¹³Atom/cm ³, acceleration energy 80KeV injects phosphorus, on the part that is positioned at residual impurity range 4ab, 4ac on the region R 1, form respectively n type GOLD structure thin-film transistor as the impurity range 4af in the LDD district of source with as the impurity range 4ag in the LDD district of leaking side.

In addition, on the part that is positioned at the remaining impurities district 4aa on the region R 2, form respectively n type LDD structure thin-film transistor as the impurity range 4af in the LDD district of source with as the impurity range 4ag in the LDD district of leaking side.

In addition, at this moment, though owing to also injected phosphorus as the source region of p type thin-film transistor and impurity range 4ad, the 4ae in drain region to being arranged in the zone on 3, the injection rate of phosphorus is enough littler than the injection rate of boron, so to inject phosphorus no problem to being positioned at impurity range 4ad, 4ae on the zone 3.

Then, use with execution mode 1 in the identical method of method that illustrated, shown in Figure 67, on glass substrate 1, form the interlayer dielectric 7 that constitutes by silicon oxide layer.By handling, form the photoresist pattern (not shown) that is used for forming contact hole then in the fixed photomechanical process of these interlayer dielectric 7 enterprising professional etiquettes.

By as mask interlayer dielectric 7 and gate insulating film 5 being carried out anisotropic etching, form the contact hole 7a that is positioned at the surface of exposing impurity range 4ad on region R 1～R3 respectively and expose the contact hole 7b on the surface of impurity range 4ae with this photoresist pattern.

Then, on interlayer dielectric 7, form the stacked film (not shown) of chromium film and aluminium film, with filling contact hole 7a, 7b.By handling, be formed for forming the photoresist pattern (not shown) of electrode in the fixed photomechanical process of the enterprising professional etiquette of this stacked film.By carrying out wet etching as mask, on region R 1～R3, form source electrode 8a and drain electrode 8b respectively then with this photoresist pattern.

As mentioned above, on region R 1, form the thin-film transistor T1 of n type GOLD structure, on region R 2, form the thin-film transistor T2 of n type LDD structure, on region R 3, form common p type thin-film transistor T3.

In the thin-film transistor T1 of n type GOLD structure, impurity range 4ad is as source region 45, and impurity range 4ae is as drain region 46, and impurity range 4ab, 4ac are as GOLD district 41,42, and impurity range 4af, 4ag are as LDD district 43,44.

In the thin-film transistor T2 of n type LDD structure, impurity range 4ad is as source region 45, and impurity range 4ae is as drain region 46, and impurity range 4af, 4ag are as LDD district 43,44.In p type thin-film transistor T3, impurity range 4ad is as source region 45, and impurity range 4ae is as drain region 46.

In above-mentioned manufacture method, except the effect that in execution mode 1, illustrated, also obtain following effect.At first, in existing method, if form the thin-film transistor of n type GOLD structure and common p type thin-film transistor, then can be to the source region of p type thin-film transistor and the n type impurity of drain region injection high concentration.Therefore, the problem that exists the resistance in the source region of p type thin-film transistor and drain region to increase.

Different therewith, in above-mentioned method, behind the source region and drain region that form p type thin-film transistor, when each source region of the thin-film transistor of thin-film transistor that forms n type GOLD structure respectively and n type LDD structure and drain region, form the zone of the thin-film transistor that covers the p type as the photoresist pattern of injecting mask.

Thus, do not inject the n type impurity of high concentration, the problem that can avoid the resistance in the source region of p type thin-film transistor and drain region to increase to the source region of p type thin-film transistor and drain region.

In addition, in existing method, in the time for example the length in GOLD district must being changed, except the change mask pattern, also must change the process conditions that are used for gate electrode is formed taper owing to the change of specification.Promptly, the process conditions that gate electrode is processed into taper must be adjusted the deposit reaction of etching reaction and reaction product, and because these reactions have big variation because of pattern and etching area, if the change mask pattern must preestablish and its matched optimum process condition.

Different therewith, in above-mentioned method,, can develop desirable semiconductor device at short notice owing to only change the change that the pattern of mask just can be realized GOLD length.

In addition, in above-mentioned method, though for example understand the thin-film transistor of single drain structure as p type thin-film transistor, but also can be behind the gate electrode that forms p type thin-film transistor, do not remove the photoresist pattern, the impurity that carries out source region and drain region injects, and removes the photoresist pattern then, the ion that is used to form the impurity in LDD district injects, and forms the p type thin-film transistor of LDD structure.

(execution mode 16)

At this, another example as the semiconductor device of the thin-film transistor of the thin-film transistor with GOLD structure, LDD structure and common thin-film transistor illustrates the also additional semiconductor device that the thin-film transistor of p type GOLD structure is arranged except the thin-film transistor of aforesaid n type GOLD structure.Its manufacture method at first is described.

At first, use with execution mode 1 in the identical method of method that illustrated, shown in Figure 68, on glass substrate 1, form silicon nitride film 2 and silicon oxide layer 3.On the silicon oxide layer 2 on the region R 1～R4 that is positioned at the regulation that will form thin-film transistor on the glass substrate 1, form the polysilicon film of island respectively.On region R 1～R4, form diverse thin-film transistor respectively.

Then, shown in Figure 69, handle the photoresist pattern 62a that on region R 3, forms the thin-film transistor that is used for forming p type GOLD structure by the photomechanical process of implementing regulation, and in the region R 1 of the thin-film transistor that forms n type GOLD structure with form on the region R 2 of thin-film transistor of n type LDD structure and form the photoresist pattern 62b that covers these region R 1, R2.In addition, on the region R 4 of the thin-film transistor that will form p type LDD structure, do not form the photoresist pattern especially.

By with this photoresist pattern 62a, 62b as mask, with dosage 1 * 10 for example ¹³Atom/cm ³, acceleration energy 60KeV injects boron to impurity range 4aa, forms impurity range 4ab, 4ac on region R 3.This injection rate becomes the injection rate in the GOLD district of p type thin-film transistor.Remove photoresist pattern 62a, 62b by carrying out the processing of ashing and soup afterwards.

Then, shown in Figure 70, handle the photoresist pattern 62a that on region R 1, forms the thin-film transistor that is used for forming n type GOLD structure by the photomechanical process of implementing regulation, and in the region R 2 of the thin-film transistor that forms n type LDD structure with form on the region R 3 of thin-film transistor of p type GOLD structure and form the photoresist pattern 62b that covers these region R 2, R3.In addition, on the region R 4 of the thin-film transistor that will form p type LDD structure, do not form the photoresist pattern especially.

By with this photoresist pattern 62a, 62b as mask, with dosage 5 * 10 for example ¹²Atom/cm ³, acceleration energy 80KeV injects phosphorus to impurity range 4aa, forms impurity range 4ab, 4ac on region R 1.This injection rate becomes the injection rate in the GOLD district of n type thin-film transistor.Remove photoresist pattern 62a, 62b by carrying out the processing of ashing and soup afterwards.

Then, on the whole surface of gate insulating film 5, form the chromium film (not shown) of the about 400nm of thickness with sputtering method.Handle by the photomechanical process of implementing regulation then, on region R 3, R4, form photoresist pattern 63b, the 63c that is used for to the gate electrode composition, and on region R 1 and R2, form the photoresist pattern 63a (with reference to Figure 71) that covers it.

Then, shown in Figure 71,, on region R 3, R4, form gate electrode 6a respectively by as mask the chromium film being carried out wet etching with this photoresist pattern 63a, 63b, 63c.In addition, their chromium film 6b of residual covering on region R 1 and R2.At this moment, the photoresist pattern 63b in the region R 3 and impurity range 4ab, 4ac form on overlaid ground in the plane.And, in impurity range 4ab, 4ac and the equitant in the plane part of gate electrode 6a as the GOLD district.

Then, under the state of residual photoresist pattern 63a, 63b, 63c, by with photoresist pattern 63a, 63b, 63c as mask, with for example dosage 1 * 10 ¹⁵Atom/cm ³, acceleration energy 60KeV injects boron, on the impurity range 4ab, the 4ac that are positioned on the region R 3, form respectively p type GOLD structure thin-film transistor as the impurity range 4ad in source region with as the impurity range 4ae in drain region.On the impurity range 4aa that is positioned on the region R 4, form respectively p type LDD structure thin-film transistor as the impurity range 4ad in source region with as the impurity range 4ae in drain region.

In addition, because the region R 2 of the thin-film transistor of the region R 1 of the thin-film transistor of formation n type GOLD structure and formation n type LDD structure is covered by photoresist pattern 63a, do not inject boron to region R 1, R2.Remove photoresist pattern 63a, 63b, 63c by carrying out the processing of ashing and soup afterwards.

Then, shown in Figure 72, by being mask, with for example dosage 5 * 10 with gate electrode 6a ¹³Atom/cm ³, acceleration energy 60KeV injects boron, on the part that is positioned at residual impurity range 4ab, 4ac on the region R 3, form respectively p type GOLD structure thin-film transistor as the impurity range 4af in the LDD district of source with as the impurity range 4ag in the LDD district of leaking side.In addition, on the part that is positioned at the remaining impurities district 4aa on the region R 4, form respectively p type LDD structure thin-film transistor as the impurity range 4af in the LDD district of source with as the impurity range 4ag in the LDD district of leaking side.

This impurity range 4af as the LDD district, the impurity concentration of 4ag are set for, liken the impurity concentration height into impurity range 4ab, the 4ac in GOLD district to, and liken to into the impurity concentration of impurity range 4ad, the 4ae in source region and drain region low.

Handle by the photomechanical process of enforcement regulation then, on region R 1 and R2, form photoresist pattern 63a, the 63b that is used for to the gate electrode composition, and on region R 3, R4, form covering this its photoresist pattern 63c, 63d (with reference to Figure 73).

Then, shown in Figure 73,, on region R 1 and region R 2, form gate electrode 6a respectively by as mask chromium film 66b being carried out wet etching with photoresist pattern 63a, 63b, 63c.Region R 3, R4 are owing to covered by photoresist pattern 63c, 63d, and gate electrode 6a does not have etched.

At this moment, the photoresist pattern 63a in the region R 1 and impurity range 4ab, 4ac form on overlaid ground in the plane.And among impurity range 4ab, the 4ac with the equitant in the plane part of gate electrode 6a as the GOLD district.

In addition, though, can carry out the overetched time by control and control this etched amount by carrying out wet etching to carried out lateral erosion quarter as the side of the chromium film of gate electrode.

Under the state of residual photoresist pattern 63a, 63b, 63c, by with photoresist pattern 63a, 63b, 63c as mask, with for example dosage 1 * 10 ¹⁴Atom/cm ³, acceleration energy 80KeV injects phosphorus, on the impurity range 4ab, the 4ac that are positioned on the region R 1, form respectively n type GOLD structure thin-film transistor as the impurity range 4ad in source region with as the impurity range 4ae in drain region.On the impurity range 4aa that is positioned on the region R 2, form respectively n type LDD structure thin-film transistor as the impurity range 4ad in source region with as the impurity range 4ae in drain region.

In addition, because the region R 4 of the thin-film transistor of the region R 3 of the thin-film transistor of formation p type GOLD structure and formation p type LDD structure is covered by photoresist pattern 63c, 63d, do not inject phosphorus to region R 3, R4.Remove photoresist pattern 63a, 63b, 63c by carrying out the processing of ashing and soup afterwards.

Then, shown in Figure 74, by being mask, with for example dosage 1 * 10 with gate electrode 6a ¹³Atom/cm ³, acceleration energy 80KeV injects phosphorus, on the part that is positioned at residual impurity range 4ab, 4ac on the region R 1, form respectively n type GOLD structure thin-film transistor as the impurity range 4af in the LDD district of source with as the impurity range 4ag in the LDD district of leaking side.In addition, on the part that is positioned at the remaining impurities district 4aa on the region R 1, form respectively n type LDD structure thin-film transistor as the impurity range 4af in the LDD district of source with as the impurity range 4ag in the LDD district of leaking side.

In addition, at this moment, though owing to also injected phosphorus with thin-film transistor impurity range 4ad, the 4ae etc. separately that are positioned on the region R 4 as source region and drain region as p type LDD structure to the thin-film transistor that is arranged on the region R 3 as p type GOLD structure, but the injection rate of phosphorus is enough littler than the injection rate of boron, so no problem to impurity range 4ad, the 4ae injection phosphorus that is positioned on zone 3 and the zone 4.

Then, use with execution mode 1 in the identical method of method that illustrated, shown in Figure 75, on glass substrate 1, form the interlayer dielectric 7 that constitutes by silicon oxide layer.By handling, form the photoresist pattern (not shown) that is used for forming contact hole then in the fixed photomechanical process of these interlayer dielectric 7 enterprising professional etiquettes.

By as mask interlayer dielectric 7 and gate insulating film 5 being carried out anisotropic etching, form the contact hole 7a that is positioned at the surface of exposing impurity range 4ad on region R 1～R4 respectively and expose the contact hole 7b on the surface of impurity range 4ae with this photoresist pattern.

Then, on interlayer dielectric 7, form the stacked film (not shown) of chromium film and aluminium film, with filling contact hole 7a, 7b.By handling, be formed for forming the photoresist pattern (not shown) of electrode in the fixed photomechanical process of the enterprising professional etiquette of this stacked film.By carrying out wet etching as mask, on region R 1～R4, form source electrode 8a and drain electrode 8b respectively then with this photoresist pattern.

As mentioned above, on region R 1, form the thin-film transistor T4 of n type GOLD structure, on region R 2, form the thin-film transistor T5 of n type LDD structure, on region R 3, form the thin-film transistor T6 of p type GOLD structure, on region R 4, form the thin-film transistor T7 of p type LDD structure.

In the thin-film transistor T4 of n type GOLD structure, impurity range 4ad is as source region 45, and impurity range 4ae is as drain region 46, and impurity range 4ab, 4ac are as GOLD district 41,42, and impurity range 4af, 4ag are as LDD district 43,44.

In the thin-film transistor T5 of n type LDD structure, impurity range 4ad is as source region 45, and impurity range 4ae is as drain region 46, and impurity range 4af, 4ag are as LDD district 43,44.

In the thin-film transistor T6 of p type GOLD structure, impurity range 4ad is as source region 45, and impurity range 4ae is as drain region 46, and impurity range 4ab, 4ac are as GOLD district 41,42, and impurity range 4af, 4ag are as LDD district 43,44.

In the thin-film transistor T7 of p type LDD structure, impurity range 4ad is as source region 45, and impurity range 4ae is as drain region 46, and impurity range 4af, 4ag are as LDD district 43,44.

In above-mentioned manufacture method, by only appending the mask of the gate electrode that is used to form p type thin-film transistor, just can form the thin-film transistor of n type GOLD structure, the thin-film transistor of n type LDD structure, the thin-film transistor of p type GOLD structure and the thin-film transistor of p type LDD structure simultaneously.

(execution mode 17)

At this, as the semiconductor device with thin-film transistor, enumerating liquid crystal indicator is that example describes.At first, the structure to liquid crystal indicator describes.

Shown in Figure 76, liquid crystal indicator comprises: be made of and the display part 21 of display image and being used for of being provided with on each of this a plurality of pixels 22 are controlled the scan line drive circuit portion 28 and the data line drive circuit portion 30 of the action of pixel section thin-film transistor 23 a plurality of pixels 22.By as the display part 21 of pixel section and as the scan line drive circuit portion 28 and the 30 composing images display circuit portions of data line drive circuit portion of the line drive circuit portion of the action of this display part of control.

Pixel 22 is configured to rectangular on display part 21.In pixel 22, filling liquid crystal (not shown) between pixel capacitors 24 and opposite electrode (not shown) and form pixel capacitance (not shown).The voltage that on liquid crystal, applies by the decision of the voltage that between pixel capacitors 24 and opposite electrode, applies.By the voltage that applies on this liquid crystal the ordered state of liquid crystal is changed, control sees through the light intensity of liquid crystal.In addition, between pixel section thin-film transistor 23 and common electrode 26, form maintenance electric capacity 25.

Data wire 29 that links to each other with data line drive circuit portion 30 and the scan line 27 that links to each other with scan line drive circuit portion 28, respectively be arranged in rectangular pixel 22 and be connected.From data line drive circuit portion 30 output pixel signals, this pixel signal that is output is input to pixel 22 by data wire 29.Select signal from scan line drive circuit portion 28 output images, the image that is output selects signal to be input to pixel 22 by scan line 27.

Scan line drive circuit portion 28 mainly comprises shift register and output circuit and constitutes, according to the clock enabling signal register shift of input.If register is high (H) level, then output circuit switches to the ON voltage of pixel 22.On the other hand, if register is low (L) level, then output circuit switches to the OFF voltage of pixel 22.Like this, scan line drive circuit portion 28 is applied to ON voltage and OFF voltage on the scan line of pixel 22 successively.

Data line drive circuit portion 30 latchs the signal (for example being 6 pixel data) of the pixel data that is transfused to successively according to the timing of clock signal, is taken in the data line drive circuit portion 30.The pixel data that is taken into is transformed into analog signal by the DA converter in the data line drive circuit portion 30.The pixel data that is transformed into analog signal is sent to data wire 29.

The grid of the pixel thin-film transistor 23 of the signal controlling pixel 22 that utilization is delivered to from scan line 27.To grid inputs ON signal, when the grid of pixel thin-film transistor become ON, the signal storage of sending here from data wire 29 pixel capacitance and maintenance electric capacity 25.Stored signal in an image duration of closing before grid are rewritten picture, remains in pixel capacitance and the maintenance electric capacity.

At this moment, if produce Leakage Current in the pixel thin-film transistor, the voltage that then applies on liquid crystal descended with the retention time, the display quality deterioration in the display part 21.Therefore, in the pixel thin-film transistor of display part 21, require to reduce as much as possible Leakage Current.That is, in the pixel thin-film transistor, require the OFF electric current low.

In addition, because the pixel thin-film transistor must be the state of complete OFF when closing grid, must on gate electrode, apply negative voltage.Like this, owing to when making pixel ON (connections), apply positive voltage, and apply negative voltage to grid when (ending) at OFF to grid, in the pixel thin-film transistor except require the OFF electric current hang down also demanding AC stress patience.

On the other hand, in the scan line drive circuit portion 28 and the part that is made of cmos circuit in the scan line drive circuit portion 30 of image display device, the grid to thin-film transistor do not apply negative voltage.Therefore, the AC stress patience that special requirement are not high in the thin-film transistor that uses in such circuit.

So, in image display device, use the thin-film transistor of the GOLD structure that for example in execution mode 1 grade, illustrated as the pixel thin-film transistor according to present embodiment.And as constituting, do not require that by cmos circuit the thin-film transistor of the circuit of high AC stress patience uses the thin-film transistor of existing LDD structure.

The thin-film transistor of the GOLD structure that illustrates in execution mode 1 grade is compared with the thin-film transistor of existing LDD structure, and the area that thin-film transistor occupies is big.So,, can suppress to form in the liquid crystal indicator increase of the area that the circuit part of thin-film transistor occupies by the thin-film transistor of suitable configuration GOLD structure and the thin-film transistor of LDD structure.

At this, the occupied area of the thin-film transistor of the thin-film transistor of this GOLD structure and LDD structure relatively particularly.At first, the grid width of the thin-film transistor of GOLD structure is that the length on the orientation in 10 μ m, GOLD district is that length on the orientation in 1 μ m, LDD district is 0.5 μ m.And the grid width of the thin-film transistor of LDD structure is a length on the orientation in 10 μ m, LDD district is 0.5 μ m.And the channel length of grid separately is 1～5 μ m.

Showed among Figure 77 according to the area of the occupied area of the thin-film transistor of the occupied area of the thin-film transistor of GOLD structure of the present invention and existing LDD structure than and the curve of the dependence of gate length.Shown in Figure 77, gate length is short more, and the occupied area of the thin-film transistor of LDD structure is compared the tendency that reduces with the occupied area of the thin-film transistor of GOLD structure.

Like this, by using the thin-film transistor of GOLD structure in the thin-film transistor that hangs down OFF electric current and high AC stress patience in the requirement of pixel thin-film transistor and so on, cmos circuit constitute and so on the loop that does not require the AC stress patience that the pixel thin-film transistor is so high in use the thin-film transistor of existing LDD structure, can be suppressed to minimum to the occupied area of the circuit in the image display device, and the inhibition effect that increases of this occupied area shortens with gate length and increases.

In addition, the thin-film transistor of having enumerated the GOLD structure that a gate electrode is arranged that illustrated as the pixel thin-film transistor in execution mode 1 is an example, but, can use for example thin-film transistor of the GOLD structure shown in Figure 58 and 59 with two gate electrodes as the thin-film transistor of GOLD structure.Especially, can further reduce the OFF electric current by having two gate electrodes, be preferred as the pixel thin-film transistor.

(execution mode 18)

At this, another example of the image display device of the thin-film transistor that has used the GOLD structure is described.Data line drive circuit portion 30 in the aforesaid image display device shown in Figure 78, is made of 30a of analog switching circuit portion and the 30b of logical circuit portion.

The clock of data-signal is sent in control to data wire 29 in the 30a of analog switching circuit portion.If the grid as the thin-film transistor of switch element among the 30a of analog switching circuit portion become the ON state,, write data-signal to the pixel of selecting by scan line 27 22 then to data wire 29 input signals.

Then, though thin-film transistor becomes the OFF state among the 30a of analog switching circuit portion, between all pixel 22 write signals that link to each other with scan line, import the ON signals to scan line 27.Therefore, during the selection of scan line 27, must keep signal, in thin-film transistor, require low OFF electric current as switch element to data wire 29 and pixel 22 inputs.

In addition, because the pixel thin-film transistor must be the state of complete OFF when closing grid, must on gate electrode, apply negative voltage.Like this, owing to apply positive voltage to grid during thin-film transistor ON (connections) in making the 30a of switching circuit portion, and apply negative voltage to grid when (ending) at OFF, in thin-film transistor except require the OFF electric current hang down also demanding AC stress patience.

So, in image display device according to present embodiment, in the 30a of analog switching circuit portion of composition data line drive circuit portion 30, use the thin-film transistor of the GOLD structure that for example in execution mode 1 grade, illustrated as the thin-film transistor of switch element.And, use the thin-film transistor of for example existing LDD structure as thin-film transistor as in the such circuit that does not require high AC stress patience of the 30b of logical circuit portion of composition data line drive circuit portion 30.

Like this, by in analog switching circuit portion, using the thin-film transistor of the low and GOLD structure that AC stress patience is high of OFF electric current, can suppress the deterioration of image.On the other hand, by in logical circuit portion, using the thin-film transistor of existing LDD structure, can suppress because the increase of the occupied area that the thin-film transistor of use GOLD structure causes.

In addition, as the thin-film transistor in the analog switching circuit portion, can use the thin-film transistor of the arbitrary type in p type and the n type.

(execution mode 19)

At this, the another example of the image display device of the thin-film transistor that has used the GOLD structure is described.Scan line drive circuit portion 28 in the aforesaid image display device shown in Figure 79, is made of the 28a of logical circuit portion, the 28b of booster circuit portion and the 28c of output circuit portion.

From the 28a of this logical circuit portion output gate select signal.Because is low from the gate select signal of the 28a of logical circuit portion output as voltage, in the 28b of booster circuit portion this signal voltage is boosted.Therefore, it is withstand voltage to require high source to leak in the thin-film transistor among the 28b of booster circuit portion.

Then, (H L) is further amplified in the 28c of output circuit portion and is outputed to scan line 27 signal after boosting.Therefore, the also demanding source of the thin-film transistor among the output circuit 28c is leaked withstand voltage.

So, in image display device according to present embodiment, in the 28b of booster circuit portion and the 28c of output circuit portion that constitute scan line drive circuit portion 28, use the thin-film transistor of the GOLD structure that for example in execution mode 1 grade, illustrated as thin-film transistor.And, use the thin-film transistor of for example existing LDD structure as thin-film transistor as in the such circuit that does not require high AC stress patience of the 28a of logical circuit portion that constitutes scan line drive circuit portion 28.

Like this, leak the thin-film transistor of withstand voltage high GOLD structure, can guarantee high driving force by use source in 28b of booster circuit portion and the 28c of output circuit portion.On the other hand, by in logical circuit portion etc., using the thin-film transistor of existing LDD structure, can suppress owing to use the increase of the occupied area that the thin-film transistor of GOLD structure causes.

(execution mode 20)

The occasion of using the thin-film transistor of GOLD structure in image display device as the thin-film transistor of the analog switching circuit portion in the data line drive circuit portion 30 has been described in execution mode 18.And the occasion of using the thin-film transistor of GOLD structure as the booster circuit portion in the scan line drive circuit portion 28 and the output circuit portion thin-film transistor in separately has been described in execution mode 19.

At this, use the thin-film transistor of GOLD structure to be prerequisite with thin-film transistor as the circuit part of afore mentioned rules, use the image display device of the thin-film transistor of LDD structure to describe to pixel thin-film transistor as pixel.

Shown in Figure 80, in image display device, at first, thin-film transistor as the switch element of the 30a of analog switching circuit portion in the data line drive circuit portion 30, use the thin-film transistor of GOLD structure, and, as the 28b of booster circuit portion in the scan line drive circuit portion 28 and the 28c of the output circuit portion thin-film transistor in separately, use the thin-film transistor of GOLD structure.

Then, used the thin-film transistor of LDD structure as the pixel thin-film transistor of display part 21.Especially, as the thin-film transistor of this LDD structure, used the thin-film transistor that for example has two gate electrodes.

In display part 21, the signal in order to keep writing to pixel capacitance and storage capacitors requires the OFF electric current low in thin-film transistor.And, in order to improve the transmitance of light, must increase the aperture opening ratio in the permeable zone of light as much as possible.In order to reduce the OFF electric current, it is effective having a plurality of gate electrodes as thin-film transistor.On the other hand, the occupied area of thin-film transistor increases.

Showed curve among Figure 81 according to the dependence of the occupied area of the thin-film transistor of the thin-film transistor of GOLD structure of the present invention and existing LDD structure and gate electrode number.From the curve shown in Figure 81 as can be seen, has the thin-film transistor of the GOLD structure of two gate electrodes for example and to have an occupied area of thin-film transistor of existing LDD structure of 3 gate electrodes roughly the same.

Therefore, in above-mentioned image display device,, can have more gate electrode, can help to reduce the OFF electric current by in the zone of limited pixel section, using the thin-film transistor of LDD structure as the pixel thin-film transistor.

Like this, in the liquid crystal indicator that in execution mode 18-20, illustrates, suitably dispose the thin-film transistor of GOLD structure and the thin-film transistor of LDD structure etc. by the specification that requires according to each circuit part, can bring into play the ability of liquid crystal indicator to greatest extent, simultaneously the increase of the occupied area of circuit part is suppressed to Min..

For example understand as thin-film transistor it is on the semiconductor layer that forms source region and drain region etc., to clip the thin-film transistor that gate insulating film has formed the so-called slab construction of gate electrode in the respective embodiments described above.

Thin-film transistor as GOLD structure according to the present invention, being not limited to the thin-film transistor of this slab construction, also can be to clip the thin-film transistor of gate insulating film formation as the contrary crossover structure of what is called of the semiconductor layer in source region and drain region etc. on gate electrode.Under this occasion also be, a sidepiece of a side GOLD district and the junction surface in LDD district and electrode is positioned on the roughly same plane, and another sidepiece of the opposing party's GOLD district and the junction surface in LDD district and electrode is in the same plane.

Though at length showed the present invention, this only is an illustration, is not construed as limiting.Obviously, the spirit and scope of the present invention are only determined by the scope of appended claims.

Claims

1. semiconductor device, comprise have semiconductor layer, dielectric film and electrode and the semiconductor element that on the substrate of regulation, forms, wherein:

The 1st impurity range that on above-mentioned semiconductor layer, forms;

On the part of the above-mentioned semiconductor layer between above-mentioned the 1st impurity range and above-mentioned the 2nd impurity range, be separated with the channel region of raceway groove that conduct that distance forms has the channel length of regulation respectively with above-mentioned the 1st impurity range and above-mentioned the 2nd impurity range;

In above-mentioned the 1st element,

2. semiconductor device as claimed in claim 1, wherein:

The impurity concentration of above-mentioned the 3rd impurity range and above-mentioned the 4th impurity range is set for lower than the impurity concentration of above-mentioned the 5th impurity range and above-mentioned the 6th impurity range.

3. semiconductor device as claimed in claim 2, wherein:

The impurity concentration of above-mentioned the 3rd impurity range and above-mentioned the 4th impurity range is 〉=1 * 10 ¹⁷Atom/cm ³And≤1 * 10 ¹⁹Atom/cm ³

4. semiconductor device as claimed in claim 2, wherein:

The impurity concentration of above-mentioned the 5th impurity range and above-mentioned the 6th impurity range is≤5 * 10 ¹⁹Atom/cm ³

5. semiconductor device as claimed in claim 2, wherein:

Length on the orientation of above-mentioned the 3rd impurity range and above-mentioned the 4th impurity range be 〉=0.5 μ m and≤2 μ m.

6. semiconductor device as claimed in claim 2, wherein:

Length on the orientation of above-mentioned the 5th impurity range and above-mentioned the 6th impurity range be 〉=0.5 μ m and≤1.5 μ m.

7. semiconductor device as claimed in claim 2, wherein:

The difference of the length on the orientation of length on the orientation of above-mentioned the 5th impurity range and above-mentioned the 6th impurity range is≤0.3 μ m.

8. semiconductor device as claimed in claim 1, wherein:

The impurity concentration of above-mentioned the 3rd impurity range and above-mentioned the 4th impurity range is set the impurity concentration height than above-mentioned the 5th impurity range and above-mentioned the 6th impurity range for.

9. semiconductor device as claimed in claim 1, wherein:

Be formed with a plurality of above-mentioned semiconductor elements,

Above-mentioned semiconductor element has the 2nd element, and the 2nd element comprises:

The 7th impurity range that on above-mentioned semiconductor layer, forms;

In above-mentioned the 2nd element,

10. image display device has the image displaying circuit portion of display image of being used for, wherein:

The 1st element has:

The 1st impurity range that on above-mentioned semiconductor layer, forms;

The 2nd element comprises:

The 7th impurity range that on above-mentioned semiconductor layer, forms;

In above-mentioned the 1st element,

In above-mentioned the 2nd element,

11. image display device as claimed in claim 10, wherein:

Above-mentioned image displaying circuit portion comprises:

Constitute and be used for the pixel section of display image by a plurality of pixels; With

Be used for making the drive circuit portion of above-mentioned pixel section action,

In above-mentioned pixel section and the above-mentioned drive circuit portion any used above-mentioned the 1st element.

12. image display device as claimed in claim 11, wherein:

Each of a plurality of above-mentioned pixels of above-mentioned pixel section is all used above-mentioned the 1st element,

Above-mentioned the 1st element has a plurality of above-mentioned electrodes.

13. image display device as claimed in claim 11, wherein:

Above-mentioned drive circuit portion comprises:

Have with above-mentioned pixel section and be connected, be used for the boost in voltage of picture signal and to the scan line drive circuit portion of the booster circuit portion of each transmission of the above-mentioned pixel of above-mentioned pixel section; With

Have with above-mentioned pixel section and be connected, be used for sending the data line drive circuit portion of the switching circuit portion of sweep signal to each of the above-mentioned pixel of above-mentioned pixel section,

In said switching circuit portion and the above-mentioned booster circuit portion any has used above-mentioned the 1st element at least.

14. image display device as claimed in claim 13, wherein:

Above-mentioned drive circuit comprises the circuit part of the regulation of having used above-mentioned the 2nd element.

15. image display device as claimed in claim 11, wherein:

Above-mentioned pixel section has been used above-mentioned the 2nd element.