CN100390960C - Non-volatile memory structure and method for manufacturing same - Google Patents
Non-volatile memory structure and method for manufacturing same Download PDFInfo
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- CN100390960C CN100390960C CNB2004100965881A CN200410096588A CN100390960C CN 100390960 C CN100390960 C CN 100390960C CN B2004100965881 A CNB2004100965881 A CN B2004100965881A CN 200410096588 A CN200410096588 A CN 200410096588A CN 100390960 C CN100390960 C CN 100390960C
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Abstract
In a fixed hydrocarbon memory of the present invention, a selecting gate is formed on the self-aligned partition wall positioned above the side wall formed by stacking up a floating and a controlling gate, and procedures that a selecting gate layer is removed above source lines (144), a groove insulating layer in a source line area is etched, the source lines are adulterated, etc. are carried out by using the same mask (1710). The memory can be formed at the inner part of a separate baseplate area or above the baseplate area; before the groove insulating layer is etched, at least partial source lines can be adulterated, and the baseplate area and a structure positioned below the baseplate area are isolated so as to avoid short circuit; the memory can be erased in a mode of a sector, or the operation is erased by executing wafers so as to erase in parallel all cell units; peripheral electric crystal grids and the selecting gate can be formed by the same layer, the partition wall of the selecting gate has extending objects, and the extending object is used as a low resistor through wires positioned above the extending object so as to contact; when a machine or a chemical machine carries out polished dressing for the insulating layer positioned above the machine or the chemical machine, and circuit elements positioned above the baseplate of a semiconductor can be protected by using an adjacent dotted placing structure.
Description
The application for application number be 01145049.5 applying date be December 31 calendar year 2001 denomination of invention be dividing an application of non-volatile memory structure and manufacture method thereof.
Technical field
The invention relates to a kind of semiconductor technology, refer to a kind of non-volatile memory architecture and manufacture method thereof especially.
Background technology
In the past when making non-volatile flash memory; regular meeting uses a kind of very typical technology-localized oxidation of silicon (local oxidation of Silicon; LOCOS) technology; to isolate and to come each element (as bit line) on the wafer; but the technology of localized oxidation of silicon tends to generate the oxide layer of beak shape; we must headspace to the structure of this protrusion; but the size of this projective structure has accounted for sizable ratio in bitline pitch; make interelement distance further to dwindle, the misalignment step becomes the principal element of limiting element size.In view of this, a kind of so-called shallow trench isolation from (shallow trench isolation, STI) technology in response to and give birth to, effectively improve this situation in self aligned mode.
Fig. 1 illustrates the U.S. Patent number 6,013,551 of people such as J.Chen at bulletin on January 11st, 2000, the manufacture method of the conventional non-volatile stacking gate flash memory of content description to Fig. 8.Growth silicon dioxide layer 108 above P doped silicon 150 (also can be described as tunnel oxide (tunnel oxide layer), can abbreviate oxide layer as in the following description), deposit a doped polysilicon layer 124 again at oxide layer 108 end faces, this polysilicon layer 124 will form the floating gate (floating gate) of memory cell transistor.
Then, form mask 106,, cause and in substrate 150, form a plurality of grooves 910 (as shown in Figure 2) via the downward etching polysilicon layer 124 of mask open, oxide layer 108 and substrate 150 on the surface of structure.
As shown in Figure 3, insert dielectric material in the groove 910 and cover total, its details step is: earlier with hot evaporating method growth silicon dioxide layer 90, then with plasma enhanced chemical vapor deposition method (plasma enhanced chemical vapor deposion, PECVD) deposition one silicon dioxide layer 94, the following again atmospheric chemical vapor deposition (subatomspheric chemicalvapor deposition, SACVD) the thicker silicon dioxide layer 96 of deposition one layer thickness.
Then to structure carry out cmp (chemical mechanical polishing, CMP) step, as shown in Figure 4, to expose polysilicon layer 124.
About cmp, we are in this explanation especially a little.Under patterned insulation layer maybe will deposit before one deck, the upper surface that needs planarization insulating layer, because so do the requirement that to relax the lithographic equipment depth of focus that is used for patterned insulation layer or upper layers, if the upper surface of insulating barrier is smooth, then we can accept the depth of focus bigger variability, and this is particular importances to making the small size article with lithographic equipment.
And chemical mechanical milling method is widely used in flatening process, because chemical mechanical milling method is very quick, does not also need at high temperature to carry out.
Handle insulating barrier with chemical mechanical milling method and normally stop at the harder one deck in insulating barrier below, give an example, when handling silicon dioxide layer with chemical mechanical milling method, can before forming silicon dioxide layer, deposit one deck silicon oxide layer earlier, as stopping layer, see also in the U.S. Patent number 5,909,628 " REDUCING NON-UNIFORMITY IN A REFILLLAYER THICKNESS FOR A SEMICONDUCTOR DEVICE " of bulletin on June 1st, 1999.
Then as shown in Figure 5, structurally form an ONO (silica, silicon nitride, silica) layer 98, deposit a silicon layer 99 then up, then deposit a tungsten silicide layer 100.
Form mask (not drawing) then, and above-mentioned 100,99,98,124 each layers (as shown in Figure 6) of patterning, this moment, polysilicon layer 124 will become floating gate, and silicon layer 99 and tungsten silicide layer 100 will become control gate (control gate) and word line (wordline) respectively.
As shown in Figure 8, then structurally form mask 101, utilize mask 101 etchings to remove the oxide layer 90,94,96 (as shown in Figure 7) of part, after the etching, keep mask 101, be used to inject alloy to form source electrode line 103.
The implantation step of carrying out other then is with suitable doped source zone and drain region.
Though said method can dwindle the size of memory,, still need dwindle the size of memory again along with the evolution of technology and the restriction of live width.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of manufacturing to comprise the method for the integrated circuit of nonvolatile memory, utilize autoregistration step repeatedly to form polysilicon layer (floating gate, control gate, selection grid), autoregistration and mutual arrangement mode by three's grid, can further reduce bit line pitch, the size of dwindling memory more significantly.
According to above-mentioned purpose, the method that the embodiment of the invention provides a kind of manufacturing to comprise the integrated circuit of nonvolatile memory, this method may further comprise the steps:
(a) form a ground floor on semiconductor regions S1, wherein integrated circuit comprises a plurality of non-volatile memory cells, and each memory cell has one by the formed floating gate of part ground floor;
(b) opening via above-mentioned ground floor forms groove in region S 1, and with the filling insulating material groove;
(C) form a ground floor on region S 1, wherein each unit has one by the formed conductive gate of the part second layer, and wherein conductive gate (conductive gate) is isolated with the floating gate of unit;
(d) the above-mentioned second layer of patterning stretches to rectangular (strip) of specific direction with formation, and each rectangular meeting is across a plurality of grooves;
(e) remove not part ground floor on the region S 1 that is covered by the second layer, to form a plurality of first structures, each first structure comprise one from the second layer form rectangular, and comprise the part ground floor of rectangular below, each first structure also has a first side wall;
(f) on the ground floor and the second layer, form one the 3rd layer, and utilize the 3rd layer of removing part to etching step such as non-, form partition at least a portion the first side wall of each first structure, each partition can be isolated with the first structural ground floor and the second layer;
(g) remove the 3rd layer of the part of subregion S1 top, not exclusively remove partition, wherein each unit comprises a formed conductive gate of part partition by first structure the first side wall top;
(h) in the region S 1 of at least a portion, mix alloy;
Step (g) and (h) be to utilize single photo etched mask technology to carry out wherein.
Other features and advantages of the present invention can have detailed introduction in the embodiment explanation, the real interest field of the present invention is defined by appended claim certainly.
Description of drawings
Fig. 1 to Fig. 7 is the process section of known flash memory;
Fig. 8 is the vertical view of Fig. 1 to Fig. 7 memory;
Fig. 9 A is the vertical view of the memory embodiment according to the present invention;
Fig. 9 B and Fig. 9 C are the profile of Fig. 9 A memory;
Figure 10 A is the circuit diagram of Fig. 9 A memory;
Figure 10 B is the vertical view of Fig. 9 A memory;
Figure 11 and Figure 12 A are the process section of Fig. 9 A memory;
Figure 12 B is the vertical view of Figure 12 A structure;
Figure 13 to Figure 15 is the process section of Fig. 9 A memory;
Figure 16 is the perspective view of Fig. 9 A memory in technology;
Figure 17 A to Figure 22 B is the process section of Fig. 9 A memory;
Figure 22 C is the vertical view of Figure 22 A and Figure 22 B structure;
Figure 23 A to Figure 24 C is the profile of memory embodiment of the present invention in technology;
Figure 25 to Figure 26 C is the profile of memory embodiment of the present invention;
Figure 27 to Figure 29 is the vertical view of memory embodiment of the present invention;
Figure 30 A and Figure 30 B are the profile of memory embodiment of the present invention;
Figure 30 C shows the mask layout of memory embodiment of the present invention;
Figure 31 A to Figure 33 B is the profile of memory embodiment of the present invention;
Figure 34 is the vertical view of memory embodiment of the present invention;
Figure 35 and Figure 36 are the process section of Figure 34 memory;
Figure 37 and Figure 38 are the vertical view of Figure 34 memory in technology
Figure 39 to Figure 41 is the process section of Figure 34 memory;
Figure 42 is the vertical view of memory embodiment of the present invention in technology;
Figure 43 is the calcspar that is used for the voltage generator of memory embodiment of the present invention;
Figure 44 to Figure 61 is the process section of memory embodiment of the present invention.
The figure number explanation:
98,1010,1810,2901,2903,3003: insulating barrier
98.1,98.3,1510,1810,2710,4408,4410: silicon dioxide layer
98.2,720,903,1203,2607: silicon nitride layer
103: source electrode line
108: tunnel oxide (can be silicon dioxide layer)
110: semiconductor structure
113: dielectric layer
120: memory cell
120S: select transistor
120F: floating gate transistor
124: floating gate (form by polysilicon, for cooperation illustrates, some the time can be called polysilicon layer, or unsteady grid line)
128: control gate (illustrate for cooperating, some the time be called the control grid line)
128.1: polysilicon layer
128.2: tungsten silicide layer
128A: part
130: bit line
133: regions and source
134,312: the bit line zone
138: the bit line contact area
141: empty interposed structure
144: source electrode line
144C, 29003C: contact openings
150: substrate regions
520: word line (form by polysilicon, for cooperation illustrates, some the time can be called polysilicon layer, or select grid)
520E: lateral projection
710: the stacked structure (or being called array structure) that comprises floating gate and control gate
901: storage array
904,1014,1710,2501,2810,4501,4601,4801: the photoresist mask
905: substrate
910: isolated groove
1103,1105:N-zone
1107,2709: the zone
1603: the neighboring area
1810: grid oxic horizon
2110,2401: inject
2605: electric conducting material
2701,3010: the gap
2703.1,2703.2: the storage array section
2903: metal tape
3301: disilicide layer
4201: voltage generator
4402,4404,4406,4404D: active region
Embodiment
The narration of relevant preferred embodiment is to illustrate and unrestricted usefulness, unless Wen Zhongyou indicates especially, not so the present invention is not limited to any special size, material, program step, alloy, doping content, crystallization position to, each layer thickness, layout or other element characteristics.
Fig. 9 A is the vertical view of the flash display of autoregistration three grid memory cell 120, Fig. 9 B is the profile along the line 9B-9B incision of Fig. 9 A, Fig. 9 C is that Figure 10 A is the circuit diagram of array along the profile of the line 9C-9C incision of Fig. 9 A, and Figure 10 B is the vertical view of other newly-increased features of explanation.
Bit line among the figure (bit lines) the 130th, horizontal expansion, bit line 130 is (as aluminium or tungsten by the conductive layer that is positioned at memory cell 120 tops, do not draw) form, bit line 130 contacts in bit line contact area 138 with the bit line zone 134 of memory cell 120, source electrode line (sourcelines) the 144th extends longitudinally in 710 of adjacent array structures, each array structure 710 comprises one and controls grid line (control gate Line) 128 longitudinally, control gate as each array storage unit, control grid line 128 in the present embodiment is made up of polysilicon layer 128.1 and tungsten silicide layer 128.2, floating polysilicon moving grid 124 is positioned at the below of control gate 128, each floating gate is positioned at adjacent isolated groove 910 grid, and 910 of grooves are laterally to be positioned at 130 of bit lines.
Each array structure 710 all is that autoregistration is piled up.
Word line 520 (as doped polysilicon layer) and bit line 130 vertical (or being a special angle), each bar word line 520 can be as the selection grid of an array storage unit, each word line 520 is the autoregistration partitions that form on the sidewall of corresponding stacked structure 710, word line 520 separates by silica partition 903 and silicon dioxide layer 1510 and adjacent control gate 128 and floating gate 124, and 903 and 1510 layers only do not need mask to generate.
Shown in Figure 10 A, the memory cell of each row has two unit 120 at 130 adjacent of two bit lines, wherein a control grid line 128 and a word line 520 are shown in each storage, two adjacent memory rows are shared a source electrode line 144, in each memory cell 120, a NMOS selects transistor 120s and a floating gate transistor 120F polyphone, selects the grid of transistor 120s to be provided by word line 520, and the control gate of floating gate transistor 120F is then provided by control grid line 128.
We can by from floating gate 124 through silicon dioxide layer 108 to the Fowler-Nordheim electrons tunnel of source electrode line 144 or substrate regions 150 with each unit of erasing (zone 150 comprises the channel region of memory cell), and the unit is stylized by the hot electron injection of source terminal, this noun " injection of source terminal hot electron " is that the bit line zone 134 of hypothesis unit is " source electrode ", in another case, if this zone is drain electrode, then source electrode line zone 144 is exactly a source electrode, the zone 134 and 144 can be called as regions and source, we especially term limit the present invention.
Memory is inside and the top (as shown in figure 11) that is formed at the independent p type island region territory 150 of silicon substrate 905, silicon substrate 905 is formed by monocrystalline silicon or other semi-conducting materials, in certain embodiments, the end face of substrate 905 has a crystal orientation＜100 〉, this substrate mixes with boron, and concentration is that 2E15 is to 2E16atom/cm
3
The generation method of above-mentioned zone 150 is as follows: in substrate 905, inject N type alloy via mask open with ion implantation, and forming N-zone 1103, can area of isolation 150 and following square structure, give an example, with energy and the 1.0E13atom/cm of 1.5MeV
2Dosage inject phosphorus.
In an independent ion implantation step or a series of ion implantation step, use other mask (not drawing) to inject N type alloy to form N-zone 1105, N-zone 1105 is surrounded zone 150 fully, in certain embodiments, this step can produce N well (not drawing) simultaneously, will form the periphery P MOS transistor of peripheral circuit within it, this class circuit has sensing amplifier, input/output driver, decoder, voltage generator or the like, in the CMOS technology, producing this class N well is known technology.
When memory operates, N-zone 1103 is identical or higher with the voltage of substrate regions 150 with 1105 voltage, the reference voltage of following table 1 viewing area 150, the voltage in the zone 1107 of the substrate 905 then voltage with zone 1103 and 1105 is identical or lower, in certain embodiments, make zone 150,1103, the 1105 formation short circuits that are connected together, make regional 1107 ground connection in addition.
The present invention is not particularly limited the isolation technology in zone 150, and also not limiting is the memory with separate substrates zone.
Shown in Figure 12 A, generate silicon dioxide layer (or be called tunnel oxide, below abbreviate oxide layer sometimes as) 108 at the end face of substrate regions 150 with thermal oxidation method, in certain embodiments, be the grow up oxide layer of thick 9nm of about 800 ℃ dry type oxidation process.
Then, form polysilicon layer 124 at oxide layer 108 end faces, in certain embodiments, be with Low Pressure Chemical Vapor Deposition (low pressure chemical vapor deposition, LPCVD) polysilicon layer 124 of deposition one bed thickness 120nm slightly mixed by (N type) at that time or afterwards in deposition, and above-mentioned polysilicon layer 124 can be as floating gate, perhaps can be as other circuit elements of peripheral circuit, this class component has intraconnections, transistor gate, resistor, capacitor board or the like.
End face at polysilicon layer 124 continues deposition one silicon nitride layer 1203, in certain embodiments, it is the nitride that deposits a bed thickness 120nm with Low Pressure Chemical Vapor Deposition, if necessary, also can above polysilicon layer 124, form layer of silicon dioxide layer (not drawing) and so can lower stress in elder generation before the depositing nitride.
Above silicon nitride layer 1203, form photoresist mask 904 then with photoetching technique, and from mask open etches both silicon nitride layer 1203 and polysilicon layer 124, form and equidirectional rectangular (strip) that passes storage array of bit line whereby, in the vertical view of Figure 12 B, " BL " axle points to the direction of bit line, and " WL " axle points to the direction of word line, in certain embodiments, be with reactive ion-etching (reactive ion etching process, RIE) etching polysilicon layer 124 and silicon nitride layer 1203.
Can not influence cell geometry even if photoresist mask 904 is aimed at yet,, only need be adjusted at the part in array edges and neighboring area (zone at peripheral circuit place) yet even need to adjust.
After the etching polysilicon layer 124, opening etching oxide layer 108 and substrate regions 150 from photoresist mask 904, to form isolated groove 910 (as shown in figure 13), the isolated groove of peripheral circuit (not drawing) also is to form in this step, etching mode then can be selected reactive ion-etching, and gash depth is about 0.25mm.
Remove photoresist mask 904 then.
Utilize mask etching two-layer or sandwich construction as long as mention here, unless mention especially, otherwise be to utilize this mask only to understand the etching the superiors, after the superiors are etched, remove mask, and then with the superiors that retain as mask, the layer that etching is remaining, or do not need mask, for instance, after the etches both silicon nitride layer 1203, remove resistance mask 904 earlier, be used as mask with silicon nitride layer 1203 then, the polysilicon layer 124 under the etching, oxide layer 108, substrate 150, the silicon nitride layer 1203 that has part is simultaneously etched, but is not to remove fully.
With trench dielectric material filling groove 910 to form an insulating barrier 1010 and to cover wafer (as shown in figure 13), in certain embodiments, insulating barrier 1010 can be generated by following method: above the exposed surface of groove 910 with known rapid thermal oxidation method (rapid termal oxide, RTO) one silica layer of generation one bed thickness 13.5nm, and then use high-density plasma (highdensity plasma, HDP) chemical vapour deposition technique (chemical vapor deposition, CVD) silicon dioxide layer of deposition one bed thickness 480nm.
Then utilize chemical mechanical milling method (CMP) and/or some comprehensive etch processs (blanketetch process) etching to remove partial insulative layer 1010, till exposing silicon nitride layer 1203 (as shown in figure 14), wherein silicon nitride layer 1203 is as etching stopping layer in this step.Remove silicon nitride layer 1203 (as in the wet etching mode) then, or insulating barrier 1010 also etched away, this can utilize regularly wet etching (timed wet etch), last structure can be as shown in figure 15, one smooth superstructure is arranged, or be the sidewall that etching isolation layer 1010 can expose polysilicon layer 124, this can improve the efficient of memory cell, and we will be in hereinafter explanation.
Then, form insulating barrier 98 (shown in Fig. 9 B and Fig. 9 C) in certain embodiments, insulating barrier 98 is oxygen nitrogen oxide (oxide-nitride-oxide, ONO) structure, its formation method is: at first, under 800 ℃ or lower temperature, adding thermosetting silicon dioxide layer 98.1 (as shown in figure 16) with dry type oxidation process above the polysilicon layer 124, the reference thickness of silicon dioxide layer 98.1 is 6nm, deposit the silicon nitride layer 98.2 of a bed thickness 4nm then with Low Pressure Chemical Vapor Deposition, then add thermosetting silicon oxide layer 98.3 being lower than under 850 ℃ the temperature with wet oxidation process.
In Figure 16,98.3 whiles of silicon dioxide layer are as the gate insulator of peripheral transistor, before forming silicon dioxide layer 98.3, on storage array, form photoresist mask (not drawing) earlier, mask does not cover neighboring area 1603, etch away 98.2 of neighboring area 1603,98.1,124,108 each layers are to expose substrate 905, remove mask then, the oxidation wafer is to generate silicon dioxide layer 98.3, the reference thickness of 1603 silicon dioxide layer 98.3 is 24nm in the neighboring area, one silica layer 98.3 above memory area silicon nitride layer 98.2 then is that 1nm is thick, one silica layer 98.3 on silicon nitride layer 98.2 is thinner, and this is because the growth speed ratio of silicon dioxide on nitride wants slow on silicon substrate 905.
Above insulating barrier 98, form polysilicon layer 128.1, in certain embodiments, deposit the polysilicon layer 128.1 of a bed thickness 80nm with Low Pressure Chemical Vapor Deposition, mixed with N+ or P+ at that time or afterwards in deposition, deposit tungsten suicide layers 128.2 then, and its reference thickness is 50nm, tungsten silicide layer 128.2 can form by chemical vapour deposition technique, follow deposited silicon nitride layer 720 above wafer, nitration case 720 can be formed by Low Pressure Chemical Vapor Deposition, and thickness is about 160nm.
In certain embodiments, wherein one deck of polysilicon layer 128.1 and tungsten silicide layer 128.2 can omit, or is replaced by other materials.
Then, form photoresist on silicon nitride layer 720 surfaces, the lithographic patterning photoresist forms rectangular, word line on itself and the storage array in the same way, this photoresist mask 1014 will be used for forming stacked structure 710, photoresist mask 1014 also can patterning neighboring area 1603 peripheral transistor grid 128.1,128.2, silicon nitride layer 720, the aligning that do not have of photoresist mask 1014 can't change the geometry of memory cell, and the border and the neighboring area that only need to adjust storage array get final product.
Etching 720; 128 (promptly 128.1 and 128.2); 98 each layers are with definition stacked structure 710; available etching mode has non-grade to reactive ion-etching; remove resistance mask 1014 earlier then; above neighboring area 1603, form another photoresist mask (not drawing) again; with silicon nitride layer 720 be under the mask etching polysilicon layer 124 and oxide layer 108; photoresist can be protected the silicon substrate 905 of peripheral active region; divest photoresist then; Figure 17 A and Figure 17 B show the storage array profile that generates; its section is parallel with bit line; these sections are obtained along arrow 17A and the 17B of Figure 16 respectively; section among Figure 17 B is to downcut along groove 910, and the section of Figure 17 A then is to downcut along the position between adjacent trenches.
Similarly, the section of Figure 18 A, Figure 19 A, Figure 20 A, Figure 21 A, Figure 22 A, Figure 23 A, Figure 24 A, Figure 31 A, Figure 32 A, Figure 33 A is to downcut along the position between adjacent trenches, and the section of Figure 18 B, Figure 19 B, Figure 20 B, Figure 21 B, Figure 22 B, Figure 23 B, Figure 24 B, Figure 31 B, Figure 32 B, Figure 33 B then is to downcut along groove 910.
In certain embodiments, do not form the peripheral transistor grid with polysilicon layer 128.1 and tungsten silicide layer 128.2, the peripheral transistor grid is formed by the polysilicon layer that deposits afterwards, and word line also is formed by polysilicon layer.This embodiment has omitted first etching 98.2 before forming silicon dioxide layer 98.3; 98.1; 124; the step of 108 each layers; and the step with the mask protection storage array has also been omitted when etching; when forming photoresist mask 1014; periphery active region top existing 108; 124; 98; 128; 720 each layers; cover those layers of storage array active region exactly; be etched in these layers in neighboring area and storage array zone simultaneously; so do not need to divest photoresist mask 1014 after the intact silicon dioxide layer 98.3 of etching, above-mentioned being used to when etching polysilicon layer 124 protects the mask of peripheral active region then can omit.
Oxidation structure (as under 1080 ℃ oxygen atmosphere, carrying out) with the rapid thermal oxidation method, so, can form the silicon dioxide layer 1510 (shown in Figure 18 A and Figure 18 B) of thick 5nm at the exposed surface of substrate regions 150, the polysilicon layer 124 and 128.1 that this step can allow oxidation expose simultaneously has the horizontal breadth of 8nm in the one silica layer 1510 of polysilicon sidewall.
Deposit the thin silicon nitride layer 903 (shown in Figure 19 A and Figure 19 B) of a bed thickness 20nm with Low Pressure Chemical Vapor Deposition, do not need mask, the above-mentioned silicon nitride layer 903 of anisotropic etching promptly can form partition on the sidewall of stacked structure 710.
This etching step can remove simultaneously and be exposed to outer silicon dioxide layer 1510, be lower than the silicon dioxide layer 1810 of above substrate regions 150, growing up again under 800 ℃ the temperature with dry type oxidation process, this is designated as 1810 silicon dioxide layer and will provides and select transistorized gate insulator in Figure 19 A, the reference thickness of this silicon dioxide layer 1810 is 5nm.
In certain embodiments, can omit the step that forms silicon nitride layer 903 or silicon dioxide layer 1510.
Then, form polysilicon layer 520 (shown in Figure 20 A, Figure 20 B, Figure 21 A, Figure 21 B), in certain embodiments, deposit the polysilicon layer 520 of a bed thickness 300nm with Low Pressure Chemical Vapor Deposition, deposition was carried out severe doping (N+ or P+) at that time or afterwards, above-mentioned polysilicon layer 520 is carried out comprehensive anisotropic etching (as reactive ion-etching), fortunately form partition on the sidewall of stacked structure 710, we can control the width of formed polysilicon partition by the vertical thickness of adjusting silicon nitride layer 720 and polysilicon layer 520.
On the stacked structure 710 two ends sidewalls among the embodiment polysilicon partition 520 is arranged all, in certain embodiments, source electrode line 144 is very narrow, so that polysilicon layer 520 can fill up the gap of 710 of source electrode line top stacked structures, and can not form partition on the sidewall near piling up of that end of source electrode line.
Except grid alternatively, polysilicon layer 520 can also be as the circuit element of other peripheral circuits such as intraconnections, transistor gate, for this purpose, before etching polysilicon layer 520, can form mask earlier in the neighboring area, above memory cell, then not need this mask.
Above part polysilicon layer 520, utilize photoetching to form photoresist mask 1710 (shown in Figure 21 A and Figure 21 B), the polysilicon layer 520 of this part will form word line, photoresist mask 1710 also can cover part or whole neighboring areas, form the rectangular of word-line direction, two adjacent stacks structures 710 that each rectangular and adjacent source polar curve is 144 are overlapping, and covering bit line zone 134, source electrode line 144 is not then covered by photoresist mask 1710.
The longitudinal edge of photoresist mask 1710 can be situated in the arbitrary position on the stacked structure 710, therefore if the error of mask alignment less than half of stacked structure 710 width, we are for the strictness so of requirement of position.In certain embodiments, minimum characteristic size is 0.14mm, and the admissible error of mask alignment is 0.07mm, and the width of each stacked structure 710 is 0.14mm, i.e. the alignment tolerance of twice.
Each stacked structure 710 of etching keeps the polysilicon partition 520 of each stacked structure 710 near that side of bit line near the polysilicon layer 520 (shown in Figure 22 A and Figure 22 B) of that side of source electrode line.
Etch away after the polysilicon layer 520, keep photoresist mask 1710, inject the usefulness of wafer as N type alloy (as phosphorus), direction as 2110 ratios of arrow among Figure 22 A, severe doping (N+) source electrode line 144, this is to allow source electrode line have high voltage for erasing and/or " deeply " of the operating voltage that stylizes injects, and when alloy spreads to side, dark injection can be suitable overlapping of 124 formation of doped source polar curve and floating gate.
In certain embodiments, alloy can not penetrate insulating barrier 1010, (shown in Figure 22 B) do not take place so this step does not have the situation of the bottom of doping groove 910, this step impure source line zone is labeled as " 144.0 " in Figure 22 C, no matter whether alloy can penetrate insulating barrier 1010, insulating barrier 1010 all can avoid alloy near or arrive 1103 (as shown in figure 11) of N-zone, therefore can avoid having high leakage current or situation of short circuit to take place at source electrode line 144 and 1103 in N-zone.In certain embodiments, finish back (after being heating steps) in technology, substrate 905 upper surfaces in the territory, upper surface abscission zone 150 in N-zone 1103 are approximately 1mm, and groove 910 degree of depth are 0.25mm.
After the injection; stay photoresist mask 1710; and the insulating barrier 1010 that exposes has removed (shown in Figure 23 B) from the groove 910 that is positioned at source electrode line 144 wholly or in part; silicon nitride layer 903 and dioxide layer 1510 can protect for 124 and 128 two-layer unlikely exposing of sidewall; etching mode can be an anisotropic etching, as reactive ion etching.Remove the silicon dioxide layer 1810 (shown in Figure 23 A) that is positioned at source electrode line 144 end faces in an etching simultaneously in this step.
Remove mask 1710 then, and carry out comprehensive N+ and inject 2401 with doped bit line zone 134 and source electrode line 144 (shown in Figure 24 A, Figure 24 B, Fig. 9 B, Fig. 9 C), stacked structure 710 and polysilicon layer 520 cover substrate when injecting.In certain embodiments, the injecting program step is included in the non-zero angle direction of vertical axis (axle of vertical wafer) and carries out the ion injection, and with the doping trenched side-wall, in certain embodiments, angle is 7 °, 8 ° or 30 °, and alloy can be an arsenic.
Above-mentioned this injection can't penetrate the insulating barrier 1010 near bit line zone 134, so the bit line zone can not form short circuit.
Next can utilize known technology to finish the manufacturing of memory, similarly being can depositing insulating layer (not drawing), form contact openings 138 (shown in Fig. 9 A), deposition and patterning conductive material to be to form bit line and other must part.
Explanation as the relevant Figure 15 in front, after grinding insulating barrier 1010, it can be etched with the sidewall that exposes polysilicon layer 124, Figure 24 C illustrates this embodiment, this figure is memory passes control gate 128 along word line a storage array profile, control gate 128 comprises the part 128A near floating gate 124 sidewalls, so can improve the capacitive coupling of 124 of control gate 128 and floating gates.In certain embodiments.Polysilicon layer 124 thick 120nm, wide 140nm, if the upper surface of polysilicon layer 124 greatly about the top 60nm of insulating barrier 1010 upper surfaces, just can the be greatly improved coupling situation of 124 of control gate 128 and floating gates that is petty.
It should be noted that the floating gate 124 autoregistration active regions of neutrality line direction of the present invention especially, 128 autoregistration floating gates 124 of the control gate of word-line direction are selected 520 autoregistration control gates 128 of grid (word line) then.Its implementation method is utilized the shallow trench isolation technology exactly, opens 124 definition active regions (or directly defining floating gate 124 and active region simultaneously with the active region mask) to float, and so floating gate 124 is the autoregistration active region; Then utilize the control gate 128 definition floating gates 124 when the thick dielectric layer of definition control gate 128 tops (or also and then define simultaneously floating gate 124 and control gate 128) of floating gate 124 tops, control gate 128 like this and autoregistration floating gate 124; Grid 520 (partition) are selected in generation at last, because select grid 520 to generate along the thick dielectric layer of control gate 128 tops, that is the control gate 128 of 520 while of the selection grid also autoregistration thick dielectric layer below of word-line direction.
Utilize autoregistration step repeatedly, not only can effectively reduce the size of memory, can also guarantee the electrical conductivity of each unit, though select the misalignment of 128 of grid 520 and control gates can't change the electrical conductivity of memory cell, but determined the electrical conductivity of memory cell because of the channel length of selecting 124 of grid 520 and floating gates, so selecting the misalignment of 124 of grid 520 and floating gates is the electrical conductivity that can have influence on memory cell, change design element electrically, utilize technology of the present invention can effectively improve this class deviation.
In certain embodiments, the grid of peripheral transistor is formed by polysilicon layer 520, rather than by 128 layers form, the part of the relevant Figure 16 in front was carried, so need before deposition control grid layer 128, not cover storage array earlier, and 1603 remove polysilicon layer 124 and 98.2,98.1,108 each layers from the neighboring area.Forming among the embodiment of peripheral transistor grid with polysilicon layer 520, photoresist mask 1014 can't cover neighboring area 1603, or can not cover the zone that the peripheral transistor grid will form at least, therefore, when definition stacked structure 710, can etch away neighboring area or 108,124,98,128,720 each layers of peripheral transistor area of grid at least, expose the substrate 905 of peripheral active region.
Handle wafer (shown in Figure 17 A to Figure 19 B) as above-mentioned mode then, silicon dioxide layer 1810 will form the gate insulator of peripheral transistor.
The deposit spathic silicon layer 520 as mentioned above, the structure of coming out as shown in figure 25, before anisotropic etching polysilicon layer 520, form photoresist mask 2501 in the top, neighboring area that will form peripheral transistor grid and other elements (as intraconnections, resistor or the like) earlier, the anisotropic etching polysilicon 520 then, then remove photoresist mask 2501, remove photoresist mask 2501 neighboring area profile afterwards shown in Figure 26 A, the profile of storage array is then shown in Figure 20 A and Figure 20 B.
In certain embodiments, can reduce the resistance of peripheral transistor grid by the following step, after deposit spathic silicon layer 520 (as shown in figure 25), above polysilicon layer 520, form one deck tungsten silicide or other layer of low resistance material (not drawing), above the neighboring area, form photoresist mask 2501 then, tungsten silicide or the other materials layer that is not covered by photoresist mask 2501 on the polysilicon layer 520 removed in etching, then polysilicon layer 520 is carried out anisotropic etching, to form partition (shown in Figure 20 A and Figure 20 B), and definition peripheral transistor grid and other peripheral elements, remove photoresist mask 2501 then, so tungsten silicide or other electric conducting materials 2605 will cover the polysilicon layer 520 (shown in Figure 26 B) of neighboring area, if electric conducting material 2605 and polysilicon layer are by the while etching, then polysilicon layer 520 tops of storage array also may stay some electric conducting materials 2605.
In certain embodiments, before forming photoresist mask 2501, above polysilicon layer 520, deposit one deck silicon nitride layer 2607 (shown in Figure 26 C) earlier, if electric conducting material 2605 is the resistance that is used to reduce the peripheral transistor grid, then silicon nitride layer 2607 is deposited on electric conducting material 2605 tops, above the peripheral transistor grid, form photoresist mask 2501 then as mentioned above, etching is the silicon nitride layer of coated region not, according to Figure 25, Figure 26 A, the mode of Figure 26 B is handled wafer, and Figure 26 C is the profile that the neighboring area has the embodiment of electric conducting material 2605.When after a while structure being carried out cmp, silicon nitride layer 720 and 2607 can be as etching stopping layer, when the stage of Figure 24 A and Figure 24 B (after doped source polar curve and the bit line), when structure is insulated material (as vapour deposition oxide (vapor deposited oxide (vapox), do not draw) cover after, carrying out cmp can the planarization wafer.In certain embodiments; insulating barrier is as the last layer protective layer before wafer cutting or the encapsulation; and in certain embodiments; the material of insulating barrier can be to mix or the undoped silicon dioxide layer; as boron-phosphorosilicate glass (borophosphosoilicate glass; BPSG), can also use other material.
In certain embodiments, some peripheral transistor grids or other elements be by 128 layers form, other periphery gates or element are formed by polysilicon layer 520, the back will illustrate a this embodiment according to Figure 44 to Figure 50.
Reduce the resistance of polysilicon layer (word line) 520, can utilize metal tape, each strip metal band is positioned on the word line, and with certain all period interval contact with word line (as per 128 the row), because word line 520 is narrow partitions, still have low resistance even there is small embossment to contact with metal tape, photoresist mask 2501 can be used for forming this projection.Figure 27 is the vertical view of this embodiment, show and utilize anisotropic etching polysilicon layer 520 to form after the partition, storage array is blocked and a gap 2701 is arranged, gap 2701 and bit line are in the same way, so produce and to form the space of word line projection, gap 2701 can be used for groove 910, storage array section 2703.1 is positioned at a side (it seems that Figure 27 be to be positioned at the top, gap) in gap, storage array section 2703.2 then depends on the below, gap, word line 520 and stacked structure 710 be continual to stride across section 2703.1 and 2703.2 and the gap, part polysilicon layer 520 before carrying out etching formation partition in formed mask 2501 coverage gap 2701, Figure 28 shows the vertical view that removes photoresist mask 2501 and form photoresist mask 1710 post gaps 2701 zones.
In Figure 27, photoresist mask 2501 comprises extend along the gap rectangular, photoresist mask 2501 is blocked in the zone 2709 of 520 of adjacent word lines, but the polysilicon layer 520 of etching word line grid like this, therefore can avoid forming between adjacent word line short circuit, one can break can be continuous above source electrode line 144 for photoresist mask 2501, photoresist mask above source electrode line need not interrupt, this be stranded for the polysilicon layer 520 in etching source electrode line zone be to utilize photoresist mask 1710 (as shown in figure 28).
Photoresist mask 1710 (as shown in figure 28) can have identical geometry external form with the photoresist mask that top relevant Figure 21 A is narrated to Figure 23 B, above-mentioned same purposes also can be arranged, be etching source electrode line 144 polysilicon layer 520, to source electrode line inject 2110 deeply, the insulating barrier 1010 of etched trench, Figure 29 shows the polysilicon layer 520 of etching source electrode line, and each polysilicon (word line) 520 has lateral projection 520E in gap 2701.
Handle wafer with reference to previous Figure 22 A to Figure 26 C then, if insulating barrier 1010 is to carry out etching with reference to the mode of figure 23B, then remove the insulating barrier 1010 in the gap 2701 that is positioned at source electrode line 144 wholly or in part, channel bottom and sidewall in the storage array intermediate gap simultaneously mix, so, source electrode line 144 can pass the gap and uninterrupted.
Figure 30 A shows the profile that is positioned at than gap of storage 2701 inside of last part technology, above memory cell, formed insulating barrier 2901, each metal tape 2903 is positioned at the top of corresponding word line 520, and the opening 2903C via insulating barrier 2901 contacts with word line 520 in grid crack 2701.In Figure 30 A, the upper surface of polysilicon layer 520 is high together with the upper surface of control control grid 128 top silicon nitride layers 720, and this is because polysilicon layer 520 is handled through chemical mechanical milling method, stops when running into silicon nitride layer.Particularly, insulating barrier 2901 is made up of plural layer, and some layer is to deposit after the step of Figure 24 A and Figure 24 B, handles through cmp again, then forms other layers to finish a complete insulating barrier 2901.Polysilicon layer 520 is overlapping with silicon nitride layer in other embodiments.
In certain embodiments, the do not use up width (be Figure 28 and Figure 29 heavy ruler cun) in whole gap 2701 of isolated groove 910, the composite bed isolated groove can be positioned at the gap, or also can be without any groove in the gap.
Figure 30 B and Figure 30 C are respectively memory section and the mask distribution patterns of another embodiment, Figure 30 c shows photoresist mask 904,1014,2501 (please also refer to Figure 12 A, Figure 12 B, Figure 16, Figure 27), bit line contact 138 can with the contact openings 290C etching simultaneously of polysilicon layer 520, also can be not simultaneously, the contact openings 144C of source electrode line 144 also can contact 138 or polysilicon contact 2903C etching simultaneously with bit line.In certain embodiments, the contact openings (not drawing) of contact openings 138,2903C, 144C and control gate 128 is to use same photoresist mask to carry out etching synchronously, from the downward etches both silicon nitride layer 720 of mask open to expose control gate, the contact openings 2903C of polysilicon layer 520 does not link to each other with control gate 128, forms short circuit to avoid word line 520 and control gate 128.
Contact openings 138 can use known technology to fill up with N+ doped polycrystalline silicon connector, if because the contact mask not have to aim at make contact openings 138 etch effects the interior insulating barrier 1010 of groove 910, the insulating barrier 1010 that then is removed in the groove will be received in the N+ polysilicon when forming connector, polysilicon plug can avoid Metal Contact and 150 in P doped substrate zone to form short circuit.
In certain embodiments, can form short circuit between the adjacent source electrode line 144, for example, source electrode line can four is one group, four source electrode lines of each group can with the metal tape 2903 formation short circuit of joining, metal tape 2903 can contact with source electrode line via the 3010 inner opening 144C of the gap between the storage array adjacent lines, the source electrode line short circuit can be reduced needs to connect the zone of source electrode line to higher metal layers (not drawing), only need a contact openings (not drawing) because four source electrode line contacts with higher metal layers, the resistance that also can be used for reducing source electrode line that contacts with higher metal layers, can be formed at the source electrode line top by the formed metal tape of higher metal layers, contact at interval with metal tape 2903,3010 inner opening 144C contact metal tape 2903 in the gap with source electrode line, and storage array can have a plurality of gaps 3010.For four source electrode lines of each group, the formation short circuit that also can be connected together of eight of being followed control grid line 128.
By photoresist mask 1014 defined control grid lines 128 along source electrode line contact openings 144C bending, if it is very close in the bit line zone 312 of adjacent control grid line 128 in gap 3010, polysilicon layer 520 may be inserted in the above-mentioned zone 312, cause word line 520 to form the short circuit of trouble in these zones, for fear of short circuit, can use photoresist mask 1710 (Figure 28) to remove polysilicon layer 520 in the gap 3010, this can make word line partition 520 be blocked in gap 3010, but the particular word line in 3010 in grid crack can be electrically connected with metal tape 2903 (shown in Figure 30 B), and 2903 of metal tapes contact with word line in gap 2701.
It is similar with Figure 24 B to Figure 24 A with 2703.2 section with 3010 storage array section 2703.1 to be positioned at grid crack 2701, and metal tape 2903 is positioned on the word line in storage array section 2703.1 and 2703.2, but is not in contact with it.
In certain embodiments, can be by silicided source polar curve 144 to reduce its resistance, for example, deposit cobalt or other suitable metals on the structure in the stage of Figure 24 A and Figure 24 B (before or after being doped bit line zone 134), heating wafer feasible exposed silicon and cobalt or other metal reactions, and the silicide of formation conduction, remove unreacted cobalt or other metals then, this silicide just can be stayed source electrode line 144 and word line 520 tops, above-mentioned silicide step therewith in the field known silicification technics (being self-aligned silicide) identical.
In certain embodiments, insulating barrier 1810 may be not enough to avoid cobalt or other metals and 134 in bit line zone to form short circuit, therefore, word line 520 is to form short circuit with bit line zone 134, we can utilize following method to avoid this situation: after wafer is through Figure 20 A and the processing in Figure 20 B stage, just before deposition photoresist mask 1710, first depositing insulating layer 3003 (as Figure 31 A and Figure 31 B), the material of above-mentioned insulating barrier 3003 can be a silicon dioxide.Aforesaid then method, form photoresist mask 1710 in regular turn, then remove the insulating barrier 3003 that exposes in photoresist mask 1710 outsides, again with the processing of wafer through Figure 21 A to Figure 23 B step, particularly be exactly etching polysilicon layer 520 and doped source polar curve 144 (promptly injecting 2110), remove photoresist mask 1710 then, just the structure of generation is shown in Figure 32 A and Figure 32 B.
And then deposition layer of metal (as cobalt), the heating wafer makes the pasc reaction in metal and the source electrode line zone, and removes unreacted metal, and is last, just formation disilicide layer 3301 (shown in Figure 33 A and Figure 33 B) above source electrode line.
Under certain conditions, if there is not complete etching to remove the insulating barrier 1010 (shown in Figure 23 B) that is positioned at groove 910, then the silicide 3301 in the groove 910 can be blocked.
Then, continue etching isolation layer 3003, inject 2401 (shown in Figure 24 A and Figure 24 B) in bit line zone 134 and source electrode line, or can pass insulating barrier 3003 and inject, insulating barrier 3003 also can be selected to be retained in the memory certainly.
And the source electrode line silicidation technique can be used with the embodiment (being that the peripheral transistor grid is formed by control grid layer 128) of Figure 16, also can use with the embodiment (being that the peripheral transistor grid is formed by polysilicon layer 520) of Figure 25, Figure 26 A, Figure 26 B, Figure 26 C, or use with the embodiment ( polysilicon layer 128 and 520 all is used for as the peripheral transistor grid) of Figure 44 to Figure 50, this part will illustrate that silicidation technique also can combine with protruding 520E (extremely shown in Figure 30 as Figure 27) in the back.
Figure 34 explanation is according to another flash memory of the present invention, and each isolated groove 910 protrudes between the adjacent source electrode line 144, but does not intersect with source electrode line, and we are denoted as 910B to the border of isolated groove.
The technology of above-mentioned sort memory is as follows: doped substrate 905 forms area of isolation 150 (as shown in figure 11), form tunnel oxide 108, polysilicon layer 124, silicon nitride layer 1203, photoresist mask 904 (shown in Figure 12 A and Figure 12 B) then in regular turn, patterned sin layer 1203 and polysilicon layer 124, but, this step does not have etching substrates zone 150, whether 108 of tunnel oxides can be decided in its sole discretion and will etch away, then remove photoresist mask 904, the structure that obtains just as shown in figure 35.
Then, deposit the one silica layer 2710 (as shown in figure 36) of the 300nm of a bed thickness with chemical vapour deposition technique, as boron-phosphorosilicate glass, lithographic patterning photoresist mask 2810 (as shown in figure 37) then, making becomes the rectangular of word-line direction, each is rectangular to be positioned at the zone that source electrode line 144 will form, other elements of photoresist mask 2810 and memory (as control gate 128) relevant (as shown in figure 38), and this step does not also form control gate 128.
By the selection of photoresist mask 2810 and silicon nitride layer 1203 is removed the dioxide layer 2710 and 108 that photoresist mask and silicon nitride layer 1203 are surrounded than etching, remove photoresist mask 2810 then, with dioxide layer 2710 and silicon nitride layer 1203 is mask etching substrates zone 150, forms rectangle groove 910; Or in etching substrates zone 150 o'clock, photoresist mask 2810 can be kept, under this situation, do not need to deposit dioxide layer 2710.Figure 39 shows the section of the embodiment that uses dioxide layer 2710, and this section is the resultant plane by groove of line 39-39 cutting-out along Figure 37, and the plane section by groove is then not the same with Figure 36.
And then deposit an insulating barrier 1010 (as shown in figure 13), and remove partial insulative layer 1010 (as shown in figure 14) with chemical mechanical milling method, then removing silicon nitride layer 1203, selective etch insulating barrier 1010 causes upper surface to become a flat surfaces.Figure 40 B is a resulting structures at parallel wordlines and the section plan by groove, and Figure 40 A then is by the section plan between adjacent trenches, and some insulating barrier 1010 may cover the substrate regions 150 of source electrode line 144 parts.Source electrode line does not stride across groove (some dioxide layer 2710 can be stayed on the sidewall of polysilicon rectangular 124, and at this moment oxide layer seems can similarly to be the part of insulating barrier 1010).
In certain embodiments, can etching remove partial insulative layer 1010,, improve the capacitive coupling (shown in Figure 24 C) of 124 of control gate 128 and floating gates whereby to expose the sidewall of polysilicon layer 124.
Remaining processing step can be identical with aforementioned Figure 16 to Figure 33 B, as form steps such as insulating barrier (material can be oxygen nitrogen oxide layer, ONO layer) 98, control grid layer 128, silicon nitride layer 720, photoresist mask 1014 (being that the peripheral transistor grid can be formed by 128 layers or word line layer 520).
Form silicon dioxide layer 1510 (shown in Figure 18 A) then, silicon nitride partition 903 and silicon dioxide layer 1810 (shown in Figure 19 A).
Deposition and anisotropic etching polysilicon layer 520 (shown in Figure 20 A), form photoresist mask 1710 (shown in Figure 21 A) then, the polysilicon layer 520 at etching source electrode line 144 places (shown in Figure 22 A), but can not etching as for insulating barrier 1010 etchings at source electrode line 144 places, inject 2110 then, because source electrode line does not intersect with groove 910, the current injection whole rectangular source electrode line that mixes, the structure that generates is identical with Figure 22 A, and Figure 41 shows the section (being that this profile is to suppose the insulating barrier 1010 at etching source electrode line place) along groove.
Explanation as the relevant Figure 24 A in front and Figure 24 B, remove photoresist and invite cover 1710, carry out the N type and inject 2401 doped bit line zone 134 and source electrode line 144, insulating barrier 1010 that can first etching source electrode line place before injecting 2410 steps, or between injection 2110 and 2410 steps, carry out etching, or after injecting 2410 steps, carry out, or not etching.
In certain embodiments, the bossing 520E of Figure 27 to Figure 30 is taken as word line 520; In certain embodiments, shown in Figure 24 A, Figure 31 A to Figure 33 B, meeting silicided source polar curve 144 is to reduce its resistance.
In Figure 42, we have omitted dioxide layer 2710 and photoresist mask 2810, isolated groove 910 shown in Figure 12 A be by photoresist mask 904 definition, but because groove 910 is rectangular (as shown in figure 37), therefore silicon nitride layer 1203 and polysilicon layer 124 have same profile with the composite bed of Figure 37, groove 910 has same profile with the groove of Figure 34 to Figure 41, remove the insulating barrier 1010 (as shown in figure 15) of source electrode line 144 tops with chemical mechanical milling method, remaining processing step is just the same with Figure 37 to Figure 41, when definition stacked structure 710, and the polysilicon layer 124 and the dioxide layer 108 of the source electrode line of etching simultaneously 144 tops, this step can expose source electrode line 144.
At Fig. 9 A in the embodiment of Figure 43, be to utilize source terminal hot electron injection method (make the become non-conductive) memory cell that stylizes, see also " the Nonvolatile Semiconductor Memory Technology " the 21st to 23 page that people such as W.D.Brown delivered in 1998, following table 1 is listed the memory reference voltage that drives with 1.8V external power source supply (VCC), oblique line is to be used for representing selecting/voltage of non-selection storage column or row, give an example, table 1 " stylizing " OK, " bit line zone 134 " row, it is 0V that bit line is selected in project " 0V/V3 " expression, and not selected bit line is voltage V3, and we do not list all non-selection voltages.
The erasing of memory cell can use from floating gate 124 to source electrode line 144 " via the source electrode line sector of erasing " of table 1 (please refer to OK) or wear tunnel to the Fowler-Nordheim of substrate regions 150 (" via the substrate sector of erasing "), the latter is than preferable technology, because reduced band and interband (band-to-band) electric current.In the flash memory of Figure 10 B and Figure 34, the whole zone (sector) of can only erasing, and other unit of can not erasing, a zone is meant row or an ordered series of numbers, the source electrode line 144 of their correspondence is connected to form short circuit via circuit, and corresponding control grid line 128 also is connected to form short circuit via circuit.
Some embodiment provide the erase a plurality of zones or the selection of whole storage array in the single operation step, the unit that wherein utilizes from floating gate 124 to substrate regions 150 Fowler-Nordheim electrons tunnel to be remained to be erased to erase synchronously, " wafer is erased " of Here it is table 1, zone 150 is a forward bias with respect to all control gates, array is erased the speed that adopts the wafer erase mode can be faster than what come by the row erase mode, and this is particularly useful when testing memory.
Table 1
| Stylize | Via the source electrode line section of erasing | Via the substrate section of erasing | Wafer is erased | | |
| Control gate | |||||
| 128 | +10V/0V | -10V | -10V | -10V | 1.8V |
| |
0V/V 3 ** (VCC＝1.8V) | V 4 *** (VCC＝1.8V) | Float | Float | 1.5 |
| |
6V | 5V | Float | Float | |
| Select grid | |||||
| 520 | VTN+ΔV 1 * | 0V | 0V | 0V | VCC+ΔV 2 * (VCC＝1.8V) |
| |
0V | 0V | 6V | 6V | 0V |
Annotate:
* in an embodiment, VTN=0.6V, Δ V
1=0.9V, Δ V
2=1.4V.
* V
3Be greater than Δ V
1Voltage.
* * V
4Voltage range 0＜V
4＜VCC.
Article one, memory can have a plurality of storage arrays, and each storage array all has bit line and the word line of oneself, and different arrays can be placed on identical substrate regions 150 or be placed on the different isolated substrates zone 150 of same integrated circuit." wafer is erased " operates the memory cell that can erase on some substrate regions 150, and can not erase in the unit of other substrate regions 150.
Voltage generator and decoder block 4201 (as shown in figure 43) can use known technology in response to power supply supply voltage VCC, address signal " ADDR ", other the necessary voltages of generation such as order/controlling signal.
Figure 44 explanation is according to the thickness of the resultant different MOS (metal-oxide-semiconductor) transistor gate insulators of memory embodiment of Fig. 9 A to Figure 43, the gate insulator that need approach during high speed operation, on the contrary, the transistor that is exposed under the high voltage then needs thicker gate insulator, simultaneously, tunnel oxide 108 also will have enough thickness to store long data.
In will narrating below among the embodiment at once, all gate insulators all are silicon dioxide layers, but this is not certain, and the thickness of relevant gate insulator is hypothesis VCC=1.8V, and operating voltage as above table 1 is listed, these voltages only for the explanation but not be used for limiting the present invention.
In Figure 44, tunnel oxide 108 thick about 9nm select 1810 of transistor gate oxide layers will relatively approach (as 5nm), and are still also enough thick so that quick computing to be provided, and just withstand voltage 3.2V (the VCC+ Δ V in the example that is used as read operation in the table 1
2=3.2V).
Neighboring area 1603 includes source region 4402,4404,4406, high voltage active region 4402 is to use to the transistor under-10V voltage (seeing also table 1) and other high voltages to being exposed to 10V, these transistors may be voltage generator 4201 parts of (as shown in figure 43), thicker on the grid oxic horizon 4408 in zone 4402, about 22 to 25nm is thick.
High speed active region 4404 is to use to being exposed to the transistor that is lower than under the VCC voltage, these transistors may be the parts of address decoder, sensing amplifier, time pulse signal generator, voltage generator, address and data buffer and other circuit, their grid oxic horizon 4410 is quite thin, and about 3.5nm is thick.
I/O active region 4406 is to using as the transistor that cuts off the wafer circuit interface, cutting off wafer circuit may operate under higher power supply supply voltage, as 2.5V or 3.3V, so the I/O transistor must have thicker grid oxic horizon to bear so high voltage, in Figure 44, I/O transistor gate oxide layer 1810 is same one decks with selecting transistor gate oxide layer 1810, and it is thick to be about 5nm.
In Figure 44, the transistor gate in zone 4402 and 4404 is formed by control grid layer 128, the I/O transistor gate in zone 4406 and the selection grid 520 (being word line) of memory cell are formed by polysilicon layer 520, explanation as Figure 26 B and Figure 26 C, selecting can have metal level and/or silicon nitride layer on the grid 520, and control gate 128 is formed by polysilicon multi-crystal silicification metal or other conductive layers.
The technology of above-mentioned formation gate insulator is as follows: the tunnel oxide 108 (shown in Figure 12 A) that generates thick 9nm, above-mentioned oxide layer 108 is to be created on the entire wafer (to comprise neighboring area 1603), deposit then and patterned polysilicon layer 124, then form isolated groove 910, and fill up groove 910 with insulating material 1010, see also Figure 12 A to Figure 15, Figure 37, Figure 42 and relevant explanatory note.
Form silicon dioxide layer 98.1 and silicon nitride layer 98.2 (as shown in figure 16), the reference thickness of above-mentioned these layers is respectively 1nm and 5nm.
Deposition and lithographic patterning photoresist mask 4501 make it cover storage array (as shown in figure 45) then, and 98.2,98.1,124,108 each layers of etching neighboring area 1603 are to expose substrate 905.
Then, remove photoresist mask 4501, oxidation wafer under 850 ℃ or lower temperature, so can generate the silicon dioxide layer 4408 (as shown in figure 46) of thick 24nm at active region 4402,4404,4406, simultaneously, above the silicon nitride layer 98.2 of storage array active region 901, then form the silicon dioxide layer 98.3 of thick 1nm to 1.5nm.
Deposition and patterning photoresist mask 4601 make it cover whole storage array and high voltage active region 4402 then, and active region 4404 and 4406 is not covered, and therefore are able to the silicon dioxide layer 4408 of etching active region 4404 and 4406.
Remove photoresist mask 4601 then, generally speaking, remove photoresist step afterwards and normally clean wafer, the dioxide layer 4408 that cleaning not too can failure area 4402 in this embodiment, this is because dioxide layer 4408 is very thick, and thin oxide layer 4410 (as shown in figure 44) is because of can contacting with photoresist, so also can be because of removing the cleaning behind the photoresist and cause damage.
Oxidation wafer then, generate the silicon dioxide layer 4410 (as shown in figure 47) of thick 3.5nm at active region 4404 and 4406, but serviceability temperature is lower than 850 ℃ dry type oxidation process here, and this step makes the thickness of dioxide layer 4408 (promptly in the zone 4402) be increased to about 25nm.
On wafer, deposit control grid layer 128 and silicon oxide layer 720 then, form photoresist mask 1014, and the transistor gate that utilizes this photoresist mask 1014 to define stacked structures 710 and be positioned at high-voltage region 4402 and high-speed region 4404, photoresist mask 1014 does not cover I/O active region 44406, and in regular turn etching photoresist mask 1014 with the silicon nitride layer 720 under exposing, control grid layer 128, and 98.3,98.2,98.1,4408,4410 each layers are as long as wherein run into the polysilicon layer 124 of array active region 901 and the substrate 905 of peripheral active region promptly stops in etching process.
Remove photoresist mask 1014 then; form another photoresist mask 4801 (as shown in figure 48) and cover all neighboring areas 1603 (have the zone that forms silicon nitride layer 720 can be) without photoresist mask 4801; on the etched wafer not by the polysilicon layer 124 and the silicon dioxide layer 108 of 720 protections of photoresist mask 4801 and silicon nitride layer; so form stacked structure 710; remove photoresist mask 4801 then, the structure that is generated as shown in figure 49.
Then; continue to form silicon dioxide layer 1510 and silicon nitride layer 903 (shown in Figure 19 A and Figure 19 B); sidewall with protection stacked structure 710; oxidation wafer then; above the exposed substrate 905 of the exposed substrate regions 150 of storage array active region 901 and I/O active region 4406, form the silicon dioxide layer 1810 (as Figure 20 A and shown in Figure 44) of thick 5nm; then deposition and patterned polysilicon layer 520 are with as I/O peripheral transistor grid (shown in Figure 25, Figure 26 A, Figure 26 B, Figure 26 C).
As mentioned above; when carrying out cmp; the silicon nitride layer 2607 (shown in Figure 26 C) of active region 4406 polysilicon layers 520 tops can be protected polysilicon layer 520; if if but do not form above-mentioned silicon nitride layer 2607; also can protect polysilicon layer 520 in the mode of Figure 50; its method is: form empty interposed structure at " void is put (dummy) " the regional 4404D near transistor active region 4406 earlier; void is put the treatment step and high-speed region 4404 identical (Figure 44) in zone; so can form silicon nitride layer 720 at regional 4404D; the upper surface of silicon nitride layer 720 is than the upper surface height of regional 4406 polysilicon layers 520; when covering brilliant figure and carrying out cmp with silicon dioxide (not drawing) after a while; the silicon nitride layer 720 of zone 4404D can not allow the silicon dioxide of regional 4406 polysilicon layers 520 tops be removed, and so can protect polysilicon layer 520.
In addition, void is put regional treatment step also can be identical with high-voltage region 4402, perhaps, available different void is put the zone and is surrounded each I/O transistor active region 4406, some is a mode of utilizing zone 4402, some then utilizes the mode in zone 4404, or is provided in the single disposal structure that arbitrary side surrounds element.Some regional 4404D can not be that void is put the zone, promptly can form transistor in these zones.Can utilize isolated groove 910 that regional 4404D is separated with zone 4406, perhaps regional 4404D may be partly overlapping with isolated groove, or be positioned at the top of isolated groove fully.
Below we at mode with empty interposed structure protective circuit element, be described further again.
Figure 51 is the profile of semiconductor structure 110, and this structure comprises that semiconductor substrate 905, polysilicon layer 128 and 520, protective layer 720 its materials can be silicon nitride), dielectric layer 113.Circuit structure 121.1 comprises by polysilicon layer 128 formed circuit elements 128.1 and by polysilicon layer 520 formed circuit elements 520.1, in one embodiment, said elements 128.1 can be the grid of capacitor board or thin-film transistor, and element 520.1 can be capacitor board, transistorized source electrode, drain electrode and/or channel region, both can be different devices, for example, element 128.1 can be a transistor gate, and element 520.1 can be resistor, capacitor board, intraconnections etc.
The protection feature 720.1 and 720.2 be by 720 layers form, can protection component 128.1,520.1,520.2 when cmp dielectric layer 113.
The element 128.3 of at least a portion does not have protected seam 720 to cover.
Form empty interposed structure 141 in place near element 128.3; can when cmp dielectric layer 113, protect this circuit element; each empty interposed structure comprises by polysilicon layer 520 formed parts 520.3; can cover other part 520.3 by protective layer 720 formed feature member 720.3; feature 520.3 can be as any circuit element; any electrical functionality is not provided yet, can be connected to a fixed voltage or allows it float.
Field area of isolation 1010 is formed by the shallow trench isolation technology, or can utilize localized oxidation of silicon (local oxidation of silicon, LOCOS) technology or other technologies formation; Empty interposed structure 141 is positioned at an area of isolation 1010 tops, but this not necessarily.
Because the non-flat forms influencing profiles of each element; make that the upper surface of dielectric layer 113 is also uneven; we carry out cmp to dielectric layer 113; stop when running into protective layer 720; reach the purpose of planarization whereby; the structure that generates is shown in Figure 52; the upper surface of structure may be fully smooth; or also leave some non-flat forms zones; a reason that forms non-flat forms is each feature member 720.1; 720.2; 720.3 it is and uneven; wherein element 720.2 and 720.3 upper surface are lower than the upper surface of element 720.1; also have; dielectric layer 113 upper surfaces of element 128.3 tops also can be lower; this is because the below does not have the structure of protective layer 720; the not good reason of another flatness may be that element is lower in some partial density of integrated circuit; see also in the U.S. Patent number 5 of bulletin on June 1st, 1999; 909; 628 " REDUCING NON-UNIFORMITYIN A REFILL LAYER THICKNESS FOR A SEMICONDUCTOR DEVICE "; but; through after the cmp; the upper surface of structure 110 is more smooth, belongs to substantive smooth.
In certain embodiments; gap is less than 15nm between the low spot of the height point of protective layer 720 and dielectric layer 113; the degree of known non-flat forms is relevant with thickness, milling time, the cmp parameter (as pressure) of dielectric layer 113; the degree of non-flat forms is also relevant with specific cmp technology (as using mud or low mud fixed abrasive), and the present invention does not limit any specific chemical mechanical milling tech or non-flat forms degree.
In certain embodiments, not every protective layer 720 all is subjected to grinding influence, such as has only higher feature member 720.1 can be subjected to grinding influence, and lower feature member 720.2 then can not.
Empty interposed structure 141 meeting protection components 128.3 are unaffected, in certain embodiments, adjacent structure 141 spacings of element 128.3 two opposite sides are about 5mm, and layer 720 be the silicon nitride of thick 160nm, and void is put upper surface about 0.21mm above element 128.3 of feature member 720.3; In other embodiments, empty interposed structure 141 spacings of element 128.3 two opposite sides surpass 10mm, and maximum can allow spacing to follow the quality of the material of use, layer thickness, cmp that relation is all arranged.
Can only provide empty interposed structure on one side of structure 121.3.
If the dielectric layer 113 above element 128.3 is thick inadequately, so that required isolation can't be provided, then can structurally deposit another layer insulating (not drawing), this one deck has the substantive smooth upper surface of comparison, because the dielectric layer of below 113 has more smooth structure through after the cmp.
Provide one below with reference to technology: according to each one demand treatment substrate 905 (as forming complementary metal oxide semiconductor (complementary metal oxide semiconductor, CMOS) well, but the present invention is not limited only to complementary metal oxide semiconductor), form then insulating barrier 4410 or 1810 and other the layer, deposition and patterning 128,520,720 each layers, depositing insulating layer 113 then, and, can form other layer or steps of mixing certainly some stage in technology with the chemical mechanical milling method processing.
Deposit spathic silicon layer 128 and 520 can utilize the technology of chemical vapour deposition technique, sputtering method or other known the unknowns.Can use single mask patterning 720 and 520 layers simultaneously, also can after forming 128 layers, just form 1810 layers.
In Figure 53, empty interposed structure 141 is to use polysilicon layer 128, the integrated circuit of Figure 53 comprises a flash memory 901, silicon layer 124 is as the floating gate of memory cell, polysilicon layer 128 is as control gate, polysilicon layer 520 is grid alternatively, insulating barrier 108 (" tunnel oxide ") is to be formed by silicon dioxide, enough thickness is arranged so that suitable data storage to be provided, in certain embodiments, oxide layer 108 thick 9nm select transistor gate oxide layer 1810 thick 5nm, the material of mentioning here and thickness only the confession explanation with but not be used for limiting the present invention.
The bit line of memory cell zone 134 is connected with top bit line (not drawing), and it stretches to the direction of bit line " BL ", and the direction of word line is stretched in source electrode line zone 144, and is vertical with bit line.
Wherein neighboring area 1603 includes source region 4402,4404,4406 (shown in Figure 53), form transistor in it, high voltage active region 4402 is to use for the transistor that is arranged in high voltage environment, transistor then is used to erase and the memory cell of the array 901 that stylizes, this regional transistor gate is formed by polysilicon layer 128, and gate insulator 4408 is silicon dioxide layers of thick about 20nm.
High-speed region 4404 comprises the transistor that has than thin grid oxide layer 4410, under low-voltage, operate, oxide layer 4410 thick 3.5nm, transistor gate be by 128 layers form.
I/O active region 4406 is for using as the transistor that cuts off the wafer circuit interface, cutting off wafer circuit can operate under higher power supply supply voltage, so transistor has thicker grid oxic horizon, to bear this voltage, gate insulator is with identical as storage array 901 1810 layers of selection transistor gate insulation.
Relevant manufacturing step is summarized as follows:
On substrate 905, form the tunnel oxide 108 (Figure 54) of thick 9nm with thermal oxidation method, deposit spathic silicon layer 124, silicon dioxide layer 98.1, silicon nitride layer 98.2 in regular turn then, then above storage array 901, form photoresist mask 4501,98.2,98.1,124 each layers in the etching area 4402,4404,4406 are to expose substrate 905.
Before deposition of silica layer 98.1, first patterned polysilicon layer 124 and substrate 905 form isolated groove, fill up groove with silica 1 010.
After the etching oxide layer 108, remove photoresist mask 4501, heating generates the oxide layer 4408 (Figure 55) of thick 19nm on substrate 905, at this moment can form very thin silicon dioxide layer 98.3 above silicon nitride layer 98.2.
Generate photoresist mask 4601 at storage array 901 and high-voltage region 4402 photoetching, the silicon dioxide layer 4408 in the etching area 4404 and 4406 on the substrate.
Remove photoresist mask 4601 then, the oxidation wafer, the silicon dioxide layer 4410 (the 56th figure) of the thick 3.5nm of generation above the substrate 905 in zone 4404 and 4406, in this step, the thickness of the oxide layer 4408 in the zone 4402 has a little to be increased.
Deposit spathic silicon layer 128 and silicon nitride layer 720 on wafer then, form photoresist mask 1014 with the floating gate of definition (i) storage array and the control gate (ii) transistor gate in the zone 4402 and 4404, the (iii) empty interposed structure 141 in the zone 4406, etching is by 720,128,98.3,98.2,98.1,4408,4410 each layers of mask overlay area, and etching will stop at polysilicon layer 124 in the storage array zone and the substrate 905 (Figure 57) in other zones.
Remove photoresist 1014 then, when cleanup step, polysilicon layer 128 and silicon nitride layer 720 can be protected the thin grid oxide layer 4410 of high-speed region 4404.
4402,4404,4406 form another photoresist mask 4801 in the zone; there is the place of silicon nitride layer 720 can; except the zone of photoresist mask 4801 and silicon nitride layer 720 protections; the polysilicon layer 1124 of etched wafer and silicon dioxide layer 108 remove photoresist mask 4801 (Figure 58) then.
124 and 128 layers expose sidewall and substrate 905 above oxidation structure generate thin silicon dioxide layer 1510 (Figure 59), deposit then and anisotropic etching thin silicon nitride layer 903, so can form partition at transistor grid structure and empty interposed structure, when etching, the silicon dioxide layer 1510 that exposes because of etches both silicon nitride layer 903 may be removed.
Above the exposed surface of substrate 905, generate the silicon dioxide layer 1810 (Figure 60) of thick 5nm with thermal oxidation.
Structurally the deposit spathic silicon layer 520, form the transistor gate of photoresist mask 2501 with definition I/O zone 4406 then, the partition that anisotropic etching polysilicon layer 520 forms on transistor grid structure and the empty interposed structure sidewall.
Remove resistance mask 2501 earlier, above the selection grid of transistorized grid of I/O and storage array, form photoresist layer 1710 (Figure 61), the polysilicon layer 520 in the remaining zone of etching.
The doping step that the suitable stage in technology suits forms transistorized source electrode and drain region, bit line and source electrode line zone and other doped regions.
In certain embodiments, memory cell is MLC (multilevel cells, MLC), be that each memory cell can store the information that surpasses a bit, each floating gate 124 can store three or more charge energy rank, corresponds to three or more different control gate 128 threshold voltage, sees also the United States Patent (USP) 5 of Lee in bulletin on September 4th, 1999,953,255.
The present invention is not limited to the above embodiments, the present invention not only be defined in specific erase or the mechanism that stylizes (as Fowler-Nordheim, or hot electron injects), non-flash electronic type programmable read-only memory (the electrically eraseableprogrammable read only memory that can erase is contained in the present invention, EEPROM) and other known or not the invention memories, the present invention also is not limited only to above-mentioned material, such as control gate, selecting the material of grid and other conducting elements can be metal, metal silicide, multi-crystal silicification metal and other electric conducting materials or compound, perhaps also can comprise conductor and conductor part simultaneously, as the part doped polycrystalline silicon layer, silicon dioxide or silicon nitride also can replace with other insulating material, P type and N type conduction pattern can exchange, the present invention is not subject to any specific program step or sequence of steps, give an example, in certain embodiments, the thermal oxidation of silicon can change into chemical vapour deposition technique or other technologies deposition layer of silicon dioxide or other insulating material, in certain embodiments, dark injection 2110 can be carried out behind etching insulating material 1010, the invention is not restricted to silicon integrated circuit, the claim scope definition other meet the embodiment and the variation of category of the present invention.
Claims (1)
- One kind erase the semiconductor intra-zone and above the method for flash memory memory cell, this storage array comprises a plurality of sections, each this section can be erased individually, each this section has a plurality of memory cell, this method comprises:This memory receives an instruction, and this instruction can be first kind of instruction all memory cell with the whole storage array of erasing, and can be second kind of instruction and selected section in the whole storage array of erasing;When receiving first kind of instruction, this substrate regions imposes one first positive voltage, and all control gates impose one second negative voltage, floats and be provided with in the bit line zone, floats and be provided with in the source electrode line zone; Select grid to impose 0V, so that the electronics in the floating gate is subjected to the attraction of this substrate regions positive voltage and erases;When receiving second kind of instruction, this substrate regions imposes a 0V voltage, the control gate of the section that this is selected imposes first negative voltage, the bit line zone imposes second positive voltage, this second positive voltage is greater than 0V but less than VCC, the source electrode line zone of the section of being chosen imposes the 3rd positive voltage, the selection grid of selected section imposes 0V, wherein, the 3rd positive voltage is relatively higher than second positive voltage, so that the electronics in this floating gate in the selected section is subjected to the attraction of the regional positive voltage of source electrode line that this quilt chooses and is erased the absolute value of above-mentioned this first negative voltage＞this first positive voltage＞the 3rd positive voltage＞VCC.
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| CN 01145049 CN1280891C (en) | 2001-12-31 | 2001-12-31 | Non-volatile storage structure and its manufacturing method |
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| CNB2004100965896A Expired - Lifetime CN100533740C (en) | 2001-12-31 | 2001-12-31 | Integrated circuit comprising non-volatile memory |
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| CNB2004100965896A Expired - Lifetime CN100533740C (en) | 2001-12-31 | 2001-12-31 | Integrated circuit comprising non-volatile memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100365817C (en) * | 2003-08-28 | 2008-01-30 | 旺宏电子股份有限公司 | Non-volatile memory array structure |
| JP4455017B2 (en) * | 2003-11-10 | 2010-04-21 | 株式会社東芝 | Nonvolatile semiconductor memory device |
| CN100452355C (en) * | 2005-08-19 | 2009-01-14 | 力晶半导体股份有限公司 | Nonvolatile memory, and manufacturing method |
| CN100385646C (en) * | 2005-08-19 | 2008-04-30 | 力晶半导体股份有限公司 | Semiconductor component of preventing breakdown, and manufacturing method |
| US8125051B2 (en) * | 2008-07-03 | 2012-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device layout for gate last process |
| US7981801B2 (en) | 2008-09-12 | 2011-07-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chemical mechanical polishing (CMP) method for gate last process |
| KR20100108715A (en) * | 2009-03-30 | 2010-10-08 | 주식회사 하이닉스반도체 | Method for manufacturing of non-volatile memory device |
| CN102931143B (en) * | 2011-08-10 | 2015-04-29 | 无锡华润上华科技有限公司 | Method for manufacturing NOR flash device |
| CN103021855B (en) * | 2011-09-27 | 2015-04-01 | 中芯国际集成电路制造(上海)有限公司 | Separate gate flash memory active region manufacturing method |
| CN103151458B (en) * | 2013-03-22 | 2015-04-29 | 厦门博佳琴电子科技有限公司 | Embedded phase change memory array and manufacturing method |
| KR102146449B1 (en) * | 2013-12-18 | 2020-08-20 | 인텔 코포레이션 | Heterogeneous layer device |
| US10043672B2 (en) * | 2016-03-29 | 2018-08-07 | Lam Research Corporation | Selective self-aligned patterning of silicon germanium, germanium and type III/V materials using a sulfur-containing mask |
| WO2018030666A1 (en) * | 2016-08-11 | 2018-02-15 | 에스케이실트론 주식회사 | Wafer and manufacturing method therefor |
| CN107845634B (en) * | 2016-09-19 | 2020-04-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN108091658B (en) * | 2017-11-16 | 2021-04-13 | 上海华力微电子有限公司 | Process integration structure and method of flash memory |
| CN114678370B (en) * | 2022-05-30 | 2022-08-02 | 广州粤芯半导体技术有限公司 | Flash structure and preparation method thereof |
| CN115274676B (en) * | 2022-09-29 | 2022-12-13 | 广州粤芯半导体技术有限公司 | Flash memory structure and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0223595A (en) * | 1988-07-12 | 1990-01-25 | Mitsubishi Electric Corp | Method for writing in nonvolatile semiconductor memory |
| US5280446A (en) * | 1990-09-20 | 1994-01-18 | Bright Microelectronics, Inc. | Flash eprom memory circuit having source side programming |
| CN1218294A (en) * | 1997-10-09 | 1999-06-02 | 美商常忆科技股份有限公司 | Nonvolatile PMOS two transistor memory cell and array |
| JPH11297081A (en) * | 1998-04-03 | 1999-10-29 | Ricoh Co Ltd | Nonvolatile semiconductor memory |
-
2001
- 2001-12-31 CN CNB2004100965881A patent/CN100390960C/en not_active Expired - Lifetime
- 2001-12-31 CN CN 01145049 patent/CN1280891C/en not_active Expired - Lifetime
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0223595A (en) * | 1988-07-12 | 1990-01-25 | Mitsubishi Electric Corp | Method for writing in nonvolatile semiconductor memory |
| US5280446A (en) * | 1990-09-20 | 1994-01-18 | Bright Microelectronics, Inc. | Flash eprom memory circuit having source side programming |
| CN1218294A (en) * | 1997-10-09 | 1999-06-02 | 美商常忆科技股份有限公司 | Nonvolatile PMOS two transistor memory cell and array |
| JPH11297081A (en) * | 1998-04-03 | 1999-10-29 | Ricoh Co Ltd | Nonvolatile semiconductor memory |
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| CN100533740C (en) | 2009-08-26 |
| CN1632952A (en) | 2005-06-29 |
| CN1280891C (en) | 2006-10-18 |
| CN1632945A (en) | 2005-06-29 |
| CN1430264A (en) | 2003-07-16 |
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