JP2010183098A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device which has memory cell with a high coupling ratio without generating etching residue on a separation oxide film of a peripheral circuit. <P>SOLUTION: The nonvolatile semiconductor memory device comprises a memory cell, a peripheral circuit adjacent to the memory cell, an element separation to separate the active region of a substrate, and a semiconductor element formed in the active region. The active region in the memory cell has a plurality of strip-like first active regions arranged in a shorter direction, and second active regions which connect ends of the first active regions with each other and are arranged as to surround the memory cell. A height of the upper surface of the element separation in the peripheral circuit is equal to, or higher than that of the substrate. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to prevention of generation of etching residue in element isolation of a peripheral circuit adjacent to a memory cell.

  A method for improving the coupling ratio of a memory cell of a nonvolatile semiconductor memory device has been proposed (see, for example, Patent Document 1).

  In addition, as a method for improving the coupling ratio of the memory cell known to the applicant, which is not a known technique, the side surface of the control electrode is exposed by etching the isolation oxide film as element isolation by a predetermined thickness. There is a method of increasing the surface area of the floating gate electrode facing the control gate electrode. Hereinafter, this method will be described.

  17 to 24 are process cross-sectional views for explaining a conventional method for manufacturing a nonvolatile semiconductor memory device.

  First, as shown in FIG. 17A, a thermal oxide film 2 is formed on the silicon substrate 1, and a silicon nitride film 3 is formed on the thermal oxide film 2. Further, a resist pattern 4 having an opening corresponding to the element isolation region is formed on the silicon nitride film 3 by photolithography.

  Next, the silicon nitride film 3 and the thermal oxide film 2 are sequentially dry etched using the resist pattern 4 as a mask. Thereafter, the resist pattern 4 is removed. Subsequently, the silicon substrate 1 is etched using the patterned silicon nitride film 3 as a mask. As a result, trenches 5 are formed in the silicon substrate 1 as shown in FIG.

  Next, a thermal oxide film (not shown) is formed on the inner wall of the trench 5, and then, as shown in FIG. 18A, a silicon oxide film 6 serving as an isolation oxide film is formed on the entire surface of the substrate 1. Next, as shown in FIG. 18B, the silicon oxide film 6 is planarized by CMP using the silicon nitride film 3 as a stopper film.

  Next, when the silicon nitride film 3 is removed by hot phosphoric acid, the structure shown in FIG. 19A is obtained. Further, when the thermal oxide film 2 is removed with hydrofluoric acid, the structure shown in FIG. 19B is obtained. FIG. 25 is a top view showing an active region in the memory cell array. As shown in FIG. 25, a plurality of strip-like active regions A are formed side by side in the lateral direction. An isolation oxide film 6 as element isolation is formed so as to isolate this active region A.

  Next, as shown in FIG. 20A, a thermal oxide film 7 to be a tunnel oxide film is formed on the surface of the substrate 1, and a polysilicon film 8 to be a floating gate electrode of the memory cell is formed on the entire surface of the substrate 1.

  Next, as shown in FIG. 20B, the polysilicon film 8 is planarized by CMP using the isolation oxide film 6 as a stopper film. As a result, the surface of the silicon oxide film 6 and the surface of the polysilicon film 8 have the same height. Here, the polysilicon film 8 is positioned in a self-aligned manner with respect to the isolation oxide film 6.

  Next, as shown in FIG. 21A, the isolation oxide film 6 is selectively etched by a predetermined thickness with hydrofluoric acid. Thereby, the upper part of the side surface of the polysilicon film 8 is exposed, the surface area of the floating gate electrode 8 facing the control gate electrode can be increased, and the coupling ratio of the memory cell can be improved.

  Thereafter, an ONO film 10 is formed on the entire surface of the substrate 1 as shown in FIG.

  Next, as shown in FIG. 22A, a resist pattern 11 covering the memory cell region is formed by photolithography.

  Then, as shown in FIG. 22B, the ONO film 10 and the polysilicon film 8 of the peripheral circuit are sequentially dry etched using the resist pattern 11 as a mask. Further, the thermal oxide film 7 in the peripheral circuit is removed with hydrofluoric acid. Thereafter, when the resist pattern 11 is removed, the structure shown in FIG. Here, as shown in FIG. 23A, in the peripheral circuit, the surface of the isolation oxide film 6 falls below the surface of the substrate 1, so that a level difference B is generated.

  Next, as shown in FIG. 23B, a thermal oxide film 12 to be a gate oxide film is formed on the surface of the substrate 1 in the peripheral circuit. Then, a polysilicon film 13 and a WSi film 14 are sequentially formed on the entire surface of the substrate 1 as conductive films to be the control gate electrode of the memory cell and the gate electrode of the peripheral circuit. A silicon nitride film 15 is formed on the WSi film 14, and a control gate electrode portion and a resist pattern 16 covering the gate electrode portion are formed on the silicon nitride film 15 by photolithography.

  Next, as shown in FIG. 24, the silicon nitride film 15 is dry-etched using the resist pattern 16 as a mask. Thereafter, the resist pattern 16 is removed. Subsequently, the WSi film 14 and the polysilicon film 13 are sequentially dry etched using the patterned silicon nitride film 15 as a mask. At this time, since the step B exists on the element isolation 6 of the peripheral circuit as described above, there is a high possibility that an etching residue (polysilicon residue) 13a is generated in the step B portion.

JP 2003-23115 A

  In the above manufacturing method, the isolation oxide film 6 in the peripheral circuit is also etched when the isolation oxide film 6 is etched in order to improve the coupling ratio of the memory cell. For this reason, when the ONO film 10 and the thermal oxide film 7 in the peripheral circuit are removed, the isolation oxide film 6 is further etched, and the surface of the isolation oxide film 6 falls more than the surface of the substrate 1, resulting in a step B. There was a problem that. For this reason, there is a problem that an etching residue 13a is generated at the step B when patterning the gate electrode thereafter. There is a problem that a circuit element that should be originally insulated is conducted through the residue 13a and a circuit failure occurs.

  The present invention has been made to solve the above-described problems, and a nonvolatile semiconductor memory device having a memory cell having a high coupling ratio without generating an etching residue on an isolation oxide film of a peripheral circuit. The purpose is to provide.

  A non-volatile semiconductor memory device according to the present invention is a non-volatile semiconductor memory device having a memory cell and a peripheral circuit adjacent to the memory cell, wherein element isolation for isolating an active region of a substrate, and the active region The active region in the memory cell includes a plurality of strip-shaped first active regions arranged in a short direction and an end of the first active region connected to each other. And a second active region disposed so as to surround the memory cell, and the upper surface of the element isolation in the peripheral circuit is equal to or higher than the surface of the substrate It is characterized by.

  As described above, the present invention removes the multilayer insulating film, the polysilicon film, and the silicon oxide film in the peripheral circuit by etching only the element isolation in the memory cell using the first resist pattern as a mask. Generation of a step with respect to the substrate surface can be suppressed on the element isolation of the peripheral circuit, and an etching residue can be prevented from being generated at the step.

It is sectional drawing for demonstrating the manufacturing method of the non-volatile semiconductor memory device by embodiment of this invention (the 1). FIG. 9 is a cross-sectional view for explaining the method of manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention (No. 2). It is sectional drawing for demonstrating the manufacturing method of the non-volatile semiconductor memory device by embodiment of this invention (the 3). FIG. 7 is a cross-sectional view for explaining the method of manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention (No. 4). It is sectional drawing for demonstrating the manufacturing method of the non-volatile semiconductor memory device by embodiment of this invention (the 5). It is sectional drawing for demonstrating the manufacturing method of the non-volatile semiconductor memory device by embodiment of this invention (the 6). It is sectional drawing for demonstrating the manufacturing method of the non-volatile semiconductor memory device by embodiment of this invention (the 7). It is sectional drawing for demonstrating the manufacturing method of the non-volatile semiconductor memory device by embodiment of this invention (the 8). It is sectional drawing for demonstrating the manufacturing method of the non-volatile semiconductor memory device by embodiment of this invention (the 9). It is sectional drawing for demonstrating the manufacturing method of the non-volatile semiconductor memory device by embodiment of this invention (the 10). It is sectional drawing for demonstrating the manufacturing method of the non-volatile semiconductor memory device by embodiment of this invention (the 11). FIG. 3 is a top view showing an active region in a memory cell array in the embodiment of the present invention. FIG. 6 is a top view showing a positional relationship between an active region of a memory cell and a resist pattern covering a peripheral circuit in the embodiment of the present invention. It is CC sectional drawing in FIG. In the comparative example with respect to embodiment of this invention, it is a top view which shows the positional relationship of the active region of a memory cell, and the resist pattern which covers a peripheral circuit. It is sectional drawing which shows the problem in the comparative example with respect to embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the conventional non-volatile semiconductor memory device (the 1). It is sectional drawing for demonstrating the manufacturing method of the conventional non-volatile semiconductor memory device (the 2). It is sectional drawing for demonstrating the manufacturing method of the conventional non-volatile semiconductor memory device (the 3). It is sectional drawing for demonstrating the manufacturing method of the conventional non-volatile semiconductor memory device (the 4). It is sectional drawing for demonstrating the manufacturing method of the conventional non-volatile semiconductor memory device (the 5). It is sectional drawing for demonstrating the manufacturing method of the conventional non-volatile semiconductor memory device (the 6). It is sectional drawing for demonstrating the manufacturing method of the conventional non-volatile semiconductor memory device (the 7). It is sectional drawing for demonstrating the manufacturing method of the conventional non-volatile semiconductor memory device (the 8). It is a top view which shows the active region in a memory cell array.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof may be simplified or omitted.

  A method for manufacturing a nonvolatile semiconductor memory device according to an embodiment of the present invention will be described below with reference to the drawings.

  1 to 11 are process cross-sectional views for explaining the method of manufacturing the nonvolatile semiconductor memory device according to the present embodiment.

  In each figure, a cross section of the active region of the peripheral circuit and a cross section of the memory cell in the gate width direction and the gate length direction are shown. Moreover, the cross section of the element isolation area | region of a peripheral circuit is shown as needed.

  First, as shown in FIG. 1A, a silicon oxide film (hereinafter referred to as “thermal oxide film”) 2 is formed on a substrate (for example, a silicon substrate) 1 by a thermal oxidation method to a thickness of, for example, about 10 nm. . Then, a silicon nitride film 3 is formed on the thermal oxide film 2 by a CVD method with a film thickness of about 100 nm, for example. Further, a resist pattern 4 is formed on the silicon nitride film 3 by photolithography so as to cover a portion corresponding to the active region and open a portion corresponding to the element isolation region.

  Next, the silicon nitride film 3 and the thermal oxide film 2 are sequentially dry etched using the resist pattern 4 as a mask. Thereafter, the resist pattern 4 is removed. Subsequently, the substrate 1 is etched using the patterned silicon nitride film 3 as a mask. Thereby, as shown in FIG. 1B, a trench 5 having a depth of about 200 nm to 300 nm is formed in the substrate 1 so as to communicate with the opening of the silicon nitride film 3.

  Next, although not shown, a thermal oxide film is formed on the inner wall of the trench 5. Thereafter, as shown in FIG. 2A, a silicon oxide film 6 to be an isolation oxide film is formed on the entire surface of the substrate 1 with a film thickness of, for example, about 500 nm. Thereby, the openings of the trench 5 and the silicon nitride film 3 are filled with the silicon oxide film 6.

  Next, as shown in FIG. 2B, the silicon oxide film 6 is planarized by CMP using the silicon nitride film 3 as a stopper film. Thereby, the surface of the silicon nitride film 3 and the surface of the silicon oxide film 6 become the same height.

  Next, when the silicon nitride film 3 is removed by hot phosphoric acid, the structure shown in FIG. 3A is obtained. Further, when the thermal oxide film 2 is removed with hydrofluoric acid, the structure shown in FIG. 3B is obtained. Thereby, an isolation oxide film 6 whose upper surface is higher than the surface of the substrate 1, that is, an isolation oxide film 6 whose upper surface protrudes from the surface of the substrate 1 is formed. FIG. 12 is a top view showing an active region in the memory cell array. As shown in FIG. 12, a plurality of strip-shaped active regions A are formed side by side in the lateral direction, and an isolation oxide film 6 is formed as an element isolation so as to isolate the active region A. Unlike the conventional memory cell array shown in FIG. 25, in this embodiment, the active region A 'is formed at the end of the memory cell array, so that the memory cell array is surrounded by the active region A'. That is, the active region A ′ is formed at the boundary portion between the memory cell and the peripheral circuit. Around the active region A ', element isolation from the peripheral circuit is formed. The active region A ′ formed at the end of the memory cell array connects the ends of the strip-shaped active region A to each other. The width W1 of the active region A ′ is set to be wider than at least the width W2 of the strip-shaped active region A. A dummy gate or the like can be formed at the end of the active region A.

  Next, as shown in FIG. 4A, a silicon oxide film 7 to be a tunnel oxide film is formed on the surface of the substrate 1 by a thermal oxidation method, and then a polysilicon film 8 to be a floating gate electrode of the memory cell is formed. For example, it is formed with a film thickness of about 150 nm. As a result, the isolation oxide film 6 is covered with the polysilicon film 8.

  Next, as shown in FIG. 4B, the polysilicon film 8 is planarized by CMP using the isolation oxide film 6 as a stopper film. As a result, the surface of the isolation oxide film 6 and the surface of the polysilicon film 8 have the same height. Here, the position of the polysilicon film 8 is determined in a self-aligned manner with respect to the isolation oxide film 6. Therefore, the floating gate electrode 8 is formed in a self-aligned manner with respect to the isolation oxide film 6, and the high-precision alignment between the isolation oxide film and the floating gate electrode, which is necessary when using photoengraving, is unnecessary. Become.

  Next, as shown in FIG. 5A, a resist pattern 9 covering the peripheral circuit is formed. Here, as described above, the thick active region A ′ is formed at the end of the memory cell array (see FIG. 12), but in this step, as shown in FIGS. 13 and 14, the end of the resist pattern 9 is the active region A. The resist pattern 9 is arranged so as to be positioned above. As a result, the surface of the isolation oxide film 6 in the peripheral circuit near the boundary with the memory cell is covered with the resist pattern 9. The width W1 of the active region A 'is set to a width that takes into account the overlay allowance and dimensional variation of the resist pattern 9 so that the end of the resist pattern 9 does not step off the active region A'.

  Next, the isolation oxide film 6 in the memory cell is etched by a predetermined thickness with hydrofluoric acid. Thereafter, when the resist pattern 9 is removed, the structure shown in FIG. 5B is obtained. Since part of the side surface 8a of the polysilicon film 8 is exposed by etching the isolation oxide film 6, the surface area of the floating gate electrode 8 facing the control gate electrode (described later) is increased, and the coupling ratio of the memory cell is improved. . At this time, since the peripheral circuit is masked by the resist pattern 9, the isolation oxide film 6 in the peripheral circuit is not etched.

  Next, as shown in FIG. 6A, an ONO film 10 as a multilayer insulating film is formed on the entire surface of the substrate 1. The ONO film 10 is a three-layer insulating film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are stacked. Instead of the ONO film 10, a two-layer insulating film (ON film or NO film) in which a silicon oxide film and a silicon nitride film are stacked, or a four-layer structure in which a silicon oxide film and a silicon nitride film are alternately stacked. An insulating film (ONON film or NONO film) can be formed.

  Then, a resist pattern 11 covering the memory cell region and having an opening corresponding to the peripheral circuit region is formed by photolithography.

  Next, as shown in FIG. 6B, the ONO film 10 and the polysilicon film 8 in the peripheral circuit region are sequentially dry etched. Subsequently, the thermal oxide film 7 in the peripheral circuit region is removed with hydrofluoric acid. Here, when the isolation oxide film 6 in the memory cell is etched, the isolation oxide film 6 in the peripheral circuit is masked by the resist pattern 9 and is not etched. Therefore, when the thermal oxide film 7 is removed, the surface of the isolation oxide film 6 does not drop more than the surface of the substrate 1 as in the prior art. That is, the step B which has occurred in the conventional peripheral circuit as shown in FIG. 22A by performing a normal etching process does not occur in the present invention. In other words, the upper surface of the isolation oxide film 6 in the peripheral circuit is equal to or higher than the surface of the substrate 1.

  Thereafter, the resist pattern 11 is removed.

  Next, as shown in FIG. 7A, a silicon oxide film 12 serving as a gate insulating film is formed in the peripheral circuit with a film thickness of, for example, about 15 nm by a thermal oxidation method. Subsequently, a polysilicon film 13 and a tungsten silicide film (hereinafter referred to as “WSi film”) 14 are stacked on the entire surface of the substrate 1 as a conductive film to be a control gate electrode of a memory cell and a gate electrode of a peripheral circuit. Further, a silicon nitride film 15 is formed on the WSi film 14, and a resist pattern 16 covering the control gate electrode portion of the memory cell and the gate electrode portion of the peripheral circuit is formed thereon by photolithography.

  Next, as shown in FIG. 7B, the silicon nitride film 15 is dry-etched using the resist pattern 16 as a mask. Thereafter, the resist pattern 16 is removed. Subsequently, the WSi film 14 and the polysilicon film 13 are sequentially dry etched using the patterned silicon nitride film 15 as a mask. As a result, the control gate electrodes (13, 14) are formed in the memory cells, and the gate electrodes (13, 14) are formed in the peripheral circuits. At this time, since there is no step on the isolation oxide film 6 of the peripheral circuit as described above, generation of etching residue can be suppressed.

  Next, a resist pattern covering the peripheral circuit is formed by photolithography. Then, the ONO film 10 and the polysilicon film 8 are sequentially dry-etched using the patterned silicon nitride film 15, WSi film 14 and polysilicon film 13 as a mask. Thereafter, source / drain regions 18 are formed in the upper layer of the substrate 1 of the memory cell by ion implantation. Subsequently, the resist pattern is removed. Next, when the silicon nitride film 19 is formed on the entire surface of the substrate after thermally oxidizing the gate sidewall, the structure shown in FIG. 8A is obtained.

  Next, the silicon nitride film 19 is etched back to form a side wall 20 covering the side wall of the gate electrode in a self-aligned manner. Then, after forming a resist pattern covering the memory cell by photolithography, a source / drain region 21 is formed on the upper layer of the substrate 1 of the peripheral circuit by ion implantation. Thereby, a structure as shown in FIG. 8B is obtained.

  Next, as shown in FIG. 9, a BPSG film 22 serving as an interlayer insulating film is formed on the entire surface of the substrate 1. Then, a resist pattern 23 having a contact hole forming portion is formed on the BPSG film 22 by photolithography. Furthermore, as shown in FIG. 10A, the contact hole 24 reaching the source / drain region 18 is formed by dry etching the BPSG film 22 using the resist pattern 23 as a mask. Thereafter, the resist pattern 23 is removed. In the same manner, contact holes 25 and 26 reaching the source / drain regions 18 and 21 are formed as shown in FIG. The cross section of the memory cell (gate width direction) in FIGS. 1 to 9 shows the cross section of the gate electrode portion, while the cross section of the memory cell (gate width direction) in FIGS. 10 to 11 shows the cross section of the contact portion.

  Next, a tungsten film is deposited on the entire surface of the substrate 1, and planarization or etch back is performed by CMP using the BPSG film 22 as a stopper film. Thus, tungsten plugs 27 are formed in the contact holes 24, 25, and 26 as shown in FIG.

  Next, a BPSG film 28 as an interlayer insulating film is formed on the BPSG film 22 and the plug 27. Then, a resist pattern in which a via hole forming portion is opened is formed on the BPSG film 28 by photolithography. Further, by dry etching the BPSG film 28 using this resist pattern as a mask, a via hole reaching the desired plug 27 is formed. Thereafter, the resist pattern is removed. Subsequently, a tungsten film is deposited on the entire surface of the substrate 1 and planarized or etched back by CMP using the BPSG film 28 as a stopper film, thereby forming a tungsten plug 29 in the via hole. Finally, an aluminum wiring 30 connected to the tungsten plug 29 is formed. Thereby, a structure as shown in FIG. 11B is obtained.

  As described above, in the present embodiment, by etching the isolation oxide film 6 in the memory cell using the resist pattern 9 as a mask, the ONO film 10, the polysilicon film 8, and the thermal oxide film 7 in the peripheral circuit are thereafter formed. When removing, it is possible to suppress the occurrence of a step with respect to the surface of the substrate 1 on the isolation oxide film 6 of the peripheral circuit. Therefore, the etching residue of the polysilicon film can be prevented from being generated on the isolation oxide film 6 of the peripheral circuit, and the reliability of the nonvolatile semiconductor memory device can be improved.

  Next, a comparative example for the above embodiment will be described.

  FIG. 15 is a top view showing the positional relationship between the active region of the memory cell and the resist pattern covering the peripheral circuit in this comparative example.

  In the above embodiment, as shown in FIGS. 13 and 14, the end portion of the resist pattern 9 is arranged on the active region A ′ surrounding the end portion of the memory cell array. Thereby, the isolation oxide film 6 at the boundary between the memory cell and the peripheral circuit is not etched, and the occurrence of a step can be prevented. That is, in the non-volatile semiconductor memory device manufactured using the method according to the above embodiment, the upper surface of the isolation oxide film 6 at the boundary between the memory cell and the peripheral circuit has the same height as the surface of the substrate 1 or Higher than the surface.

  On the other hand, in this comparative example, as shown in FIG. 15, the active region A ′ that connects the end portions of the strip-shaped active region A is not formed, and the isolation oxide film 6 at the boundary between the memory cell and the peripheral circuit An end portion of the resist pattern 9 was arranged on the top. In this case, as shown in FIG. 16, the portion of the isolation oxide film 6 not covered with the resist pattern 9 is etched, and as a result, a step C is generated. Due to this step C, by removing the ONO film 10, the polysilicon film 8, and the thermal oxide film 7 of the peripheral circuit performed by masking the memory cell after that, the conventional peripheral circuit is formed at the boundary portion between the memory cell and the peripheral circuit. A step on the isolation oxide film 6 as generated occurs.

  In the present embodiment, the step C can be prevented from occurring by disposing the end portion of the resist pattern 9 on the active region A ′. Therefore, it is possible to prevent the occurrence of a step on the isolation oxide film 6 at the boundary portion between the memory cell and the peripheral circuit, and further to prevent the generation of etching residue.

    1 substrate (silicon substrate), 2 thermal oxide film, 3 silicon nitride film, 4 resist pattern, 5 trench, 6 isolation oxide film (silicon oxide film), 7 tunnel oxide film (silicon oxide film), 8 floating gate electrode (poly Silicon film), 9 resist pattern, 10 ONO film, 11 resist pattern, 12 gate insulating film (silicon oxide film), 13 polysilicon film, 14 WSi film, 15 silicon nitride film, 16 resist pattern, 19 silicon nitride film, 20 Sidewall, 21 source / drain region, 22 interlayer insulating film (BPSG film), 23 resist pattern, 24, 25, 26 contact hole, 27 plug, 28 interlayer insulating film (BPSG film).

Claims (3)

A nonvolatile semiconductor memory device having a memory cell and a peripheral circuit adjacent to the memory cell,
Element isolation for isolating the active region of the substrate;
A semiconductor element formed in the active region,
The active regions in the memory cell are arranged so that a plurality of strip-shaped first active regions arranged in a short direction and the end portions of the first active region are connected to each other and surround the memory cell. A second active region formed,
A non-volatile semiconductor memory device, wherein an upper surface of the element isolation in the peripheral circuit is equal to or higher than a surface of the substrate. A nonvolatile semiconductor memory device having a memory cell and a peripheral circuit adjacent to the memory cell,
Element isolation for isolating the active region of the substrate;
A semiconductor element formed in the active region,
The active regions in the memory cell are arranged so that a plurality of strip-shaped first active regions arranged in a short direction and the end portions of the first active region are connected to each other and surround the memory cell. A second active region formed,
A non-volatile semiconductor memory device, wherein a height of an upper surface of the element isolation in the memory cell is lower than a height of an upper surface of the element isolation in the peripheral circuit.   The nonvolatile semiconductor memory device according to claim 1, wherein a width of the second active region is wider than a width of the first active region.

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