KR100660548B1 - Non-volatile memory device and method of forming the same - Google Patents

Abstract

A nonvolatile memory device and a method of forming the same are provided. This device is characterized in that the upper surface of the floating gate is bent in double. As a result, the area where the floating gate overlaps with the control gate becomes very large, thereby increasing the coupling ratio. Therefore, even if the height of the floating gate is lowered, the area is enlarged by the bending, so that the program efficiency is increased by the increased coupling ratio. In addition, since one sidewall of the floating gate is aligned with one sidewall of the device isolation layer, misalignment does not occur, thereby damaging the substrate, thereby improving reliability of the semiconductor device.

Nonvolatile Memory Device.

Description

Non-volatile memory device and method of forming the same

1 to 6 are cross-sectional views sequentially illustrating a method of forming a nonvolatile memory device according to an embodiment of the present invention.

7 is a cross-sectional view of a nonvolatile memory device formed in accordance with another embodiment of the present invention.

 8 is a cross-sectional view of a nonvolatile memory device formed in accordance with another embodiment of the present invention.

The present invention relates to a semiconductor device and a method of forming the same, and more particularly, to a nonvolatile memory device and a method of forming the same.

 Nonvolatile memory devices, such as flash memory devices, have floating gates for storing data and control gates for program, read, and erase functions. The nonvolatile memory device may be divided into a split gate type and a stack gate type due to the structure of the gates.

On the other hand, the gap between the floating gates is also narrowed due to high integration of semiconductor devices. As a result, the coupling ratio between the floating gates increases, and a malfunction occurs in the program operation due to the mutual coupling. One way to prevent this is to lower the height of the floating gate. However, if the height of the floating gate is lowered, the area coupled between the control gate and the floating gate is reduced, so that the coupling ratio is lowered, thereby decreasing program efficiency.

Accordingly, an object of the present invention is to provide a nonvolatile memory device and a method of forming the same, which can reduce the coupling ratio between floating gates, prevent malfunction of the device, and increase program efficiency. .

According to an aspect of the present invention, there is provided a nonvolatile memory device, comprising: an isolation layer disposed on a semiconductor substrate to define an active region; A gate insulating layer on the active region; A floating gate positioned on the gate insulating layer; A control gate positioned on the floating gate; And an interlayer insulating film interposed between the control gate and the floating gate, wherein an upper surface of the floating gate includes a plurality of recessed regions.

The recessed regions may include at least a first recessed region; And a second recessed region having a narrower width than the first recessed region and formed at the bottom of the first recessed region. Sidewalls of the first recessed region may be inclined or vertical. Sidewalls of the second recessed region may be inclined or vertical. One side wall of the device isolation layer may be aligned with one side wall of the floating gate.

The nonvolatile memory device may be formed by the following method. First, an isolation layer is formed on a semiconductor substrate to define an active region. A gate insulating film is formed on the active region. A floating gate film is formed on the gate insulating film. The upper portion of the floating gate layer is patterned to form a plurality of recessed regions. A gate interlayer insulating film and a control gate film are formed. The control gate layer, the gate interlayer insulating layer, and the floating gate layer are sequentially patterned to form a floating gate and a control gate.

In the method, a plurality of the recessed regions may be formed as follows. First, a mask pattern for partially exposing the floating gate layer is formed on the floating gate layer. The floating gate layer is etched using the mask pattern as an etching mask to form a first recessed region having a first width on the floating gate layer. A spacer is formed to cover sidewalls of the mask pattern and sidewalls of the first recessed region. The floating gate layer on the bottom of the recessed region is etched using the mask pattern and the spacer as an etching mask to form a second recessed region having a second width on the floating gate layer.

The nonvolatile memory device may be formed by the following method. First, a first mask pattern is formed on a semiconductor substrate. The semiconductor substrate is etched using the first mask pattern to form trenches. A device isolation insulating layer is formed to fill and planarize the trench to expose the first mask pattern. The first mask pattern is removed to expose the semiconductor substrate between the device isolation insulating layers. A gate insulating film is formed on the exposed surface of the semiconductor substrate. A floating gate film is formed to fill between the device isolation insulating films on the semiconductor substrate. The floating gate layer is planarized to expose the device isolation insulating layer, and a floating gate layer pattern is formed between the device isolation insulating layers. A second mask pattern having a first opening having a first width that partially exposes the floating gate layer pattern is formed. The floating gate layer pattern is etched using the second mask pattern to form a first recessed region. A mask spacer is formed to cover sidewalls of the second mask pattern and sidewalls of the first recessed area, and partially expose a bottom of the first recessed area. The floating gate layer pattern is etched using the second mask pattern and the mask spacer as an etch mask to form a second recessed region. The device isolation layer insulating layer is etched to expose sidewalls of the floating gate layer pattern. The second mask pattern and the mask spacer are removed, and a gate interlayer insulating film and a control gate film are conformally stacked. The gate interlayer insulating film, the control gate film, and the floating gate film pattern are sequentially etched to form a floating gate, a gate interlayer insulating film pattern, and a control gate stacked in this order.

Sidewalls of the first recessed region may be formed to have an inclined or vertical profile. Sidewalls of the second recessed region may be formed to have an inclined or vertical profile.

 Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Portions denoted by like reference numerals denote like elements throughout the specification.

 1 to 6 are cross-sectional views sequentially illustrating a method of forming a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 1, a pad oxide film 3 is formed on a semiconductor substrate 1 and a first mask pattern 5 is formed thereon. The pad oxide film 3 may be formed of, for example, a thermal oxide film. The first mask pattern 5 may be formed of, for example, a nitride film and / or a medium temperature oxide (MTO) to a thickness of, for example, 1400 kPa. The trench 7 is formed by etching the pad oxide layer 3 and a predetermined portion of the semiconductor substrate 1 by using the first mask pattern 5 as an etching mask.

Referring to FIG. 2, a device isolation insulating layer 9 is stacked to fill and planarize the trench 7 to expose the first mask pattern 5. The exposed first mask pattern 5 and the pad oxide layer 3 are removed to form a space 13 through which upper walls of the device isolation insulating layers 9 are exposed. When the first mask pattern 5 is formed of a silicon nitride film, the first mask pattern 5 may be removed by wet etching using an etchant containing phosphoric acid. The pad oxide layer 3 may be removed with an etchant containing hydrofluoric acid. A gate insulating film 11 is formed on the surface of the semiconductor substrate 1 on which the pad oxide film 3 is exposed. The gate insulating layer 11 may be formed as a thermal oxide film by, for example, a thermal oxidation process.

Referring to FIG. 3, the floating gate layer 15 may be entirely formed of a polysilicon layer doped with impurities or not doped to fill the space 13. A planarization process is performed on the floating gate layer 15 to expose the isolation isolation layer 9, and the floating gate layer 15 is left in the space 13.

Referring to FIG. 4, a second mask pattern 17 having an opening exposing a part of the exposed floating gate layer 15 is formed on the entire surface of the semiconductor substrate 1. The second mask pattern 17 may be formed of, for example, a silicon nitride film and / or an MTO. A first recessed region having a first width on the floating gate layer 15 by partially patterning the exposed floating gate layer 15 by using the second mask pattern 17 as an etching mask. 19). In this embodiment the sidewalls of the first recessed region 19 are preferably formed to be inclined.

Referring to FIG. 5, a spacer film is conformally stacked on the entire surface of the semiconductor substrate 1. The spacer film may be formed, for example, of silicon nitride film and / or MTO. Anisotropic etching is performed on the spacer layer to form a spacer 21 covering the sidewall of the second mask pattern 17 and the sidewall of the first recessed region 19, and at the same time the first recessed The floating gate layer 15 at the bottom of the region 19 is partially exposed. The exposed floating gate layer 15 is etched using the second mask pattern 17 and the spacer 21 as an etch mask to narrow the first width above the floating gate layer 15. A second recessed region 23 having two widths is formed. The sidewalls of the second recessed region 23 are formed to have a vertical profile.

Referring to FIG. 6, the second mask pattern 17 and the spacer 21 are removed by wet etching. An etching process is performed on the exposed device isolation insulating layer 9 to lower the height of the device isolation insulating layer 9 to form the device isolation layer 9, and expose sidewalls of the floating gate layer 15. The gate interlayer insulating film 25 and the control gate film 27 are conformally stacked on the entire surface of the semiconductor substrate 1. The gate interlayer insulating film 25 may be formed of, for example, a triple layer of an oxide film, a nitride film, and an oxide film. The control gate layer 27 may be formed of, for example, a double layer of a polysilicon and a tungsten silicide layer doped with impurities. The control gate layer 27, the gate interlayer insulating layer 25, and the floating gate layer 15 are sequentially patterned to form the floating gate 15 and the control gate 27.

According to the nonvolatile memory device disclosed in FIG. 6, the upper surface of the floating gate 15 is bent in double by the first recessed region 19 and the second recessed region 23. Therefore, the area of the upper surface of the floating gate 15 is widened, and the area where the control gate 27 overlaps with the floating gate 15 is increased, thereby increasing the coupling ratio. Therefore, even if the height of the floating gate 15 is lowered, the area is widened by the bending, so that the program efficiency is increased by the increased coupling ratio. In addition, according to the nonvolatile memory device formed by the above-described method, since one sidewall of the floating gate 15 is aligned with one sidewall of the device isolation layer 9, misalignment does not occur, thereby damaging the substrate and thereby It can improve the reliability.

Sidewalls of the first recessed region 19 and sidewalls of the second recessed region 23 may have a vertical profile as shown in FIG. 7. Alternatively, the sidewalls of the first recessed region 19 and the sidewalls of the second recessed region 23 may both have an inclined profile as shown in FIG. 8. All of these may be easily formed by adjusting the etching conditions in the etching process of FIGS. 4 and 5.

In the present embodiment, a method of forming two recessed regions is described, but three or more recessed regions may be formed on the floating gate. If three recessed regions are to be formed on the floating gate, the sidewalls of the spacer 21 and the second recessed region 23 may be formed while the second recessed region 23 is formed. An additional mask spacer covering the sidewalls is further formed and the upper portion of the floating gate is etched using the mask spacer as an etch mask (not shown) to form a third recessed region (not shown).

Therefore, according to the nonvolatile memory device and the method for forming the same according to the present invention, the upper surface of the floating gate is bent in double, so that the overlapping area with the control gate becomes very wide, thereby increasing the coupling ratio. Therefore, even if the height of the floating gate is lowered, the area is enlarged by the bending, so that the program efficiency is increased by the increased coupling ratio. In addition, since one sidewall of the floating gate is aligned with one sidewall of the device isolation layer, misalignment does not occur, thereby damaging the substrate, thereby improving reliability of the semiconductor device.

Claims (12)

An isolation layer disposed on the semiconductor substrate to define an active region; A gate insulating layer on the active region; A floating gate positioned on the gate insulating layer; A control gate positioned on the floating gate; And A gate interlayer insulating film interposed between the control gate and the floating gate; And an upper surface of the floating gate includes a plurality of recessed regions. The method of claim 1, The recessed areas, At least a first recessed area; And And a second recessed region having a narrower width than the first recessed region and formed at a bottom of the first recessed region. The method of claim 2, And sidewalls of the first recessed region are inclined or vertical. The method of claim 2, And sidewalls of the second recessed region are inclined or vertical. The method of claim 1, And one side wall of the isolation layer is aligned with one side wall of the floating gate. Forming an isolation layer on the semiconductor substrate to define an active region; Forming a gate insulating film on the active region; Forming a floating gate film on the gate insulating film; Patterning an upper portion of the floating gate layer to form a plurality of recessed regions; Forming a gate interlayer insulating film and a control gate film; And And patterning the control gate film, the gate interlayer insulating film, and the floating gate film in order to form a floating gate and a control gate. The method of claim 6, Patterning an upper portion of the floating gate layer to form a plurality of recessed regions, Forming a mask pattern on the floating gate layer to partially expose the floating gate layer; Etching the floating gate layer by using the mask pattern as an etching mask to form a first recessed region having a first width on the floating gate layer; Forming a spacer covering sidewalls of the mask pattern and sidewalls of the first recessed region; And Etching the floating gate layer on the bottom of the recessed region by using the mask pattern and the spacer as an etching mask to form a second recessed region having a second width on the floating gate layer. A method of forming a nonvolatile memory device, characterized in that.  The method of claim 7, wherein Wherein the sidewalls of the first recessed region are formed to have an inclined or vertical profile.   The method of claim 7, wherein Sidewalls of the second recessed region are formed to have an inclined or vertical profile. Forming a first mask pattern on the semiconductor substrate; Etching the semiconductor substrate using the first mask pattern to form a trench; Forming a device isolation insulating film to fill and planarize the trench to expose the first mask pattern; Removing the first mask pattern to expose the semiconductor substrate between the device isolation insulating layers; Forming a gate insulating film on a surface of the exposed semiconductor substrate; Forming a floating gate layer to fill the gaps between the device isolation insulating layers on the semiconductor substrate; Forming a floating gate layer pattern between the device isolation insulating layers by exposing the device isolation insulating layer by planarizing etching the floating gate layer; Forming a second mask pattern having a first opening having a first width to partially expose the floating gate layer pattern; Etching the floating gate layer pattern using the second mask pattern to form a first recessed region; Forming a mask spacer covering a sidewall of the second mask pattern and a sidewall of the first recessed region, wherein the mask spacer partially exposes a bottom of the first recessed region; Etching the floating gate layer pattern using the second mask pattern and the mask spacer as an etching mask to form a second recessed region; Etching the device isolation layer insulating layer to expose sidewalls of the floating gate layer pattern; Removing the second mask pattern and the mask spacer and conformally stacking a gate interlayer insulating film and a control gate film; And And sequentially etching the gate interlayer insulating film, the control gate film, and the floating gate film pattern to form a floating gate, a gate interlayer insulating film pattern, and a control gate stacked in this order. The method of claim 10, Wherein the sidewalls of the first recessed region are formed to have an inclined or vertical profile.  The method of claim 10, Sidewalls of the second recessed region are formed to have an inclined or vertical profile.

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