JP2003249578A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a non- volatile memory cell unit of high scalability (reducibility). <P>SOLUTION: The semiconductor integrated circuit device comprises element isolation regions STI for isolating element active regions AA in a semiconductor substrate, a first interconnection BL, a second interconnection SL, and a memory cell unit MU. The memory cell unit MU comprises two selector transistors STS and STD which are formed in the element isolation regions AA and are connected between the first and second interconnections BL and SL, and not more than two memory cell transistors MT connected between the selector transistors. Each of the memory cell transistors MT has an electric charge accumulation layer, with side faces of the electric charge accumulation layer being nearly the same faces or nearly the same faces as the side faces of the element isolation regions AA. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device including a non-volatile memory transistor.

[0002]

2. Description of the Related Art Nonvolatile semiconductor memory devices such as NAN
A typical memory cell of a D-type flash memory is described in Non-Patent Document 1 (R. Shirota).

In Non-Patent Document 1, especially in element isolation, ST
256 Mbit using I (Shallow Trench Isolation)
The history of development of NAND flash memory products is shown.

The memory cell unit described in Non-Patent Document 1 has a structure in which selection transistors are arranged on both sides of a plurality of memory cell transistors connected in series. Each of the plurality of memory cell transistors is formed in the element active region. The element active region is separated by an element isolation region, for example, STI, and the element active region and STI are arranged in parallel with each other to form a memory cell array.

A part of the floating gate layer of the memory cell transistor covers the STI. The volume of the covered portion earns a so-called "coupling ratio", which is the ratio of the capacitance between the floating gate layer and the channel and the capacitance between the floating gate layer and the control gate layer.

In order to form such a memory cell transistor, a conductive layer which is a part of the floating gate layer,
Very thin strip patterns, so-called "slits" must be formed. FIG. 28 shows a stage in which the slit is formed.

As shown in FIG. 28, the conductor layer 104 is
It is a part of the floating gate layer of the memory cell transistor and a conductor which becomes the gate of the selection transistor. The slit 103 is formed in a portion on the STI of the conductor layer 104 in parallel with the STI. Its width is narrower than STI. By forming such slits 103 in the conductor layer 104, the floating gate layer can be separated for each memory cell transistor.

In a normal NAND flash memory,
By connecting a plurality of memory cell transistors in series and reducing the number of contacts between the bit line and the memory cell unit, miniaturization of the memory cell is realized.

However, as shown in FIG. 29, in the memory cell transistor, when the number of memory cell transistors is as small as one or two, the distance D _{SG -SG} between the gates of the select transistors becomes relatively narrow. When the distance D _SG-SG is relatively narrowed, it becomes difficult to form the slit 103 in the conductor layer 104.

According to Non-Patent Document 1, it is possible to process a region narrower than a region patterned by lithography by a so-called spacer process.

However, when the spacing D _SG-SG becomes narrower, it is difficult to form the slit 103 sufficiently wider than the element isolation width required in the memory cell unit, considering the processing conversion difference and the like. It will become. Also, ST
When the width of I and the width of the element active area AA are formed with the minimum processing dimensions, it is difficult to form the slit 103 by patterning by exposure.

Examples of reducing the number of memory cell transistors in the memory cell unit are, for example, Non-Patent Document 2 (K. Imamiya, et al.) And Patent Document 1 (Japanese Patent Laid-Open No. 2000-2000).
-149581 (Sakui et al.), Non-Patent Document 3 (G.
Tao et al.).

For example, Non-Patent Document 2 reports the use of a single memory cell transistor. E using so-called 3-transistor cell unit
EPROM. Such a flash memory is likely to be affected by the above-mentioned problems in advancing miniaturization.

Therefore, Non-Patent Document 4 (S. Aritome, et a
As described in (1.), a method of forming a floating gate layer in self-alignment with STI has been proposed.

However, as described in Non-Patent Document 4, when the floating gate layer is formed in a self-aligned manner with respect to STI, for example, a part of the gate layer of the select transistor becomes a floating portion of the memory cell transistor. As in the case of the portion to be the gate layer, there is a situation in which it is separated for each select transistor.

[0016]

[Patent Document 1] Japanese Patent Laid-Open No. 2000-149581

[0017]

[Non-Patent Document 1] R. Shirota, “A Review of 256Mb
it NAND Flash Memories and NAND Flash Futur
e Trend ”, Non-Volatile Semiconductor Memory Works
hop (= NVSMW) 2000 pp22-31.

[0018]

[Non-Patent Document 2] K. Imamiya, et al., “32 kbyte th
ree-transistor flash for embedded applications usi
ng 0.4um NAND flash technology ”, Non-Volati
leSemiconductor Memory Workshop (= NVSMW) 2000 p
p78-80.

[0019]

[Non-Patent Document 3] G. Tao et al., “Reliability aspec
t of embedded floating-gate non-volatile memories
with uniform channel FN tunneling for both progra
m ”, Non-Volatile Semiconductor Memory Workshop (= N
VSMW) 2001 pp130-132.

[0020]

[Non-Patent Document 4] S. Aritome, et al., “A 0.67um
2 SELF-ALIGNED SHALLOW TRENCHISOLATION CELL (SA-ST
I CELL) FOR 3V-only 256Mbit NAND EEPROMs ”
IEDM (1994) pp 61-64.

[0021]

The present invention has been made in view of the above circumstances, and a first object thereof is to provide a small number, for example, two or less memory cell transistors and one or more select gates. It is an object of the present invention to provide a semiconductor integrated circuit device having high scalability (reducibility) that enables a memory cell unit including a transistor to be formed with a minimum processing size.

A second object of the present invention is to provide a semiconductor integrated circuit device having a semiconductor memory part which has both a large capacity, high speed performance and high reliability.

A third object is to provide a semiconductor integrated circuit device suitable for an IC card, which has a main memory and a controller for controlling the main memory.

[0024]

In order to achieve the above object, a semiconductor integrated circuit device according to a first aspect of the present invention comprises:
A semiconductor substrate; an element isolation region formed in the semiconductor substrate for isolating an element active region in the semiconductor substrate;
A wire, a second wire, two select transistors formed in the element active region and connected between the first and second wires, and two or less connected between the two select transistors Memory cell unit including one memory cell transistor, or one select transistor and one
The memory cell unit includes a pair of memory cell transistors. Further, the memory cell transistor has a charge storage layer, and a side surface of the charge storage layer is on the same plane or substantially the same plane as a side surface of the element isolation region.

In order to achieve the above object, a semiconductor integrated circuit device according to a second aspect of the present invention includes a memory cell array, a plurality of electrically rewritable memory cells provided in the memory cell array, and at least one memory cell. A first cell block in which a plurality of memory cell strings in which selection transistors are connected in series are arranged, and a plurality of electrically rewritable numbers provided in the memory cell array and different in number from the first cell block A second cell block in which a plurality of memory cell strings in which a plurality of memory cells and at least one selection transistor are connected in series are arranged.

To achieve the above object, a semiconductor integrated circuit device according to a third aspect of the present invention includes a memory circuit having a non-volatile memory cell array and a control circuit for controlling the memory circuit. The control circuit has a page buffer, and the page buffer includes a 3-transistor cell block or a 2-transistor cell block.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the present invention will be described below with reference to the drawings. In this description, common reference numerals are given to common portions throughout the drawings.

(First Embodiment) In order to form a select gate line, as a method of connecting portions which become gate layers separated for each select transistor to each other, for example, one of floating gate layers of memory cell transistors is connected. It is conceivable to use a conductor layer serving as a portion or a conductor layer serving as a control gate layer for connecting the portions serving as gate layers separated for each select transistor to each other.

An example of forming such a contact is as follows:
This is a method in which a conductor layer which is a part of the floating gate layer of the memory cell transistor is extended over the STI in the portion where the select transistor is formed and a contact is made on the STI (for example, Japanese Patent Application No. 2000-301380). issue).

In another example, a contact is formed with respect to a conductor layer which is a part of the gate layer of the select transistor,
This is a system in which a conductor layer that serves as a control gate layer of a memory cell transistor is short-circuited to this conductor layer to make a contact on the element active area AA (for example, Japanese Patent Application No. 2000-2).
91910).

FIG. 1 is a plan view showing an example of a plane pattern of the nonvolatile semiconductor memory device according to the first embodiment of the present invention, FIG. 2A is a sectional view taken along the line 2A-2A in FIG.
2B is a sectional view taken along the line 2B-2B in FIG.

As shown in FIGS. 1, 2A and 2B, a device isolation region STI is formed in a semiconductor substrate such as a P-type silicon substrate or a P-type well 1. The element isolation region STI isolates the element active region AA in the P-type well 1. In the example shown in FIG. 1, the STI is formed in a stripe shape, and a stripe-shaped element active area AA is separated on the surface of the P-type well 1. The memory cell unit MU is formed in the element active area AA.

Memory cell unit MU of the first embodiment
Is a so-called 3-transistor cell unit. The three-transistor cell unit includes a source-side selection transistor STS, a drain-side selection transistor STD, and one memory cell transistor MT connected between these selection transistors STS and STD.

The N-type source / drain diffusion layer 2 of the source side select transistor STS is connected to the common source line SL via the contact 3. In addition, the N-type source / drain diffusion layer 2 of the drain side select transistor STD
Is the data line or the bit line BL via the contact 4.
It is connected to the. As a result, the memory cell unit M
U is connected between the source line SL and the data line or the bit line BL.

The common source line SL extends, for example, in a direction orthogonal to the extending direction of the element active region AA and the element isolation region STI. Then, the common source line SL is formed, for example, from the first-layer metal wiring layer formed on the gate electrodes of the transistors STS, STD, and MT. The common source line SL in this example is, for example, the select transistor ST.
It extends from above the gate electrodes of S and STD to above the gate electrode of the memory cell transistor MT.

The bit line BL is, for example, the element active area AA.
And in the extending direction of the element isolation region STI. And
The bit line BL is formed of, for example, a second-layer metal wiring layer formed on a layer further above the common source line SL.

The memory cell transistor MT has a charge storage layer, for example, the floating gate layer 5. In the floating gate layer 5 of this example, the side surface of the floating gate layer 5 is on the same plane as the side surface of the element isolation region STI, or almost the same plane, as indicated by the dashed circle A in FIG. 2B, for example.

An inter-gate insulating film 6 is formed on the floating gate 5 layer.
The control gate layer 7 is formed via the. The control gate layer 7 functions as the word line WL. The inter-gate insulating film 6 is composed of, for example, a three-layer insulating film including a silicon oxide film, a silicon nitride film, and a silicon oxide film. The three-layer structure insulating film is generally called an ONO film.

Each of the select transistors STS and STD has a gate layer 8 formed of the same conductor layer as the floating gate layer 5, for example. The gate layer 8 is the floating gate layer 5
Unlike, for example, it is short-circuited to a gate layer 9 formed of the same conductor layer as the control gate layer 7. The gate layer 9 is
It functions as select gate lines SGS and SGD. An example of a method of short-circuiting the gate layer 8 to the gate layer 9 is, for example, an insulating film 10 formed of the same insulator layer as the intergate insulating film 6.
An opening 11 is formed in the gate layer 9, and the gate layer 9 is brought into contact with the gate layer 8 through the opening 11. As a result, the gate layer 8 is integrated with the gate layer 9 and the select transistor ST
It functions as a gate electrode for S and STD.

By the way, an impurity for controlling the channel concentration of the select transistors STS and STD is introduced into the gate layer 8 through the opening 11 formed in the insulating film 10.
The present inventors have proposed a method of implanting ions through the gate (Japanese Patent Application No. 2001-158066). An example of the channel impurity introducing step according to this method is shown in FIG. 3A.

As shown in FIG. 3A, an insulating layer, for example, an ONO film 13 is formed on a conductive layer, for example, a conductive polysilicon layer 12, which is patterned in the pattern of the element active area AA. Conductive polysilicon layer 12
Is a conductor layer serving as the floating gate layer 5 and the gate layer 8. Further, the ONO film 13 is an insulator layer to be the inter-gate insulating film 6 and the insulating film 10. Then, the ONO film 1
A mask layer, for example, a photoresist layer 14 is formed on the photoresist layer 3, and a window 15 corresponding to the opening 11 is formed in the photoresist layer 14. Next, the insulating film 10 is etched by using the photoresist layer 14 as a mask,
An opening 11 is formed in the. Next, using the photoresist layer 14 as a mask, for example, the same P-type impurity as the P-type well 1, for example, boron is ion-implanted into the P-type well 1 through the conductive polysilicon 12. As a result, the P-type well 1 below the portion that becomes the gate layer 8 of the select transistors STS and STD, that is, the select transistor ST
The impurity concentration (channel concentration) of the S and STD channel regions is higher than that of the other regions.

FIG. 3B shows a cross section of a nonvolatile semiconductor memory device formed according to an example of such a channel impurity introduction step.

As shown in FIG. 3B, the selection transistor S
The impurity concentration of the channel regions 16 of TS and STD is higher than that of the channel region 17 of the memory cell transistor MT. As described above, by using the example of the channel impurity introduction step shown in FIG. 3A, the fine memory cell transistors MT, the fine select transistors STS, and STD are arranged at high density as shown in FIG. 3B, for example. , The channel concentration of the memory cell transistor MT and the selection transistors STS and ST
The channel concentration of D can be controlled separately.

The N-type source / drain diffusion layer 2 of the source-side selection transistor STS and the common source line SL are connected via a contact 3, and similarly the N-type source / drain diffusion layer 2 of the drain-side selection transistor STD and the bit are connected. The connection with the line BL is made via the contact 4.
The contact 3 of this example is formed directly from the layer in which the common source line SL is formed (first metal wiring layer) to the N-type source / drain diffusion layer 2 of the source side select transistor STS. There is. Similarly, contact 4 of this example
Is formed directly from the layer in which the bit line BL is formed (second metal wiring layer) to the N-type source / drain diffusion layer 2 of the drain side select transistor STD.

The contacts 3 and 4 in this example are so-called self-aligned contacts. In the self-aligned contact, some of the contacts are select transistors STS and S.
It has a structure that covers the upper part of the gate electrode (8, 9) of the TD. For example, a mask material insulating film 18 is formed on the gate electrodes (8, 9) of the select transistors STS and STD. The mask material insulating film 18 is an interlayer insulating film 19
Has etching selectivity with respect to. Mask material insulating film 18
One example of the material is a silicon nitride film (SiN). When the material of the mask material insulating film 18 is a silicon nitride film,
An example of the material of the interlayer insulating film 19 is a silicon oxide film (Si
O ₂ ). Since the mask material insulating film 18 has etching selectivity with respect to the interlayer insulating film 19 as described above, only the interlayer insulating film 19 embedded between the gate electrodes of the selection transistors STS and between the gate electrodes of the STD is It can be selectively etched. Thereby, contact holes can be opened in a self-aligned manner between the gate electrodes of the select transistor STS and between the gate electrodes of the STD. At this time, the conductor of the self-aligned contact 3 is close to the gate electrode of the select transistor STS via the sidewall insulating film 20, and covers the gate electrode via the mask material insulating film 18. Similarly, the conductor of the self-aligned contact 4 is close to the gate electrode of the select transistor STD via the sidewall insulating film 20, and covers the gate electrode via the mask material insulating film 18. However, it is not the gate electrode of the memory cell transistor MT but the gate electrodes of the select transistors STS and STD that are close to the conductors of the self-aligned contacts 3 and 4. For this reason,
For example, the high voltage induced on the bit line BL or the like does not act on the gate electrode of the memory cell transistor MT, for example, the floating gate layer 5.

It is also possible that the contacts 3 and 4 are not self-aligned contacts. In this case, the space between the select transistor and the memory cell transistor is filled with, for example, a silicon oxide film, and the space between the memory cell transistor and the select transistor is blocked. A structure in which only the drain diffusion layer 2, the gate electrode of the peripheral transistor, the gate electrode of the selection transistor, and the control gate electrode of the memory cell transistor are silicide films is also conceivable (for example, Japanese Patent Application Nos. 2001-0755511 and 2).
001-244557).

According to the nonvolatile semiconductor memory device of the first embodiment, the gate electrodes of the select transistors STS and STD include the gate layer 8 and the gate layer 9, for example, the same insulator layer as the intergate insulating film 6. Insulating film 10 formed from
, For example, by forming the opening 11 in the central portion, a short circuit occurs. That is, a method of making contact with the gate layer 8 from below the gate layer 9 is adopted (for example, Japanese Patent Application No. 2000-291910). The gate layer 9 is formed of, for example, the same conductor layer as the control gate layer 7. Therefore, the electric resistance value of the gate layer 9 of the select transistors STS and STD, that is, the electrode material of the select gate lines SGD and SGS, is the electric resistance value of the control gate layer 7 of the memory cell transistor MT, that is, the electrode material of the word line WL. Is the same as
The electrode material of the control gate layer 7 has, for example, a laminated structure of conductive polysilicon and metal silicide. The metal silicide is, for example, tungsten silicide (WSi) or the like. The electrode material of the floating gate layer 5 is, for example, conductive polysilicon.

In this way, the select gate lines SGD, SGS
Since the electric resistance value of the electrode material of is the same as the electric resistance value of the electrode material of the word line WL, the selection gate line SG
The electric resistance value of the D and SGS electrode materials is, for example, the word line W
It does not become higher than the electric resistance value of the L electrode material.
Therefore, the delay in the select gate lines SGD and SGS is reduced, and high speed operation becomes possible.

Further, the common source line SL and the bit line B
Regarding the wiring material of L, the wiring material having a low electric resistance value,
For example, by using aluminum (Al), it is possible to suppress the delay in the common source line SL with respect to the select gate lines SGS and SGD. At the same time, it becomes possible to form a compact common source line SL that can be sufficiently accommodated in the three-transistor cell unit.

If the wiring material of the common source line SL does not have a low resistance with respect to the bit line BL, the common source line SL is connected to, for example, the select transistors STS and STD as in the first embodiment. It may be formed so as to extend from the upper part of the gate electrode of the memory cell transistor MT to the upper part of the gate electrode of the memory cell transistor MT. In the case of forming such a common source line SL, if the shape is such that the contact 4 is directly formed from the bit line BL as in the first embodiment, for example, it is within a range that fits in the region above the memory cell transistor MT. It is sufficient to secure the common source line region.

The wide common source line SL is
The electrical resistance can be reduced, and the bit line BL can be shielded from noise from the memory cell transistor MT, for example.

The operation of the memory cell transistor MT of the nonvolatile semiconductor memory device according to the first embodiment is basically the same as that of the memory cell transistor of the NAND flash memory.

For example, when writing data, the high voltage V is applied to the control gate of the selected memory cell transistor MT.
Apply pp. As a result, the floating gate layer 5 has F
Electrons are injected by the N tunnel current and data is written. Here, if the coupling ratio is about 0.6, the high voltage Vpp is set to about 20V.

As data, for example, electrons are injected,
When the threshold voltage of the memory cell transistor MT is higher than a certain reference voltage, it is regarded as data “0”, and electrons are not injected or electrons are extracted and the threshold voltage of the memory cell transistor MT is higher than the reference voltage. When it is low, the data is “1”. This is similar to the conventional flash memory. Therefore, the point of determining the presence or absence of data is the same as the conventional one.

On the other hand, when erasing data, for example, P
Data is erased by applying a high voltage Vpp to the mold well 1 and drawing electrons into the P-well 1.

When reading data, since there is only one memory cell transistor MT, the select gate line SG
With respect to the memory block selected by S and SGD, when a voltage higher than the reference voltage is applied to the control gate layer 7 of the memory cell transistor MT, whether the transistor MT is turned on or off is "0" or " Data of "1" can be determined.

Further, since there is only one memory cell transistor MT in the memory cell unit MU,
The threshold voltage of the memory cell transistor MT may be higher than a certain value when data is written. That is, since the upper limit of the threshold voltage distribution is removed, the control of the threshold voltage distribution is simplified and the structure has a strong resistance to manufacturing variations.

(Second Embodiment) FIG. 4 is a plan view showing an example of a plane pattern of a nonvolatile semiconductor memory device according to a second embodiment of the present invention, and FIG. 5A is a cross section taken along line 5A-5A in FIG. 5 and 5B are sectional views taken along the line 5B-5B in FIG.

The second embodiment is shown in FIGS. 4, 5A and 5B.
As shown in, the 3-transistor cell unit of the nonvolatile semiconductor memory device according to the first embodiment is a so-called 4-transistor cell unit. The 4-transistor cell unit is a source-side selection transistor STS
And a drain-side selection transistor STD and two memory cell transistors MT1 and MT2 connected in series between the selection transistors STS and STD.

Memory cell unit MU of the second embodiment
There are two memory cell transistors MT1 and MT2
There is. Therefore, for example, the memory cell transistor MT
When reading data from 1, the memory cell transistor MT2 must be turned on regardless of the presence or absence of data, and similarly, when reading data from the memory cell transistor MT2, the memory cell transistor MT1 must be turned on regardless of the presence or absence of data.

As described above, in the 4-transistor cell unit, it is necessary to apply the voltage Vpass for turning on the memory cell transistor, which is not selected, to the gate of the non-selected memory cell transistor when reading data, regardless of the presence or absence of data. The threshold voltage of the memory cell transistor must be lower than the voltage Vpass. For this reason, the lower limit and the upper limit of the threshold voltage distribution are required, which is the so-called “read disturb”.
b) ”exists, which is a limitation of conventional NAND.
Type flash memory.

However, the 4-transistor cell unit
For example, N including 16 memory cell transistors
Since the number of memory cell transistors is smaller than that of the AND type cell unit, a larger cell current can be obtained, and the time for sensing the cell current can be shortened. That is, the 4-transistor cell unit can operate at higher speed than the NAND cell unit. The 4-transistor cell unit is intended to reduce the area per memory bit and to maintain high-speed operation. It is a compromise between cost advantage due to the chip area reduction effect and high-speed accessibility due to the memory cell having a small number of transistors. It meets the demand for the requirements of the non-volatile semiconductor memory device.

The 3-transistor cell unit has one memory cell per unit cell, which is advantageous for random access.

On the other hand, although the 4-transistor cell unit can also be randomly accessed, it is basically a serial access since there are two memory cells per unit cell.

As in the second embodiment, the nonvolatile semiconductor memory device according to the first embodiment can be a 4-transistor cell unit.

(Third Embodiment) FIG. 6 is a plan view showing an example of a plane pattern of a nonvolatile semiconductor memory device according to a third embodiment of the present invention, and FIG. 7A is a cross section taken along line 7A-7A in FIG. 7 and 7B are sectional views taken along line 7B-7B in FIG.

In the third embodiment, the contact 4 of the nonvolatile semiconductor memory device according to the first embodiment is divided into a plurality of layers to be formed.

As shown in FIGS. 6, 7A and 7B, the N-type source / drain diffusion layer 2 of the drain side select transistor STD is connected to the contact wiring 21 via the first layer contact 4-1. . The contact wiring 21 is formed of, for example, the same first source metal wiring layer as the common source line SL. The contact wiring 21 is connected to the bit line BL via the second layer contact 4-2. The nonvolatile semiconductor memory device according to the third embodiment has the contact 4
-1, contact wiring 21, contact 4-2,
The configuration is almost the same as the nonvolatile semiconductor memory device according to the first embodiment except that the contact 4 is divided into a plurality of layers.

As in the third embodiment, the contact 4 of the non-volatile semiconductor memory device according to the first embodiment is not directly formed. For example, the first layer contact 4-1 and
The contact wiring 21 and the second-layer contact 4-2 can be formed separately in a plurality of layers.

When the contact 4 is formed in a plurality of layers, it is necessary to consider a margin to some extent, for example, in consideration of processing variations of the contact wiring 21 and the like.
Therefore, there may be a situation in which the area for arranging the common source SL cannot be sufficiently secured.

In such a situation, as in the nonvolatile semiconductor memory device according to the first embodiment, for example, the contact 4 is connected to the layer in which the bit line BL is formed (second metal wiring layer). From the drain side select transistor STD
The structure formed directly on the N-type source / drain diffusion layer 2 is advantageous.

(Fourth Embodiment) FIG. 8 is a plan view showing an example of a plane pattern of a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention, and FIG. 9A is a sectional view taken along line 9A-9A in FIG. FIG. 9B is a sectional view taken along line 9B-9B in FIG.

The fourth embodiment is shown in FIGS. 8, 9A and 9B.
As shown in FIG. 5, the contact 4 of the nonvolatile semiconductor memory device according to the second embodiment is formed by being divided into a plurality of layers. The nonvolatile semiconductor memory device according to the fourth embodiment includes a contact 4-1, a contact wiring 21,
Like the contact 4-2, the configuration is almost the same as the nonvolatile semiconductor memory device according to the second embodiment except that the contact 4 is divided into a plurality of layers.

As in the fourth embodiment, the contact 4 of the non-volatile semiconductor memory device according to the second embodiment is not directly formed. For example, the first layer contact 4-1 and
The contact wiring 21 and the second-layer contact 4-2 can be formed separately in a plurality of layers.

(Fifth Embodiment) FIG. 10 shows the fifth embodiment of the present invention.
FIG. 3 is a circuit diagram showing a circuit example of a memory cell unit included in the nonvolatile semiconductor memory device according to the embodiment.

As the memory cell unit MU, the first,
The three-transistor cell unit described in the third embodiment,
Alternatively, in addition to the 4-transistor cell unit described in the second and fourth embodiments, a memory cell unit MU as shown in FIG. 10 can be considered.

The memory cell unit shown in FIG. 10 has one select transistor ST and one memory cell transistor M connected between the source line SL and the bit line BL.
It is a pair of T and T. In this specification, this memory cell unit MU is referred to as a 2-transistor cell unit.

In the 2-transistor cell unit shown in FIG. 10, the select transistor ST is connected to the common source line SL, and the memory cell transistor MT is connected to the bit line BL.
It is connected to the. However, as a two-transistor cell unit, it would be possible to connect the select transistor ST to the bit line BL and connect the memory cell transistor MT to the bit line BL.

FIG. 11 is a plan view showing an example of a plane pattern of a nonvolatile semiconductor memory device according to the fifth embodiment of the present invention, FIG. 12A is a sectional view taken along line 12A-12A in FIG. 11, and FIG. It is sectional drawing which follows the 12B-12B line in 11.

As shown in FIGS. 11, 12A, and 12B, the two-transistor cell unit includes one selection transistor ST and one memory cell transistor MT connected to the selection transistor ST.

The N-type source / drain diffusion layer 2 of the select transistor ST is connected to the common source line S via the contact 3.
It is connected to L. In addition, the memory cell transistor M
The T N-type source / drain diffusion layer 2 is connected to the bit line BL via a contact 4. As a result, the memory cell unit MU is connected between the source line SL and the data line or the bit line BL.

The contacts 3 and 4 of this example are respectively the first
~ It is not a self-aligned contact like the contact 4 described in the fourth embodiment. One of the reasons for this is that, for example, when a self-aligned contact is formed with respect to the gate electrode of the memory cell transistor MT, the high voltage induced in the bit line BL or the like causes the gate electrode of the memory cell transistor MT, for example, the floating gate layer. This is because there is a possibility that it will act on 5.

However, as the contact 3, a self-aligned contact could be applied. This is because in this case, a self-aligned contact is formed with the gate electrode of the select transistor ST. Then, when the self-aligned contact is applied to the contact 3,
In the nonvolatile semiconductor memory device shown in FIGS. 11, 12A, and 12B, the omitted mask material insulating film 18 will be formed at least on the gate electrode of the select transistor ST.

As in the fifth embodiment, the nonvolatile semiconductor memory device according to the first embodiment can be a two-transistor cell unit.

The nonvolatile semiconductor memory devices according to the second to fourth embodiments can also be a two-transistor cell unit.

(Sixth Embodiment) FIG. 13 shows a sixth embodiment of the present invention.
3 is a circuit diagram showing a circuit example of a memory cell array included in the nonvolatile semiconductor memory device according to the embodiment. FIG.

An application of the nonvolatile semiconductor memory device having the structure according to the first to fifth embodiments of the present invention is NA.
The ND type cell block and the three-transistor cell block described in the first and third embodiments, for example, are arranged in the same memory cell array. Then, the 3-transistor cell block is used as a portion for storing information that requires high-speed memory access, and the NAND cell block is used as a portion for storing data, for example. An architecture similar to the memory system of the nonvolatile semiconductor memory device according to the sixth embodiment is disclosed in Japanese Patent Laid-Open No. 10-134588.

As shown in FIG. 13, in the architecture in which the NAND type cell block and the three-transistor cell block are arranged in the same memory cell array, when the miniaturization is advanced as described in the section of the prior art, NA
Even if the slits can be formed in the ND type cell block, it becomes difficult to form the slits in the three-transistor cell block, and the NAND type cell block and the three-transistor cell block can be arranged in the same memory cell array. It will be difficult.

Therefore, for example, the non-volatile semiconductor memory device according to the first or third embodiment is used for a 3-transistor cell block, for example. Thereby, for example, the length of the memory cell block sandwiched between the selection transistors STS and STD can be freely adjusted. As a result, even if the miniaturization progresses, a NAND cell block and a three-transistor cell block can be arranged in the same memory cell array 50 as in the memory cell array 50 shown in FIG.

Regarding the 3-transistor cell block of the sixth embodiment, for example, a 4-transistor cell such as the non-volatile semiconductor memory device according to the second and fourth embodiments, or the non-volatile semiconductor according to the fifth embodiment. It can be replaced with a two-transistor cell such as a memory device.

Further, the NAND type cell block of the sixth embodiment can be replaced with an AND type cell block as shown in FIG.

Also, as shown in FIG. 14, when the NAND type cell block is replaced with an AND type cell block, it is possible to make the four-transistor cell an AND type.

(Seventh Embodiment) NAND flash E
As described above, the EPROM has an advantage that it is advantageous in increasing the capacity as compared with the NOR type.

In the NAND type EEPROM, a plurality of non-volatile memory cells are connected in series, and a select transistor is provided at an end thereof, so-called a memory cell string.
(NAND string). In the NAND string, the larger the number of memory cells, the smaller the area occupied by the bit line contacts and the common source lines becomes, and the scalability of the memory cell array is improved. Therefore, in order to increase the density and increase the capacity, it is preferable to increase the NAND string length (that is, the number of memory cells).

However, as the NAND string length increases, the cell current at the time of reading data decreases. NA
This is because when the selected cell in the ND string is read out, the non-selected cells connected in series to the selected cell are made conductive, and the total decrease in the conductance of these non-selected cells becomes large. If the cell current becomes small, high-speed operation cannot be performed, and the read cell current further decreases due to repeated writing and erasing, which may make it impossible to ensure reliability.

Since the cell current is proportional to the width of the active region of the memory cell, the cell current can be secured by increasing the width of the active region, but this hinders the increase in capacity.

As described above, the NAND type EEPROM
It is difficult to achieve both high capacity and high speed performance and high reliability. The seventh embodiment of the present invention relates to a semiconductor memory device that achieves both high capacity and high speed performance and high reliability.

FIG. 15A is an equivalent circuit diagram showing an equivalent circuit example of the memory cell array of the NAND type EEPROM according to the seventh embodiment of the present invention, and FIG. 15B is a plan view showing its layout example.

In the example shown in FIGS. 15A and 15B, the memory cell array is divided into, for example, three cell blocks A, B, and C, which is the range of collective data erasing. The first cell block A is a memory cell string (that is, a NAND string or a NAND cell unit) in which n non-volatile memory cells MC0 to MCn-1 are directly connected and selection transistors S1 and S2 are provided at both ends thereof. It is configured by arranging 30a. The drain of one selection transistor S1 is connected to the data transfer line (hereinafter, bit line) BL provided in each NAND string 30a, and the drain of the other selection transistor S2.
Is connected to a reference potential line (hereinafter referred to as a common source line) SL that is commonly provided to the plurality of NAND strings 30a.

The number of the second cell blocks B is m (however, m
The non-volatile memory cells MC0 to MCm-1 of <n) are directly connected to each other, and NAND strings 30b having selection transistors S1 and S2 provided at both ends thereof are arranged. The drain of the one selection transistor S1 is connected to the bit line BL provided in each NAND string 30b, and the source of the other selection transistor S2 is connected to the common source line SL commonly arranged in the plurality of NAND strings 30b. It is connected.

The third cell block C is a NAND string 30c formed by one memory cell M0 having select transistors S1 and S2 connected at both ends. The drain of the selection transistor S1 is connected to the bit line BL, and the source of the selection transistor S2 is connected to the common source line SL.

The control gates of the corresponding memory cells of the NAND strings 30a, 30b, 30c in each of the cell blocks A, B, C are connected to the word line WL in common, and the control gates of the select transistors S1, S2 are connected. The gates are similarly connected to the select gate lines SSL and GSL. The bit lines BL are the cell blocks A to C in this embodiment.
It is formed continuously over the entire area.

Here, the cell blocks A, B and C are all 2
Value storage may be performed. Alternatively, as another example, for example, the cell block A having the largest NAND string performs multi-value storage such as four-value storage to store a large amount of data,
The cell blocks B and C having a small string can perform binary storage. Alternatively, as still another example, only the cell block C having the smallest NAND string is binary-stored, and the other cell blocks A and B have 4 bits.
Value storage may be performed.

FIG. 15B shows a pattern of an active region (element region) divided into stripes, and a word line WL and select gate lines SSL, GSL in which memory cells and gates of select transistors are continuously arranged. Therefore, the bit line and the common source line are shown only in the contacts and omitted.

As shown in FIG. 15B, cell blocks A to
The width of the active region of C is constant d0. The word line pitches of the cell blocks A and B having a plurality of word lines WL are also set to w0.

In the example shown in FIGS. 15A and 15B, one NAND string is arranged in the pit line direction in each cell block A, B, C, but in reality, each cell block A, A plurality of NAND strings may be arranged in B and C in the bit line direction. In this case, in one cell block, two NAND strings adjacent to each other in the bit line direction may be formed so as to share the bit line contact and the common source line contact, for example.

A more specific cell block layout example is shown in FIG. 16, and its cross section taken along line 17-17 is shown in FIG.
FIG. 18 shows a cross section taken along line 18-18 of FIG.
Here, the cell block A shown in FIG. 15A is assumed, but other cell blocks have the same configuration except that the number of cells is different.

As shown in FIGS. 16 to 18, in the cell array region of the silicon substrate 51, a p-type well is formed for each cell block. A stripe-shaped element region (active region) 53 is defined by the element isolation insulating film 52 in this p-type well. One example of the element isolation insulating film 52 is STI.

In each element region 3, a floating gate 55 is formed via a tunnel insulating film 54, a control gate 57 is formed on the floating gate 55 via an inter-gate insulating film 56, and further self-aligned with the control gate. The formed source / drain diffusion layer 59 is formed to form the memory cell MC. The control gate 57 is continuously patterned in one direction to form the word line WL.

In this embodiment, the floating gate 55 of the memory cell is formed between the element isolation insulating films 52 in a self-aligned manner as shown in FIG. After the floating gate 55 is buried, the floating gate 55 is formed in a protruding state by etching the upper portion of the element isolation insulating film 52. Therefore, the control gate 57 faces not only the upper surface of the floating gate 55 but also both side surfaces thereof, so that a large coupling capacitance is obtained.

Regarding the selection transistors S1 and S2,
As shown in FIG. 17, the gate electrode is formed in a state where the floating gate 55 of the memory cell and the upper and lower polycrystalline silicon films to be the control gate 57 are short-circuited. The memory cell MC and the gates of the select transistors S1 and S2 are patterned while being covered with the silicon nitride film 8.

A first interlayer insulating film 60a is formed on the substrate on which the memory cell and the select transistor are formed, and a common source line (SL) 6 which is a first layer metal wiring is formed on the first interlayer insulating film 60a.
2 is formed. The common source line 62 is the interlayer insulating film 60.
It is connected to the diffusion layer 59 on the source side of the NAND string via the contact plug 61a embedded in the contact hole formed in a. A second interlayer insulating film 60b is further formed on the first interlayer insulating film 60a, and a bit line (BL) 64 which is a second layer metal wiring is formed thereon. The bit line 64 is connected to the drain side diffusion layer 69 of the NAND string via a contact plug 61b embedded in a contact hole formed in the interlayer insulating films 60a and 60b.

The contact plugs 61a and 61b are composed of two select transistors S1 and S between adjacent cell blocks.
It is embedded in a self-aligned manner between the two. That is, by using the silicon nitride film 58 covering the gate electrode as an etching stopper and performing interlayer insulating film etching using a mask having an opening larger than the inter-gate space, a contact hole self-aligned with the inter-gate space is opened. This allows
The contact plugs 61a and 61b are embedded so as to partially cover the gate electrode of the selection transistor.

As described above, FIGS. 15A and 15B
In FIG. 16, the size of one cell block in the bit line direction is one NAND string. However, in the example of FIGS. 16 to 18, in the cell block, the adjacent NAND strings in the bit line direction are drain-diffused. An example in which a plurality of NAND strings are arranged in the bit line direction by sharing the layer and the source diffusion layer is shown.

In this embodiment, FIG. 15A and FIG.
As shown in B, the bit line BL has cell blocks A to
It is formed continuously over C. Therefore, as shown in FIG. 19, the sense amplifier 70 shared by the cell blocks A to C is arranged at one end of each of the cell blocks A to C.

According to this embodiment, the cell blocks having different sizes of the NAND strings are integrated into one chip. Therefore, it is possible to obtain the performance for each application by properly using the area in the chip according to the application. For example, NAN
Since the cell block C having the smallest number of memory cells in the D string has excellent high-speed performance, the number of times of rewriting is large,
It is used as a storage area for program code that requires high-speed access. The cell blocks A and B are used as, for example, image data storage areas, which are not required to have high speed performance but need to have a large capacity because of their high density. Since the string lengths of the cell blocks A and B are different, the cell block A can be used as a data area having a larger capacity, and the cell block B can be used as a data area that requires higher speed than the cell block A.

As a result, as compared with the case where the length of the NAND string in the chip is constant, it is possible to solve the relationship of high-speed performance and the trade-off between high reliability and high density and large capacity. Further, the cell block C is used for high-speed writing / writing.
In order to read out, binary storage shall be performed, and N
If the cell block A having a large AND string length stores four values as a large-capacity data storage area,
The use of the cell block can be further optimized. The cell block B corresponds to the cell block A depending on the memory application.
It is also possible to carry out 4-value storage together with it, or to carry out binary storage together with the cell block C.

Further, as shown in FIGS. 15A and 15B, since the width of the active region is constant among the plurality of cell blocks A to C, the microfabrication condition becomes uniform in the entire cell array region, A fine memory cell can be realized with high reliability. Further, since the word line hitches of the cell blocks A and B are made equal, the row decoders for selectively driving the word lines can be arranged at a constant pitch. This is also preferable for fine processing.

Next, a modification of the seventh embodiment will be described.

FIG. 20 is a plan view showing a memory cell array of a nonvolatile semiconductor memory device according to a first modification of the seventh embodiment, and FIG. 21 is a sectional view taken along line 21-21 in FIG.

FIGS. 20 and 21 show modified examples of the bit line contact structure in correspondence with FIGS. 16 and 17. The parts corresponding to those in FIGS. 16 and 17 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the first modification, the pit line 64 is connected to the diffusion layer 59 via the relay wiring 66. The relay wiring 66 is formed on the first interlayer insulating film 60a using the same conductor material as that of the common source line 62.
The relay wiring 66 has the n-type diffusion layer 59 via the contact plug 61b1 embedded in the first interlayer insulating film 60a.
Connected with. The bit line 64 formed on the second interlayer insulating film 60b is connected to the relay wiring 66 via the contact plug 61b2 embedded in the second interlayer insulating film 60b.

The contact plug 61b1 for connecting the relay wiring 66 to the n-type diffusion layer 59 is self-aligned and embedded between the gate electrodes of two adjacent select transistors S1 and partially overlaps the gate electrodes. They are formed and arranged in a line in the direction of the word lines. Bit line 64
Plug 6 for connecting the wiring to the relay wiring 66
1b2, as shown in FIG.
They are arranged alternately on both sides of the array of b1 so as to be located on the word line. As a result, the contact plug 61b2
The arrangement pitch is 2 times that of the contact plug 61b1.
Double. Such an arrangement is used for the contact plug 61b1.
Contact plug 61 that is not self-aligned unlike
It is possible to reliably contact the relay wiring 66 without short-circuiting b2 with a relatively large area.

FIG. 22 is a plan view showing a memory cell array of a nonvolatile semiconductor memory device according to a second modification of the seventh embodiment, and FIG. 23 is a sectional view taken along the line 23-23 in FIG.

22 and 23 show another example in which the configuration of the bit line contact is modified, corresponding to FIGS. 16 and 17. The parts corresponding to those in FIGS. 16 and 17 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the second modification, a metal wiring is not used as the one corresponding to the common source line 62 and the contact plug 61a described with reference to FIGS. 16 and 17, but a buried wiring 61 made of polycrystalline silicon or a metal such as tungsten is used.
c is used. The embedded wiring 61c is self-aligned between the gate electrodes of the adjacent select transistors S2,
It is a local interconnect wiring that is embedded so as to be continuous in the word line direction and serves as a common source line.

In this case, the interlayer insulating film 60 is a single layer, and the metal wiring is only the bit line 64. The bit line 64 is
Similar to FIG. 16 and FIG. 17, it is connected to the n-type diffusion layer 59 through the contact plug 61b embedded in the interlayer insulating deer 60. By reducing the metal wiring layer in this manner, it is possible to simplify the process and reduce the manufacturing process.

FIG. 24A is a plan view showing the memory cell array of the nonvolatile semiconductor memory device according to the third modification of the seventh embodiment.

FIG. 24A shows an example in which the layout of the memory cell array is changed, corresponding to FIG. 15B.

In the third modification, the widths of active regions (element regions) between a plurality of cell blocks are made different. In the third modification, specifically, the width of the active regions of the cell blocks A and C is set to d1, and the width of the active region of the cell block B is set to d2 which is larger than d1. The word line pitch of the cell blocks A and B is set to the same w0 as in the seventh embodiment.

As a concrete cell array structure, except for the relationship between the widths of the element region and the element isolation region, FIGS.
8, the structure described in FIGS. 20 and 21,
Any of the structures described in FIGS. 22 and 23 can be applied.

In the prior art, generally, in order to separate the floating gate for each cell in the word line direction, the floating gate material film is slit on the element isolation region. On the other hand, as described with reference to FIGS. 16 to 18, when the method of embedding the floating gate in the element isolation region in a self-aligned manner is used, slit formation is not necessary, and thus the width of the element isolation region and the element region is reduced. You can freely choose the relationship.

As in the third modification, if the widths of the element regions are made different between the cell blocks, the optimum characteristics can be selected according to the use of the cell blocks.

In the example shown in FIG. 24A, focusing attention on the two cell blocks A and B, the active region width of the cell block B having the smaller NAND string length is made larger than that of the cell block B. That is, the cell block B having a small NAND string length is preferable to the application of high-speed operation as compared with the cell block A. Is preferably ensured.

As shown in FIG. 24A, cell block A,
It is difficult to form the bit lines BL in the cell blocks A and B continuously when the widths of the element regions are made different between B, especially when the pitch becomes large. Therefore, in this case, the bit lines BL are arranged at different pitches independently for each of the cell blocks A and B. Further, in this case, as shown in FIG. 25A, the sense amplifiers 70a and 70b are arranged independently for each of the cell blocks A and B.

FIG. 24B is a plan view showing the memory cell array of the nonvolatile semiconductor memory device according to the fourth modification of the seventh embodiment.

FIG. 24B shows an example in which the layout of the memory cell array is changed, corresponding to FIG. 15B.

The fourth modified example is similar to the third modified example described above.
For example, the width of the active region of the cell block B is different from the width of the active regions of the cell blocks A and C. The fourth modification is particularly different from the third modification in that each of the cell blocks A, B, and C has a bit line BL (BL0 to BL0).
4 are only shown).

In this example, the width of the active area of the cell block B is wider than the width of the active area of each of the cell blocks A and B, for example. Therefore, in this example, the bit lines BL0 to BL
Among the four, BL0, BL2, BL4, that is, the even bit lines are connected to the NAND strings in the cell block B.

Specifically, the bit lines BL0 to BL4 are
It is connected to the NAND string in cell block A via bit line contacts CA0 to CA4, and is similarly connected to the three-transistor cell block in cell block C via bit line contacts CC0 to CC4. Further, of the bit lines BL0 to BL4, the bit line BL
0, BL2, and BL4 are connected to the NAND string in the cell block B via bit line contacts CB0 to CB2. Note that the bit lines BL1 and BL3, that is, the odd bit lines pass through the cell block B. Figure 2
5B shows a layout example of the memory cell array and the sense amplifier of the nonvolatile semiconductor memory device according to the fourth modification. Further, FIG. 25B shows an equivalent circuit of the portion shown in FIG. 24B.

In the fourth modification, for example, the cell block B in which the width of the active region is wider than that of the other cell blocks A and C.
Of the bit lines, for example, the even bit lines are
The AND string is contacted and the odd bit line is passed through. Thus, for example, in a device in which the width of the active region of the cell block B is different from the width of the active regions of the cell blocks A and C, the bit line BL can be shared, and, for example, the senses of the cell blocks A, B, and C can be shared. The advantage is that the amplifier can be shared.

In the fourth modification, the cell block B is
The pitch between the bit lines in the inside can be made the same as the pitch between the bit lines in the cell blocks A and C. Therefore, it is possible to obtain an advantage that microfabrication is easily performed as compared with an apparatus in which the pitch between bit lines in the cell block B is different from the pitch between bit lines in the cell blocks A and C.

In the fourth modification, even bit lines,
That is, although ½ of all bit lines are contacted with, for example, the NAND strings in the cell block B, the present invention is not limited to this. For example, 1/4, 1/8, ... Of all the bit lines may be brought into contact with the NAND strings in the cell block B, for example. When the 1/4 bit line is brought into contact with the NAND string in the cell block B, for example, the bit lines BL0 and BL4 are connected to N in the cell block B.
Contact the AND string. For the bit lines BL1, BL2, BL3, the cell block B
Just pass the inside.

In the fourth modification, the cell block B is
NAND string length is the NAND of cell block A
Although the description has been made with the example shorter than the string length, the NAND string length of the cell block B is set to the NAN of the cell block A.
It may be equal to the D string length.

Furthermore, in the fourth modification, the width of the active region of the cell block B is different from the width of the active regions of the cell blocks A and C, but, for example, the width of the active region of the cell block C is described. Can be different from the width of the active regions of the cell blocks A and B.

As described above, according to the seventh embodiment, it is possible to obtain a NAND-type EEPROM that achieves both high capacity and high speed performance and high reliability due to high density.

(Eighth Embodiment) Recently, a nonvolatile semiconductor memory device has come to be used as a main memory of an IC card, for example, a memory card. A typical memory card includes a main memory and a controller that controls the main memory. Conventionally, in this type of memory card, for example, two IC chips, that is, both a controller IC chip and a memory IC chip are housed in one card type package (for example, Shigeo).
Araki, “The Memory Stick”, http: //www.ece.umd.e
du / courses / enee759m.S2002 / papers / araki2000-micro20
-4.pdf pp40-46.).

However, housing both the controller IC chip and the memory IC chip in one card type package hinders downsizing of the memory card and reduction of its manufacturing cost. In order to solve such a situation, for example, the controller and the memory may be integrated into one chip.

26A to 26C are block diagrams showing a nonvolatile semiconductor memory device according to the eighth embodiment of the present invention.

FIG. 26A shows a first example of the eighth embodiment.

As shown in FIG. 26A, the IC chip (IC c
The hip 90 has a main memory as a functional circuit block, for example, a flash memory 92, and a controller (contro) for controlling the flash memory 92.
ller) 91 and are included. In FIG. 26A, among some circuit blocks included in the controller 91, only circuit blocks particularly related to the main memory will be described.

The circuit blocks related to the main memory include, for example, Serial / Parallel and Parallel / Serial Inte
rface) 93, page buffer (Page Buffer) 94, and memory interface (Memory Interface) 95
Is included.

The serial / parallel and parallel / serial interface 93 stores data in the flash memory 9
When writing to 2, the serial input data (Inpu
t data) to parallel internal data. The converted parallel internal data is input to the page buffer 94 and accumulated therein. The accumulated internal data is
It is written in the flash memory 92 via the memory interface 95.

When reading data from the IC chip 90, the data read from the flash memory 92 is input to the page buffer 94 via the memory interface 95 and stored therein. The accumulated internal data is input to the serial / parallel and parallel / serial interface 93, where the parallel internal data is converted into serial output data (Output data) and output outside the chip.

Such an IC chip 90, as shown in FIG. 27, is a card type package.
By being accommodated in, mounted on, or attached to 97, it functions as an IC card, for example, a memory card.

In the first example shown in FIG. 26A, in the IC chip 90, the memory cell array of the flash memory 92 is configured to include the NAND cell block 96 described in the above embodiment, and the page buffer 94 is formed by the three-transistor cell block described in the above embodiment.

Further, in the second example shown in FIG. 26B, in the IC chip 90, the memory cell array of the flash memory 92 is configured to include the AND cell block 96 described in the above embodiment. The page buffer 94 is composed of the three-transistor cell block described in the above embodiment.

Further, in the third example shown in FIG. 26C, in the IC chip 90, the memory cell array of the flash memory 92 has the cell blocks A and B (cell blocks A) described in the above embodiment, particularly in the seventh embodiment. and B)
And the page buffer 94 is configured by the cell block C (cell block C) described in the seventh embodiment.

According to the eighth embodiment as described above, for example, in the IC chip 90 in which the controller and the memory are integrated into one chip, the flash memory 92 is configured by the NAND type cell block or the AND type cell block, and the page is The buffer 94 is composed of a 3-transistor cell block. The memory cell of the NAND cell block, the memory cell of the AND cell block, and the memory cell of the 3-transistor cell block are the same.
Therefore, for example, the advantage that the IC chip 90 is easy to manufacture can be obtained.

Further, for example, the page buffer 94 is set to 2
An advantage that the number of transistors in the page buffer 94 can be reduced can be obtained as compared with the case of being configured by a latch circuit using one CMOS inverter.

In the eighth embodiment, the page buffer 94 can also be formed by the 2-transistor cell block described in the above embodiments.

Further, the memory cell array of the flash memory 92 may be configured to include a three-transistor cell block or a two-transistor cell block and a NAND cell block as in the sixth embodiment, for example. As in the seventh embodiment, cell blocks A, B,
And C may be included.

As described above, according to the eighth embodiment, the semiconductor integrated circuit device having the main memory and the controller for controlling the main memory, which is suitable for the IC card, and the semiconductor integrated circuit device are provided. You can get an IC card.

Although the present invention has been described above with reference to the first to eighth embodiments, the present invention is not limited to each of these embodiments, and various modifications can be made without departing from the scope of the invention. It can be transformed into

Further, although each of the above-described embodiments can be carried out independently, it is of course possible to carry out them in appropriate combination.

Further, the above embodiments include inventions at various stages, and inventions at various stages can be extracted by appropriately combining a plurality of constituent elements disclosed in each embodiment. Is.

In each of the above embodiments, the present invention has been described based on an example applied to a non-volatile semiconductor memory device. However, a semiconductor integrated circuit device, such as a processor or a system, incorporating the above-mentioned non-volatile semiconductor memory device. LS
I and the like are also within the scope of the present invention.

[0168]

As described above, according to the present invention, a memory cell unit including a small number, for example, two or less memory cell transistors and one or more select gate transistors is formed with the minimum processing size. Thus, it is possible to provide a semiconductor integrated circuit device having high scalability (reducibility).

Further, it is possible to provide a semiconductor integrated circuit device provided with a semiconductor memory portion which achieves both high capacity and high speed performance and high reliability.

Further, it is possible to provide a semiconductor integrated circuit device suitable for an IC card, which has a main memory and a controller for controlling this main memory.

[Brief description of drawings]

FIG. 1 is a plan view showing an example of a plane pattern of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

2A is a sectional view taken along line 2A-2A in FIG.
2B is a sectional view taken along line 2B-2B in FIG.

3A is a cross-sectional view showing an example of a channel impurity introducing step, and FIG. 3B is a cross-sectional view showing an example of a nonvolatile semiconductor memory device formed according to the example shown in FIG. 3A.

FIG. 4 is a plan view showing an example of a plane pattern of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

5A is a cross-sectional view taken along line 5A-5A in FIG.
5B is a sectional view taken along line 5B-5B in FIG.

FIG. 6 is a plan view showing an example of a plane pattern of a nonvolatile semiconductor memory device according to a third embodiment of the present invention.

7A is a sectional view taken along the line 7A-7A in FIG.
FIG. 7B is a sectional view taken along the line 7B-7B in FIG.

FIG. 8 is a plan view showing an example of a plane pattern of a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention.

9A is a sectional view taken along line 9A-9A in FIG.
9B is a sectional view taken along the line 9B-9B in FIG.

FIG. 10 is a circuit diagram showing a circuit example of a memory cell unit included in a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 11 is a plan view showing an example of a plane pattern of a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention.

12A is a sectional view taken along line 12A-12A in FIG. 11, and FIG. 12B is a sectional view taken along line 12B-12B in FIG.

FIG. 13 is a circuit diagram showing a circuit example of a memory cell array included in a nonvolatile semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 14 is a circuit diagram showing a circuit example of a memory cell array included in a nonvolatile semiconductor memory device according to a modification of the sixth embodiment of the invention.

FIG. 15A is an equivalent circuit diagram showing an example of an equivalent circuit of a memory cell array of a nonvolatile semiconductor memory device according to a seventh embodiment of the present invention, and FIG. 15B is a NAND type EEPROM according to the seventh embodiment of the present invention. Plan view showing a layout example of the memory cell array of FIG.

FIG. 16 is a plan view showing a specific example of the layout example shown in FIG. 15B.

FIG. 17 is a sectional view taken along line 17-17 in FIG.

FIG. 18 is a sectional view taken along the line 18-18 in FIG.

FIG. 19 is a plan view showing a layout example of the memory cell array and the sense amplifier of the nonvolatile semiconductor memory device according to the seventh embodiment of the present invention.

FIG. 20 is a plan view showing a memory cell array of a nonvolatile semiconductor memory device according to a first modification of the seventh embodiment.

FIG. 21 is a cross-sectional view taken along line 21-21 in FIG.

FIG. 22 is a plan view showing a memory cell array of a nonvolatile semiconductor memory device according to a second modification of the seventh embodiment.

23 is a sectional view taken along line 23-23 in FIG.

FIG. 24A is a plan view showing a memory cell array of a nonvolatile semiconductor memory device according to a third modification of the seventh embodiment, and FIG. 24B is a nonvolatile semiconductor memory device according to the fourth modification of the seventh embodiment. Plan view showing the memory cell array of

FIG. 25A is a plan view showing a layout example of a memory cell array and sense amplifiers of a nonvolatile semiconductor memory device according to a third modification of the seventh embodiment, and FIG. 25B is a fourth modification of the seventh embodiment. A plan view showing a layout example of a memory cell array and a sense amplifier of the nonvolatile semiconductor memory device.

26A to 26C are block diagrams showing a nonvolatile semiconductor memory device according to an eighth embodiment of the present invention.

FIG. 27 is a block diagram showing an IC card using the nonvolatile semiconductor memory device according to the eighth embodiment.

FIG. 28 is a plan view showing a conventional nonvolatile semiconductor memory device when a slit is formed.

FIG. 29 is a plan view showing another conventional nonvolatile semiconductor memory device when a slit is formed.

[Explanation of symbols]

1 ... P-type well 2 ... N-type source / drain diffusion layer 3 ... Contact 4 ... Contact 4-1 ... 1st stage contact 4-2 ... Second stage contact 5 ... Floating gate layer (memory cell transistor) 6 ... Insulating film between gates 7 ... Control gate layer (memory transistor) 8 ... Gate layer (selection transistor) 9 ... Gate layer (selection transistor) 10 ... Insulating film 11 ... Opening 12 ... Conductive polysilicon layer 13 ... ONO film 14 ... Photoresist layer 15 ... window 16 ... Channel region (selection transistor) 17 ... Channel region (memory cell transistor) 18 ... Mask material layer 19 ... Interlayer insulating film 20 ... Sidewall insulating film 21 ... Contact wiring 30a, 30b, 30c ... NAND string 50 ... Memory cell array 51 ... Silicon substrate 52 ... Element isolation insulating film 53 ... Element area 54 ... Tunnel insulating film 55 ... floating gate 56 ... Inter-gate insulating film 57 ... Control gate 58 ... Silicon nitride film 59 ... Source / drain diffusion layer 60a, 60b ... Interlayer insulating film 61a, 61b ... Contact plug 62 ... Common source line 64 ... Bit line

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/788 G06K 19/00 N 29/792 (72) Inventor Kikuko Sugimae Shinsugita, Isogo-ku, Yokohama-shi, Kanagawa town address 8 Co., Ltd. Toshiba Yokohama workplace F-term (reference) 5B025 AC02 AC03 AE05 AE08 AF04 5B035 AA00 AA01 BB09 CA11 CA29 5F083 EP02 EP23 EP33 EP34 EP55 EP56 EP75 EP76 EP79 ER09 ER19 ER22 GA02 GA09 GA13 JA04 JA35 JA36 JA39 JA53 KA11 LA02 LA21 MA03 MA06 MA19 MA20 NA01 NA06 PR36 ZA05 ZA21 5F101 BA01 BA29 BA36 BB05 BD22 BD33 BD34 BD35 BE02 BE05 BE07 BF05 BH09 BH19 BH21

Claims (24)

[Claims] 1. A semiconductor substrate, an element isolation region formed in the semiconductor substrate for isolating an element active region in the semiconductor substrate, a first wiring, a second wiring, and formed in the element active region. Together with the first and second
A memory cell unit including two selection transistors connected between wirings and two or less memory cell transistors connected between the two selection transistors, wherein the memory cell transistor is a charge storage layer. And a side surface of the charge storage layer is flush with a side surface of the element isolation region,
Alternatively, a semiconductor integrated circuit device characterized by being on substantially the same plane. 2. A semiconductor substrate, an element isolation region formed in the semiconductor substrate for isolating an element active region in the semiconductor substrate, a first wiring, a second wiring, and formed in the element active region. And a memory cell unit, which is connected between the first wiring and the second wiring and has a pair of one selection transistor and one memory cell transistor, wherein the memory cell transistor stores charge. A side surface of the charge storage layer is flush with the side surface of the element isolation region,
Alternatively, a semiconductor integrated circuit device characterized by being on substantially the same plane. 3. The connection between one end of the current path of the selection transistor and the first wiring or the second wiring is connected through a contact partially covering the gate electrode of the selection transistor. 3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a semiconductor integrated circuit device. 4. The gate electrode of the select transistor is
3. The semiconductor integrated circuit device according to claim 1, comprising a first conductive layer and a second conductive layer short-circuited to the first conductive layer. 5. The semiconductor integrated circuit device according to claim 1, wherein the channel concentration of the select transistor is higher than the channel concentration of the memory cell transistor. 6. The first wiring is in a layer above the second wiring, and the first wiring selects one of the two selection transistors from a layer in which the first wiring is formed. The source / drain diffusion layer of the transistor is connected via a contact formed directly, and the second wiring is the other of the two selection transistors from the layer in which the second wiring is formed. 3. The semiconductor integrated circuit device according to claim 1, wherein the selection transistor is connected to the source / drain diffusion layer via a contact formed directly. 7. The semiconductor integrated circuit device according to claim 1, wherein the memory cell unit is integrated in a memory cell array in which NAND type memory cell units are integrated. 8. The memory cell unit according to claim 1, wherein the memory cell unit is integrated in a memory cell array in which AND type memory cell units are integrated.
The semiconductor integrated circuit device according to any one of claims. 9. A first memory cell array, and a plurality of memory cell strings arranged in the memory cell array, wherein a plurality of electrically rewritable memory cells and at least one select transistor are connected in series. A plurality of memory cell strings, in which a plurality of electrically rewritable memory cells provided in the memory cell array and different in number from the first cell block and at least one selection transistor are connected in series. And a second cell block arranged individually. 10. The semiconductor integrated circuit device according to claim 9, wherein the memory cell strings of the first cell block and the second cell block have the same element region width. 11. The semiconductor integrated circuit device according to claim 9, wherein the memory cell strings of the first cell block and the second cell block have different element region widths. 12. The one of the first and second cell blocks has a smaller number of memory cells in a memory cell string and a wider element region than the other one. Semiconductor integrated circuit device. 13. A data transfer line continuous across the first and second cell blocks is arranged to be connected to one end of each memory cell string, and the first and second data transfer lines are connected to one end of the data transfer line. 10. The semiconductor integrated circuit device according to claim 9, wherein a common sense amplifier is arranged in each of the cell blocks. 14. A data transfer line is provided independently for each of the first and second cell blocks, and a sense amplifier independent for each of the first and second cell blocks is provided at one end of each data transfer line. 10. The semiconductor integrated circuit device according to claim 9, wherein the semiconductor integrated circuit device is arranged. 15. A plurality of memory cell strings are arranged in each cell block, and a diffusion layer on one end side of the plurality of memory cell strings in each cell block is a reference potential formed inside an interlayer insulating film covering the memory cell strings. 10. The semiconductor integrated circuit device according to claim 9, wherein the semiconductor integrated circuit device is connected in common to the lines, and the diffusion layer on the other end side is connected to respective data transfer lines formed on the interlayer insulating film. 16. The interlayer insulating film has a laminated structure of first and second interlayer insulating films, and the reference potential line is formed on the first interlayer insulating film to form the first interlayer insulating film. The data transfer line is connected to one end side diffusion layer of the memory cell string through a first contact plug embedded in the film, and the data transfer line is formed on a second interlayer insulating film.
16. The semiconductor integrated circuit device according to claim 15, wherein the semiconductor integrated circuit device is connected to the other diffusion layer on the other end side of the memory cell string through a second contact plug embedded in the second interlayer insulating film. 17. The interlayer insulating film has a laminated structure of first and second interlayer insulating films, and the reference potential line is formed on the first interlayer insulating film to form the first interlayer insulating film. The data transfer line is connected to one end side diffusion layer of the memory cell string through a first contact plug embedded in the film, and the data transfer line is formed of the same conductor film as the reference potential line on the first interlayer insulating film. It is connected to the other end side diffusion layer of the memory cell string through the relay wiring formed by using the second contact plug embedded in the first interlayer insulating film. The semiconductor integrated circuit device according to claim 15. 18. The reference potential line is a conductor layer embedded between two gate electrodes sandwiching one end side diffusion layer of the memory cell string, and the data transfer line is embedded in the interlayer insulating film. 10. The semiconductor integrated circuit device according to claim 9, wherein the semiconductor integrated circuit device is connected to the other end side diffusion layer of the memory cell string via a contact plug. 19. Among the first and second cell blocks, one having a smaller number of memory cells in a memory cell string performs binary storage, and one having a larger number of memory cells performs multilevel storage. The semiconductor integrated circuit device according to claim 9. 20. A memory circuit having a non-volatile memory cell array, and a control circuit for controlling the memory circuit, wherein the control circuit has a page buffer, and the page buffer includes a 3-transistor cell block. Semiconductor integrated circuit device. 21. A memory circuit having a non-volatile memory cell array, and a control circuit for controlling the memory circuit, wherein the control circuit has a page buffer, and the page buffer includes a 2-transistor cell block. Semiconductor integrated circuit device. 22. The nonvolatile memory cell array comprises N
3. An AND type cell block is included.
22. The semiconductor integrated circuit device according to claim 0 or claim 21. 23. The non-volatile memory cell array is A
21. An ND type cell block is included.
22. The semiconductor integrated circuit device according to claim 21. 24. The non-volatile memory cell array includes a first NAND cell block having a first string length and a second NAND cell block having a second string length different from the first string length. 22. The semiconductor integrated circuit device according to claim 20, comprising a block.