JP3941517B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a semiconductor device having a plurality of wirings arranged in parallel to each other, for example, word lines of a memory cell array, and the distance between the wirings to the limit.ShortenedThe present invention relates to a method for manufacturing a semiconductor device.
[0002]
[Prior art]
  For example, a word line of a nonvolatile memory device such as a flash EEPROM (Flash Electrically Erasable and Programmable ROM) is arranged long in the row direction of the memory cell array also serving as a gate electrode of a memory transistor. The word lines are also repeatedly arranged at a certain distance in the column direction. In addition, when the bit lines are formed by patterning metal or polycrystalline silicon, the bit lines are also arranged in parallel to each other with a distance therebetween.
  There are many other wirings arranged in this way, such as word lines and bit lines of other memories (other ROMs and RAMs) or gate lines of gate arrays.
[0003]
  In such wiring patterning, after a conductive material is formed, a resist is applied on the conductive material, and a pattern on a photomask such as a reticle is transferred to the resist. Then, patterning is performed by etching the conductive material using the resist to which the pattern is transferred as a mask.
  Alternatively, a material having higher etching resistance is interposed between the conductive material and the resist, and the resist pattern is once transferred to the layer of material having higher etching resistance. Then, patterning is performed by etching the conductive material using the layer of material having strong etching resistance to which the pattern is transferred as a mask.
[0004]
[Problems to be solved by the invention]
  In such a method, patterning cannot be performed below the resolution limit of photolithography depending on the wavelength of light used.
[0005]
  A so-called phase shift method is known as a method for performing patterning below the resolution limit of photolithography.
  However, there is a limit to shortening the distance between wires by this method, and the distance between wires cannot be extremely reduced.
[0006]
  Therefore, for example, word lines in a conventional semiconductor memory are generally formed in a parallel stripe shape having a space width comparable to the word line width. For this reason, there is a waste of space in the column direction, which is one factor that hinders bit cost reduction.
  The problem that the area reduction is restricted by the wiring pitch in this way is basically common to semiconductor devices having many fine repetitive wiring patterns, such as other wiring of a memory device and wiring of a gate array.
[0007]
  A first object of the present invention is to provide a semiconductor device including a plurality of wirings of an isolation structure that can be arranged at a distance that is significantly closer than that of the prior art.
  A second object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming a plurality of wirings while being separated from each other at a distance much shorter than that of the prior art.
[0008]
[Means for Solving the Problems]
  A semiconductor device according to a first aspect of the present invention uses a plurality of memory transistors arranged in a matrix and the gate electrodes of memory transistors in the same row, and is repeatedly arranged at intervals in the column direction that are long in the row direction. A plurality of word lines, and the plurality of word linesInsulation between A film is formed and the word lines are insulated from each other, the distance between the word lines is defined by the film thickness of the insulating film, and the insulating film between the word lines is composed of a plurality of films and has a charge storage capability. A charge storage film and a thermal oxide film formed on the surface of the word line every other word line..
[0009]
  A semiconductor device according to a second aspect of the present invention provides:A plurality of memory transistors arranged in a matrix, and a plurality of word lines which are used in common in the row and repeated in the column direction, and which are used as gate electrodes of the memory transistors in the same row. A line is formed on the side surface of one word line and the cross-section is substantially ¼ elliptical, and is formed between the side wall insulating layer and the word line. The word lines are separated by an insulating film whose dimension in the direction away from the word lines is defined by the film thickness, and the plurality of word lines have a vertical side surface or a forward tapered cross-sectional shape, and the sidewall insulating layers are The first shape word lines formed on the two side surfaces and the first shape word lines in the column direction are alternately arranged, and at least an upper end portion of the side wall insulating layer is arranged. A second shape word line having a reverse taper reflecting the shape, between the first shape word line and the semiconductor, between the second shape word line and the semiconductor, and the first shape. A charge storage film including charge storage means is formed between the first word line and the sidewall insulating layer and between the second shape word line and the sidewall insulating layer. A thermal oxide film is formed between the charge storage film on the side of the shape word line and the sidewall insulating layer.
[0010]
  In the semiconductor device according to the first and second aspects, a plurality of word lines are arranged long in one side in parallel with each other. Here, the long arrangement on one side does not necessarily mean that the wiring is necessarily a straight line, and includes a case where the wiring is meandering in the same direction.
  The word lines are separated from each other by an insulating film interposed such that the distance between the word lines is set to a film thickness, for example, a charge storage film including charge storage means inside. Further, a thermal oxide film is formed on every other word line (for example, the first shape word line) of the plurality of word lines. Furthermore, particularly in the second aspect, the word lines are separated from each other by a sidewall insulating layer formed on one side surface between the word lines.
[0011]
  In these semiconductor devices, since the distance between the word lines is determined by the film thickness of the insulating film and / or the width of the sidewall insulating layer, the distance between the wirings is significantly smaller than the wiring width of the word lines. As the insulating film, a charge storage film having a charge storage capability of the memory transistor can be used by extending to the side wall and the upper surface of every other wiring.
[0012]
  A method of manufacturing a semiconductor device according to a third aspect of the present invention uses a plurality of memory transistors arranged in a matrix on a semiconductor and the gate electrodes of memory transistors in the same row, and is long in the row direction and long in the column direction. A plurality of word lines arranged repeatedly, an insulating film is formed between the plurality of word lines, and the word lines are insulated from each other, and the dimension of the insulating film in the separation direction of the word lines is a film A method of manufacturing a semiconductor device defined by a thickness, wherein a stacked pattern of a first charge storage film comprising a plurality of films and having a charge storage capability and a first word line is formed on a semiconductor in parallel with each other at a predetermined interval. A step of etching the semiconductor surface region exposed between the first word lines, and a plurality of semiconductor regions exposed on the surface of the first word line and the semiconductor region exposed between the first word lines. Made of membrane A step of forming a second charge storage film having a load storage capability and at least a portion between the first word lines are embedded with the second charge storage film interposed between the first word lines. Forming a second word line.
[0013]
  Preferably, in the present invention, each of the steps of forming the first charge storage film and the second charge storage film includes a step of thermally oxidizing a semiconductor surface to form a first potential barrier film, and the first potential storage film. Nitriding the barrier film or forming a nitride film on the first potential barrier film, wherein the first word line forming step includes forming the first word line on the semiconductor made of single crystal silicon. A step of forming one charge storage film, and a first word made of polycrystalline silicon or amorphous silicon on the first charge storage film. Forming a conductive film to be a line, and continuously etching the conductive film and the first charge storage film in the same pattern.
[0014]
  More preferably, in the etching of the semiconductor surface region, a sacrificial oxide film is formed on the single crystal silicon exposed between the first word lines, and the sacrificial oxide film is removed, thereby being consumed during sacrificial oxidation. The surface layer of the single crystal silicon is removed.
[0015]
  Preferably, in the present invention, after the formation of the second word line, overetching is performed selectively on at least one end of the first word line under a condition that the material of the second word line is removed. A further step of performing.
[0016]
  More preferably, in the step of forming the first and second word lines, the first and second word lines extend outside the memory cell array, bend in a direction different from the wiring direction of the word lines, and end from the bent portion. The wiring pitch between the first word line and the second word line on the side is set larger than the wiring pitch between the first word line and the second word line in the memory cell array, and the end on the side where the wiring pitch is large. And the electrode extraction portion of the first word line is disposed outside the electrode extraction portion of the second word line.
[0017]
  In the present invention, preferably, when the outermost first word line is present, a mask that opens around the outer side wall of the outermost first word line after the formation of the second word line. Over-etching under the condition that the material of the second word line is selectively removed through the opening of the mask layer and around the sidewall of the outermost first word line through the opening of the mask layer. And the step of performing.
[0018]
  Of the present invention4thA method of manufacturing a semiconductor device according to the aspect ofA plurality of memory transistors arranged in a matrix on a semiconductor, and a plurality of word lines that are long in the row direction and repeated in the column direction, which also serve as gate electrodes of the memory transistors in the same row. A semiconductor device in which a word line is formed on a side surface of one of the word lines and is separated by a sidewall insulating layer having a substantially elliptical cross section and an insulating film formed on the surface of the sidewall insulating layer A plurality of stacked films each including a charge storage film including a charge storage means and a first conductive film formed on the semiconductor in parallel with each other at a predetermined interval; and the stacked film A step of forming the sidewall insulating layer on the two side surfaces, and charge accumulation internally on the surface of the sidewall insulating layer and on the semiconductor region exposed between the sidewall insulating layers Forming a charge storage film including a step again, depositing a second conductive film so as to fill a recess in the surface of the charge storage film, scraping the second conductive film from the surface, and Forming a plurality of word lines separated by a wall insulating layer and the charge storage film.
[0019]
  I have said above3rd and 4thIn the method of manufacturing a semiconductor device according to the above aspect, a high-density word line arrangement can be realized by simply repeating the patterning by laminating the charge storage film and the word line material twice.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
  [First Embodiment]
  First embodimentThe virtualThe present invention relates to a nonvolatile memory device having a ground (VG) type memory cell array.
  FIG. 1A is a plan view of a VG memory cell array in which the distance between word lines is reduced by applying the present invention. 1B is a cross-sectional view taken along the line AA in FIG. 1A, and FIG. 1C is a cross-sectional view taken along the line BB in FIG.
[0021]
  As shown in FIG. 1C, source / drain regions S / D made of N-type impurity regions are formed on the surface side in a P-type semiconductor substrate SUB so as to be separated from each other. As shown in FIG. 1A, the source / drain regions S / D constitute bit lines BL1, BL2, BL3, BL4,..., And a pattern in which long lines in the column direction are arranged in parallel stripes in the entire cell array. Have
[0022]
  The substrate region sandwiched between the source / drain regions S / D is referred to as a channel formation region. This channel formation region inevitably has a parallel stripe shape that is long in the column direction.
  Long word lines WL1, WL2, WL3, WL4, WL5,... Are arranged in the row direction orthogonal to the channel formation region and the source / drain regions S / D. As shown in FIG. 1B, the even-numbered word lines WL2, WL4,... And the odd-numbered word lines WL1, WL3, WL5,. In the present embodiment, even-numbered word lines WL2, WL4,.Charge storage filmIt is formed on the semiconductor substrate SUB with the GD1 interposed. In the present embodiment, this even-numbered word line becomes the “first word line”. Also,Charge storage filmGD1 is"First charge storage film"Applicable.
[0023]
  Covering the surface of the first word lines WL2, WL4,... And the surface of the substrate region exposed between the first word lines,Charge storage filmGD2 is formed. And thisCharge storage filmWith the GD2 interposed, odd-numbered word lines WL1, WL3, WL5,... Are formed between the first word lines. In the present embodiment, the odd-numbered word lines WL1, WL3, WL5,... Become “second word lines”. All the word lines are configured by alternately arranging the second word lines and the first word lines. Also,Charge storage filmGD2"Second charge storage film"Applicable.
  The relationship between the first word line and the second word line will be described in more detail.Charge storage filmIt faces the semiconductor region between the first word lines with GD2 interposed. Most of the side of the second word lineCharge storage filmIt faces the side surface between the first word lines with GD2 interposed. In addition, both end portions in the width direction of the second word line are respectively connected to end portions in the width direction of two adjacent first word lines.Charge storage filmIt rides with GD2 interposed.
  As described above, the word line in the present embodiment is interposed between two adjacent word lines so that the dimension in the separation direction is the film thickness.Charge storage filmIt is insulated and separated by GD2. The word line is made of doped polycrystalline silicon or doped amorphous silicon.
[0024]
  In this embodiment, a MONOS type memory transistor is illustrated, soCharge storage filmEach of GD1 and GD2 includes a so-called ONO type three-layer film.
  Specifically,Charge storage filmGD1 and GD2 are the lowest layersFirst potential barrier filmBTM, middle charge trap film CHS, and top layerSecond potential barrier filmIt consists of TOP.First potential barrier filmThe BTM includes, for example, a thermal silicon oxide film formed by thermally oxidizing the substrate surface and an oxynitride film formed by nitriding the thermal silicon oxide film. The charge trap film CHS is made of, for example, silicon nitride or silicon oxynitride, and includes a large number of charge traps as discrete charge storage means.Second potential barrier filmTOP is made of, for example, a silicon oxide film.
  In the case of the so-called MNOS type,Second potential barrier filmTOP is omitted, and the charge trap film CHS is formed relatively thick. In the case of the so-called nanocrystal type,First potential barrier filmInnumerable fine particles made of, for example, polycrystalline silicon are discretely embedded between the oxide film and the oxide film.
[0025]
  Charge storage filmGD1 and GD2 have a total thickness of about a dozen nm in terms of silicon dioxide.
  Charge storage filmGD1 and GD2 are formed so that the film structures including the film thickness are equal in the portion in contact with the single crystal silicon (semiconductor substrate SUB). However,Charge storage filmThe portion of GD2 that contacts polycrystalline silicon or amorphous silicon (first word lines WL2, WL4,...) Is thicker in terms of silicon dioxide than the portion that contacts single crystal silicon. This is because the thermal oxidation rate of polycrystalline silicon or amorphous silicon is about twice that of single crystal silicon. For this reason, a satisfactory level of insulation characteristics between the word lines can be secured.
[0026]
  When writing dataWhen charge is injected into the memory portion 1 shown in FIG. 1C, a positive drain voltage is applied to the bit line BL3, a reference voltage is applied to the bit line BL4, and a predetermined positive voltage is applied to the word line WL2. At this time, electrons supplied to the channel from the source / drain regions S / D constituting the bit line BL4 are accelerated in the channel, obtaining high energy on the bit line BL3 side,First potential barrier filmIt is injected and stored in the storage unit 1 beyond the potential barrier of the BTM.
  When injecting charges into the storage unit 2, the voltage between the bit lines BL3 and BL4 is switched. As a result, the electron supply side and the side on which the electrons become energetically hot are opposite to those described above, and the electrons are injected into the storage unit 2.
[0027]
  When reading data, Read targetBit dataA predetermined read drain voltage is applied between the bit lines BL3 and BL4 so that the memory portion side in which is written becomes the source. In addition, although the channel portion sandwiched between the memory portions at both ends can be turned on, the optimized positive voltage is set to the word line WL2 which is low enough not to change the threshold voltage of the memory portions at both ends of the memory transistor. Apply to. At this time, the channel conductivity effectively changes depending on the amount of accumulated charge in the storage unit to be read or the presence or absence of charge, and as a result, the stored information is converted into the current amount or potential difference on the drain side and read.
  The otherBit dataIf you want to readBit data isReading is performed in the same manner as described above by switching the bit line voltage so that the written storage side becomes the source.
[0028]
  When erasing dataIn addition, the channel formation region and the source / drain region S / D side are high and the word line WL2 side is low.Of the above dataAn erase voltage is applied in the opposite direction to that at the time of writing. As a result, accumulated charges are extracted from one or both of the storage portions to the substrate SUB side, and the memory transistor returns to the erased state. As another erasing method, it is generated near the PN junction (not shown) on the source / drain region S / D side or inside the substrate, and has a polarity opposite to the accumulated charge, and is generated due to tunneling between bands. It is also possible to adopt a method in which the high energy charges thus injected are attracted by the electric field of the control gate and injected into the memory portion.
[0029]
  A procedure for forming a VG memory cell array will be described with reference to the drawings.To do.
Figure2 to 5 are cross-sectional views (and plan views) at each step of word line formation. 2A is a plan view, and FIG. 2B is a cross-sectional view taken along line AA in FIG. The other FIGS. 3 to 5 all show sectional views along the line AA.
[0030]
  A well is formed in the semiconductor substrate SUB as necessary, and ion implantation for adjusting a threshold voltage is performed. Then, a mask layer such as a resist is formed on the semiconductor substrate, ion-implanted, and activated to form source / drain regions S / D (bit lines BL1, BL2, BL3, BL4,...).
[0031]
  On the semiconductor substrate SUB,Charge storage filmA first charge storage film to be GD1 is formed. For example, the surface of the semiconductor substrate SUB is thermally oxidizedFirst potential barrier filmForm a BTM and if necessaryFirst potential barrier filmBTM is nitrided,First potential barrier filmA charge trap film CHS made of silicon nitride or silicon oxynitride is formed on the BTM, and the surface of the charge trap film CHS is thermally oxidized.Second potential barrier filmForm TOP.
  First charge storage film GD1A conductive film made of doped polycrystalline silicon or doped amorphous is deposited thereon, for example, by CVD.
  A resist pattern is formed on the conductive film, and anisotropic etching such as RIE is performed to pattern the conductive film. Subsequently, the first charge storage film exposed between the conductive film patterns is, for example, CF₄/ CHF₃Patterning is performed using a dry etching apparatus using / Ar. Thereafter, the resist pattern is removed. ThisCharge storage filmA stacked pattern composed of GD1 and the first word line WL2 or WL4 is formed in a parallel stripe pattern orthogonal to the source / drain regions S / D, as shown in FIG.
[0032]
  As shown in FIG. 3, the surface layer of the semiconductor substrate SUB is etched. This etching may be ordinary dry etching, but a method using sacrificial oxidation is desirable. That is, the substrate surface is thermally oxidized to form a thin sacrificial oxide film, which is removed by wet etching or the like. As a result, the silicon surface layer consumed during the sacrificial oxidation is etched uniformly and without leaving any damage. This sacrificial oxidation condition is that the first charge storage film (Charge storage filmAccording to the formation conditions of GD1), it is determined in advance so that the nitrogen atoms introduced into the substrate surface layer are sufficiently removed.
[0033]
  As shown in FIG. 4, a second charge storage film is formed under the same conditions as the first charge storage film described above. As a result, the second charge storage film (Charge storage filmGD2) is formed.
[0034]
  As shown in FIG. 5, a conductive film WLF that completely fills the space between the first word lines WL2, WL4,..., For example, a doped polycrystalline silicon film or a doped amorphous silicon film is deposited.
  A resist pattern R opening above the first word lines WL2, WL4,... Is formed on the conductive film WLF.
[0035]
  Thereafter, anisotropic etching such as RIE is performed using the resist pattern R as a mask. Thereby, the conductive film WLF is separated, and second word lines WL1, WL3, WL5,... Shown in FIG.
[0036]
  [Second Embodiment]
  Second embodimentState is NAThe present invention relates to a nonvolatile memory device having an ND type memory cell array.
  FIG. 6 is a plan view of a NAND type memory cell array in which the distance between word lines is reduced by applying the present invention. 7A is a cross-sectional view taken along the line AA in FIG. 6, and FIG. 7B is a cross-sectional view in which a part of FIG. 7A is enlarged.
[0037]
  As shown in FIGS. 7A and 7B, word lines WL1, WL2,... WLn having substantially the same cross-sectional structure as in the first embodiment are formed on a P-type semiconductor substrate SUB. That is, odd-numbered word lines WL1, WL3,..., WLn (first word lines) areCharge storage filmIt is formed on the semiconductor substrate SUB with the GD1 interposed. Covering the surface of the first word lines WL1, WL3,..., WLn and the surface of the substrate region exposed between the first word lines,Charge storage filmGD2 is formed. And thisCharge storage filmEven numbered word lines WL2, WL4,... (Second word lines) are formed between the first word lines with GD2 interposed. More specifically, the bottom surface of the second word line isCharge storage filmIt faces the semiconductor region between the first word lines with GD2 interposed. The main side of the second word line isCharge storage filmIt faces the side surface between the first word lines with GD2 interposed. In addition, both end portions in the width direction of the second word line are respectively connected to end portions in the width direction of two adjacent first word lines.Charge storage filmIt rides with GD2 interposed.
  As described above, the word line in the present embodiment is interposed between two adjacent word lines so that the dimension in the separation direction is the film thickness.Charge storage filmIt is insulated and separated by GD2. The word line is made of doped polycrystalline silicon or doped amorphous silicon.
[0038]
  Charge storage filmGD1 and GD2, for example, in the MONOS type memory transistor, as in the first embodiment,First potential barrier filmBTM, middle charge trap film CHS, and top layerSecond potential barrier filmIt consists of TOP.
[0039]
  Outside the word line WL1, for exampleCharge storage filmControl gate lines SG1 separated by GD2 are arranged in parallel. Similarly, outside the word line WLn, for exampleCharge storage filmControl gate lines SG2 separated by GD2 are arranged in parallel. These control gate lines SG1 and SG2 also serve as the gate electrode of the select transistor, and the gate insulating film GD3 is used.SandwichSemiconductor substrate SUBFacing. Gate insulating film GD3 is formed of, for example, a single-layer silicon dioxide film. In this case, although the manufacturing process is slightly complicated, a single-layer gate insulating film is formed only in this portion, and the select transistor becomes a normal MOS type. OrCharge storage filmWith GD2Gate insulation filmThe GD3 may be the same film, and the charge may not be injected into the gate insulating film GD3 due to the applied bias condition.
[0040]
  A drain region DR composed of an N-type impurity region is formed outside the control gate line SG1. This drain region DR is shared with other NAND strings (not shown).
  A common source line CSL made of an N-type impurity region is formed outside the control gate line SG2. The common source line CSL isRow directionA row of NAND strings, andColumn directionIs shared by another NAND string of one row (not shown) adjacent to.
[0041]
  An interlayer insulating film INT is formed on the transistors constituting these NAND strings. Bit lines BL1 and BL2 are arranged in parallel stripes on the interlayer insulating film INT. Each bit line is connected to the corresponding drain region DR by a bit contact BC formed in the interlayer insulating film INT.
[0042]
  When writing dataWhen charge is injected into the memory portion 1 shown in FIG. 7B, a positive drain voltage is applied to the bit line BL2, a reference voltage is applied to the common source line CSL, and a voltage for turning on the two select transistors is controlled by the control gate. Apply to lines SG1, SG2. A pass voltage capable of transmitting the drain voltage or the reference voltage to the write target cell is applied to other word lines WL1, WL2, WL4,... WLn other than the word line WL3 to which the write target cell is connected. As a result, a predetermined write drain voltage is applied between the source and drain of the memory transistor constituting the cell to be written. In this state, a predetermined program voltage is applied to the word line WL3. At this time, in FIG.Source sideElectrons supplied to the channel from theDrain side endTo get high energy,First potential barrier filmIt is injected and stored in the storage unit 1 beyond the potential barrier of the BTM.
  When injecting charges into the storage unit 2, the voltage between the bit line BL2 and the common source line CSL is switched. As a result, the electron supply side and the side on which the electrons become energetically hot are opposite to those described above, and the electrons are injected into the storage unit 2.
[0043]
  Other more desirabledataAs a writing method, a source side injection method can be adopted. In this case, at the time of writing to the storage unit 1, the reference voltage is supplied from the bit line BL2, and the drain voltage is supplied from the common source line. Further, the voltage applied to the word line WL2 closer to the source of the word line WL3 to which the cell to be written is connected is not a mere pass voltage but a voltage optimized to enable source side injection. As a result, the lateral electric field is strengthened near the boundary between the word line WL2 and the word line WL3, and electrons can be more efficiently injected into the source end (memory portion 1) of the memory transistor.
  When injecting charges into the storage unit 2, the voltage between the bit line BL2 and the common source line CSL is switched, and the voltage value of the word line 4 is optimized to a value that allows source side injection. As a result, the electron supply side and the side on which the electrons become energetically hot are opposite to those described above, and the electrons are injected into the storage unit 2.
[0044]
  When reading dataIn addition, a predetermined read drain voltage is applied between the bit line BL2 and the common source line CSL so that the storage unit side in which the read target bit is written serves as a source, and a word other than the word line to which the read target cell is connected. Apply a pass voltage to the line. In addition, although the channel portion sandwiched between the memory portions at both ends can be turned on, the optimized positive voltage is set to the word line WL3 which is low enough not to change the threshold voltage of the memory portions at both ends of the memory transistor. Apply to. At this time, the channel conductivity effectively changes depending on the amount of accumulated charge in the storage unit to be read or the presence or absence of charge, and as a result, the stored information is converted into the current amount or potential difference on the drain side and read.
  The otherBit dataWhen readingBit dataIs read out in the same manner as described above by switching the voltage between the bit line BL2 and the common source line CSL so that the storage unit side in which is written becomes the source.
[0045]
  When erasing dataThen, erasing is performed by pulling out charges on the substrate side using FN tunneling on the entire surface of the channel or pulling out charges on the word line side.
[0046]
  A procedure for forming a NAND type memory cell array will be described with reference to the drawings.
  8 to 11 are cross-sectional views (and plan views) at each step of word line formation. 8A is a plan view, and FIG. 8B is a cross-sectional view taken along line AA in FIG. The other FIGS. 9 to 11 all show cross-sectional views along the line AA.
[0047]
  A well is formed in the semiconductor substrate SUB as necessary, and ion implantation for adjusting a threshold voltage is performed.
[0048]
  On the semiconductor substrate SUB,First charge storage film GD1Form. For example, the surface of the semiconductor substrate SUB is thermally oxidizedFirst potential barrier filmForm a BTM and if necessaryFirst potential barrier filmBTM is nitrided,First potential barrier filmA charge trap film CHS made of silicon nitride or silicon oxynitride is formed on the BTM, and the surface of the charge trap film CHS is thermally oxidized.Second potential barrier filmForm TOP.
  A conductive film made of doped polycrystalline silicon or doped amorphous is deposited on the first charge storage film, for example, by CVD.
  A resist pattern is formed on the conductive film, and anisotropic etching such as RIE is performed to pattern the conductive film. The first charge storage film exposed between the conductive film patterns is, for example, CF₄/ CHF₃Patterning is performed using a dry etching apparatus using / Ar. Thereafter, the resist pattern is removed. ThisCharge storage filmA stacked pattern composed of GD1 and first word lines WL1, WL3,... WLn is formed in a parallel stripe pattern as shown in FIG.
[0049]
  As shown in FIG. 9, the surface layer of the semiconductor substrate SUB is etched. This etching may be ordinary dry etching, but a method using sacrificial oxidation is desirable. That is, the substrate surface is thermally oxidized to form a thin sacrificial oxide film, which is removed by wet etching or the like. As a result, the silicon surface layer consumed during the sacrificial oxidation is etched uniformly and without leaving any damage. This sacrificial oxidation condition is the first charge accumulationMembrane GD1The nitrogen atoms introduced into the substrate surface layer are determined in advance according to the formation conditions.
[0050]
  As shown in FIG. 10, a second charge storage film is formed under the same conditions as the first charge storage film. As a result, the second charge accumulationMembrane GD2Is formed. As needed, the outer region of the word line WL1 and the outer region of the word line WLn.Charge storage filmGD2 is selectively removed and a single layer isInsulation filmGD3 is selectively formed.
[0051]
  As shown in FIG. 11, a conductive film WLF that completely fills between the first word lines WL1, WL3,..., WLn, for example, a doped polycrystalline silicon film or a doped amorphous silicon film is deposited.
  A resist pattern R opening above the first word lines WL1, WL3,..., WLn is formed on the conductive film WLF.
[0052]
  Using the resist pattern R as a mask, anisotropic etching such as RIE is performed. Thereby, the conductive film WLF is separated, and the second word lines WL2, WL4,... And the control gate lines SG1, SG2 shown in FIG.
[0053]
  N-type impurities are ion-implanted into the semiconductor substrate region outside the select gate lines SG1, SG2. At this time, the source / drain regions are not formed because ions do not pass through the word line arrangement region.
  Thereafter, through the deposition of the interlayer insulating film INT, the formation of the bit contact BC, and the formation of the bit line, the NAND type nonvolatile memory device is completed.
[0054]
  In the first and second embodiments described above, the second word line to be formed later may be formed so as to be embedded between the first word lines so as not to overlap. In that case, it is desirable to form a stopper film for preventing polishing such as CMP on the first word line. Further, in this structure that does not overlap, by optimizing the ion implantation conditions in the NAND type, the gap between the word lines (Charge storage filmGD2) may transmit ions to form narrow source / drain impurity regions S / D in the word line direction.
[0055]
  In the semiconductor memory devices according to the first and second embodiments described above, the distance between word lines isLaminated film (charge storage filmSince it is determined by the film thickness of GD2), the distance between the word lines is significantly smaller than the word line width. Therefore, 2F²(F: Lithographic resolution limit or design rule) and2-bit dataAs a cell for storing the memory cell, a memory cell having an extremely small area can be realized.
[0056]
  Further, in the method of manufacturing the semiconductor memory device according to the above-described embodiment, a high-density word line arrangement can be realized by simply repeating the patterning by laminating the charge storage film and the word line material twice.
  In addition, since the substrate is etched thinly before the second charge storage film formation, the accuracy of the second charge storage film formation is improved.
[0057]
  Here, the present inventor has an RTN process at the first charge storage film formation.WaferA and no RTN processingWaferB is prepared and the second charge storage filmFirst potential barrier filmThermal oxidation was performed assuming the formation of.
  The table in FIG. 12 shows the measured values of this oxide film. Here, in order to accurately measure the film thickness, it is thermally oxidized for a long time with the aim of 18 nm,WaferThe film thickness of the thermal oxide film was measured at five measurement points.
  As a result, RTN processing is performed.WaferIn the thermal oxidation of A, the oxidation rate is low, andWaferIt can be seen that the variation of the oxide film thickness is larger than that of B. This is because nitrogen is introduced into the substrate during the RTN process, which inhibits oxidation.
  In the above-described embodiment of the present invention, the surface layer of the substrate containing nitrogen is removed by sacrificing the substrate surface and etching the oxide film before the second charge storage film is formed. As a result, the second charge storage film can be formed with high accuracy and the characteristic fluctuation can be suppressed.
[0058]
  [Third Embodiment]
  The third embodiment relates to a partial change in the steps of the first and second embodiments.
[0059]
  In the process of FIG. 2B of the first embodiment described above or the process of FIG. 8B of the second embodiment, the conductive film pattern and the first charge storage film are continuously dry etched, FirstCharge storage filmA pattern composed of GD1 and the first word line WL2 or WL4 is formed. However, dry etching is not preferable because it slightly damages the substrate.
  Here, only the conductive film pattern is dry etched to obtain the firstCharge storage filmA method of removing the first charge storage film to be GD1 by wet etching is conceivable.
  When the first charge storage film is an ONO film, silicon nitride is present, so that it cannot be removed with a silicon oxide etchant mainly composed of hydrofluoric acid, and treatment using hot phosphoric acid is required. However, the hot phosphoric acid treatment causes a new problem that the surface of polycrystalline silicon having a high concentration is etched.
[0060]
  The third embodiment provides a manufacturing method suitable for removing such a first charge storage film by wet processing.
  The method shown in this embodiment can be applied not only to the VG type and the NAND type, but will be described with reference to FIGS.
[0061]
  FIG. 13 shows the first ONO structure.Charge storage filmFIG. 9 is a cross-sectional view at the time when the first word lines WLi, WLi + 2,... Are formed by patterning the conductive material on the GD1, and corresponds to FIGS.
  At the end of dry etching of this conductive material, depending on the amount of overetchingSecond potential barrier filmA part of TOP may be removed, and in some cases, as shown in the figureSecond potential barrier filmTOP is removed around the first word line.
[0062]
  In this embodiment, at this time, the surface of the first word lines WLi, WLi + 2,... Is thermally oxidized to form, for example, a thermal oxide film TOX of about 10 nm on the surface of the first word line as shown in FIG.
[0063]
  The first word line exposed between the first word lines in a state where the surface of the first word line is protected by the thermal oxide film TOX.Charge storage filmGD1 is removed by wet etching. That is, the silicon nitride film (charge trap film CHS) is removed with an etchant using hot phosphoric acid, and the silicon dioxide film (with the etchant mainly containing hydrofluoric acid is used).First potential barrier filmBTM) is removed.
  During this etching, of course, the thermal oxide film TOX is also thinned. In the present embodiment, the thickness of the thermal oxide film TOX may be set in advance so that the thermal oxide film is etched off at the end of the etching. Alternatively, as shown in FIG. 15, the film thickness may be increased to some extent so that the thermal oxide film TOX remains.
  In any case, there is an advantage that the amount of the first word line can be reduced compared to the case where the thermal oxide film is not formed.
[0064]
  Thereafter, as in the first and second embodiments, the secondCharge storage filmGD2 is formed, and a conductive material is embedded between the first word lines and patterned to form second word lines WLi-1, WLi + 1,.
  If the thermal oxide film TOX is left to the end, the insulation characteristics between the word lines are remarkably improved in this thermal oxide film, and the parasitic capacitance between the word lines is also reduced.
[0065]
  [Fourth Embodiment]
  The fourth embodiment is a modification of the first to third embodiments. More specifically, the fourth embodiment relates to a pattern of the electrode lead-out portion and a part of a process for preventing occurrence of a short-circuit between electrodes.
[0066]
  In the process of FIG. 5 of the first embodiment described above or the process of FIG. 11 of the second embodiment, patterning of the second word line is performed. In this etching, the base is second.Charge storage filmSince it is GD2, too much overetching time cannot be set. Because of excessive over-etching,Charge storage filmThis is because if GD2 becomes thin, the insulation between word lines may be lowered.
[0067]
  After the etching of the second word line, for example, as shown in FIG. 16A, a conductive substance that is the material of the second word line may remain in the vicinity of the skirt of the first word line. In particular, when a conductive layer (for example, polycrystalline silicon) serving as the second word line is deposited, if it is thinner in the region above the first word line than the other regions, it is formed at the bottom of the first word line. Residue of conductive material tends to remain.
  This residue is generated along the end face of the first word line as shown in FIG. 16B, causing a short circuit between the second word lines.
[0068]
  In the present embodiment, in order to prevent this short circuit between word lines, a step of cutting the residue in the middle is added.
  Further, when the word lines are formed at a pitch close to the minimum line width of photolithography as in the first to third embodiments, it is difficult to extract electrodes for connecting the word lines to the upper wiring. In the present embodiment, details of the pattern that facilitates the electrode extraction will be described.
[0069]
  FIG. 17 shows an end pattern including an electrode lead-out portion of the word line in the present embodiment.
  The word line arrangement in the memory cell array is the same as in the first or second embodiment.
  A word line extending in one direction from the memory cell array is bent in a direction different from the wiring direction. Here, each is bent 90 degrees from the row direction to the column direction. The portions where the word lines are bent are sequentially shifted, and the pitch of the word line portions extending in the column direction is relaxed from the pitch in the memory cell array. For this reason, there is a margin for forming wide electrode extraction portions PAD1 and PAD2 for connecting each word line to an upper wiring (not shown). The first word lines WL1a, WL1b, WL1c formed from the first-layer polycrystalline silicon have an electrode lead-out portion PAD1, are formed from the second-layer polycrystalline silicon, and are connected to the first word lines on both sides. The overlapping second word lines WL2a, WL2b, WL2c have an electrode extraction portion PAD2. Of these, the electrode lead-out portion PAD1 is arranged at a position further outside the electrode lead-out portion PAD2.
  Also at the other end of each word line, the first word lines WL1a, WL1b, WL1c extend outward from the second word lines WL2a, WL2b, WL2c.
[0070]
  The reason for extending the first word line to the outside is that the conductive residue remaining at the edge of the first word line when the second word line is formed is removed at the end of the first word line, This is to prevent electrical shorting.
[0071]
  Specifically, in the steps of FIGS. 2A and 2B of the first embodiment, the steps of FIGS. 8A and 8B of the second embodiment, or FIGS. 13 to 15 of the third embodiment. When forming the first word line, as shown in FIG. 17, one end is relatively long, the electrode lead-out portion PAD1 is formed at the tip, and the other end is formed relatively long. A photomask having a first word line pattern is used.
[0072]
  After the steps of FIG. 3, FIG. 4 or FIG. 9, FIG.Charge storage filmGD2 is formed, and in the step of FIG. 5 or FIG. 11, polycrystalline silicon to be the second word line is deposited, and a resist pattern R is formed thereon. At this time, as shown in FIG. 17, one end is relatively short (that is, shorter than the first word line), the electrode lead-out portion PAD2 is formed at the tip, and the other end is from the first word line. A photomask having a short second word line pattern is used.
[0073]
  Next, in this embodiment, a step of removing the conductive residue is added. For example, a resist pattern is formed which opens at broken line portions A1 and A2 shown in FIG. 17 to expose the end portion of the first word line and covers and protects the entire second word line. Partial over-etching is performed using this resist pattern as a mask. The conditions such as the etching gas at this time are the same as those at the time of forming the second word line, and the etching time is a time for sufficiently removing the conductive residue at the opening. As a result, the conductive residue is cut at this portion, and the second word lines are completely electrically separated.
[0074]
  Thereafter, the nonvolatile memory is completed through steps similar to those in the first or second embodiment.
[0075]
  [Fifth Embodiment]
  This embodiment is for solving other problems due to the residue of the second word line forming material.
  Under the residue shown in FIG. 16 (A), the second protected by the residue and maintaining the charge storage capability in a high state.Charge storage film(Charge storage film) GD2 is left intact. In contrast, the second around itCharge storage filmSince GD2 has been removed or exposed to etching, if left, its charge storage capability is significantly reduced.
[0076]
  Charges may be stored in the charge storage film under the residue during gate processing or during operation. When the cell is N-channel type, the accumulation of electrons isThreshold voltageHowever, if holes are accumulated, the channel immediately below the residue becomes depletion, and leakage between the source and drain of the cell increases. And even if it ’s not a depression,Threshold voltageIs low, the capacitive coupling with the adjacent word line to which a high positive voltage is applied increases the potential of the electrically floating residue, and the channel of the parasitic transistor is turned on to increase leakage.
  This increase in leakage causes a disadvantage that the S / N ratio of the read signal is lowered for all the cells, especially at the time of reading, and thus erroneous reading is caused.
[0077]
  This embodiment is for preventing this increase in leak. In this embodiment, there are the following three methods for preventing leakage.
  In the first method, the residue is selectively removed at this portion.
  In the second method, the number of word lines is set to an odd number so that the residue in this portion is reduced.Occurrence itselfTo prevent.
  In the third method, considering that the number of word lines is usually an even number, in addition to the second method, the outer word line is used as a dedicated line for applying a leak prevention voltage.
[0078]
  Hereinafter, these three methods will be sequentially described with reference to the drawings. In addition, although the technique of 4th Embodiment mentioned above is applied to the drawing used here duplication, this duplication application is not necessarily essential. In addition, configurations that have already been described and assigned the same reference numerals will not be described here again.
[0079]
  FIG. 18 is a plan view showing a residue removal place in the first method. Moreover, FIG. 19 is sectional drawing along the AA line of FIG. 18 after the residue removal using a 1st method.
  In the resist pattern R for removing the residue of the second word line used in the fourth embodiment described above,ApertureIn addition to A 1 and A 2, as shown in FIG. 18, an opening A 3 that opens in the vicinity of one of the outermost first word lines, here at least the outer long side of WL 1 a, is added in advance on the pattern. Therefore, during etching using the resist pattern R as a mask, in addition to the openings A1 and A2, as shown in FIG. 19, the residue of the conductive material that is the formation material of the second word line exposed through the opening A3 is effectively used. To be removed.
  As a result, according to the first method, the above-described leakage current caused by the residue in the opening A3 can be prevented or reduced.
[0080]
  FIG. 20 is a plan view when the above-described second method is applied.
  In the second method, an odd number of word lines are provided. That is, if the number of first word lines is n, (n + 1) second word lines are provided. As a result, the second word line is arranged on the outermost side of the memory cell array, and as a result, the problem of leakage due to the residue of the second word line is solved.
  Note that the number of normal word lines is an even number, and one extra word line is required as compared with this. In this case, for example, an address signal may not be assigned so that an extra word line is not used.
[0081]
  FIG. 21 is a plan view and a block diagram when the third method is applied.
  In the third method, the number of word lines is odd as in the second method. Among these, n word lines WL1a to WL2c are connected to a normal word line driving circuit 51 driven by a row decoder 50 that decodes an input row address signal RAD. On the other hand, a predetermined voltage that is not driven by the row decoder 50 and is always applied to the extra one second word line WL2 regardless of the write data, or always turns off the channel at the time of reading. An applied word line driving circuit 52 is connected. The word line driving circuit 52 corresponds to the “first word line driving circuit” in the present invention, and the normal word line driving circuit 51 driven by the row decoder 50 is the “second word line driving circuit” in the present invention. It corresponds to.
  In the third method, the voltage applied to the word line driving circuit 52 is optimized, so that the channel immediately below the word line WL2 is always turned off to prevent leakage current at the time of reading. Alternatively, the write operation is always performed regardless of the write data, so thatCharge storage filmA sufficient amount of electrons is always accumulated in GD2, and the cells having the word line WL2 as a gate are all of the enhancement type, thereby preventing the occurrence of leakage current.
[0082]
  [Sixth Embodiment]
  This embodimentState is semiconductorRelates to the device.
  FIG. 22A is a plan view of the semiconductor device according to the sixth embodiment after wiring formation, and FIG. 22B is a cross-sectional view taken along the line AA of FIG.
  In this semiconductor device, the wiring separation structure of the present invention is applied to a plurality of wirings arranged in parallel in one layer in the multilayer wiring structure.
[0083]
  On the dielectric 1 supported by the substrate SUB, first-shaped wirings IL1 having a substantially vertical side surface or a forward tapered cross-sectional shape are formed at equal intervals. Further, between the first shape wiring IL1, a second shape wiring IL2 having a cross-sectional shape in which at least the upper part is reversely tapered is formed. Between the first shape wiring IL1 and the first shape wiring IL2Side wall insulating layer having a substantially elliptical cross sectionSW (hereinafter, simply referred to as a side wall) is interposed, thereby insulating and separating the two wirings. here"Cross section is approximately 1/4 oval"Is a substantially planar first side surface as shown in FIG. 22 (B), and a second side surface including at least part of a curved surface that is curved in an arc shape so as to be closer to the first side surface at the top. The shape which has.
  The sidewall SW is formed on the side surface of the first shape wiring IL1. Therefore, the surface of the sidewall SW opposite to the first shape wiring IL1 is a curved surface. The second shape wiring IL2 is formed so as to be embedded in a concave portion formed by the curved surface. As a result, the second-shaped wiring IL2 has a reverse tapered cross-sectional shape.
[0084]
  The first and second shape wirings IL1 and IL2 only need to be parallel to each other. For example, the wirings IL1 and IL2 may meander as a whole. Further, it may be a wiring (for example, Schottky metal) in direct contact with the substrate SUB.
[0085]
  Next, the wiring formation procedure will be described with reference to the drawings.To do.
Figure23 to 27 are cross-sectional views (and plan views) at each step of wiring formation. 23, 25, and 26, (A) is a plan view, and (B) is a cross-sectional view taken along line AA of (A). All other drawings represent cross-sectional views along the line AA.
[0086]
  As shown in FIGS. 23A and 23B, a plurality of sacrificial layers 2 made of a dielectric are formed on the dielectric 1 above the substrate SUB. The plurality of sacrificial layers 2 are formed in stripes parallel to each other at a pitch approximately twice that of the wiring to be formed.
  As shown in FIG. 24, different materials are used to cover the sacrificial layer 2.Insulation film3 is deposited.Insulation filmAs the material 3, a material having a higher etching selectivity than the sacrificial layer 2 is selected. For example, the sacrificial layer 2 is a silicon nitride film,Insulation film3 is a silicon dioxide film. Also,Insulation filmSince a part of 3 finally remains as a sidewall, the material and the formation method are selected in consideration of the quality of the film and the insulating characteristics.
[0087]
  continue,Insulation film3 is etched back by anisotropic etching. Thereby, as shown in FIGS. 25A and 25B, the sidewall SW is formed on the side surface of the sacrificial layer 2. The width of the sidewall SW is mainly determined by the height of the sacrificial layer 2 and the anisotropic etching conditions. However, when the anisotropy is strong to some extent, the sidewall width does not change much even if the etching time varies somewhat, so the uniformity is relatively high.
[0088]
  Thereafter, the sacrificial layer 2 is selectively removed by a predetermined method. For example, in the case where the sacrificial layer 2 is silicon nitride, a wet process using an etchant containing hydrofluoric acid FH is performed. Thereby, as shown in FIGS. 26A and 26B, the sidewall SW is left.
  As shown in FIG. 27, a conductive film 4 that completely fills the sidewall SW, for example, a metal, doped polycrystalline silicon or doped amorphous silicon film is deposited.
  Thereafter, the surface of the conductive film 4 is ground and / or polished by, for example, a CMP method or other methods. This grinding and / or polishing is performed until the conductive film 4 is separated into a plurality of parts when the sidewall SW is exposed, and then the separation distance becomes a required value. As a result, a plurality of wiring layers IL1 and IL2 separated by the sidewall SW at a necessary distance are formed.
[0089]
  In the sixth embodiment, the distance between the wiring layers isSide wall insulation layerSince it is determined by the width of SW, the wiring layer can be made sufficiently smaller than the limit of photolithography. At this time, the controllability of the wiring interlayer distance is also high.
[0090]
  [Seventh Embodiment]
  Seventh embodimentThe semiconductorRelates to the device.
  FIG. 33 is a cross-sectional view showing a wiring structure according to the seventh embodiment.
  A plan view of this wiring structure is the same as FIG. 22A, and the wiring structure is composed of a plurality of wirings IL1 and IL2 arranged in parallel stripes. In the cross-sectional view, the first shape wiring IL1 and the second shape wiring IL2 are alternately arranged in common with FIG.
[0091]
  The wiring isolation structure in the seventh embodiment is different from the first embodiment in that a thin thermal oxide film 10 is interposed between the sidewall SW and the first-shaped wiring IL1 in addition to the sidewall SW. .
  The thermal oxide film 10 is obtained by thermally oxidizing the surface of the first shape wiring IL1 made of doped polycrystalline silicon or doped amorphous silicon. Therefore, the controllability of the film thickness is extremely high, and the film quality is good because it is silicon dioxide obtained by thermal oxidation. For this reason, there exists an advantage that the insulation characteristic between wiring improves.
[0092]
  28 to 32 are cross-sectional views in forming this wiring structure.
  As shown in FIG. 28, the first-shaped wiring IL1 is formed on the dielectric 1 supported by the substrate SUB at a pitch that is approximately twice that of the final wiring. Since the first shape wiring IL1 is finally left, it is formed from doped polycrystalline silicon or doped amorphous silicon.
[0093]
  As shown in FIG. 29, the surface of the first-shaped wiring IL1 is thermally oxidized to form a thermal oxide film 10 made of silicon dioxide of about several nm to several tens of nm. Note that nitriding treatment or oxynitriding treatment by heating may be performed instead of thermal oxidation.
[0094]
  After that, as in the seventh embodiment,Insulation film3 is deposited (FIG. 30) and etched back to form a sidewall SW (FIG. 31). Further, the conductive film 4 is deposited (FIG. 32), and this is ground and / or polished to form a plurality of wirings IL1 and IL2.
[0095]
  In the seventh embodiment, it is possible to effectively improve the insulation characteristics of the inter-wiring dielectric simply by performing a treatment such as thermal oxidation. Note that the step of removing the sacrificial layer as in the first embodiment is unnecessary, and therefore the number of steps is not increased.
[0096]
  [Eighth Embodiment]
  The eighth embodiment shows a first example when the wiring formation method of the sixth embodiment is applied to formation of a word line of a nonvolatile memory. Here, application to a NOR type memory cell array will be described.
  FIG. 34A is a plan view of a NOR type memory cell array in which the distance between word lines is reduced by applying the present invention. 34B is a cross-sectional view taken along the line AA in FIG. 34A, and FIG. 34C is a cross-sectional view taken along the line BB in FIG.
[0097]
  As shown in FIG. 34C, source / drain regions S / D made of N-type impurity regions are formed on the surface side in the P-type semiconductor substrate SUB so as to be separated from each other. As shown in FIG. 34 (A), the source / drain regions S / D constitute source lines SL1, SL2,... And bit lines BL1, BL2,. It has the pattern arranged in.
  Sidewalls SW are formed on the semiconductor substrate SUB so as to be long in parallel to the source / drain regions S / D and in parallel with each other.
[0098]
  Covering the surface of the sidewall SW and the surface of the semiconductor substrate SUB,Charge storage filmGD is formed.Charge storage filmGD is a film containing charge storage means inside. In the present embodiment, a MONOS type memory transistor is illustrated, so thisCharge storage filmThe GD is a so-called ONO type three-layer film.
  Specifically,Charge storage filmGD is the lowest layerFirst potential barrier filmBTM, middle charge trap film CHS, and top layerSecond potential barrier filmIt consists of TOP.First potential barrier filmThe BTM includes, for example, a thermal silicon oxide film formed by thermally oxidizing the substrate surface and an oxynitride film formed by nitriding the thermal silicon oxide film. The charge trap film CHS is made of, for example, silicon nitride or silicon oxynitride, and includes a large number of charge traps as discrete charge storage means.Second Potential barrier membraneTOP is made of, for example, a silicon oxide film.
  In the case of the so-called MNOS type,Second potential barrier filmTOP is omitted, and the charge trap film CHS is formed relatively thick. In the FG type using a conductive layer as a charge storage film, from the lower layer,First potential barrier filmAnd a floating gate, and a gate between ONO filmsInsulation filmAre often laminated.
[0099]
  thisCharge storage filmGD has a total thickness of about a dozen nm in terms of silicon dioxide.Charge storage filmA conductive material is buried in the recesses on the surface of the GD, thereby forming word lines WL1, WL2,. In the illustrated example, even-numbered word lines WL2, WL4,... Have a first shape, and odd-numbered word lines WL1, WL3,.
[0100]
  Next, the formation procedure of this NOR type memory cell array will be described with reference to the drawings.
  35 to 39 are cross-sectional views (and plan views) at each step of word line formation. 35, 37, and 38, (A) is a plan view, and (B) is a cross-sectional view taken along line AA of (A). All other drawings represent cross-sectional views along the line AA.
[0101]
  First, if necessary, a layer for dielectric isolation between elements is provided on the semiconductor substrate SUB, and ion implantation for adjusting a threshold voltage is performed. Then, a mask layer such as a resist is formed on the semiconductor substrate, ion-implanted, and activated to form source / drain regions S / D (source lines SL1, SL2 and bit lines BL1, BL2).
[0102]
  As shown in FIG. 35A, in a parallel stripe pattern orthogonal to the source / drain regions S / D, a plurality of dielectricsSacrificial layer 20Are formed on the substrate SUB. The plurality of sacrificial layers 20 are formed in stripes parallel to each other at a pitch that is approximately twice the pitch of the word lines to be formed.
  As shown in FIG. 36, different materials are used to cover the sacrificial layer 20.Insulation film3 is deposited.Insulation filmAs the third material, a material having a high etching selectivity with respect to the sacrificial layer 20 is selected. For example, the sacrificial layer 20 is a silicon nitride film,Insulation film3 is a silicon dioxide film. Also,Insulation filmSince a part of 3 finally remains as a sidewall, the material and the formation method are selected in consideration of the quality of the film and the insulating characteristics.
[0103]
  continue,Insulation film3 is etched back by anisotropic etching. Thereby, as shown in FIGS. 37A and 37B, the sidewall SW is formed on the side surface of the sacrificial layer 20. The width of the sidewall SW is mainly determined by the height of the sacrificial layer 20 and the anisotropic etching conditions. However, when the anisotropy is strong to some extent, the sidewall width does not change much even if the etching time varies somewhat, so the uniformity is relatively high.
[0104]
  Thereafter, the sacrificial layer 20 is selectively removed by a predetermined method. For example, when the sacrificial layer 20 is silicon nitride, phosphoric acid (H₃PO₄) Is performed using an etchant including Thereby, the sidewall SW is left as shown in FIGS.
[0105]
  As shown in FIG. 39, a conductive film 4 that completely fills the sidewall SW, for example, a metal, doped polycrystalline silicon or doped amorphous silicon film is deposited.
  Thereafter, the surface of the conductive film 4 is ground and / or polished by, for example, a CMP method or other methods. This grinding and / or polishing is performed until the conductive film 4 is separated into a plurality of parts when the sidewall SW is exposed, and then the separation distance becomes a required value. As a result, a plurality of word lines WL1, WL2,..., WL5,.
  The grinding and / or polishing is preferably performed until the charge trap film CHS is completely divided for each word line. However, in the case of the FG type in which the charge storage film is a conductive material, it is essential to divide the charge storage film. This is because if the floating gate FG is connected at this location, the stored charge leaks to the adjacent cell, making data storage itself impossible. Moreover, in order to avoid electric field concentration in this portion, it is necessary to perform sufficient grinding and / or polishing.
[0106]
  [Ninth Embodiment]
  The ninth embodiment shows a second example in which the wiring formation method of the sixth embodiment is applied to formation of a word line of a nonvolatile memory. Here, application to a NAND type memory cell array will be described.
  FIG. 40 is a plan view of a NAND type memory cell array in which the distance between word lines is reduced by applying the present invention. 41A is a cross-sectional view taken along line AA in FIG. 40, and FIG. 41B is a cross-sectional view in which a part of FIG. 41A is enlarged.
[0107]
  As shown in FIGS. 41A and 41B, word lines WL1, WL2,... WLn having substantially the same cross-sectional structure as in the sixth embodiment are formed on a P-type semiconductor substrate SUB. That is, the sidewalls SW are formed in parallel stripes on the semiconductor substrate SUB, covering the surface of the sidewalls SW and the surface of the semiconductor substrate SUB,Charge storage filmGD is formed. For example, in the MONOS type memory transistor, as in the sixth embodiment,Charge storage filmGD is the lowest layerFirst potential barrier filmBTM, middle charge trap film CHS, and top layerSecond potential barrier filmIt consists of TOP.
  thisCharge storage filmGD has a total thickness of about a dozen nm in terms of silicon dioxide.Charge storage filmA conductive material is embedded in the recesses on the surface of the GD, thereby forming word lines WL1, WL2,. In the illustrated example, odd-numbered word lines WL1, WL3,... Have a first shape, and even-numbered word lines WL2, WL4,.
[0108]
  A control gate line SG1 separated by a sidewall SW is arranged outside the word line WL1 in parallel. Similarly, a control gate line SG2 separated by the sidewall SW is arranged in parallel outside the word line WLn. These control gate lines SG1 and SG2 are shown in FIG.Charge storage filmGDAcrossFor semiconductor substrate SUBFacingHowever, depending on the applied bias conditions,Charge storage filmNo charge is injected into the GD. Although the manufacturing process is slightly complicated, only this part is a single layer.Charge storage filmAnd the select transistor may be a normal MOS type.
[0109]
  For such a wiring structure, source / drain regions S / D made up of N-type impurity regions are formed only in the substrate portion centering on the region below the sidewall SW. The source / drain regions S / D are discretely formed only between word lines or between a word line and a control gate line, and the lateral direction in FIG. 40 is separated by an element isolation layer (for example, LOCOS) not shown. ing.
  A drain region DR composed of an N-type impurity region is formed outside the control gate line SG1. This drain region DR is shared with other NAND strings (not shown).
  A common source line CSL made of an N-type impurity region is formed outside the control gate line SG2. The common source line CSL isRow directionIn one row of NAND strings lined up, andColumn directionIs shared with another one row of NAND strings not shown.
[0110]
  An interlayer insulating film INT is formed on the transistors constituting these NAND strings. Bit lines BL1 and BL2 are arranged in parallel stripes on the interlayer insulating film INT. Each bit line is connected to the corresponding drain region DR by a bit contact BC formed in the interlayer insulating film INT.
[0111]
  Then thisNAND typeA procedure for forming a memory cell array will be described with reference to the drawings.
  42 to 49 are cross-sectional views (and plan views) at each step of word line formation. 42, 44, 45, 47 and 49, (A) is a plan view, and (B) is a cross-sectional view taken along line AA of (A). All other drawings represent cross-sectional views along the line AA.
[0112]
  First, if necessary, an element isolation layer is provided on the semiconductor substrate SUB, and ion implantation for adjusting a threshold voltage is performed.
[0113]
  As shown in FIG. 42A, a plurality of sacrificial layers 30 made of a dielectric are formed on the substrate SUB in a parallel stripe pattern. The plurality of sacrificial layers 30 are formed in stripes parallel to each other at a pitch approximately twice that of the word lines to be formed.
  As shown in FIG. 43, different materials are used to cover the sacrificial layer 30.Insulation film3 is deposited. thisInsulation filmAs the third material, a material having a high etching selectivity with respect to the sacrificial layer 30 is selected. For example, the sacrificial layer 30 is a silicon nitride film,Insulation film3 is a silicon dioxide film. Also,Insulation filmSince a part of 3 finally remains as a sidewall, the material and the formation method are selected in consideration of the quality of the film and the insulating characteristics.
[0114]
  continue,Insulation film3 is etched back by anisotropic etching. As a result, as shown in FIGS. 44A and 44B, the sidewall SW is formed on the side surface of the sacrificial layer 30. The width of the sidewall SW is mainly determined by the height of the sacrificial layer 30 and the anisotropic etching conditions. However, when the anisotropy is strong to some extent, the sidewall width does not change much even if the etching time varies somewhat, so the uniformity is relatively high.
[0115]
  Thereafter, the sacrificial layer 30 is selectively removed by a predetermined method. For example, in the case where the sacrificial layer 3 is silicon nitride, a wet process using an etchant containing phosphoric acid (H3PO4) is performed. As a result, the sidewall SW is left as shown in FIGS. 45 (A) and 45 (B).
[0116]
  As shown in FIG. 46, a conductive film 4 that completely fills the sidewall SW, for example, a metal, doped polycrystalline silicon or doped amorphous silicon film is deposited.
  Thereafter, the surface of the conductive film 4 is ground and / or polished by, for example, a CMP method or other methods. Grinding and / or polishing is performed until the conductive film 4 is separated into a plurality of parts when the sidewall SW is exposed, and then the separation distance becomes a required value. Thus, as shown in FIGS. 47A and 47B, the plurality of word lines WL1, WL2,..., WLn and control gate lines SG1, SG2 separated by the sidewall SW at a necessary distance. Is formed.
  The grinding and / or polishing is preferably performed until the charge trap film CHS is completely divided for each word line. However, in the case of the FG type in which the charge storage film is a conductive material, it is essential to divide the charge storage film. This is because if the floating gate FG is connected at this location, the stored charge leaks to the adjacent cell, making data storage itself impossible. Moreover, in order to avoid electric field concentration in this portion, it is necessary to perform sufficient grinding and / or polishing.
[0117]
  As shown in FIG. 48, a mask layer covering word lines WL1, WL2,..., WLn and a part of the control gate lines SG1, SG2 is formed so that the control gate lines SG1, SG2 have a predetermined line width. Etching is performed to selectively remove the peripheral portion of the mask layer.
  After removing the mask layer, N-type impurities are ion-implanted into the semiconductor substrate SUB. At this time, the ion implantation conditions are determined so that ions do not permeate through the wiring layer portion but ions penetrate through the sidewall portion and reach the substrate. Thereby, the source / drain region S / D, the drain region DR, and the common source line CSL are simultaneously formed. At this time, the element isolation layer formed in advance also functions as a mask at the time of ion implantation.
  If it is difficult to form the source / drain region S / D having a desired concentration and depth only by optimizing the ion implantation conditions, the sidewall SW is removed once, and after the ion implantation, this side Again in the wall-shaped spaceInsulating materialIt may be embedded.
[0118]
  After that, the nonvolatile memory is completed through the deposition of the interlayer insulating film INT, the formation of the bit contact BC, and the formation of the bit line.
[0119]
  [Tenth embodiment]
  The tenth embodiment shows a first modification of word line formation in a nonvolatile memory.
  50A to 50C and FIGS. 51A to 51D are cross-sectional views in the line width direction centering on the word line portion. This embodiment can be applied to any of the memory cell array systems of the eighth and ninth embodiments.
[0120]
  In the wiring isolation structure according to the tenth embodiment, as shown in FIG. 51D, in addition to the sidewall SW, the first-shaped word lines WL2, WL4,.Charge storage filmA difference from the eighth and ninth embodiments is that a thin thermal oxide film 10 is interposed between the GD and the sidewall SW.
  The thermal oxide film 10 is obtained by thermally oxidizing the surface of doped polycrystalline silicon or doped amorphous silicon. Therefore, the controllability of the film thickness is extremely high, and the film quality is good because it is silicon dioxide obtained by thermal oxidation. For this reason, there exists an advantage that the insulation characteristic between wiring improves.
[0121]
  In the formation of this wiring structure, first, as shown in FIG. 50A, the sacrificial layer 40 is formed on the substrate SUB at a pitch approximately twice that of the final wiring. The sacrificial layer 40 is formed from doped polycrystalline silicon or doped amorphous silicon.
  As shown in FIG. 50B, the surface of the sacrificial layer 40 is thermally oxidized to form a thermal oxide film 10 made of silicon dioxide having a thickness of several nanometers to several tens of nanometers. Note that nitriding treatment or oxynitriding treatment by heating may be performed instead of thermal oxidation.
[0122]
  After that, as in the eighth and ninth embodiments,Insulation film3 is deposited (FIG. 50C) and etched back to form a sidewall SW (FIG. 51A).
  Further, after the upper surface of the sacrificial layer 40 is exposed, the sacrificial layer 40 is selectively removed (FIG. 51B), a conductive film 4 is deposited (FIG. 51C), and this is ground and / or polished. Thus, a plurality of word lines WL1 to WL5 are formed (FIG. 51D).
[0123]
  In the tenth embodiment, it is possible to effectively improve the insulation characteristics of the inter-wordline dielectric simply by performing a treatment such as thermal oxidation. Since the sacrificial layer 40 is made of a conductive material unlike the side wall or the like, there is an advantage that selective etching is easy.
[0124]
  [Eleventh embodiment]
  The eleventh embodiment shows a second modification of word line formation in a nonvolatile memory.
  52 (A) to 52 (C) and FIGS. 53 (A) to 53 (C) are cross-sectional views in the line width direction centering on the word line portion. This embodiment can be applied to any of the memory cell array systems of the eighth and ninth embodiments.
[0125]
  In the wiring isolation structure according to the eleventh embodiment, as shown in FIG. 53 (C), a sidewall between the first shape word lines WL2, WL4,... The first that exists between the SW and the substrate SUBCharge storage filmGD1, the second shape word lines WL1, WL3,... And the second SUB existing between the substrate SUB.Charge storage filmGD2. A thin thermal oxide film 10 is interposed between the first shape word lines WL2, WL4,... And the sidewall SW. These points are different from the eighth and ninth embodiments.
  FirstCharge storage filmGD1 and secondCharge storage filmGD2 has the same specifications for the film structure.
  The thermal oxide film 10 is obtained by thermally oxidizing the surface of the first shape word lines WL2, WL4,... Made of doped polycrystalline silicon or doped amorphous silicon. Therefore, the controllability of the film thickness is extremely high, and the film quality is good because it is silicon dioxide obtained by thermal oxidation. For this reason, there exists an advantage that the insulation characteristic between wiring improves.
[0126]
  In the formation of this wiring structure, first, as shown in FIG. 52A, the first SUB is formed on the substrate SUB.Charge storage filmGD1 is formed, and first-shaped word lines WL2, WL4,... Are formed thereon with a pitch that is approximately twice the final pitch. The first shape word lines WL2, WL4,... Are formed from doped polycrystalline silicon or doped amorphous silicon.
  As shown in FIG. 52B, the surface of the first-shaped word lines WL2, WL4,... Is thermally oxidized to form a thermal oxide film 10 made of silicon dioxide having a thickness of several nanometers to several tens of nanometers. Note that nitriding treatment or oxynitriding treatment by heating may be performed instead of thermal oxidation.
[0127]
  After that, as in the eighth and ninth embodiments,Insulation film3 is deposited (FIG. 52C) and etched back to form sidewalls SW (FIG. 53A).
[0128]
  Here, in the eleventh embodiment, as shown in FIG. 53A, the first shape word lines WL2, WL4,...Charge storage filmRemove GD1.
  Then the secondCharge storage filmAfter forming GD2 over the entire surface, a conductive film 4 is deposited (FIG. 53B), and this is ground and / or polished to form a plurality of word lines WL1 to WL5 (FIG. 53C).
[0129]
  In the eleventh embodiment, it is possible to effectively improve the insulation characteristics of the inter-wordline dielectric simply by performing a treatment such as thermal oxidation. Also,Charge storage filmHowever, since the first shape word line is not removed, the number of processes is not greatly changed.
[0130]
【The invention's effect】
  According to the semiconductor device of the present invention, the distance between wirings such as word lines of a semiconductor memory device can be made significantly smaller than the wiring width beyond the limit of photolithography, and as a result, useless space is reduced. In particular, when this wiring isolation structure is applied to isolation between word lines of a memory cell array, the dimension in the column direction of each memory cell can be significantly reduced, and the bit cost is greatly reduced accordingly.
  Further, it is possible to take out the electrodes despite the narrow word line pitch.
[0131]
  In the method for manufacturing a semiconductor device according to the present invention, the above-described wiring isolation structure can be easily formed using a normal photolithography technique, an etching technique, or the like without using a special process.
[0132]
  The above wiring distance isInsulation filmThickness and / orSide wall insulation layerSpecified by the width of
  Insulation filmCan be controlled with very high accuracy, as is well known.
  Also,Side wall insulation layerThe width can be controlled by the height of the sacrificial layer or the first shape wiring and the etching conditions of the dielectric.Side wall insulation layerSince the etching at the time of forming is usually performed under conditions of strong anisotropy, the variation in the sidewall width is small even if the etching time varies somewhat. Therefore,Side wall insulation layerThe uniformity of the width is relatively high. Also,Side wall insulation layerIn addition to theInsulation filmEven when there is intervening, the width is very uniform because it is determined by the film thickness.
  As described above, the variation in the distance between wirings is considerably small.
[0133]
  Further, in the manufacturing method according to the present invention, introduction of substrate damage and etching of the first word line can be suppressed as much as possible.
  By introducing the substrate surface etching, fluctuations in the thickness of the charge storage film caused by forming the first word line and the second word line in two steps are effectively suppressed, and fluctuations in characteristics are prevented.
  In addition, there is an electrical isolation (residue removal) step of the second word line, and as a result, over-etching is minimized when forming the second word line, and the insulation isolation characteristics between the word lines can be maintained at a high level. Further, it is possible to suppress or prevent leakage current particularly at the time of reading.
[Brief description of the drawings]
1A and 1B are a plan view and a cross-sectional view showing a configuration of a semiconductor memory device having a VG type memory cell array according to a first embodiment.
FIG. 2 is a cross-sectional view after forming a first word line in manufacturing the semiconductor memory device according to the first embodiment;
FIG. 3 is a cross-sectional view during substrate etching in manufacturing the semiconductor memory device according to the first embodiment.
FIG. 4 shows a second time in the manufacture of the semiconductor memory device according to the first embodiment.Charge storage filmIt is sectional drawing after forming.
FIG. 5 is a cross-sectional view after forming a resist pattern for a processing mask for a second word line in the manufacture of the semiconductor memory device according to the first embodiment;
FIG. 6 is a plan view showing a configuration of a semiconductor memory device having a NAND memory cell array according to a second embodiment.
FIG. 7 is a cross-sectional view showing a configuration of a semiconductor memory device having a NAND memory cell array according to a second embodiment and an enlarged view thereof.
FIG. 8 is a cross-sectional view after forming a first word line in manufacturing a semiconductor memory device according to a second embodiment;
FIG. 9 is a cross-sectional view during substrate etching in manufacturing a semiconductor memory device according to the second embodiment;
FIG. 10 shows a second time in the manufacture of the semiconductor memory device according to the second embodiment.Charge storage filmIt is sectional drawing after forming.
11 is a cross-sectional view after forming a resist pattern for a processing mask of a second word line in the manufacture of a semiconductor memory device according to a second embodiment; FIG.
FIG. 12 is a graph showing the measurement results when the film thickness variation of the thermal oxide film with and without RTN is investigated in order to explain the necessity of substrate etching in the manufacturing method according to the first and second embodiments. .
FIG. 13 is a cross-sectional view after patterning a first word line in manufacturing a nonvolatile memory device according to a third embodiment;
FIG. 14 is a cross-sectional view after forming a thermal oxide film in the manufacture of the nonvolatile memory device according to the third embodiment;
FIG. 15 is a cross-sectional view after forming a thermal oxide film in the manufacture of the nonvolatile memory device according to the third embodiment;
FIGS. 16A and 16B are a cross-sectional view and a plan view showing problems of the first to third embodiments to be solved in the manufacture of the nonvolatile memory device according to the fourth embodiment. FIGS.
FIG. 17 is a view showing a planar pattern of word lines around the memory cell array in the nonvolatile semiconductor memory device according to the fourth embodiment.
FIG. 18 is a plan view of a word line pattern of a non-volatile memory device showing a portion where a residue is removed in the first method for preventing leakage according to the fifth embodiment.
FIG. 19 is a cross-sectional view of the nonvolatile memory device taken along line AA in FIG. 18, showing a state after residue removal using the first method for preventing leakage according to the fifth embodiment.
FIG. 20 is a plan view of a word line pattern of a nonvolatile memory device when a second method for preventing leakage according to a fifth embodiment is applied.
FIG. 21 is a diagram showing a configuration of a nonvolatile memory device to which a third method for preventing leakage according to a fifth embodiment is applied.
22 is a plan view showing a wiring structure of a semiconductor device according to a sixth embodiment and a cross-sectional view taken along the line AA. FIG.
FIG. 23 is a plan view after formation of a sacrificial layer and a cross-sectional view along the line AA in the manufacture of the semiconductor device according to the sixth embodiment.
FIG. 24 is a cross-sectional view after dielectric deposition in the manufacture of the semiconductor device according to the sixth embodiment.
FIG. 25 is a plan view after forming a sidewall and a cross-sectional view along the line AA in the manufacture of the semiconductor device according to the sixth embodiment;
FIG. 26 is a plan view after removal of the sacrificial layer and a cross-sectional view along the line AA in the manufacture of the semiconductor device according to the sixth embodiment.
FIG. 27 is a cross-sectional view after conductive film deposition in the manufacture of the semiconductor device according to the sixth embodiment.
FIG. 28 is a cross-sectional view after forming a first shape wiring in manufacturing a semiconductor device according to the seventh embodiment;
FIG. 29 is a cross-sectional view after forming a thermal oxide film in the manufacture of a semiconductor device according to the seventh embodiment.
FIG. 30 is a cross-sectional view after dielectric deposition in the manufacture of the semiconductor device according to the seventh embodiment.
FIG. 31 is a cross-sectional view after sidewall formation, in the manufacture of the semiconductor device according to the seventh embodiment.
FIG. 32 is a cross-sectional view after conductive film deposition in the manufacture of the semiconductor device according to the seventh embodiment.
FIG. 33 is a cross-sectional view showing a wiring structure of a semiconductor device according to a seventh embodiment.
FIG. 34 is a plan view of a NOR type memory cell array according to an eighth embodiment and a cross-sectional view taken along the lines AA and BB.
FIG. 35 is a plan view after formation of a sacrificial layer and a cross-sectional view along the line AA in the manufacture of the semiconductor device according to the eighth embodiment.
FIG. 36 is a cross-sectional view after dielectric deposition in the manufacture of the semiconductor device according to the eighth embodiment.
FIG. 37 is a plan view after formation of a sidewall and a cross-sectional view along the line AA in the manufacture of the semiconductor device according to the eighth embodiment.
FIG. 38 is a plan view after removal of the sacrificial layer and a cross-sectional view along the line AA in the manufacture of the semiconductor device according to the eighth embodiment.
FIG. 39 is a cross-sectional view after deposition of a conductive film in the manufacture of a semiconductor device according to the eighth embodiment.
FIG. 40 is a plan view of a NAND memory cell array according to a ninth embodiment.
FIG. 41 is a cross-sectional view taken along line AA of the NAND memory cell array according to the ninth embodiment and a partially enlarged view thereof.
FIG. 42 is a plan view after formation of a sacrificial layer and a cross-sectional view along the line AA in the manufacture of the semiconductor device according to the ninth embodiment.
FIG. 43 is a cross-sectional view after dielectric deposition in the manufacture of the semiconductor device according to the ninth embodiment.
44 is a plan view after sidewall formation and a cross-sectional view along the AA line in the manufacture of the semiconductor device according to the ninth embodiment; FIG.
45 is a plan view after removal of the sacrificial layer and a cross-sectional view along the line AA in the manufacture of the semiconductor device according to the ninth embodiment; FIG.
FIG. 46 is a cross-sectional view after the conductive film is deposited in the manufacture of the semiconductor device according to the ninth embodiment.
47 is a plan view after formation of a word line and a cross-sectional view along the line AA in the manufacture of the semiconductor device according to the ninth embodiment; FIG.
FIG. 48 is a cross-sectional view after processing the select gate line in the manufacture of the semiconductor device according to the ninth embodiment.
FIG. 49 is a plan view after formation of source / drain regions and a sectional view taken along line AA in the manufacture of the semiconductor device according to the ninth embodiment;
FIG. 50 is a cross-sectional view showing the steps up to dielectric deposition in the manufacture of the semiconductor device according to the tenth embodiment.
FIG. 51 is a cross-sectional view showing the steps up to word line formation in the manufacture of the semiconductor device according to the tenth embodiment;
FIG. 52 is a cross-sectional view showing the steps up to dielectric deposition in the manufacture of the semiconductor device according to the eleventh embodiment.
FIG. 53 is a cross-sectional view showing the formation of up to word lines in the manufacture of the semiconductor device according to the eleventh embodiment.
[Explanation of symbols]
SUB ... Substrate (semiconductor), WL1, etc .... Word line, PAD1, etc .... Electrode extraction part, WLF ... Conductive film to be word line, BL1, etc .... Bit line, S / D ... Source / drain region, GD, GD1, GD2 ...Charge storage film (First or second charge storage film), BTM ...First potential barrier film, CHS ... charge trapping film, TOP ...Second potential barrier filmSG1, SG2 ... selection gate line, DR ... drain region, CSL ... common source line, BC ... bit contact, INT ... interlayer insulating film, 1 ... dielectric, 2, 20, 30, 40 ... sacrificial layer, 3 ...Insulation filmDESCRIPTION OF SYMBOLS 4 ... Conductive film, 50 ... Row decoder, 51 ... Word line drive circuit (2nd word line drive circuit), 52 ... Word line drive circuit (1st word line drive circuit), TOX, 10 ... Thermal oxide film , SW ...Side wall insulation layer, TL1, IL2 ... wiring

Claims (9)

A plurality of memory transistors arranged in a matrix;
A plurality of word lines which are also used as gate electrodes of memory transistors in the same row and are repeatedly arranged at intervals in the column direction and in the row direction;
An insulating film is formed between the plurality of word lines to isolate the word lines from each other,
The distance between the word lines is defined by the thickness of the insulating film,
The insulating film between the word lines is
A charge storage film comprising a plurality of films and having a charge storage capability;
A thermal oxide film formed on the surface of the word line every other word line
A semiconductor device including: A plurality of memory transistors arranged in a matrix on a semiconductor, and a plurality of word lines that are also used as gate electrodes of the memory transistors in the same row and are repeatedly arranged in the column direction and extending in the row direction. An insulating film is formed between the word lines so that the word lines are insulated and separated, and a dimension of the insulating film in a direction in which the word lines are separated is defined by a film thickness. There,
Forming a stacked pattern of a first charge storage film composed of a plurality of films and having a charge storage capability and a first word line on a semiconductor in parallel with each other at a predetermined interval;
Etching a semiconductor surface region exposed between the first word lines;
Forming a second charge storage film comprising a plurality of films and having a charge storage capability on the surface of the first word line and the semiconductor region exposed between the first word lines;
Forming a second word line buried at least partially between each of the first word lines with a second charge storage film interposed between the first word lines. . Each of the steps of forming the first charge storage film and the second charge storage film includes
Forming a first potential barrier film by thermally oxidizing the surface of the semiconductor;
Nitriding the first potential barrier film , or forming a nitride film on the first potential barrier film ,
The step of forming the first word line includes:
Forming the first charge storage film on the semiconductor made of single crystal silicon;
Forming a conductive film made of polycrystalline silicon or amorphous silicon on the first charge storage film to be the first word line;
The method for manufacturing a semiconductor device according to claim 2, further comprising: continuously etching the conductive film and the first charge storage film in the same pattern. In the etching of the semiconductor surface region, the sacrificial oxide film is formed on the single crystal silicon exposed between the first word lines, and the sacrificial oxide film is removed to thereby remove the single crystal silicon consumed during the sacrificial oxidation. The method for manufacturing a semiconductor device according to claim 3, wherein the surface layer is removed. The method further includes a step of performing over-etching selectively on at least one end portion of the first word line under the condition that the material of the second word line is removed after the formation of the second word line. Item 3. A method for manufacturing a semiconductor device according to Item 2 . In the step of forming the first and second word lines, the first and second word lines extend outside the memory cell array, bend in a direction different from the wiring direction of the word lines, and are first on the tip side from the bent portion. A wiring pitch between the word line and the second word line is set larger than a wiring pitch between the first word line and the second word line in the memory cell array, and an electrode is provided at each end on the side where the wiring pitch is large. The method for manufacturing a semiconductor device according to claim 5, further comprising an extraction portion, wherein the electrode extraction portion of the first word line is arranged outside the electrode extraction portion of the second word line. Forming a mask layer opening around the outer sidewall of the outermost first word line after the formation of the second word line when the outermost first word line exists; and ,
And over-etching through the opening of the mask layer selectively on the periphery of the sidewall of the first word line located on the outermost side under the condition that the material of the second word line is removed. A method for manufacturing a semiconductor device according to claim 2 . A plurality of memory transistors arranged in a matrix;
A plurality of word lines which are also used as gate electrodes of memory transistors in the same row and repeated in the row direction and in the column direction;
Two adjacent word lines are formed on a side surface of one word line and formed between a side wall insulating layer having a substantially elliptical cross section, and between the side wall insulating layer and the word line, The sidewall insulating layer and the word line are separated by an insulating film whose dimension in the direction of separation is defined by the film thickness,
The plurality of word lines have a vertical side surface or a forward tapered cross-sectional shape, the first shape word line in which the sidewall insulating layer is formed on two side surfaces, and the first shape in the column direction. And a second shape word line having an inverse taper reflecting at least the upper end portion reflecting the shape of the sidewall insulating layer,
Between the first shape word line and the semiconductor, between the second shape word line and the semiconductor, between the first shape word line and the sidewall insulating layer, and with the second shape. A charge storage film including charge storage means is formed between the word line and the sidewall insulating layer,
A semiconductor device in which a thermal oxide film is formed between the charge storage film on the first shape word line side and the sidewall insulating layer . A plurality of memory transistors arranged in a matrix on a semiconductor, and a plurality of word lines that are long in the row direction and repeated in the column direction, both serving as gate electrodes of the memory transistors in the same row; A semiconductor device in which a word line is formed on a side surface of one of the word lines and separated by a sidewall insulating layer having a substantially elliptical cross section and an insulating film formed on the surface of the sidewall insulating layer A manufacturing method of
Forming a plurality of stacked films composed of a charge storage film including a charge storage means and a first conductive film on the semiconductor in parallel with each other at regular intervals;
Forming the sidewall insulating layer on two side surfaces of the laminated film;
To the side wall surface of the insulating layer and the sidewall insulating layer semiconductor region exposed between, forming a charge storage layer comprising a charge storing means therein again,
Depositing a second conductive film so as to fill a recess in the surface of the charge storage film ;
Cutting the second conductive film from the surface to form the plurality of word lines separated by the sidewall insulating layer and the charge storage film .

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