JP2003168750A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an isolation structure between word lines, which permits the lines to be arranged close. <P>SOLUTION: The semiconductor device is provided with a plurality of memory transistors arranged in lines and a plurality of word lines WL1, WL2,..., being gate electrodes of the memory transistors in the same line and long in the direction of the lines and repeated in the direction of a row, while two word lines, neighbored in the direction of the row among the plurality of word lines, are separated by a dielectric film GD2 interposed so that the size in the separating direction of them becomes the thickness of the film. The dielectric film GD2 is constituted of a plurality of dielectric films BTM, CHS, TOP, for example, and is a charge accumulation film having charge retaining ability. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of wirings arranged in parallel with each other, for example, a word line of a memory cell array, and a method of manufacturing a semiconductor device in which the distance between the wirings is minimized. .

[0002]

2. Description of the Related Art For example, a flash EEPROM (Flash
A word line of a non-volatile memory device such as an Electrically Erasable and Programmable ROM) doubles as a gate electrode of a memory transistor and is arranged long in the row direction of the memory cell array. The word lines are also repeatedly arranged in the column direction with a certain distance therebetween. When the bit lines are formed by patterning metal or polycrystalline silicon, the bit lines are also arranged in parallel with each other with a distance therebetween. There are many other wirings arranged in this way, such as word lines and bit lines of other memories (other ROMs and RAMs) or gate lines of gate arrays.

In such wiring patterning, after forming a conductive material, a resist is applied on the conductive material and the pattern on a photomask such as a reticle is transferred to the resist. Then, the conductive material is etched using the resist to which the pattern is transferred as a mask for patterning. Alternatively, a material having a stronger etching resistance is interposed between the conductive material and the resist, and the resist pattern is once transferred to the layer of the material having a strong etching resistance. Then, the conductive material is etched and patterned by using the layer of the material having a high etching resistance to which the pattern is transferred as a mask.

[0004]

SUMMARY OF THE INVENTION In such a method,
Patterning cannot be performed below the resolution limit of photolithography depending on the wavelength of light used.

A so-called phase shift method is known as a method for performing patterning below the resolution limit of photolithography. However, there is a limit to the reduction of the inter-wiring distance by this method, and the inter-wiring distance cannot be extremely reduced.

Therefore, for example, word lines in a conventional semiconductor memory are generally formed in parallel stripes having a space width almost equal to the word line width. Therefore, there is a waste of space in the column direction, which is one of the factors that hinder the bit cost reduction.
The problem that the area reduction is restricted by the wiring pitch is basically common to other semiconductor devices such as other wirings of a memory device and wirings of a gate array, which have many fine repeating wiring patterns.

It is a first object of the present invention to provide a semiconductor device including a plurality of wirings having an isolation structure which can be arranged at a distance much shorter than that of the conventional one. Second of the present invention
It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a plurality of wirings can be formed while being separated from each other by a distance that is significantly shorter than in the conventional case.

[0008]

A semiconductor device according to a first aspect of the present invention uses a plurality of memory transistors arranged in rows and columns as gate electrodes of memory transistors in the same row and is long in the row direction. A plurality of word lines that are repeatedly arranged at intervals in the column direction, and two word lines that are adjacent to each other in the column direction among the plurality of word lines have a dimension in the separating direction that is a film thickness. They are separated by an intervening dielectric film (claim 1).

A semiconductor device according to a second aspect of the present invention is
A semiconductor device having a plurality of wirings arranged in parallel to each other, wherein adjacent wirings are separated by a dielectric, and the dielectric between the wirings is formed on one side surface of two adjacent wirings. And a sidewall-shaped dielectric material (claim 24).

A semiconductor device according to a third aspect of the present invention is
A semiconductor device having a plurality of wirings arranged in parallel to each other, wherein adjacent wirings are separated by a dielectric, and the dielectric between the wirings is formed on one side surface of two adjacent wirings. And a dielectric film interposed between the sidewall dielectric and the wiring so that the dimension in the direction of separation between the two becomes a film thickness (claim 27).

In the semiconductor device according to the first to third aspects, a plurality of the wirings (hereinafter, word lines are included) are arranged in parallel to one another and long in one side. Here, “longer arrangement on one side” does not necessarily mean that the wiring is a straight line, and includes a case where the wiring is meandering in the same direction, for example. When the wirings are separated by a dielectric, but separated by a dielectric film interposed so that the distance between the wirings becomes a film thickness (first viewpoint), the wirings are formed on one side surface between the wirings. When separated by a sidewall-type dielectric (second viewpoint), the sidewall-type dielectric is interposed between the sidewall dielectric and one of the wirings so that the distance becomes a film thickness. There is a case where it is separated by the dielectric film (third aspect).

In these semiconductor devices, the distance between wirings is determined by the film thickness of the dielectric film and / or the width of the sidewall type dielectric, so the distance between wirings is much smaller than the wiring width. As the dielectric film, a charge storage film having the charge storage ability of the memory transistor may be used by extending it to the side walls and the upper surface of every other wiring. Polycrystalline silicon or amorphous silicon is usually used as the wiring material, but the oxidation rate of these is twice as high as the oxidation rate of single crystal silicon. It does not become.

In order to further improve the insulation characteristics, in the first and third aspects, it is preferable to form a thermal oxide film formed by thermally oxidizing the surface of every other wiring. If the dielectric film between the wirings is a charge storage film, the film thickness is limited due to the charge storage function of the memory transistor. There are also cases where it is desired to satisfy the improvement of insulation characteristics between wirings and the reduction of capacitance at the same time while complying with the film thickness limitation. The above-mentioned interposition of the thermal oxide film serves to meet such a demand.

Further, for example, when an electrode lead-out portion is provided, it is preferable that one end of the word line is bent outside the memory cell array and the pitch is relaxed on the tip side of the bent portion (claim 6).

In the present invention, it is desirable that the second word line is located on the outermost side. That is, the number of second word lines is preferably one more than the number of first word lines (claim 10).
As will be described later, a residue of the second word line forming material remains outside the first word line, and between the source and the drain of the memory cell depending on the accumulated charge amount of the charge accumulation film formed below the residue. This is because a leak is likely to occur. In this case, further, at least one of the second word lines on the outer side is applied with a voltage which is constantly lower than the threshold value at the time of reading or a voltage which injects sufficient electric charge for leak prevention regardless of the memory operation. It is desirable to use a word line for this purpose. Specifically, it is desirable that only this word line is not driven based on the row address signal (claim 10).

In a method of manufacturing a semiconductor device according to a fourth aspect of the present invention, a plurality of memory transistors arranged in a matrix on a semiconductor are also used as gate electrodes of the memory transistors in the same row, and they are long in the row direction. A method of manufacturing a semiconductor device having a plurality of word lines repeatedly arranged in a column direction, and two adjacent word lines are separated by an intervening dielectric film so that the dimension in the separating direction is a film thickness. Which is composed of a plurality of dielectric films and has a charge storage capability
A step of forming a stacked pattern of the charge storage film and the first word line in parallel with each other at a predetermined interval on the semiconductor, Forming a second charge storage film made of the dielectric film having a charge storage capability, and at least a part of the second charge storage film is provided in the space between the first word lines.
And a step of forming a buried second word line with a charge storage film interposed (claim 12).

This manufacturing method corresponds to the semiconductor device of the first aspect described above. The formation of the thermal oxide film between the wirings is preferably performed during the formation of the laminated pattern under the condition that a film having a predetermined thickness remains after the laminated pattern is formed. That is, the surface of the formed first word line is thermally oxidized with the first charge storage film left, and then the first charge storage film is removed (claim 14). According to this method, etching damage during processing of the first word line is protected by the first charge storage film and is difficult to be introduced into the semiconductor.

After removing the first charge storage film, the semiconductor surface thereof may be thinly etched through the steps of forming a sacrificial oxide film and removing the sacrificial oxide film. If there is a step of using nitrogen for forming the charge storage film and nitrogen is introduced into the substrate, the oxidation rate fluctuates during the subsequent formation of the second charge storage film. If the step of substrate etching using this sacrificial oxidation or the like is included, there is no such variation in the oxidation rate.

Further, it is preferable that the end portion of the first word line is selectively overetched under the condition that the second word line material is removed. At the time of patterning the second word lines, since the underlying layer is the second charge storage film, excessive over-etching cannot be performed in order to prevent deterioration of insulation characteristics between the word lines. Therefore, in some cases, the second word line forming material (conductive material) may remain at the bottom of the pattern of the first word line. In this case, the second word lines are short-circuited with each other due to the slender residue at the bottom. Therefore, to prevent this, the residue is cut at the end of the first word line.

Further, as described above, when the second word line forming material remains on the side surface of the outermost first word line, this portion becomes a leak path depending on the charge amount of the charge storage film below this residue. there is a possibility. Therefore, it is preferable to add a step of selectively removing the residue of this portion (claim 23).

A semiconductor device manufacturing method according to a fifth aspect of the present invention has a plurality of wirings arranged in parallel with each other,
A method of manufacturing a semiconductor device in which two adjacent wirings are separated by a dielectric, the method comprising: forming a plurality of sacrificial layers parallel to each other at regular intervals; and sidewall spacers on two side surfaces of the sacrificial layers. Forming the conductive film, removing the sacrificial layer, depositing a conductive film so as to fill the space between the sidewall-shaped spacers, scraping the conductive film from the surface, and separating by the sidewall-shaped spacers. And a step of forming a plurality of wiring layers (claim 3
3).

A semiconductor device manufacturing method according to a sixth aspect of the present invention has a plurality of wirings arranged in parallel with each other,
A method of manufacturing a semiconductor device in which two adjacent wirings are separated by a dielectric, which comprises a step of forming a plurality of first wirings parallel to each other at regular intervals, and a sidewall shape on two side surfaces of the first wirings. Forming a spacer, a step of depositing a conductive film so as to fill the space between the sidewall-shaped spacers, a step of scraping the conductive film from the surface, and a plurality of first wirings separated from the first wiring by the sidewall-shaped spacer. Two
Forming a wiring in a space between the first wirings (claim 34). The semiconductor device manufacturing method according to the sixth aspect and the fifth aspect corresponds to the semiconductor device according to the second aspect.

In the method for manufacturing a semiconductor device according to the sixth aspect, the surface of the first wiring is thermally oxidized to form a thermal oxide film corresponding to the dielectric film of the semiconductor device according to the third aspect. You can

A method of manufacturing a semiconductor device according to a seventh aspect of the present invention uses a plurality of memory transistors arranged in a matrix on a semiconductor as gate electrodes of memory transistors in the same row, and extends in the row direction. Adjacent two word lines having a plurality of word lines repeated in the column direction are formed on the side wall of one of the word lines and on the surface of the side wall spacer. A method of manufacturing a semiconductor device separated by a dielectric film formed thereon, a step of forming a plurality of sacrificial layers on a semiconductor in parallel with each other at regular intervals, and sidewall-shaped spacers on two side surfaces of the sacrificial layer. A step of forming a film, a step of removing the sacrificial layer, and a step of removing the sacrificial layer on the surface of the sidewall spacer and on the semiconductor region exposed between the sidewall spacers. A step of forming a gate dielectric film including a charge accumulating means, a step of depositing a conductive film so as to fill a recess in the surface of the gate dielectric film, and a step of scraping the conductive film from the surface to form a sidewall spacer and a gate dielectric film. Forming a plurality of word lines separated by a body film (claim 36). This manufacturing method corresponds to the semiconductor device of the third aspect described above, and the dielectric film thereof is not the thermal oxide film but the charge storage film.

A method of manufacturing a semiconductor device according to an eighth aspect of the present invention uses a plurality of memory transistors arranged in a matrix on a semiconductor as gate electrodes of memory transistors in the same row, and extends in the row direction. Adjacent two word lines having a plurality of word lines repeated in the column direction are formed on the side wall of one of the word lines and on the surface of the side wall spacer. A method of manufacturing a semiconductor device, wherein a plurality of laminated films including a gate dielectric film including a charge storage unit inside and a first conductive film are parallel to each other at a constant interval. And forming a sidewall type spacer on the two side surfaces of the laminated film, on the surface of the sidewall type spacer and the sidewall type spacer. A step of re-forming a gate dielectric film having charge storage means therein on the semiconductor region exposed between the spacers, and a step of depositing a second conductive film so as to fill the concave portion on the surface of the gate dielectric film. Removing the second conductive film from the surface to form the plurality of word lines separated by the sidewall-shaped spacer and the gate dielectric film (claim 38). This manufacturing method corresponds to the semiconductor device of the third aspect, has a charge storage film as its dielectric film, and is one of the modes capable of forming a thermal oxide film (see claim 39). ).

A method of manufacturing a semiconductor device according to a ninth aspect of the present invention uses a plurality of memory transistors arranged in a matrix on a semiconductor as gate electrodes of the memory transistors in the same row, and extends in the row direction. Adjacent two word lines having a plurality of word lines repeated in the column direction are formed on the side wall of one of the word lines and on the surface of the side wall spacer. A method of manufacturing a semiconductor device separated by a formed dielectric film, the method comprising: forming a gate dielectric film having charge storage means therein on the semiconductor; and a plurality of conductive films made of a first conductive film. Forming layers on the gate dielectric film at regular intervals in parallel with each other; forming sidewall-shaped spacers on two side surfaces of the plurality of conductive layers;
A step of removing the gate dielectric film portion between the sidewall-shaped spacers by etching using the conductive layer and the sidewall-shaped spacers as a mask;
Re-forming a gate dielectric film having charge storage means therein on the surface of the sidewall-shaped spacer and on the semiconductor region exposed between the sidewall-shaped spacers, and filling the recess on the surface of the gate dielectric film. The step of depositing the second conductive film as described above, and the step of removing the second conductive film from the surface to form the plurality of word lines separated by the sidewall spacer and the gate dielectric film. (Claim 40). This manufacturing method corresponds to the semiconductor device of the third aspect, has a charge storage film as its dielectric film, and is one of the modes capable of forming a thermal oxide film (see claim 41). ). Further, in the ninth aspect, etching damage is less likely to be introduced into the semiconductor surface during processing of the conductive layer and the sidewall, as compared with the manufacturing method of the eighth aspect.

In the method of manufacturing a semiconductor device according to the fourth to ninth aspects described above, it is necessary to roughly stack the charge storage film and the word line material for patterning.
A high-density word line arrangement can be realized simply by repeating the operation.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] A first embodiment relates to a first aspect of the present invention and relates to a non-volatile memory device having a virtual ground (VG) type memory cell array. FIG. 1A is a plan view of a VG type memory cell array in which the distance between word lines is reduced by applying the present invention. 1B is a cross-sectional view taken along the line AA of FIG. 1A, and FIG. 1C is a cross-sectional view taken along the line BB of FIG.

As shown in FIG. 1C, source / drain regions S / D made of N-type impurity regions are formed on the front surface side of the P-type semiconductor substrate SUB so as to be spaced from each other. The source / drain regions S / D have bit lines BL1, BL2, BL3, BL4, ... As shown in FIG.
And the entire cell array has a pattern in which long lines in the column direction are arranged in parallel stripes.

The substrate region sandwiched between the source / drain regions S / D is called a channel forming region. This channel formation region is inevitably in the form of parallel stripes that are long in the column direction. A word line WL1, which is long in the row direction orthogonal to the channel forming region and the source / drain region S / D.
WL2, WL3, WL4, WL5, ... Are arranged. As shown in FIG. 1B, the even-numbered word lines WL
2, WL4, ... And odd-numbered word lines WL1, WL3
The sectional shapes of WL5, ... Are slightly different. In this embodiment,
Even-numbered word lines WL2, WL4, ... Are formed on the semiconductor substrate SUB with the gate dielectric film GD1 interposed. In the present embodiment, this even-numbered word line is the “first word line”. Further, the gate dielectric film GD1 corresponds to the “first charge storage film” in the present invention.

The surface of the first word lines WL2, WL4, ...
A gate dielectric film GD2 is formed so as to cover the surface of the substrate region exposed between the first word lines. Then, with the gate dielectric film GD2 interposed, odd-numbered word lines WL1, WL3, WL5, ... Are formed between the first word lines. In the present embodiment, the odd-numbered word lines WL1, WL3, WL5, ... Become “second word lines”. All the word lines are configured by alternately arranging the second word lines and the above-mentioned first word lines. Further, the gate dielectric film GD2 corresponds to the "second charge storage film" in the present invention. The relationship between the first and second word lines will be described in more detail. The bottom surface of the second word line faces the semiconductor region between the first word lines with the gate dielectric film GD2 interposed. Most of the side surface of the second word line faces the side surface between the first word lines with the gate dielectric film GD2 interposed. Further, both widthwise ends of the second word line run over the respective widthwise ends of two adjacent first wordlines with the gate dielectric film GD2 interposed therebetween. As described above, in the word line in the present embodiment, the space between two adjacent word lines is insulated and separated by the gate dielectric film GD2 interposed so that the dimension in the separating direction becomes the film thickness. The word line is made of doped polycrystalline silicon or doped amorphous silicon.

Since the MONOS type memory transistor is exemplified in this embodiment, the gate dielectric films GD1 and GD2 are used.
Each is composed of a so-called ONO type three-layer film. Specifically, the gate dielectric films GD1 and GD2 are the bottom dielectric film BTM at the bottom layer and the charge trap film C in the middle, respectively.
It consists of HS and the top dielectric film TOP of the uppermost layer. The bottom dielectric film BTM is formed of, for example, a thermal silicon oxide film formed by thermally oxidizing the substrate surface, or an oxynitride film formed by nitriding the thermal silicon oxide film. Charge trap film CHS
Is made of, for example, silicon nitride or silicon oxynitride, and includes a large number of charge traps therein as discrete charge storage means. The top dielectric film TOP is made of, for example, a silicon oxide film. In the case of a so-called MNOS type, the top dielectric film TOP is omitted and the charge trap film CHS is formed relatively thick. In the case of a so-called nanocrystal type, countless fine particles made of, for example, polycrystalline silicon are discretely embedded between the bottom dielectric film and the oxide film.

The gate dielectric films GD1 and GD2 have a total thickness of about ten and several nm in terms of silicon dioxide.
Further, the gate dielectric films GD1 and GD2 are formed so that the film structures including the film thickness become equal in the portion in contact with the single crystal silicon (semiconductor substrate SUB). However,
The portion of the gate dielectric film GD2 that is in contact with polycrystalline silicon or amorphous silicon (first word lines WL2, WL4, ...)
It becomes thicker in terms of silicon dioxide than the portion in contact with single crystal silicon. This is because the thermal oxidation rate of polycrystalline silicon or amorphous silicon is about twice the thermal oxidation rate of single crystal silicon. Therefore, the insulation characteristic between the word lines can be secured at a level that does not cause a problem.

At the time of writing, the storage unit 1 shown in FIG.
In the case of injecting charges into the memory cell, a positive drain voltage is applied to the bit line BL3, a reference voltage is applied to the bit line BL4, and a predetermined positive voltage is applied to the word line WL2. At this time, the electrons supplied to the channel from the right source / drain region S / D forming the bit line BL4 are accelerated in the channel,
High energy is obtained on the side of the bit line BL3, and the high energy is injected into the storage unit 1 over the potential barrier of the bottom dielectric film BTM and accumulated. When injecting charges into the storage unit 2, the voltage between the bit lines BL3 and BL4 is switched. As a result, the electron supply side and the electron energetically hot side are opposite to the above case, and the electrons are injected into the storage unit 2.

At the time of reading, the bit line B is set so that the memory side in which the bit to be read is written becomes the source.
A predetermined read drain voltage is applied between L3 and BL4. In addition, the channel portion sandwiched between the storage portions at both ends can be turned on, but the threshold voltage of the storage portions at both ends of the memory transistor is low enough not to change, and an optimized positive voltage is applied to the word line WL2. Apply to. At this time, the conductivity of the channel is effectively changed depending on the amount of accumulated charge in the storage unit to be read or the presence or absence of charge, and as a result, the stored information is converted into the amount of current on the drain side or the potential difference and read. When reading the other bit, the bit line voltage is switched so that the memory section side where the bit is written serves as the source, and the reading is performed in the same manner as above.

At the time of erasing, the channel forming region and the source
An erase voltage in the opposite direction to that at the time of writing is applied so that the drain region S / D side is high and the word line WL2 side is low. As a result, the accumulated charge is extracted from one or both of the storage portions to the substrate SUB side, and the memory transistor returns to the erased state. As another erasing method, it is generated in the source / drain region S / D side or in the vicinity of a PN junction (not shown) inside the substrate and has a polarity opposite to the accumulated charge and is generated due to tunneling between bands. A method of injecting the high-energy charge described above into the memory portion by attracting it with the electric field of the control gate can also be adopted.

Next, the procedure for forming this VG type memory cell array will be described with reference to the drawings. This forming procedure relates to the fourth aspect of the present invention. 2 to 5 are cross-sectional views (and plan views) at each step of word line formation.
Is. In FIG. 2, (A) shows a plan view, and (B) shows a sectional view taken along the line AA of (A). Other Figure 3
5A to 5C are all sectional views taken along the line AA.

First, if necessary, a well is formed in the semiconductor substrate SUB, and ion implantation for adjusting the threshold voltage is performed. Then, a mask layer such as a resist is formed on the semiconductor substrate, ions are implanted, and activated to activate the source / drain regions S / D (bit lines BL1, BL2, BL3,
BL4, ...) are formed.

A gate dielectric film G is formed on the semiconductor substrate SUB.
A first charge storage film to be D1 is formed. For example, the surface of the semiconductor substrate SUB is thermally oxidized to form the bottom dielectric film BTM, the bottom dielectric film BTM is subjected to a nitriding treatment if necessary, and a charge made of silicon nitride or silicon oxynitride is formed on the bottom dielectric film BTM. The top dielectric film TOP is formed by forming the trap film CHS and thermally oxidizing the surface of the charge trap film CHS. A conductive film made of doped polycrystalline silicon or doped amorphous is deposited on the first charge storage film by, for example, a CVD method. A resist pattern is formed on this conductive film, and anisotropic etching such as RIE is performed to pattern the conductive film. Then, the first charge storage film exposed between the conductive film patterns is removed by, for example, CF.
Patterning is performed using a dry etching apparatus using 4 / CHF3 / Ar. Then, the resist pattern is removed. As a result, the laminated pattern of the gate dielectric film GD1 and the first word line WL2 or WL4 has a parallel stripe pattern orthogonal to the source / drain regions S / D as shown in FIG. It is formed.

Next, as shown in FIG. 3, the semiconductor substrate S
Etch the UB surface layer. This etching may be normal dry etching, but a method using sacrificial oxidation is preferable. That is, the substrate surface is thermally oxidized to form a thin sacrificial oxide film, which is removed by wet etching or the like. As a result, the silicon surface layer consumed at the time of sacrificial oxidation is etched uniformly and without leaving any damage. The sacrificial oxidation condition is determined in advance so that the nitrogen atoms introduced into the substrate surface layer are sufficiently removed according to the formation condition of the first charge storage film (gate dielectric film GD1).

As shown in FIG. 4, the second charge storage film is formed under the same conditions as the first charge storage film described above. As a result, the second charge storage film (gate dielectric film GD2) is formed.

As shown in FIG. 5, the first word lines WL2,
A conductive film WLF that completely fills the spaces between WL4, ..., For example, a film of doped polycrystalline silicon or doped amorphous silicon is deposited. On the conductive film WLF, the first word line WL2
A resist pattern R having an opening above WL4, ... Is formed.

Thereafter, using this resist pattern R as a mask, anisotropic etching such as RIE is performed. Thus, the conductive film WLF is separated and the second conductive film WLF shown in FIG.
Word lines WL1, WL3, WL5, ... Are formed.

[Second Embodiment] A second embodiment relates to the first aspect of the present invention and relates to a nonvolatile memory device having a NAND type memory cell array. FIG. 6 is a plan view of a NAND type memory cell array in which the distance between word lines is reduced by applying the present invention. Further, FIG. 7 (A) shows A of FIG.
7A is a cross-sectional view taken along line A, and FIG. 7B is a cross-sectional view in which a part of FIG. 7A is enlarged.

As shown in FIGS. 7A and 7B, P
Word lines WL1, WL2, ... WLn having substantially the same sectional structure as that of the first embodiment are formed on the semiconductor substrate SUB of the mold. That is, odd-numbered word lines WL1, WL
3, ..., WLn (first word line) is a gate dielectric film G
It is formed on the semiconductor substrate SUB with D1 interposed. A gate dielectric film GD2 is formed so as to cover the surfaces of the first word lines WL1, WL3, ..., WLn and the surface of the substrate region exposed between the first word lines. And
Even-numbered word lines WL2, WL4, ... (Second word line) are formed between the first word lines with the gate dielectric film GD2 interposed. More specifically, the bottom surface of the second word line faces the semiconductor region between the first word lines with the gate dielectric film GD2 interposed. The main side surface of the second word line faces the side surface between the first word lines with the gate dielectric film GD2 interposed. Further, both widthwise ends of the second word line run over the respective widthwise ends of two adjacent first wordlines with the gate dielectric film GD2 interposed therebetween. As described above, in the word line in the present embodiment, the space between two adjacent word lines is insulated and separated by the gate dielectric film GD2 interposed so that the dimension in the separating direction becomes the film thickness. The word line is made of doped polycrystalline silicon or doped amorphous silicon.

For example, in the MONOS type memory transistor, the gate dielectric films GD1 and GD2 are the bottom dielectric film BTM of the lowermost layer, the charge trapping film CHS of the intermediate layer, and the top dielectric film of the uppermost layer, as in the first embodiment. It consists of a membrane TOP.

Outside the word line WL1, for example, the control gate line SG1 separated by the gate dielectric film GD2 is arranged in parallel. Similarly, the control gate line SG2 separated by, for example, the gate dielectric film GD2 is arranged in parallel outside the word line WLn. These control gate lines SG1 and SG2 also serve as the gate electrodes of the select transistors, and are in contact with the semiconductor substrate SUB via the gate dielectric film GD3. Gate dielectric film GD3
Is composed of, for example, a single-layer silicon dioxide film. In this case, although the manufacturing process is slightly complicated, a single-layer gate dielectric film is formed only in this portion, and the select transistor becomes a normal MOS type. Alternatively, the gate dielectric film GD
2 and GD3 as the same film, depending on the applied bias conditions,
Charge may not be injected into this gate dielectric film GD3.

A drain region DR made of an N-type impurity region is formed outside the control gate line SG1. The drain region DR is shared with another NAND string (not shown). A common source line CSL made of an N-type impurity region is formed outside the control gate line SG2. The common source line CSL is shared by one row of NAND strings arranged in the word direction and another one row of NAND strings (not shown) adjacent in the bit direction.

An interlayer insulating film INT is formed on the transistors forming these NAND strings. Bit lines BL1 and BL2 are arranged in parallel stripes on the interlayer insulating film INT. Each bit line is connected to the corresponding drain region DR by the bit contact BC formed in the interlayer insulating film INT.

At the time of writing, the storage unit 1 shown in FIG.
In the case of injecting electric charges into the gate lines, a positive drain voltage is applied to the bit line BL2, a reference voltage is applied to the common source line CSL, and a voltage for turning on the two select transistors is applied to the control gate lines SG1 and SG2. In addition, a word line WL other than the word line WL3 to which the cell to be written is connected
A pass voltage capable of transmitting the drain voltage or the reference voltage to the cell to be written is applied to 1, WL2, WL4, ... WLn. As a result, a predetermined write drain voltage is applied between the source and drain of the memory transistor forming the cell to be written. In that state, a predetermined program voltage is applied to the word line WL3. At this time, electrons supplied to the channel from the right side of FIG. 7B are accelerated in the channel, high energy is obtained at the left end of the channel, and the electrons are injected into the storage unit 1 over the potential barrier of the bottom dielectric film BTM. Are stored. When injecting charges into the storage unit 2, the voltage between the bit line BL2 and the common source line CSL is switched. As a result, the electron supply side and the electron energetically hot side are opposite to the above case, and the electrons are injected into the storage unit 2.

As another more preferable writing method,
The source side injection method can be adopted. In this case, the storage unit 1
At the time of writing to, the reference voltage is supplied from the bit line BL2 and the drain voltage is supplied from the common source line. The applied voltage of the word line WL2 closer to one source of the word line WL3 to which the cell to be written is connected is not a simple pass voltage but an optimized voltage capable of source side injection. As a result, the lateral electric field is strengthened near the boundary between the word line WL2 and the word line WL3, and electrons can be injected into the source end (memory unit 1) of the memory transistor more efficiently. When injecting charges into the storage unit 2,
The voltage between the bit line BL2 and the common source line CSL is switched, and the voltage value of the word line 4 is optimized to a value that allows source side injection. As a result, the electron supply side and the electron energetically hot side are opposite to the above case, and the electrons are injected into the storage unit 2.

At the time of reading, the bit line B is set so that the memory section side in which the bit to be read is written becomes the source.
A predetermined read drain voltage is applied between L2 and the common source line CSL, and a pass voltage is applied to a word line other than the word line to which the cell to be read is connected. In addition, the channel portion sandwiched between the storage portions at both ends can be turned on, but the threshold voltage of the storage portions at both ends of the memory transistor is low enough not to change, and an optimized positive voltage is applied to the word line WL3. Apply to. At this time, the conductivity of the channel is effectively changed depending on the amount of accumulated charge in the storage unit to be read or the presence or absence of charge, and as a result, the stored information is converted into the amount of current on the drain side or the potential difference and read. When reading the other bit, the voltage is switched between the bit line BL2 and the common source line CSL so that the memory section side in which the bit is written serves as the source, and the reading is performed in the same manner as above.

At the time of erasing, electric charges are extracted to the substrate side by using FN tunneling on the entire surface of the channel or are collectively erased by extracting electric charges to the word line side.

Next, a procedure for forming this NAND type memory cell array will be described with reference to the drawings. 8 to 11 are cross-sectional views (and plan views) at each step of forming the word line. In FIG. 8, (A) shows a plan view, and (B) shows a sectional view taken along the line AA of (A).
The other FIGS. 9 to 11 are all sectional views taken along the line AA.

First, a well is formed in the semiconductor substrate SUB, if necessary, and ion implantation for adjusting the threshold voltage is performed.

A gate dielectric film G is formed on the semiconductor substrate SUB.
A first charge storage film to be D1 is formed. For example, the surface of the semiconductor substrate SUB is thermally oxidized to form the bottom dielectric film BTM, the bottom dielectric film BTM is subjected to a nitriding treatment if necessary, and a charge made of silicon nitride or silicon oxynitride is formed on the bottom dielectric film BTM. The top dielectric film TOP is formed by forming the trap film CHS and thermally oxidizing the surface of the charge trap film CHS. A conductive film made of doped polycrystalline silicon or doped amorphous is deposited on the first charge storage film by, for example, a CVD method. A resist pattern is formed on this conductive film, and anisotropic etching such as RIE is performed to pattern the conductive film. Then, the first charge storage film exposed between the conductive film patterns is removed by, for example, CF.
Patterning is performed using a dry etching apparatus using 4 / CHF3 / Ar. Then, the resist pattern is removed. As a result, a laminated pattern composed of the gate dielectric film GD1 and the first word lines WL1, WL3, ... WLn is formed in a parallel stripe pattern as shown in FIG. 8 (A).

Next, as shown in FIG. 9, the semiconductor substrate S
Etch the UB surface layer. This etching may be normal dry etching, but a method using sacrificial oxidation is preferable. That is, the substrate surface is thermally oxidized to form a thin sacrificial oxide film, which is removed by wet etching or the like. As a result, the silicon surface layer consumed at the time of sacrificial oxidation is etched uniformly and without leaving any damage. The sacrificial oxidation condition is determined in advance so that the nitrogen atoms introduced into the substrate surface layer are sufficiently removed according to the formation condition of the first charge storage film (gate dielectric film GD1).

As shown in FIG. 10, the second charge storage film is formed under the same conditions as the first charge storage film. As a result, the second charge storage film (gate dielectric film GD2) is formed. If necessary, the gate dielectric film GD2 in the word line WL1 outer region and the word line WLn outer region is selectively removed, and a single-layer dielectric film GD3 is selectively formed in this portion.

As shown in FIG. 11, the first word line WL
, WL3, ..., WLn to completely fill the conductive film WL
Deposit a film of F, eg doped polycrystalline silicon or doped amorphous silicon. A resist pattern R having an opening above the first word lines WL1, WL3, ..., WLn is formed on the conductive film WLF.

Thereafter, using this resist pattern R as a mask, anisotropic etching such as RIE is performed. As a result, the conductive film WLF is separated, and the second conductive film WLF shown in FIG.
Word lines WL2, WL4, ... And control gate line SG
1, SG2 are formed.

N-type impurities are ion-implanted into the semiconductor substrate region outside the select gate lines SG1 and SG2. At this time, the source / drain regions are not formed because ions do not permeate in the region where the word lines are arranged. After that, the interlayer insulating film INT is deposited, the bit contact BC is formed, and the bit line is formed to complete the NAND-type nonvolatile memory device.

In the first and second embodiments described above, the second word line to be formed later is set to the first word line.
It may be formed so as to be embedded between the word lines so that no overlap occurs. In that case, it is desirable to form a stopper dielectric film on the first word line to prevent polishing such as CMP. Further, in the structure in which this overlap is not performed, by optimizing the ion implantation conditions in the NAND type, ions are allowed to pass through the gap between the word lines (gate dielectric film GD2), and thin source / drain impurities are formed in the word line direction. The area S / D may be formed.

In the semiconductor memory device according to the first and second embodiments described above, the distance between word lines is determined by the film thickness of the dielectric film (gate dielectric film GD2), so that the word line width is smaller than the word line width. The distance between lines is significantly small.
Therefore, a memory cell having an extremely small area can be realized as a cell for storing 2F ² (F: resolution limit of lithography or design rule) and 2 bits.

Further, in the method of manufacturing the semiconductor memory device according to the above-described embodiment, a high-density word line arrangement can be realized only by repeating stacking and patterning the charge storage film and the word line material twice. To be done. Also,
Since the substrate is thinly etched before the second charge storage film formation, the accuracy of the second charge storage film formation is improved.

Here, the present inventor prepares a wafer A that has been subjected to the RTN process and a wafer B that has not been subjected to the RTN process at the time of forming the first charge storage film, and forms the bottom dielectric film of the second charge storage film. Thermal oxidation was carried out assuming. The table of FIG. 12 shows the measured values of this oxide film. Here, in order to accurately measure the film thickness, the film was thermally oxidized for a long period of 18 nm, and the film thickness of the thermal oxide film was measured at five measurement points in the wafer. As a result, it can be seen that in the thermal oxidation of the wafer A that has been subjected to the RTN process, the oxidation rate is low and the variation in the oxide film thickness is larger than that of the wafer B. This is because nitrogen is introduced into the substrate during the RTN process,
This is because it inhibits oxidation. In the above-described embodiment of the present invention, the surface layer of the substrate containing nitrogen is removed by sacrificing the surface of the substrate and etching the oxide film before the second formation of the charge storage film. As a result, the charge storage film for the second time can be formed with high precision, and it becomes possible to suppress the characteristic fluctuation.

[Third Embodiment] In the third embodiment,
The present invention relates to a partial modification of the process of the second embodiment.

In the process of FIG. 2B of the first embodiment or the process of FIG. 8B of the second embodiment described above,
The conductive film pattern and the first charge storage film are continuously dry-etched to form a pattern including the first gate dielectric film GD1 and the first word line WL2 or WL4. However, dry etching is not preferable because it damages the substrate to some extent. Here, a method is conceivable in which only the conductive film pattern is dry-etched and the first charge storage film to be the first gate dielectric film GD1 is removed by wet etching. First charge storage film is ON
In the case of an O film, it cannot be removed with a silicon oxide etchant mainly containing hydrofluoric acid because there is silicon nitride, and a treatment using hot phosphoric acid is required. However, the hot phosphoric acid treatment causes a new problem that the surface of polycrystalline silicon having a high concentration is etched.

The third embodiment provides a manufacturing method suitable for removing such a first charge storage film by a wet process. The method shown in this embodiment is a VG type, NAND type.
The present invention is applicable not only to the mold, but here, description will be given with reference to FIGS. 13 to 15 showing the AA cross section.

FIG. 13 is a sectional view at the time when the first word lines WLi, WLi + 2, ... Are formed by patterning the conductive material on the first gate dielectric film GD1 having the ONO structure, and FIG. , Which corresponds to FIG. At the end of the dry etching of the conductive material, a part of the top dielectric film TOP may be scraped off due to the overetching amount, and in some cases, the top dielectric film TOP may be formed around the first word line as illustrated. To be removed.

In this embodiment, the surfaces of the first word lines WLi, WLi + 2, ... Are thermally oxidized at this point, and a thermal oxide film TOX of, for example, about 10 nm is formed on the surface of the first word lines as shown in FIG. Form.

Then, with the surface of the first word line protected by the thermal oxide film TOX, the first gate dielectric film GD1 exposed between the first word lines is removed by wet etching. That is, the silicon nitride film (charge trap film CHS) is removed by an etchant using hot phosphoric acid, and the silicon dioxide film (bottom dielectric film BTM) is removed by an etchant mainly containing hydrofluoric acid. Of course, during this etching, the thermal oxide film TOX also becomes thin. In the present embodiment, the film thickness of the thermal oxide film TOX may be preset so that the thermal oxide film is etched off at the end of this etching. Alternatively, as shown in FIG. 15, the film thickness may be increased to some extent so that the thermal oxide film TOX remains. In any case, there is an advantage that the amount of the first word line scraped is reduced as compared with the case where the thermal oxide film is not formed.

After that, as in the first and second embodiments,
A second gate dielectric film GD2 is formed, and a conductive material is embedded between the first word lines and patterned to form second word lines WLi-1, WLi + 1, .... When the thermal oxide film TOX is left to the end, the insulating property between the word lines is significantly improved in this thermal oxide film, and the parasitic capacitance between the word lines is also reduced.

[Fourth Embodiment] In the fourth embodiment,
It is a modification of the third embodiment, and more specifically, relates to a pattern of an electrode lead-out portion and a partial addition of a step for preventing occurrence of a short circuit between electrodes.

The process of FIG. 5 of the first embodiment described above,
Alternatively, in the step of FIG. 11 of the second embodiment, patterning of the second word line is performed. In the etching at this time, since the base is the second gate dielectric film GD2, it is not possible to set an excessive overetching time. Because of excessive over-etching, the second
This is because if the gate dielectric film GD2 becomes thin, the insulation between word lines may deteriorate.

After the etching of the second word line, as shown in FIG. 16A, for example, a conductive material that is the material of the second word line may remain in the vicinity of the skirt of the first word line. In particular, when a conductive layer (for example, polycrystalline silicon) to be the second word line is deposited and is thinner in the region above the first word line than in other regions, the hem of the first word line is formed. Residues of conductive material tend to remain. This residue is formed along the end face of the first word line as shown in FIG. 16 (B) and short-circuits the second word lines.

In this embodiment, in order to prevent the short circuit between the word lines, a step of cutting the residue halfway is added. Further, if the word lines are formed with a pitch close to the minimum line width of photolithography as in the first to third embodiments, it is difficult to take out electrodes for connecting the word lines to the wiring in the upper layer. In the present embodiment, details of the pattern that facilitates the extraction of the electrode will be described.

FIG. 17 shows a pattern of the end portion including the electrode lead-out portion of the word line in this embodiment. The arrangement of word lines in the memory cell array is the same as in the first or second embodiment. The word line extending from the memory cell array to one side is bent in a direction different from the wiring direction.
Here, each is bent 90 degrees from the row direction to the column direction. The bent portion of each word line is sequentially shifted, and the pitch of word line portions extending in the column direction is relaxed more than the pitch in the memory cell array. Therefore, there is a margin for forming wide electrode lead-out portions PAD1 and PAD2 for connecting each word line to a wiring (not shown) in the upper layer. The first word lines WL1a, WL1b, WL1c formed of the first-layer polycrystalline silicon have an electrode lead-out portion PAD1, are formed of the second-layer polycrystalline silicon, and have a first word line on each side. Second word line WL overlapping
2a, WL2b, WL2c have an electrode lead-out portion PAD2. Of these, the electrode lead-out portion PAD1 is arranged at a position further outside the electrode lead-out portion PAD2. Also at the other end of each word line, the first word line WL
1a, WL1b, WL1c are the second word lines WL2a,
It extends to the outside from WL2b and WL2c.

The reason for extending the first word line to the outside is that the conductive residue remaining on the edge of the first word line when the second word line is formed is removed at the end of the first word line, and the second word line is removed. This is to prevent the word lines from being electrically short-circuited.

Specifically, FIG. 2A of the first embodiment,
When the first word line is formed in the step (B), the steps of FIGS. 8A and 8B of the second embodiment, or FIGS. 13 to 15 of the third embodiment, as shown in FIG. In addition, one end is relatively long, and the electrode lead-out portion PA
A photomask having a first word line pattern in which D1 is formed and the other end is formed relatively long is used.

A second gate dielectric film GD2 is formed through the steps of FIGS. 3, 4 or 9 and 10, and polycrystalline silicon to be the second word line is deposited in the step of FIG. 5 or 11. Then, a resist pattern R is formed thereon. At this time, as shown in FIG. 17, one end portion is relatively short (that is, the first word line), the electrode lead-out portion PAD2 is formed at the tip thereof, and the other end portion is shorter than the first word line. A photomask having a second word line pattern formed to be short is used.

Next, in this embodiment, a step of removing the conductive residue is added. For example, the broken line portion A shown in FIG.
1 and A2 are opened to expose the end of the first word line, and a resist pattern for covering and protecting the entire second word line is formed. Partial overetching is performed using this resist pattern as a mask. The conditions of the etching gas and the like at this time are the same as those at the time of forming the second word line, and the etching time is such that the conductive residue is sufficiently removed at the opening. As a result, the conductive residue is cut at this portion, and the second word lines are completely electrically separated from each other.

After that, the nonvolatile memory is completed through the same steps as those of the first or second embodiment.

[Fifth Embodiment] This embodiment is for solving another problem caused by the residue of the second word line forming material. Under the residue shown in FIG. 16A, the second gate dielectric film (charge storage film) GD2, which is protected by the residue and maintains the charge storage capability at a high level, is left in a complete form. On the other hand, the second gate dielectric film GD2 around the second gate dielectric film GD2 is removed, or even if it is left, it is exposed to etching, so that its charge storage capability is considerably lowered.

In some cases, charges are accumulated in the charge accumulation film under the residue during gate processing or operation. When the cell is an N-channel type, the accumulation of electrons raises the threshold value, so it is not a big problem, but when holes are accumulated, the channel directly below the residue becomes depletion, increasing the leak between the source and drain of the cell. To do. If the threshold value is low even if it is not depletion, the potential of the residue in the electrically floating state rises due to capacitive coupling with the adjacent word line to which a high positive voltage is applied, turning on the channel of this parasitic transistor. The leak increases. This increase in leak brings about a disadvantage that the S / N ratio of the read signal is lowered for all cells, especially during reading, and thus erroneous reading is caused.

The present embodiment is for preventing this increase in leakage. In this embodiment, there are the following three methods for preventing leakage. In the first method, the residue is selectively removed at this portion. In the second method, the number of word lines is set to an odd number to prevent the occurrence of residues in this portion. In the third method, in view of the fact that the number of word lines is usually an even number, in addition to the above second method, the word line outside thereof is used as a dedicated line for applying the leak prevention voltage.

The three methods will be sequentially described below with reference to the drawings. Note that the drawings used here are also applied to the technique of the fourth embodiment described above, but this application is not essential. Further, the configurations already described and given the same reference numerals will not be repeated here.

FIG. 18 is a plan view showing a residue removal portion in the first method. Further, FIG. 19 is a cross-sectional view taken along the line AA of FIG. 18 after removing the residue using the first method. In the resist pattern R for removing the residue of the second word line used in the above-described fourth embodiment, in addition to the opening portions A1 and A2, as shown in FIG. Then, an opening A3 that opens at least near the long side outside WL1a is added in advance on the pattern. Therefore, during etching using this resist pattern R as a mask, in addition to the openings A1 and A2,
As shown in FIG. 19, the residue of the conductive material that is the material for forming the second word line exposed through the opening A3 is effectively removed. As a result, according to the first method, there is an advantage that the above-mentioned leak current caused by the residue in the opening A3 is prevented or reduced.

FIG. 20 is a plan view when the above-mentioned second method is applied. In the second method, an odd number of word lines are provided. That is, assuming that the number of first word lines is n, (n + 1) second word lines are provided. As a result, the second word line is arranged on the outermost side of the memory cell array, and as a result, the problem of leakage due to the residue of the second word line is solved. Note that the normal number of word lines is an even number, and in comparison with this, one extra word line is required. In this case, for example, an address signal may not be assigned so that an extra word line is not used.

FIG. 21 is a plan view and a block diagram when the third method is applied. In the third method, the number of word lines is an odd number as in the second method. A normal word line drive circuit 51 driven by a row decoder 50 that decodes the input row address signal RAD is connected to the n word lines WL1a to WL2c. On the other hand, an extra second word line WL2
Further, a word line drive circuit 52 which is not driven by the row decoder 50 and which constantly applies a write voltage regardless of write data or applies a predetermined voltage which always turns off a channel at the time of reading is connected. The word line drive circuit 52 corresponds to the "first word line drive circuit" in the present invention, and the normal word line drive circuit 51 driven by the row decoder 50 is the "second word line drive circuit" in the present invention. Corresponds to. In the third method, by optimizing the voltage applied to the word line drive circuit 52, the channel immediately below the word line WL2 is always in the off state to prevent a leak current at the time of reading. Alternatively, by always performing the write operation regardless of the write data, the gate dielectric film GD2 immediately below the word line WL2.
At this time, sufficient electrons are always accumulated, and all the cells having the word line WL2 as a gate are of the enhancement type to prevent the generation of the leak current.

[Sixth Embodiment] This embodiment relates to a semiconductor device according to a second aspect of the present invention. FIG. 22A is a plan view of the semiconductor device according to the sixth embodiment after the wiring is formed,
22B is a cross-sectional view taken along the line AA of FIG. This semiconductor device has the following multilayer wiring structure.
The wiring separation structure of the present invention is applied to a plurality of wirings arranged in parallel in one layer.

On the dielectric 1 supported by the substrate SUB,
The first shape wiring IL1 having a substantially vertical side surface or a cross-sectional shape of a forward taper is formed at equal intervals. Also,
A second-shaped wiring IL2 having at least an upper portion having a cross-sectional shape of an inverse taper is formed between the first-shaped wiring IL1. First shape wiring IL1 and first shape wiring IL2
A sidewall type dielectric (hereinafter, simply referred to as “sidewall”) SW is interposed between the wirings and the wirings, thereby insulating the wirings from each other. Here "sidewall type"
As shown in FIG. 22 (B), the term means a substantially planar first side surface and a second side surface including at least a part of a curved surface curved in an arc shape so that the upper portion is closer to the first side surface. Refers to the shape that it has. The sidewall SW is formed on the side surface of the first shape wiring IL1. Therefore, the surface of the sidewall SW on the side opposite to the first shape wiring IL1 is a curved surface. The second shape wiring IL2 is formed so as to be embedded in the concave portion formed by the curved surface. As a result, the second shape wiring IL2 has an inverse tapered cross-sectional shape.

The wirings IL1 of the first and second shapes are formed.
The ILs 2 may be parallel to each other, and may be, for example, meandering as a whole. Alternatively, the wiring may be in direct contact with the substrate SUB (for example, Schottky metal).

Next, the procedure for forming this wiring will be described with reference to the drawings. This forming procedure relates to the fifth aspect of the present invention. 23 to 27 are cross-sectional views (and plan views) at each step of wiring formation. 23, 25, and 26, a plan view is shown in FIG.
A sectional view taken along line AA of (A) is shown in (B). All the other drawings represent sectional views taken along the line AA.

As shown in FIGS. 23A and 23B, a plurality of sacrificial layers 2 made of a dielectric material are formed on the dielectric material 1 above the substrate SUB. The plurality of sacrificial layers 2 are formed in stripes in parallel with each other at a pitch almost twice that of the wiring to be formed. As shown in FIG. 24, a dielectric film 3 of a different material is deposited so as to cover the sacrifice layer 2. As the material of the dielectric film 3, a material having a high etching selection ratio with respect to the sacrifice layer 2 is selected. For example, the sacrificial layer 2 is a silicon nitride film and the dielectric film 3 is a silicon dioxide film. Further, since a part of the dielectric film 3 finally remains as a sidewall, the material and the forming method are selected in consideration of the quality of the film and the insulating property.

Then, the dielectric film 3 is etched back by anisotropic etching. As a result, as shown in FIG.
As shown in (B), the sidewall SW is formed on the side surface of the sacrificial layer 2. The width of the sidewall SW is mainly determined by the height of the sacrificial layer 2 and the anisotropic etching conditions. However, when the anisotropy is strong to some extent, the sidewall width does not change much even if the etching time varies to some extent, and thus the uniformity is relatively high.

After that, the sacrifice layer 2 is selectively removed by a predetermined method. For example, in the case where the sacrificial layer 2 is silicon nitride, a wet process using an etchant containing hydrofluoric acid FH is performed. As a result, as shown in FIGS. 26A and 26B, the sidewall SW is left. As shown in FIG. 27, a conductive film 4 that completely fills the sidewall SW, for example, a film of metal, doped polycrystalline silicon or doped amorphous silicon is deposited. After that, the surface of the conductive film 4 is ground and / or polished by, for example, the CMP method or another method. This grinding and / or polishing is performed until the conductive film 4 is separated into a plurality when the sidewall SW is exposed, and then the separation distance becomes a required value. As a result, the sidewall S is kept at a necessary distance.
A plurality of wiring layers IL1 and IL2 separated by W are formed.

In the sixth embodiment, since the distance between the wiring layers is determined by the width of the sidewall-shaped dielectric SW, the wiring layers can be made sufficiently smaller than the limit of photolithography. At this time, the controllability of the distance between the wiring layers is also high.

[Seventh Embodiment] The seventh embodiment relates to a semiconductor device according to a third aspect of the present invention. FIG. 33 is a sectional view showing the wiring structure according to the seventh embodiment. A plan view of this wiring structure is similar to that of FIG. 22A, and the wiring structure has a plurality of wirings IL arranged in parallel stripes.
1, IL2. In the cross-sectional view, the fact that the first-shape wiring IL1 and the second-shape wiring IL2 are alternately arranged is common to FIG. 22B.

In the wiring separation structure according to the seventh embodiment,
In addition to the sidewall SW, the thin thermal oxide film 10 is interposed between the sidewall SW and the first-shaped wiring IL1 unlike the first embodiment. Thermal oxide film 10
When the first shape wiring IL1 is made of doped polycrystalline silicon or doped amorphous silicon, is obtained by thermally oxidizing the surface of the wiring IL1. Therefore, the controllability of the film thickness is extremely high, and the film quality is good because it is silicon dioxide obtained by thermal oxidation. Therefore, there is an advantage that the insulating characteristic between the wirings is improved.

28 to 32 are sectional views showing the formation of this wiring structure. As shown in FIG. 28, the substrate SUB
The first shape wirings IL1 are formed on the dielectric 1 supported by the substrate 1 at a pitch almost twice as large as that of the final wiring. Since the first shape wiring IL1 is finally left, it is formed of doped polycrystalline silicon or doped amorphous silicon.

As shown in FIG. 29, the first shape wiring IL
The surface of No. 1 is thermally oxidized to form a thermal oxide film 10 made of silicon dioxide having a thickness of several nm to several tens of nm. Note that nitriding treatment or oxynitriding treatment by heating may be performed instead of thermal oxidation.

After that, similarly to the seventh embodiment, the dielectric film 3 is deposited (FIG. 30), and this is etched back to form the sidewall SW (FIG. 31). In addition, the conductive film 4
Is deposited (FIG. 32), and this is ground and / or polished to form a plurality of wirings IL1 and IL2.

In the seventh embodiment, it is possible to effectively improve the insulation characteristics of the inter-wiring dielectric simply by performing a process such as thermal oxidation. It should be noted that the step of removing the sacrificial layer as in the first embodiment is unnecessary, and therefore the number of steps does not increase.

[Eighth Embodiment] An eighth embodiment shows a first example in which the wiring forming method of the sixth embodiment is applied to the formation of word lines of a nonvolatile memory. Here, NO
The application to the R type memory cell array will be described. FIG. 34
FIG. 3A is a plan view of a NOR type memory cell array in which the distance between word lines is reduced by applying the present invention. Also, FIG.
4B is a sectional view taken along the line AA of FIG. 34A, and FIG. 34C is a sectional view taken along the line BB of FIG. 34A.

As shown in FIG. 34C, source / drain regions S / D made of N-type impurity regions are formed apart from each other on the surface side in the P-type semiconductor substrate SUB. As shown in FIG. 34 (A), the source / drain regions S / D form source lines SL1, SL2, ... And bit lines BL1, BL2 ,. Has a pattern arranged in. The sidewalls SW are formed on the semiconductor substrate SUB so as to be long and parallel to each other in the direction orthogonal to the source / drain regions S / D.

A gate dielectric film GD is formed so as to cover the surface of the sidewall SW and the surface of the semiconductor substrate SUB. The gate dielectric film GD is a film including charge storage means inside. In this embodiment, a MONOS type memory transistor will be exemplified, so that the gate dielectric film GD
Is a so-called ONO type three-layer film. Specifically,
The gate dielectric film GD is the bottom dielectric film BT of the lowermost layer.
M, an intermediate charge trap film CHS, and a top dielectric film TOP. The bottom dielectric film BTM is
For example, a thermal silicon oxide film formed by thermally oxidizing the substrate surface, and an oxynitride film formed by nitriding the thermal silicon oxide film. The charge trap film CHS is made of, for example, silicon nitride or silicon oxynitride, and includes a large number of charge traps therein as discrete charge storage means. Top dielectric film TOP
Is made of, for example, a silicon oxide film. The so-called MN
In the case of the OS type, the top dielectric film TOP is omitted and the charge trap film CHS is formed relatively thick. Further, in the FG type using a conductive layer as a charge storage film, from the lower layer,
In many cases, a bottom dielectric film and a floating gate are stacked, and an inter-gate dielectric film made of an ONO film is further stacked thereon.

The gate dielectric film GD has a total thickness of about ten and several nm in terms of silicon dioxide. A conductive material is embedded in the recessed portion of the surface of the gate dielectric film GD, whereby word lines WL1, WL2, ..., WL5 ,. In this illustrated example, the even-numbered word lines WL
2, WL4, ... Have a first shape, and odd-numbered word lines WL1, WL3, ... Have a second shape.

Next, the procedure for forming this NOR type memory cell array will be described with reference to the drawings. 35 to 39 are cross-sectional views (and plan views) at each step of word line formation. 35, 37 and 38, a plan view is shown in (A), and a sectional view taken along the line AA of (A) is shown in (B). All the other drawings represent sectional views taken along the line AA.

First, a layer for dielectric isolation between elements is provided on the semiconductor substrate SUB, if necessary, and ion implantation or the like for adjusting the threshold voltage is performed. Then, a mask layer such as a resist is formed on the semiconductor substrate, ions are implanted, and activated to activate the source / drain regions S / D (source lines SL1,
SL2 and bit lines BL1, BL2) are formed.

As shown in FIG. 35A, a plurality of sacrificial layers 2 made of a dielectric material are formed on the substrate SUB in a parallel stripe pattern orthogonal to the source / drain regions S / D.
Form on top. The plurality of sacrificial layers 20 are formed in stripes parallel to each other at a pitch approximately twice that of the word line to be formed. As shown in FIG. 36, a dielectric film 3 of a different material is deposited so as to cover the sacrifice layer 20. A material having a high etching selection ratio with respect to the sacrificial layer 20 is selected as the material of the dielectric film 3. For example, the sacrificial layer 20 is a silicon nitride film and the dielectric film 3 is a silicon dioxide film. Moreover, since a part of the dielectric film 3 finally remains as a sidewall,
The material and the forming method are selected in consideration of the quality of the film and the insulating property.

Subsequently, the dielectric film 3 is etched back by anisotropic etching. As a result, as shown in FIG.
As shown in (B), the sidewall SW is formed on the side surface of the sacrificial layer 20. The width of this sidewall SW is
It is mainly determined by the height of the sacrificial layer 20 and the conditions of anisotropic etching. However, when the anisotropy is strong to some extent, the sidewall width does not change much even if the etching time varies to some extent, and thus the uniformity is relatively high.

After that, the sacrifice layer 20 is selectively removed by a predetermined method. For example, in the case of removing the sacrifice layer 20 of silicon nitride, a wet process using an etchant containing phosphoric acid (H3 PO4) is performed. As a result, FIG.
Sidewalls SW are left as in (A) and (B).

As shown in FIG. 39, the sidewall SW
A conductive film 4 for completely filling the film is deposited, for example, a film of metal, doped polycrystalline silicon or doped amorphous silicon. After that, the surface of the conductive film 4 is ground and / or polished by, for example, the CMP method or another method. This grinding and / or polishing is performed until the conductive film 4 is separated into a plurality when the sidewall SW is exposed, and then the separation distance becomes a required value. As a result, a plurality of word lines WL1, WL2, ..., WL5, .. Note that this grinding and / or polishing is desirably performed until the charge trap film CHS is completely divided into word lines. However, when the charge storage film is an FG type which is a conductive material, the division of the charge storage film is essential. This is because if the floating gate FG is connected at this location, the accumulated charge leaks to the adjacent cell, making it impossible to store data. Further, in order to avoid electric field concentration at this portion, it is necessary to perform sufficient grinding and / or polishing.

[Ninth Embodiment] A ninth embodiment shows a second example in which the wiring forming method of the sixth embodiment is applied to the formation of a word line of a nonvolatile memory. Here, NA
The application to the ND type memory cell array will be described. Figure 40
Is a NAN in which the distance between word lines is reduced by applying the present invention.
It is a top view of a D-type memory cell array. In addition, FIG.
41A is a cross-sectional view taken along the line AA of FIG. 40, FIG.
FIG. 41B is an enlarged cross-sectional view of a part of FIG.

As shown in FIGS. 41 (A) and 41 (B), word lines WL1, WL2, ... WLn having substantially the same sectional structure as that of the sixth embodiment are formed on the P-type semiconductor substrate SUB. There is. That is, the sidewalls SW are formed in parallel stripes on the semiconductor substrate SUB, and the gate dielectric film GD is formed so as to cover the surfaces of the sidewalls SW and the surface of the semiconductor substrate SUB. For example, M
In the ONOS type memory transistor, as in the sixth embodiment, the gate dielectric film GD is composed of the bottom dielectric film BTM of the lowermost layer, the charge trap film CHS of the middle layer, and the top dielectric film TOP of the uppermost layer. This gate dielectric film G
D has a total thickness of about a dozen nm in terms of silicon dioxide. A conductive material is embedded in the recesses on the surface of the gate dielectric film GD, so that the word lines WL1, WL2, ...
WLn is formed. In this example, the odd-numbered word lines WL1, WL3, ... Have a first shape and the even-numbered word lines WL2, WL4 ,.

Outside the word line WL1, the control gate line SG1 separated by the sidewall SW is arranged in parallel. Similarly, the control gate lines SG2 separated by the sidewalls SW are arranged in parallel outside the word lines WLn. These control gate lines SG1 and S
In FIG. 41A, G2 is in contact with the semiconductor substrate SUB via the gate dielectric film GD, but no charge is injected into this portion of the gate dielectric film GD due to the applied bias condition. Although the manufacturing process is slightly complicated, it is advisable to form a single-layer gate dielectric film only in this portion and make the select transistor a normal MOS type.

With respect to such a wiring structure, N is formed only in the substrate portion centered on the region below the sidewall SW.
Source / drain regions S / D formed of type impurity regions are formed. The source / drain regions S / D are discretely formed only between the word lines or between the word lines and the control gate lines, and the lateral direction in FIG. 40 is separated by an element isolation layer (eg, LOCOS) not shown. ing. A drain region DR made of an N-type impurity region is formed outside the control gate line SG1. The drain region DR is shared with another NAND string (not shown). Further, outside the control gate line SG2,
A common source line CSL made of an N-type impurity region is formed. The common source line CSL is shared within one row of NAND strings arranged in the word direction and with another one row of NAND strings (not shown) adjacent in the bit direction.

An interlayer insulating film INT is formed on the transistors forming these NAND strings. Bit lines BL1 and BL2 are arranged in parallel stripes on the interlayer insulating film INT. Each bit line is connected to the corresponding drain region DR by the bit contact BC formed in the interlayer insulating film INT.

Next, the procedure for forming this NOR type memory cell array will be described with reference to the drawings. 42 to 49 are cross-sectional views (and plan views) at each step of word line formation. 42, 44, 45, 47
49A shows a plan view and FIG. 49B shows a cross-sectional view taken along the line AA of FIG. All the other drawings represent sectional views taken along the line AA.

First, if necessary, an element isolation layer is provided on the semiconductor substrate SUB, and ion implantation for adjusting the threshold voltage is performed.

As shown in FIG. 42A, a plurality of sacrificial layers 30 made of a dielectric material are formed in a parallel stripe pattern.
Are formed on the substrate SUB. The plurality of sacrificial layers 30 are formed in stripes parallel to each other at a pitch that is approximately twice the pitch of the word line to be formed. As shown in FIG. 43, a dielectric film 3 of a different material is deposited so as to cover the sacrifice layer 30.
A material having a high etching selection ratio with respect to the sacrificial layer 30 is selected as the material of the dielectric film 3. For example, the sacrificial layer 30
Is a silicon nitride film and the dielectric film 3 is a silicon dioxide film.
Further, since a part of the dielectric film 3 finally remains as a sidewall, the material and the forming method are selected in consideration of the quality of the film and the insulating property.

Subsequently, the dielectric film 3 is etched back by anisotropic etching. Thereby, as shown in FIGS. 44A and 44B, the sidewall SW is formed on the side surface of the sacrifice layer 30. The width of the sidewall SW is mainly determined by the height of the sacrificial layer 30 and the anisotropic etching conditions. However, when the anisotropy is strong to some extent, the sidewall width does not change much even if the etching time varies to some extent, and thus the uniformity is relatively high.

After that, the sacrifice layer 30 is selectively removed by a predetermined method. For example, in the case of removing the sacrificial layer 3 from silicon nitride, a wet process using an etchant containing phosphoric acid (H ₃ PO ₄ ) is performed. As a result, FIG.
As shown in FIGS. 45A and 45B, the sidewall SW is left.

As shown in FIG. 46, the sidewall SW
A conductive film 4 for completely filling the film is deposited, for example, a film of metal, doped polycrystalline silicon or doped amorphous silicon. After that, the surface of the conductive film 4 is ground and / or polished by, for example, the CMP method or another method. This grinding and / or polishing is performed until the conductive film 4 is separated into a plurality when the sidewall SW is exposed, and then the separation distance becomes a required value. As a result, FIG.
(A) and FIG. 47 (B), the plurality of word lines WL1, WL2, ..., WLn and the control gate line SG separated by the sidewall SW at a necessary distance.
1, SG2 are formed. Note that this grinding and / or polishing is desirably performed until the charge trap film CHS is completely divided into word lines. However, when the charge storage film is an FG type which is a conductive material, the division of the charge storage film is essential. This is because if the floating gate FG is connected at this location, the accumulated charge leaks to the adjacent cell, making it impossible to store data. Also,
In order to avoid the electric field concentration at this portion, it is necessary to perform sufficient grinding and / or polishing.

As shown in FIG. 48, the control gate line SG
1, SG2 have a predetermined line width so that the word line W
, WLn and control gate lines SG1,
A mask layer that covers a portion of SG2 is formed and etched to selectively remove the peripheral portion of the mask layer. After removing the mask layer, N-type impurities are ion-implanted into the semiconductor substrate SUB. At this time, the ion implantation conditions are determined so that the ions do not permeate in the wiring layer portion but the ions permeate in the sidewall portion and reach the substrate. As a result, the source / drain region S / D, the drain region DR, and the common source line CSL are simultaneously formed. At this time, the element isolation layer formed in advance also functions as a mask during ion implantation. The source / drain region S having a desired concentration and depth can be obtained only by optimizing the ion implantation conditions.
If it is difficult to form / D, temporarily switch the sidewall SW
May be removed, and the dielectric material may be embedded again in the sidewall-shaped space after the ion implantation.

After that, the nonvolatile memory is completed by depositing an interlayer insulating film INT, forming a bit contact BC, and forming a bit line.

[Tenth Embodiment] The tenth embodiment shows a first modification of the word line formation of the nonvolatile memory. 50 (A) to 50 (C) and 51 (A) to 51
(D) is a cross-sectional view in the line width direction centering on the word line portion. This embodiment can be applied to any of the memory cell array systems of the eighth and ninth embodiments.

In the wiring isolation structure of the tenth embodiment, as shown in FIG. 51D, in addition to the sidewall SW, the gate dielectric film GD and the side of the first shape word lines WL2, WL4, ... The thin thermal oxide film 10 is interposed between the wall SW and the wall SW, which is different from the eighth and ninth embodiments. Thermal oxide film 10 is obtained by thermally oxidizing the surface of doped polycrystalline silicon or doped amorphous silicon. Therefore, the controllability of the film thickness is extremely high, and the film quality is good because it is silicon dioxide obtained by thermal oxidation. Therefore, there is an advantage that the insulating characteristic between the wirings is improved.

In the formation of this wiring structure, first, as shown in FIG.
As shown in (A), the sacrificial layer 40 is formed on the substrate SUB at a pitch almost twice that of the final wiring. This sacrificial layer 4
0 is formed of doped polycrystalline silicon or doped amorphous silicon. As shown in FIG. 50B, the surface of the sacrificial layer 40 is thermally oxidized to form the thermal oxide film 10 made of silicon dioxide having a thickness of several nm to several tens nm. Instead of thermal oxidation,
Nitriding treatment or oxynitriding treatment by heating may be performed.

After that, as in the eighth and ninth embodiments,
Dielectric film 3 is deposited (FIG. 50 (C)) and is etched back to form sidewall SW (FIG. 51).
(A)). Further, after exposing the upper surface of the sacrificial layer 40, the sacrificial layer 40 is selectively removed (FIG. 51B), and the conductive film 4 is formed.
Is deposited (FIG. 51C), and this is ground and / or polished to form a plurality of word lines WL1 to WL5 (FIG. 51D).

In the tenth embodiment, the insulation characteristics of the inter-word line dielectric can be effectively improved only by performing the process such as thermal oxidation. Since the sacrificial layer 40 is made of a conductive material unlike the sidewalls, there is an advantage that selective etching is easy.

[Eleventh Embodiment] The eleventh embodiment shows a second modification of the word line formation of the nonvolatile memory. 52 (A) to 52 (C) and 53 (A) to 53
(C) is a cross-sectional view in the line width direction centering on the word line portion. This embodiment can be applied to any of the memory cell array systems of the eighth and ninth embodiments.

In the wiring isolation structure of the eleventh embodiment, as shown in FIG. 53C, the word lines WL2, WL4 of the first shape are used as the dielectric film having the charge storage ability.
... and the substrate SUB, the sidewall SW and the substrate SU
B has a first gate dielectric film GD1 and a second gate dielectric film GD2 existing between the second shape word lines WL1, WL3, ... And the substrate SUB.
Further, a thin thermal oxide film 10 is interposed between the first shape word lines WL2, WL4, ... And the sidewall SW. These points are different from the eighth and ninth embodiments. The first gate dielectric film GD1 and the second gate dielectric film GD2 have the same film structure specifications. Thermal oxide film 10
When the first shape word lines WL2, WL4, ... Are made of doped polycrystalline silicon or doped amorphous silicon,
It is obtained by thermally oxidizing the surface. Therefore, the controllability of the film thickness is extremely high, and the film quality is good because it is silicon dioxide obtained by thermal oxidation. Therefore, there is an advantage that the insulating characteristic between the wirings is improved.

In forming this wiring structure, first, as shown in FIG.
As shown in (A), a first gate dielectric film GD1 is formed on a substrate SUB, and a first shape word line WL is formed thereon.
2, WL4, ... Are formed at a pitch that is approximately twice the final pitch. The first shape word lines WL2, WL4, ...
Is formed of doped polycrystalline silicon or doped amorphous silicon. As shown in FIG. 52B, the surfaces of the first shape word lines WL2, WL4, ... Are thermally oxidized to form a thermal oxide film 10 made of silicon dioxide and having a thickness of several nm to several tens of nm. Note that nitriding treatment or oxynitriding treatment by heating may be performed instead of thermal oxidation.

After that, as in the eighth and ninth embodiments,
Dielectric film 3 is deposited (FIG. 52C), and this is etched back to form sidewall SW (FIG. 53).
(A)).

Here, in the eleventh embodiment, FIG.
As shown in (A), the first shape word lines WL2, WL
, And the sidewall SW are used as a mask to remove the first gate dielectric film GD1 around the mask. afterwards,
After forming the second gate dielectric film GD2 on the entire surface, a conductive film 4 is deposited (FIG. 53 (B)), and this is ground and / or polished to form a plurality of word lines WL1 to WL5 (FIG. 53B). 53 (C)).

In the eleventh embodiment, the insulation characteristics of the inter-word line dielectric can be effectively improved only by performing the process such as thermal oxidation. Further, although steps for partially removing and re-forming the gate dielectric film are added, the number of steps does not change greatly because the word line of the first shape is not removed.

[0138]

According to the semiconductor device of the present invention, the distance between wirings such as word lines of a semiconductor memory device can be made much smaller than the wiring width, exceeding the limit of photolithography, and as a result, useless space is saved. Has been reduced. In particular, when this wiring isolation structure is applied to the isolation between word lines of a memory cell array, the dimension of each memory cell in the column direction can be significantly reduced, and the bit cost is greatly reduced accordingly. Further, the electrodes can be taken out even though the word line pitch is narrow.

In the method of manufacturing a semiconductor device according to the present invention,
The wiring isolation structure described above can be easily formed by using ordinary photolithography technology and etching technology without using a special process.

The distance between the wirings is defined by the dielectric film thickness and / or the width of the sidewall type dielectric. Dielectric films can be controlled with very high precision, as is well known. Further, the width of the sidewall-shaped dielectric can be controlled by the height of the sacrificial layer or the wiring of the first shape and the etching conditions of the dielectric. Etching during formation of the sidewall-type dielectric is usually performed under highly anisotropic conditions.
Even if the etching time varies a little, the variation in the sidewall width is small. Therefore, the width uniformity of the sidewall dielectric is relatively high. Further, even when a dielectric film is interposed in addition to the sidewall type dielectric, the width is extremely uniform because it is determined by the film thickness. From the above, the variation in the distance between the wirings is quite small.

Further, in the manufacturing method according to the present invention, the introduction of substrate damage and the etching of the first word line can be suppressed as much as possible. By introducing substrate surface etching,
The film thickness variation of the charge storage film caused by forming the word line and the second word line twice is effectively suppressed, and the characteristic variation is prevented. Further, the method has an electric isolation (residue removal) step of the second word lines, and as a result, it is possible to maintain the insulation isolation characteristics between the word lines at a high level by minimizing overetching when forming the second word lines. In addition, it is possible to suppress or prevent a leak current particularly at the time of reading.

[Brief description of drawings]

FIG. 1 is a plan view and a cross-sectional view showing a configuration of a semiconductor memory device having a VG type memory cell array according to a first embodiment.

FIG. 2 is a cross-sectional view after formation of the first word line in the manufacturing of the semiconductor memory device according to the first embodiment.

FIG. 3 is a cross-sectional view at the time of etching a substrate in manufacturing the semiconductor memory device according to the first embodiment.

FIG. 4 is a cross-sectional view after the second gate dielectric film is formed in the manufacturing of the semiconductor memory device according to the first embodiment.

FIG. 5 is a cross-sectional view after forming a resist pattern for a processing mask of a second word line in the manufacturing of the semiconductor memory device according to the first embodiment.

FIG. 6 is a plan view showing a configuration of a semiconductor memory device having a NAND type memory cell array according to a second embodiment.

FIG. 7 is a cross-sectional view showing a configuration of a semiconductor memory device having a NAND memory cell array according to the second embodiment and an enlarged view thereof.

FIG. 8 is a cross-sectional view after formation of a first word line in the manufacturing of the semiconductor memory device according to the second embodiment.

FIG. 9 is a cross-sectional view at the time of etching a substrate in manufacturing the semiconductor memory device according to the second embodiment.

FIG. 10 is a cross-sectional view after the second gate dielectric film is formed in the manufacturing of the semiconductor memory device according to the second embodiment.

FIG. 11 is a cross-sectional view after forming a resist pattern for a processing mask of a second word line in manufacturing the semiconductor memory device according to the second embodiment.

FIG. 12 is an RTN for explaining the necessity of substrate etching in the manufacturing method according to the first and second embodiments.
7 is a graph showing the measurement results when the change in film thickness of the thermal oxide film due to the presence or absence of is examined.

FIG. 13 is a cross-sectional view after patterning the first word line in the manufacture of the nonvolatile memory device according to the third embodiment.

FIG. 14 is a cross-sectional view after forming a thermal oxide film in the manufacture of the nonvolatile memory device according to the third embodiment.

FIG. 15 is a cross-sectional view after formation of a thermal oxide film in the manufacture of the nonvolatile memory device according to the third embodiment.

16A and 16B are a cross-sectional view and a plan view showing the problems of the first to third embodiments to be solved in manufacturing the nonvolatile memory device according to the fourth embodiment.

FIG. 17 is a diagram showing a plane pattern of word lines around a memory cell array in the nonvolatile semiconductor memory device according to the fourth embodiment.

FIG. 18 is a plan view of a word line pattern of a non-volatile memory device showing a residue removal portion in a first method for preventing leakage according to a fifth embodiment.

FIG. 19 is a cross-sectional view of the nonvolatile memory device taken along the line AA of FIG. 18, showing a state after removing the residue using the first method for preventing leakage according to the fifth embodiment.

FIG. 20 is a plan view of a word line pattern of a non-volatile memory device when the second method of leak prevention according to the fifth embodiment is applied.

FIG. 21 is a diagram showing a configuration of a non-volatile memory device to which a third method of leak prevention according to the fifth embodiment is applied.

FIG. 22 is a plan view and a cross-sectional view taken along the line AA showing the wiring structure of the semiconductor device according to the sixth embodiment.

FIG. 23 is a plan view after formation of a sacrifice layer and a cross-sectional view taken along the line AA in the manufacturing of the semiconductor device according to the sixth embodiment.

FIG. 24 is a cross-sectional view after dielectric deposition in the manufacturing of the semiconductor device according to the sixth embodiment.

FIG. 25 is a plan view after formation of a sidewall and a cross-sectional view taken along the line AA in the manufacturing of the semiconductor device according to the sixth embodiment.

FIG. 26 is a plan view after removing a sacrifice layer and a cross-sectional view taken along the line AA in the manufacturing of the semiconductor device according to the sixth embodiment.

FIG. 27 is a cross-sectional view after a conductive film is deposited in the manufacturing of the semiconductor device according to the sixth embodiment.

FIG. 28 is a cross-sectional view after the formation of the first shape wiring in the manufacturing of the semiconductor device according to the seventh embodiment.

FIG. 29 is a cross-sectional view after forming a thermal oxide film in the manufacturing of the semiconductor device according to the seventh embodiment.

FIG. 30 is a cross-sectional view after dielectric deposition in the manufacturing of the semiconductor device according to the seventh embodiment.

FIG. 31 is a sectional view after formation of sidewalls in the manufacturing of the semiconductor device according to the seventh embodiment.

FIG. 32 is a cross-sectional view after depositing a conductive film in the manufacturing of the semiconductor device according to the seventh embodiment.

FIG. 33 is a cross-sectional view showing the wiring structure of the semiconductor device according to the seventh embodiment.

FIG. 34 is a plan view of a NOR type memory cell array according to an eighth embodiment and a cross-sectional view taken along line AA and line BB.

FIG. 35 is a plan view after formation of a sacrifice layer and a cross-sectional view taken along the line AA in the manufacture of the semiconductor device according to the eighth embodiment.

FIG. 36 is a cross-sectional view after dielectric deposition in the manufacturing of the semiconductor device according to the eighth embodiment.

37A and 37B are a plan view and a cross-sectional view taken along the line AA after formation of sidewalls in the manufacturing of the semiconductor device according to the eighth embodiment.

38A and 38B are a plan view and a cross-sectional view taken along the line AA after the sacrifice layer is removed in the manufacturing of the semiconductor device according to the eighth embodiment.

FIG. 39 is a cross-sectional view after the conductive film is deposited in the manufacturing of the semiconductor device according to the eighth embodiment.

FIG. 40 is a plan view of a NAND memory cell array according to a ninth embodiment.

FIG. 41 is a cross-sectional view taken along the line AA of the NAND memory cell array according to the ninth embodiment and a partially enlarged view thereof.

42A and 42B are a plan view and a cross-sectional view taken along the line AA after the sacrifice layer is formed in the manufacturing of the semiconductor device according to the ninth embodiment.

FIG. 43 is a cross-sectional view after dielectric deposition in the manufacturing of the semiconductor device according to the ninth embodiment.

44A and 44B are a plan view and a cross-sectional view taken along the line AA after formation of sidewalls in the manufacturing of the semiconductor device according to the ninth embodiment.

FIG. 45 is a plan view after removal of a sacrifice layer and a cross-sectional view taken along the line AA in the manufacturing of the semiconductor device according to the ninth embodiment.

FIG. 46 is a cross-sectional view after depositing a conductive film in the manufacturing of the semiconductor device according to the ninth embodiment.

47A and 47B are a plan view after formation of word lines and a cross-sectional view taken along the line AA in the manufacture of the semiconductor device according to the ninth embodiment.

FIG. 48 is a cross-sectional view after processing a select gate line in manufacturing the semiconductor device according to the ninth embodiment.

FIG. 49 is a plan view after formation of source / drain regions and a cross-sectional view taken along the line AA in the manufacturing of the semiconductor device according to the ninth embodiment.

FIG. 50 is a sectional view showing the process up to dielectric deposition in the manufacturing of the semiconductor device according to the tenth embodiment.

FIG. 51 is a cross-sectional view showing the formation of word lines in the manufacturing of the semiconductor device according to the tenth embodiment.

FIG. 52 is a cross-sectional view showing the steps up to dielectric deposition in the manufacturing of the semiconductor device according to the eleventh embodiment.

FIG. 53 is a cross-sectional view showing the formation of word lines in the manufacturing of the semiconductor device according to the eleventh embodiment.

[Explanation of symbols]

SUB ... Substrate (semiconductor), WL1, etc .... Word line, PAD
1 etc .... Electrode extraction portion, WLF ... Conductive film to be word line, BL1 etc .... Bit line, S / D ... Source / drain regions, GD, GD1, GD2 ... Gate dielectric film (charge storage film, first or first) 2 charge storage film), BTM ... bottom dielectric film, CHS ... charge trap film, TOP ... top dielectric film, SG1, SG2 ... Select gate line, DR ... Drain region, CSL ... Common source line, BC ... Bit contact,
INT ... interlayer insulation film, 1 ... dielectric, 2, 20, 30, 4
0 ... Sacrificial layer, 3 ... Dielectric film, 4 ... Conductive film, 50 ... Row decoder, 51 ... Word line drive circuit (second word line drive circuit), 52 ... Word line drive circuit (first word line drive) Circuit), TOX, 10 ... Thermal oxide film, SW ... Side wall type dielectric, TL1, IL2 ... Wiring

   ─────────────────────────────────────────────────── ─── Continued front page    (31) Priority claim number Japanese Patent Application 2001-285100 (P2001-285100) (32) Priority date September 19, 2001 (September 19, 2001) (33) Priority claiming country Japan (JP) (72) Inventor Ichiro Fujiwara             6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Soni             -Inside the corporation (72) Inventor Toshio Terano             6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Soni             -Inside the corporation (72) Inventor Toshio Kobayashi             6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Soni             -Inside the corporation F term (reference) 5F083 EP18 EP22 EP76 EP77 ER02                       GA09 JA04 KA01 LA16 PR05                       PR12 PR16                 5F101 BA45 BB02 BC01 BD02 BD10                       BD22 BD32 BD33 BD34 BH03                       BH06 BH15

Claims (41)

[Claims] 1. A plurality of memory transistors arranged in a matrix and also serving as gate electrodes of memory transistors in the same row,
A plurality of word lines that are long in the row direction and are repeatedly arranged at intervals in the column direction, and two word lines that are adjacent to each other in the column direction among the plurality of word lines have a dimension in the separating direction that is a film thickness. Device separated by a dielectric film interposed so as to be. 2. The semiconductor device according to claim 1, wherein the dielectric film is a charge storage film composed of a plurality of dielectric films and having a charge retaining ability. 3. The dielectric film includes a charge storage film composed of a plurality of dielectric films and having a charge storage capability, and a thermal oxide film formed on the surface of every other one of the word lines. The semiconductor device according to claim 1. 4. A first charge storage film composed of a plurality of dielectric films and having a charge storage capability, and a first charge storage film formed on a semiconductor in parallel with each other with a predetermined space therebetween. A first charge storage film, a second charge storage film that covers the surface of the first word line and the surface of the semiconductor exposed between the first word lines and that is composed of a plurality of dielectric films and has a charge storage capability; A dielectric that faces the surface of the semiconductor exposed between the word lines with the second charge storage film interposed therebetween, and includes the second charge storage film and is interposed so that the distance from the first word line is the film thickness. 2. The semiconductor device according to claim 1, wherein the semiconductor device has a first word line and a second word line insulated and separated by a film. 5. A method according to claim 4, wherein at least one of both ends of the second word line in the width direction is overlaid on the end of the first word line in the width direction with the dielectric film interposed. The semiconductor device described. 6. The first word line and the second word line,
5. The semiconductor device according to claim 4, wherein the semiconductor device extends outward from the memory cell array region, is bent in a direction different from the wiring direction of the word line, and the pitch between the first word line and the second word line is relaxed on the tip side of the bent portion. . 7. The first word line and the second word line are:
7. The semiconductor device according to claim 6, wherein each of the end portions on the side where the pitch is relaxed has an electrode lead-out portion. 8. The semiconductor device according to claim 7, wherein the electrode lead-out portion of the first word line is arranged outside the electrode lead-out portion of the second word line. 9. An end portion provided with the electrode lead-out portion,
8. The semiconductor device according to claim 7, wherein an end of the first word line is arranged outside an end of the second word line at both ends on the opposite side. 10. The semiconductor device according to claim 4, wherein the number of the second word lines is one more than the number of the first word lines. 11. A predetermined voltage which is connected to at least one of the outermost second word lines and which always turns off the channel regardless of the amount of charge stored in the second charge storage film below the second word line, or A first word line drive circuit for injecting a sufficient amount of charges into the second charge storage film to apply a voltage for always turning off the channel, and another first or second word line connected to the first word line drive circuit. Alternatively, the channel is turned on or off in accordance with a voltage suitable for inputting / outputting charges to / from the first or second charge storage film below the second word line, or according to the amount of charge stored in the first or second charge storage film. 11. The semiconductor device according to claim 10, further comprising a second word line drive circuit for controlling a voltage suitable for the above based on the input row address signal. 12. A semiconductor device comprising: a plurality of memory transistors arranged in a matrix on a semiconductor; and a plurality of word lines long in a row direction and repeatedly arranged in a column direction, serving as gate electrodes of the memory transistors in the same row. A method of manufacturing a semiconductor device in which two adjacent word lines are separated by an intervening dielectric film so that the dimension in the direction of separation is the film thickness, and the word line is composed of a plurality of dielectric films. Forming a laminated pattern of the first charge storage film having the above and the first word line on the semiconductor in parallel at a predetermined interval, and the semiconductor exposed between the surface of the first word line and the first word line. Forming a second charge storage film composed of a plurality of dielectric films and having a charge storage capability on the region, and at least a part of each of the first word lines is provided with a second charge in a space between the first word lines. Accumulation film Method of manufacturing a semiconductor device and forming a second word line embedded in a state of being interposed. 13. The method of manufacturing a semiconductor device according to claim 12, further comprising the step of thermally oxidizing the surface of the first word line. 14. The step of forming the laminated pattern comprises the step of patterning the first word lines, the step of thermally oxidizing the surface of the first word lines, and the first charge accumulation between the first word lines. The method of manufacturing a semiconductor device according to claim 13, further comprising the step of removing the film. 15. The first charge storage film is removed and then the first charge storage film is removed.
15. The method of manufacturing a semiconductor device according to claim 14, wherein the thickness of the thermal oxide film and the etching conditions for the first charge storage film are set so that the thermal oxide film remains on the surface of the word line. 16. The method of manufacturing a semiconductor device according to claim 12, further comprising the step of etching the semiconductor surface region exposed between the first word lines. 17. A step of forming a bottom dielectric film by thermally oxidizing a surface of a semiconductor in each of the steps of forming the first charge storage film and the second charge storage film; and nitriding the bottom dielectric film, Or a step of forming a nitride film on the bottom dielectric film, wherein the step of forming the first word line includes the step of forming the first charge storage film on the semiconductor made of single crystal silicon; A step of forming a conductive film which is made of polycrystalline silicon or amorphous silicon and serves as a first word line on one charge storage film, and the conductive film and the first charge storage film are continuously etched in the same pattern The method for manufacturing a semiconductor device according to claim 16, further comprising: 18. The etching of the semiconductor surface region comprises:
18. The surface layer of single crystal silicon consumed during sacrificial oxidation is removed by forming a sacrificial oxide film on the single crystal silicon exposed between the first word lines and removing the sacrificial oxide film.
A method for manufacturing a semiconductor device as described above. 19. The first word line is formed after the second word line is formed.
Selectively for at least one end of the word line,
13. The method of manufacturing a semiconductor device according to claim 12, further comprising the step of performing over-etching under the condition that the material of the second word line is removed. 20. In the step of forming the first word line, a pattern is arranged in which an end portion of the first word line for which the over-etching is performed is located outside a place where an end portion of the second word line is to be located. 20. The method of manufacturing a semiconductor device according to claim 19, wherein a photomask is used. 21. In the over-etching step, a mask layer is formed to protect the second word line and open the end of the first word line located outside the end of the second word line. 21. The method of manufacturing a semiconductor device according to claim 20, wherein the second word line forming material is selectively removed by over-etching through the opening of the mask layer. 22. In the step of forming the first and second word lines, the first and second word lines extend outside the memory cell array and bend in a direction different from the wiring direction of the word lines,
The pitch between the first word line and the second word line is relaxed on the tip side of the bent portion, and the electrode lead-out portion is provided at each end on the side where the pitch is relaxed, and the electrode of the first word line 20. The method of manufacturing a semiconductor device according to claim 19, wherein a photomask having a required pattern is used because the extraction portion is arranged outside the electrode extraction portion of the second word line. 23. When the outermost first word line is present, after forming the second word line, a mask layer is formed to open around the outer sidewall of the outermost first word. And a step of selectively performing overetching on the periphery of the sidewall of the outermost first word line through the opening of the mask layer under the condition that the material of the second word line is selectively removed. 13. The method for manufacturing a semiconductor device according to claim 12, further comprising: 24. A semiconductor device having a plurality of wirings arranged in parallel to each other, wherein adjacent wirings are separated by a dielectric, wherein the dielectric between the wirings is composed of two adjacent wirings. A semiconductor device made of a sidewall-shaped dielectric formed on one side surface. 25. The cross-sectional shape of the plurality of wirings in the width direction is
25. The semiconductor device according to claim 24, wherein two adjacent wirings are different from each other. 26. The plurality of wirings have a vertical side surface or a forward taper cross-sectional shape, and a first shape wiring in which the sidewall-shaped dielectric is formed on two side surfaces, and a first shape. A second shape wiring adjacent to both sides in the width direction of the wiring and having at least an upper end portion having a reverse taper, and the reverse taper shape of the second shape wiring reflects the shape of the sidewall-shaped dielectric. 26. The semiconductor device according to claim 25, wherein the formed wirings and the wirings of the second shape are alternately arranged. 27. A semiconductor device having a plurality of wirings arranged in parallel to each other, wherein adjacent wirings are separated by a dielectric, wherein the dielectric between the wirings comprises two adjacent wirings. A semiconductor including a sidewall-type dielectric formed on one side surface and a dielectric film interposed between the sidewall-type dielectric and the wiring so that the dimension in the direction of separation between them becomes a film thickness. apparatus. 28. A plurality of memory transistors arranged in a matrix also serve as gate electrodes of the memory transistors in the same row,
A plurality of word lines that are long in the row direction and repeated in the column direction, and two adjacent word lines have a sidewall-shaped dielectric formed on the side surface of one of the word lines and a sidewall-shaped dielectric. 28. The semiconductor device according to claim 27, wherein the dielectric and the word line are separated from each other by a dielectric film interposed so that the dimension in the direction of separation between the dielectric and the word line becomes a film thickness. 29. The plurality of word lines have a vertical side surface or a forward tapered cross-sectional shape, and the sidewall-shaped dielectric is formed on two side surfaces, and a first shape word line, A second shape word line that is adjacent to both sides in the width direction of the first shape word line and has at least an upper end portion having a reverse taper, and the reverse taper shape of the second shape word line is a sidewall type dielectric 29. The semiconductor device according to claim 28, wherein the first-shape word lines and the second-shape word lines are formed to reflect the shape and are alternately arranged in the column direction. 30. Between the first shape word line and the semiconductor, between the second shape word line and the semiconductor, between the first shape word line and the sidewall dielectric, and 30. The semiconductor device according to claim 29, wherein a gate dielectric film including charge storage means is formed inside between the second-shaped word line and the sidewall-shaped dielectric. 31. The semiconductor device according to claim 30, wherein a thermal oxide film is formed between the gate dielectric film on the word line side of the first shape and the sidewall type dielectric. 32. The semiconductor device according to claim 30, wherein the charge storage means is spatially discretized in the gate dielectric film. 33. A method of manufacturing a semiconductor device having a plurality of wirings arranged in parallel with each other, wherein two adjacent wirings are separated by a dielectric, wherein a plurality of sacrificial layers are parallel to each other at regular intervals. A step of forming a sidewall type spacer on two side surfaces of the sacrificial layer, a step of removing the sacrificial layer, and a step of depositing a conductive film so as to fill the space between the sidewall type spacers. A step of shaving the conductive film from the surface to form the plurality of wiring layers separated by the sidewall-shaped spacers. 34. A method of manufacturing a semiconductor device, comprising a plurality of wirings arranged in parallel with each other, wherein two adjacent wirings are separated by a dielectric, wherein a plurality of first wirings are arranged at regular intervals. The steps of forming in parallel, the steps of forming sidewall-shaped spacers on the two side surfaces of the first wiring, the step of depositing a conductive film so as to fill up the space between the sidewall-shaped spacers, and the conductive film being removed from the surface. And forming a plurality of second wirings separated from the first wirings by the sidewall type spacers in the space between the first wirings. 35. The method of manufacturing a semiconductor device according to claim 34, further comprising the step of thermally oxidizing the surface of said first wiring to form a dielectric film. 36. A plurality of memory transistors arranged in a matrix on a semiconductor, and a plurality of word lines which are long in the row direction and are repeated in the column direction and which also serve as gate electrodes of the memory transistors in the same row. Manufacture of a semiconductor device in which two adjacent word lines are separated by a sidewall spacer formed on the side surface of one of the word lines and a dielectric film formed on the surface of the sidewall spacer. A method of forming a plurality of sacrificial layers on a semiconductor at regular intervals in parallel with each other, forming sidewall-shaped spacers on two side surfaces of the sacrificial layer, and removing the sacrificial layer, A process of forming a gate dielectric film including charge storage means inside thereof on the surface of the sidewall spacer and on the semiconductor region exposed between the sidewall spacers. And a step of depositing a conductive film so as to fill the recesses on the surface of the gate dielectric film, removing the conductive film from the surface, and removing the plurality of word lines separated by the sidewall spacers and the gate dielectric film. A method of manufacturing a semiconductor device, the method including the step of forming. 37. The method of manufacturing a semiconductor device according to claim 36, wherein the charge storage means is spatially discretely formed in the gate dielectric film when the gate dielectric film is formed. 38. A plurality of memory transistors arranged in a matrix on a semiconductor, and a plurality of word lines which are long in the row direction and are repeated in the column direction and which also serve as gate electrodes of the memory transistors in the same row. Manufacture of a semiconductor device in which two adjacent word lines are separated by a sidewall spacer formed on the side surface of one of the word lines and a dielectric film formed on the surface of the sidewall spacer. A method of forming a plurality of laminated films, each of which is composed of a gate dielectric film including a charge storage means inside and a first conductive film, on the semiconductor at a constant interval in parallel with each other; The process of forming the sidewall type spacer on one side surface and the inside of the semiconductor region exposed on the surface of the sidewall type spacer and between the sidewall type spacers A step of re-forming a gate dielectric film including a charge storage means, a step of depositing a second conductive film so as to fill a recess in the surface of the gate dielectric film, and a step of removing the second conductive film from the surface to And a step of forming the plurality of word lines separated by a wall-shaped spacer and a gate dielectric film. 39. The method of manufacturing a semiconductor device according to claim 38, further comprising the step of thermally oxidizing the surface of said first conductive film to form a dielectric film. 40. A plurality of memory transistors arranged in a matrix on a semiconductor, and a plurality of word lines which are long in the row direction and are repeated in the column direction and which also serve as gate electrodes of the memory transistors in the same row. Manufacture of a semiconductor device in which two adjacent word lines are separated by a sidewall spacer formed on the side surface of one of the word lines and a dielectric film formed on the surface of the sidewall spacer. A method of forming a gate dielectric film having charge storage means inside thereof on the semiconductor, and a plurality of conductive layers made of a first conductive film are parallel to each other at regular intervals. Step of forming above, step of forming sidewall type spacers on two side surfaces of a plurality of conductive layers, etching using the conductive layer and sidewall type spacers as a mask By removing the gate dielectric film portion between the sidewall-shaped spacers, and on the surface of the conductive layer, on the surface of the sidewall-shaped spacer and on the semiconductor region exposed between the sidewall-shaped spacers, A step of re-forming a gate dielectric film including a charge storage means, a step of depositing a second conductive film so as to fill a recess in the surface of the gate dielectric film, and a step of scraping the second conductive film from the surface,
A method of manufacturing a semiconductor device, comprising the step of forming a plurality of word lines separated by a sidewall spacer and a gate dielectric film. 41. The method of manufacturing a semiconductor device according to claim 40, further comprising the step of thermally oxidizing the surface of said conductive layer to form a dielectric film.