JP2005149617A - Nonvolatile semiconductor memory device and its operation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of the difficulty of reducing an erasure voltage which obstructs the realization of single power voltage driving. <P>SOLUTION: The intial value V0 of data is stored in the memory cell group of arbitrary M bits in storage areas B0 to B10 having a capacity of (N+1) multiple, e.g., 11 times larger, of the bit number M necessary for data storage. When a data rewriting is instructed, instead of erasing the initial value V10 and writing a new data value in the same memory cell, the unused other memory cell group of M bits is selected to write a new data value V1. By executing this operation for each data rewriting instruction, the writing of new data values V1 to V10 is executed up to 10 times. When reading, by reading a latest value, data rewriting not using erasure is executed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a nonvolatile semiconductor memory device in which the number of rewrites of data stored in a memory cell array is determined to be N (N: a positive integer) at maximum, and an operation method thereof.

  Non-volatile semiconductor memory transistors can be broadly divided into FG (Floating Gate) type, in which charge storage means (floating gate) for holding charge is continuous in a plane, and charge storage means (charge trap, etc.) are made discrete in a plane. For example, there is a MONOS (Metal-Oxide-Nitride-Oxide Semiconductor) type.

  In the FG type nonvolatile memory transistor, a first dielectric film, a floating gate FG made of polysilicon or the like, for example, an ONO (Oxide-Nitride-Oxide) film or the like is formed on a semiconductor substrate or well. The body film and the control gate are stacked in this order.

In the MONOS type nonvolatile memory transistor, a bottom dielectric film on a semiconductor substrate or well, a nitride film mainly responsible for charge accumulation [Si _x N _y (0 <x <1, 0 <y <1) ], A top dielectric film and a gate electrode are sequentially laminated.
In the MONOS type nonvolatile memory transistor, carrier traps as charge storage means are spatially discrete (that is, in the plane direction and the film thickness direction) in the nitride film or in the vicinity of the interface between the top dielectric film and the nitride film. Is spreading. For this reason, the charge retention characteristics depend on the energy and spatial distribution of charges trapped in carrier traps in the nitride film, in addition to the thickness of the bottom dielectric film.

  When a local leakage current path occurs in the bottom dielectric film due to a defect or the like, in the FG type memory transistor, most of the accumulated charge leaks to the substrate side through the leakage path and holds the charge. Characteristics are likely to deteriorate. On the other hand, in the MONOS type memory transistor, since the charge storage means is spatially discretized, the local stored charge around the leak path only leaks locally through the leak path, and the charge of the entire memory transistor Retention characteristics are unlikely to deteriorate. For this reason, in the MONOS type memory transistor, the problem of deterioration of the charge retention characteristic due to the thinning of the bottom dielectric film is not as serious as the FG type memory transistor.

  Nonvolatile memory devices are roughly classified into a stand-alone type and a logic circuit mixed type. In the stand-alone type, a nonvolatile memory transistor is used as a memory element of a dedicated memory IC. In the logic circuit mixed type, a memory block and a logic circuit block are provided as a system-on-chip core, and a nonvolatile memory transistor is used as a memory element that holds data in a nonvolatile manner in the memory block.

In many of the logic circuit mixed nonvolatile memory devices, one memory transistor type memory cell is used.
As a representative example of one memory transistor cell in the FG type, an Intel ETOX cell is known. When the ETOX cells are arranged in an array, a common source type memory cell array system sharing a source is adopted.
One memory transistor cell of the MONOS type is attracting attention because the cell area can be reduced and the voltage can be easily reduced. As a representative example, a high-density memory cell called NROM of Saifan Semiconductor is known. Since the NROM cell uses a discrete carrier trap as a charge storage means, it is possible to store data of 2 bits / cell by injecting charges into two different regions in the cell. When arranging NROM cells in an array, a virtual ground array method is used in which an impurity diffusion layer is shared between adjacent cells in the row direction, and the function of the impurity diffusion layer is switched between the source and drain when storing or reading 2-bit data. Adopted.

  In the data writing of the ETOX cell and the NROM cell, channel hot electron (CHE) injection, which can easily reduce the voltage as compared with the FN tunnel injection, is used. In CHE injection writing, an electric field is applied to the source and drain, and electrons supplied to the channel from the source side are energized at the drain side end of the channel to generate hot electrons. Of the generated hot electrons, hot electrons exceeding the energy barrier height of the bottom dielectric film (3.2 eV in the case of a silicon dioxide film) are injected into the charge storage means (floating gate or carrier trap).

However, in CHE injection writing of the FG type memory cell, it is necessary to apply a voltage of 10 V or more to the gate in order to excite electrons as the energy barrier height exceeds 3.2 eV. This write gate voltage is lower than that at the time of FN tunnel writing which required 18 V or higher, but is considerably higher than the power supply voltage of 2.5 to 5.0 V. The gate application voltage at the CHE injection write of the MONOS type memory cell is lower than the gate application voltage at the CHE injection write of the FG type memory cell, but higher than the power supply voltage. For example, in the case of NROM, the gate application voltage required for data writing is 9V.
Therefore, it is necessary to boost the power supply voltage in the booster circuit in the memory peripheral circuit to generate the write gate voltage regardless of the FG type or the MONOS type.

  In the booster circuit and the circuit for applying the boosted write gate voltage in the memory peripheral circuit, a high breakdown voltage transistor is required. The high breakdown voltage transistor has low process commonality with other transistors of the power supply voltage specification in the memory peripheral circuit and logic transistors in the logic circuit block. For this reason, a process dedicated to the high breakdown voltage transistor is necessary, which hinders the reduction of the manufacturing cost of the logic circuit mixed memory IC.

  In view of such circumstances, the present applicant has already filed a nonvolatile semiconductor memory device that injects charges using ionization collision, which is a charge injection mode different from CHE injection (see Patent Document 1). .

The applied voltage at the time of charge injection can be reduced by the technique described in this application. However, as the gate length becomes shorter than 100 nm in particular, the miniaturization of the memory cell has progressed, and accordingly, the demand for reducing the operating voltage to, for example, 5 V or less has increased. Only the reduction of the applied voltage at the time of the above charge injection (data writing) cannot sufficiently meet the demand for the low voltage operation of 5 V or less. That is, in such a fine memory cell, it is necessary to reduce the voltage (erase voltage) when erasing data by extracting the stored charge or injecting the charge having the opposite polarity. In particular, the erase speed is generally slower than the data write, and if the erase voltage is reduced, the rewrite operation is slowed and the influence on the memory operation speed is large. Therefore, the erase voltage is difficult to reduce. As a result, as the miniaturization of memory cells progresses, the improvement does not progress much in terms of lowering the voltage when erasing data, and this significantly hinders the low voltage operation of the entire nonvolatile memory device. It is coming. As a result, it is difficult to realize a single power supply drive that performs a memory cell operation without boosting a single power supply voltage, or in a logic-embedded application, a process of a memory peripheral circuit transistor and a logic transistor is difficult. Numerous problems are becoming apparent regarding the difficulty in reducing the erase voltage, such as difficulty in sharing.
It should be noted that charges are injected when data is written and accumulated charges are extracted when data is erased (or charges of opposite polarity are injected), and when data is written and data is written to all memory cells when data is erased. In some cases, the stored charge is extracted from the memory cell (or a charge having a reverse polarity is injected).
International Publication No. WO 03/028111 A1

  The problem to be solved by the present invention is to reduce the voltage during the operation of writing and erasing data in realizing a single power supply voltage drive or logic embedded memory by advancing miniaturization and low voltage of the memory cell. It is that being difficult is becoming a major obstacle.

  A nonvolatile semiconductor memory device according to the present invention includes a memory cell array in which memory cells made of nonvolatile memory transistors are arranged in a matrix, and rewrite of data stored in the memory cell array at most N times (N: A memory peripheral circuit that controls the memory peripheral circuit, and the memory peripheral circuit has an arbitrary M-bit memory within a storage area having a capacity of (N + 1) times the number of bits M required for storing the data. When the initial value of the data is stored in the cell group and there is an instruction to rewrite the data, instead of erasing the initial value and writing a new data value in the same memory cell group, the (N + 1) × M In the bit storage area, another unused M-bit memory cell group is selected and a new data value is written, and each time the data is rewritten, the other unused M bits are written. Control the memory cell array so that the selection of a new memory cell group and the writing of a new data value to the unused memory cell group are repeated N times in the (N + 1) × M bit storage area. To do.

In the present invention, preferably, each time the memory peripheral circuit is instructed to rewrite data to the memory cell array, the memory peripheral circuit according to the number of bits M of data to be newly written and the maximum rewritable number N thereof. Then, control for securing a storage area of (N + 1) × M bits dedicated to the data is performed.
Preferably, the memory peripheral circuit sets a value from the M-bit memory cell group written last in the (N + 1) × M-bit storage area corresponding to the data for which the read instruction has been received when reading data. Is read.
Preferably, the memory peripheral circuit is configured such that the maximum number of rewrites N can be changed for each data in accordance with an input signal.

In the nonvolatile semiconductor memory device of the present invention, when writing certain data, an instruction to write the data is given to the memory peripheral circuit. Then, the memory peripheral circuit secures the data storage area in the memory cell array in accordance with not only the number of data bits M but also the maximum number N of rewrites. The capacity of this storage area is (N + 1) × M bits. Alternatively, when the number of bits M of data is known in advance, for example, a block configuration in which (N + 1) storage areas for the M-bit data are prepared in advance may be used. These storage areas are dedicated to the data, and are not used for storing other data. Under the control of the memory peripheral circuit, the initial value of the data instructed for writing is written and stored in the storage area of the memory cell array.
Next, it is assumed that there is an instruction to rewrite this data. In the conventional nonvolatile semiconductor memory device, the initial value of already written data is erased and a new data value is written at the same address. However, in the present invention, instead of such a rewriting method, every time a data rewrite instruction is issued, an unused M-bit memory cell group is selected in the storage area assigned to the data, and the selected memory is selected. Control to write a new data value to the cell group is executed by the memory peripheral circuit. Selection and writing of such unused M-bit memory cell groups are performed each time data rewrite control is performed, and each time M bits are unused, unused memory cells are reduced in the storage area. The number of bits in this storage area is determined as (N + 1) × M, and the remaining unused area after the initial value is written is N × M bits. Therefore, the maximum number of times by such a rewriting method is N times. It turns out that. It is also possible to designate the maximum number of rewrites N for each data. In this case, storage areas having different capacities are flexibly secured according to the number of data bits M and the maximum number of rewrites N.
When reading data, the value of the data written last in the storage area assigned to the data is read.

  According to the operation method of the nonvolatile semiconductor memory device of the present invention, the data stored in the memory cell array in which the memory cells made of the nonvolatile memory transistors are arranged in a matrix is rewritten up to N times (N: positive) Integer) An operation method of a nonvolatile semiconductor memory device to be executed, wherein the data is stored in an arbitrary M-bit memory cell group in a storage area having a capacity of (N + 1) times the number of bits M required for storing the data. In the write step for storing the initial value and the data rewrite instruction, instead of erasing the initial value and writing a new data value in the same memory cell group, the (N + 1) × M bit In the storage area, another unused M-bit memory cell group is selected and a new data value is written, and each time the data is rewritten, the other unused M bits are written. Selection of Tsu preparative memory cell groups, and includes a rewriting step of repeating the maximum N times the writing of the new data values to the memory cell group of the unused said (N + 1) × M bit storage area, a.

  According to the present invention, when a data rewrite instruction is given, the actual rewrite operation is not performed, but the pseudo rewrite operation equivalent to the conventional rewrite operation of writing a new data value after erasing the stored value of the data is performed. Can be executed. That is, a memory space capable of always storing up to (N + 1) pieces of the data is prepared, and for each rewrite instruction, a memory cell group to which a new data value is actually written is shifted to an unused memory cell group one after another, for example. By writing a new data value and limiting the data to be read to the latest writing, a pseudo-rewriting operation that does not use the erasure can be realized. In this pseudo-rewrite operation, the memory space to be used becomes large and the number of rewrites is limited, but the actual operation is only writing, and a single-polar power supply voltage drive is possible. In other words, for example, when electrons are injected at the time of data writing, a positive voltage is applied to the drain with respect to the source of the memory transistor, and a positive voltage is applied to the gate separately from this. Can be done with voltage drive. As a result, there is an advantage that the configuration of the memory peripheral circuit can be simplified. In addition, there is a great advantage in that it is possible to make the manufacturing process of the transistors constituting the memory peripheral circuit completely common with the manufacturing process of the logic transistors when the logic is mixed. Furthermore, an operation method suitable for the case of adopting a write / erase operation that can reduce the data write operation voltage but difficult to reduce the erase voltage can be realized. As described above, writing and erasing of data here are not unambiguous in the relationship between charge injection and extraction.

  In general, general-purpose nonvolatile semiconductor memory devices that are currently mainstream often guarantee 100,000 rewrites. However, since the nonvolatile semiconductor memory device has been widely used as a recording medium for all rewritable data, the number of rewrites is increased from several to several tens as long as it is limited to an appropriate application. Yes. For example, the number of rewrites may be limited to protect the interests of the copyright holder. Alternatively, in the field of system LSIs, etc., some functions are electrically selected according to the customer's request, or a predetermined characteristic value (for example, supply voltage value) is changed according to the customer's request. Therefore, there is a case where a nonvolatile memory cell array capable of electrically rewriting data is embedded in a part of the IC. In these applications, the number of input data bits M or the maximum number of rewrites N is often determined in advance.

For example, as an application to which the present invention is applied, there is an analog trimming application in which resistance is adjusted in order to change a supply voltage value. In such applications, it has been found that a maximum number of data rewrites of about 10 is sufficient. The details of the embodiments of the present invention will be described below, taking as an example a MONOS type nonvolatile memory device (hereinafter referred to as a logic-embedded memory device) in which a nonvolatile memory cell array is embedded with a logic circuit in order to provide the analog trimming function. To do.
This logic mixed memory device has a memory block and a logic circuit block.

FIG. 1 shows a schematic configuration of the memory block.
The memory block illustrated in FIG. 1 includes a memory cell array (MCA) 1 and a memory peripheral circuit that controls the operation of the memory cell array.
The memory peripheral circuit includes a column buffer 2a, a row buffer 2b, a pre-row decoder (PR.DEC) 3, a main row decoder (MR.DEC) 4, a column decoder (C.DEC) 5, and an input / output circuit (I / O). 6, a column gate array (C.SEL) 7, a source line driver circuit (SLD) 8, and a well charge / discharge circuit (WC / DC) 9. Although not specifically illustrated, the memory peripheral circuit slightly increases the power supply voltage as necessary, and supplies the boosted voltage to the main row decoder 4, the source line drive circuit 8, and the well charge / discharge circuit 9. A circuit and a control circuit for controlling power supply. If the maximum voltage range that can be output from the memory peripheral circuit to the memory cell array 1 is ± 5 V, the above-described boosting is required when the externally supplied power supply voltage is 2.5 V or less. When the voltage is 5V, boosting is unnecessary.

The main row decoder 4 includes a word line driving circuit (WLD) that applies a predetermined voltage to the word line designated by the pre-row decoder 3.
The input / output circuit 6 includes a buffer (BUF) for program and read data, a bit line drive circuit (BLD) for applying a predetermined voltage to the bit line BL at the time of writing or reading data, and a sense amplifier (SA). .

  The present embodiment is characterized in a data rewriting method for the memory cell array 1, and this method is executed by the memory peripheral circuit controlling the memory cell array 1. More specifically, the nonvolatile memory device according to the present embodiment secures a storage area having a capacity corresponding to the number of bits M of data to be written and the maximum number of rewrites N in the memory cell array 1 for each data. This method is suitable when the number of data bits M and the maximum number of rewrites are different for each data, and these are not known in advance. Data storage areas defined by the method are schematically shown in FIGS.

  In the example shown in FIG. 2, data 1 is 4 bytes, the maximum number of rewrites is 10 times, data 2 is 8 bytes, and the maximum number of rewrites is 3 times. In the example shown in FIG. 2, the storage area R1 for data 1 is defined as the first (10 + 1) × 4 = 44 bytes, and the subsequent (3 + 1) × 8 = 32 bytes is defined as the storage area R2 for data 2. The information of the address ranges of the storage areas R1 and R2 for each data may be held in other areas of the memory cell array 1 in a rewritable manner, or may be held in other memories in a rewritable manner. Alternatively, the memory cell array may be provided with a so-called mask register that inputs the address range information from the outside and restricts the access range of the memory cell array based on the information.

When the data storage ranges R1, R2,... Are determined within the memory cell array 1 as shown in FIG. 2, the use efficiency of the memory cells is high, but the address range designation is complicated.
Therefore, as shown in FIG. 3, the data storage range can be defined by a multiple of the word line sector as a minimum unit. In FIG. 3, the storage range R1 for data 1 is secured for 3 word line sectors (60 bytes), and the storage range R2 for data 2 is secured for 2 word line sectors (40 bytes). Even when the maximum number of rewrites of data 1 is 10 and the maximum number of rewrites of data 2 is determined to be 3, the capacity of the memory cell array is configured so that a larger number of rewrites is possible. . In other words, in FIG. 3, the number of data 1 values (4 bytes) that can be stored from the memory capacity is 15 in total, one initial value and 14 new data values. 14 times. In addition, since the number of data 2 values (8 bytes) that can be stored from the memory capacity is 5 in total for one initial value and four new data values, the number of rewrites of data 2 is four. . The number of rewritable times 14 and 4 of data 1 and 2 possible from these memory capacities is larger than the maximum number of rewrites 10 and 3 defined in data 1 and 2, respectively. And R2 have extra memory cells, and the utilization efficiency of the memory cells is lower than in the case of FIG. However, the data storage method shown in FIG. 3 has the advantage that the memory peripheral circuit including address designation by this can be simplified by selecting the storage area with the word line sector as the minimum unit.
2 and 3, in each of the storage areas R1, R2,..., For example, if an address with the upper left corner as the origin is determined, the initial value of data and the first rewrite are performed in ascending order of the address. A new data value 1, a new data value 2, etc. by the next rewrite are sequentially stored.

  When the number of data bits M and the maximum number of rewrites N are constant, the memory cell array 1 can be configured as shown in FIG. FIG. 4 shows a case where the maximum number of rewrites N = 10. In this case, the memory cell array 1 is divided into 11 blocks B0 to B10 having a constant bit length M. For data 1, the initial value V0 is stored in the block B0, the new data value V1 by the first rewrite is stored in the block B1, and the new data value V2 by the second rewrite is stored in the block B2, and this is repeated. The value V10 obtained by the last rewrite is stored in the block B10.

Next, on the premise of the configuration of the storage area shown in FIG. 4, the control operation at the time of data writing and rewriting of the memory peripheral circuit will be briefly described.
First, the data 1 write operation will be described. First, in a state where a chip enable signal (not shown) is in a “high (H)” state, the address signals A1 to Am + n input to the address terminals are passed through the address buffers (column buffer 2a and row buffer 2b) and the pre-row decoder 3 and Input to the column decoder 5.
A part of the input address signal is decoded by the pre-row decoder 3, a predetermined word line WL designated by the address signal is selected, and the selected word line WLsel. A predetermined voltage is applied to the word line drive circuit (WLD) in the main row decoder 4.
When data 1 is written, the word line in the first row shown in FIG. 4 is selected by the input address signal, and a word line WLsel in which a predetermined high level positive voltage, for example, 3.3 V is selected from the word line driving circuit. . To the unselected word line WLunsel. Is held at 0V, for example.

The remaining address signal is decoded by the column decoder 5, the column selection line YL designated by the address signal is selected, and a predetermined voltage is applied thereto.
When a predetermined voltage is applied to the column selection line YL, a predetermined bit line selection transistor in the column gate array 7 changes to a conductive state, and the initial value V0 of data 1 is set in the memory cell array 1 accordingly. M selected bit lines BLsel. Corresponding to the block B0 to be stored. Are connected to the input / output circuit 6.

The source line driving circuit 8 controlled by the control signal CS applies the ground potential GND to the source line SL at the time of writing.
Further, the well charge / discharge circuit 9 controlled by the control signal CS ′ charges the well of the memory cell array to a predetermined reverse bias voltage (for example, negative voltage) only at the time of writing.

  As a result, when data 1 is written, according to the initial value V0 of data 1 in the input / output buffer, the high level voltage when the bit is “1” and the low level when the bit is “0” Of the M bit lines BLsel. To be applied. As a result, these selected M bit lines BLsel. And the selected and excited word line WLsel. The initial value V0 of data 1 is written and stored in a group of M memory cells at the intersection with. Specifically, according to the initial value V0 of the write data 1, a positive voltage of about 3.3 V is applied to the selected bit line corresponding to the “1” bit, and the selected bit line corresponding to the “0” bit. Is applied with 0V. Among these, hot electrons due to ionization collision (for example, secondary ionization collision) are injected into the memory cell in which a positive voltage (3.3 V) is applied to the selected bit line, and as a result, the threshold value of the memory cell increases. The stored data is “1”. In the memory cell corresponding to the bit of “0” in which the selected bit line is maintained at 0 V, the ionization collision does not occur and the threshold value does not rise, so the stored data becomes “0”.

  As will be described later, when the wells are divided into parallel stripes that are long in the bit line direction, the well selection is preferably performed based on the column address in the configuration of FIG. In hot electron injection writing by secondary ionization collision, it is desirable to negatively bias the well. In this case, for example, about −1.0 to −3.5 V is applied to the selected well.

Next, the data 1 rewrite operation will be described.
First, as in the case of writing data 1, the pre-row decoder 3 and the column decoder 5 receive the address signals A1 to Am + n inputted to the address terminals through the address buffer while the chip enable signal is in the “high (H)” state. Is input.
A part of the input address signal is decoded by the pre-row decoder 3, a predetermined word line WL designated by the address signal is selected, and the selected word line WLsel. A predetermined voltage is applied to the word line drive circuit (WLD) in the main row decoder 4.
Since the data 1 is rewritten, the word line in the first row shown in FIG. 4 is selected by the input address signal, and a predetermined high level positive voltage, for example, 3.3 V is selected from the word line driving circuit. Word line WLsel. To the unselected word line WLunsel. Is held at 0V, for example.

The remaining address signal is decoded by the column decoder 5, the column selection line YL designated by the address signal is selected, and a predetermined voltage is applied thereto.
When a predetermined voltage is applied to the column selection line YL, a predetermined bit line selection transistor in the column gate array 7 is changed to a conductive state, and accordingly, the first rewrite of data 1 in the memory cell array 1 is performed. The next M selected bit lines BLsel. Corresponding to the block B1 storing the new data value V1. Are connected to the input / output circuit 6. At this time, access to the block B0 is prohibited.

  By this time, a new data value V1 of data 1 has been input into the input / output buffer. Therefore, according to the new data value V1 of data 1, when the bit is “1”, the high level voltage (3.3V) is high, and when the bit is “0”, the low level voltage (0V) is high. Are respectively selected M bit lines BLsel. To be applied. As a result, the M bit lines BLsel. Corresponding to these selected blocks B1. And the selected and excited word line WLsel. A new data value V1 of data 1 is written and stored in a group of M memory cells (block B1) at the intersection with.

Thereafter, in the same manner, whenever there is an instruction to rewrite data 1, the new data values V2,..., V10 are sequentially written in a different area from the blocks B2,. Access prohibition is set for the old block each time. For this reason, when data 1 is read when the number of rewrites is arbitrary, only the block in which the value is stored at the time of the latest rewrite can be accessed.
When data 2, data 3,... And other data need to be stored, the basic data initial value writing and rewriting method are the same as those for data 1 described above. .

  Thus, in order to realize data rewrite driving with a power supply voltage of about 3.3 V or 2.5 V, it is necessary to devise the structure of the memory transistor, the data writing method, and the like. Hereinafter, a memory cell array method, a cross-sectional structure of a memory transistor, a method for writing and reading data, and the like that can be applied to this embodiment will be described in detail.

FIG. 5 is an equivalent circuit diagram of a non-volatile memory device of the source isolation NOR type. FIG. 6 is a plan view thereof, and FIG. 7 is a bird's-eye view as seen from the cross section indicated by the line AA ′ in FIG.
Memory transistors M11 to M33 constituting the memory cell are arranged in a matrix, and these transistors are wired by a word line, a bit line, and a separated source line.
The drains of the memory transistors M11, M12, and M13 adjacent in the column (COLUMN) direction are connected to the bit line BL1, and the sources are connected to the source line SL1. The drains of the memory transistors M21, M22, and M23 adjacent in the column direction are connected to the bit line BL2, and the sources are connected to the source line SL2. The drains of the memory transistors M31, M32, and M33 adjacent in the column direction are connected to the bit line BL3, and the sources are connected to the source line SL3.
The gates of the memory transistors M11, M21, and M31 adjacent in the row (ROW) direction are connected to the word line WL1. Each gate of memory transistors M12, M22 and M32 adjacent in the row direction is connected to word line WL2. Each gate of memory transistors M13, M23, and M33 adjacent in the row direction is connected to word line WL3.
In the entire memory cell array, the cell arrangement and inter-cell connection illustrated in FIG. 5 are repeated.

In the fine NOR type cell array, as shown in FIG. 7, an element isolation insulating layer ISO is formed from a trench or LOCOS in a surface region of a P-type semiconductor substrate SUB or a P-well not shown. The element isolation insulating layer ISO has a parallel line shape that is long in the column (COLUMN) direction. Word lines WL1, WL2, WL3, WL4,... Are formed at equal intervals, and each word line is substantially orthogonal to the element isolation insulating layer ISO.
Between the word line and the semiconductor substrate SUB, a three-layered film (charge storage film) including a bottom dielectric film, a main charge storage film, and a top dielectric film is formed. The width (gate length) of the gate line is reduced to 0.18 μm or less, for example, 0.13 μm.
In the surface region of the semiconductor substrate within the interval between the element isolation insulating layers ISO, N-type impurities are introduced at a high concentration, and a first source / drain region (hereinafter referred to as a source region) S and a second source / drain region ( (Hereinafter referred to as the drain region) D are alternately formed. The dimension of the source region S and the drain region D in the row (ROW) direction is defined by the distance between the element isolation insulating layers ISO. The dimension in the column (COLUMN) direction of the source region S and the drain region D is defined by the interval between the word lines WL1 to WL4. The source region S and the drain region D are formed to be very uniform because almost no mask alignment error is introduced with respect to variations in dimensions and arrangement.

Between the two adjacent word lines, an elongated self-aligned contact portion SAC is opened along the word line. In the self-aligned contact portion SAC, the word line is covered with the offset insulating layer OF and the sidewall insulating layer SW.
Conductive materials are alternately buried in the self-aligned contact portions SAC so as to partially overlap the source region S or the drain region D, whereby the bit contact plug BC and the source contact plug SC are formed. The bit contact plug BC overlaps the drain region D at one end in the row (ROW) direction. The source contact plug SC overlaps the other end portion in the row (ROW) direction with respect to the source region S. As a result, the bit contact plugs BC and the source contact plugs SC are alternately formed as shown in FIG. This is because the bit contact plug BC is connected to the bit line, and the source contact plug SC is connected to the source line.

In forming the bit contact plug BC and the source contact plug SC, a conductive material is deposited so as to fill the entire self-aligned contact portion SAC, and a resist for an etching mask is formed on the conductive material. At this time, the resist is made slightly larger than the width of the self-aligned contact portion, and a part of the resist is overlaid on the element isolation insulating layer. Using the resist as a mask, the conductive material around the resist is removed by etching. As a result, the bit contact plug BC and the source contact plug SC are formed simultaneously.
A recess around the contact is filled with an insulating film (not shown). On the insulating film, bit lines BL1, BL2,... Contacting the bit contact plug BC and source lines SL contacting the source contact plug SC are alternately formed. The bit line and the source line have a parallel line shape that is long in the column (COLUMN) direction.

In the fine NOR type cell array, the contact formation with respect to the bit line or the source line is achieved by the formation of the self-aligned contact portion SAC and the formation of the plugs BC and SC. By forming the self-aligned contact portion SAC, insulation isolation from the word line is achieved. When the self-aligned contact portion SAC is formed, the exposed surface of the source region S or the drain region D is formed uniformly. The bit contact plug BC and the source contact plug SC are formed on the exposed surface of the source region S or the drain region D in the self-aligned contact portion contact SAC. The size of the substrate contact surface of each plug in the column (COLUMN) direction is determined when the self-aligned contact portion SAC is formed, and the variation in the contact area is small.
The bit contact plug BC or the source contact plug SC can be easily isolated from the word line. The sidewall insulating layer SW is formed by simply forming the offset insulating layer OF at the time of forming the word line and then performing the formation of the insulating film and the entire surface etching (etchback). The bit contact plug BC and the source contact plug SC, and the bit line and the source line are formed by patterning conductive layers in the same layer. For this reason, the wiring structure is very simple, the number of processes is small, and the structure is advantageous for keeping the manufacturing cost low.

FIG. 8 is an enlarged cross-sectional view of the memory transistor in the row direction (hereinafter referred to as channel direction).
In FIG. 8, a portion sandwiched between the drain region D and the source region S and intersecting the word line WL is a channel formation region CH of the memory transistor. A high concentration channel region HR in contact with the drain region D is formed in the channel formation region CH. The high-concentration channel region HR is a P-type having a higher concentration than other channel formation regions CH. As will be described later, the high-concentration channel region HR has a role of increasing the concentration of the electric field in the channel direction in the adjacent channel formation region CH.

  A charge storage film GD is formed on the channel formation region CH including the high concentration channel region HR, and a gate electrode (word line WL) of the memory transistor is formed on the charge storage film GD. The word line WL is made of doped polycrystalline silicon, refractory metal silicide, or a laminated film of doped polycrystalline silicon and refractory metal silicide that has been made conductive by introducing a high concentration of P-type or N-type impurities. The effective portion of the word line WL, that is, the length in the channel direction (gate length) corresponding to the distance between the source and the drain is 0.18 μm or less, for example, about 130 nm.

The charge storage film GD in the present embodiment is composed of a bottom dielectric film BTM, a main charge storage film CHS, and a top dielectric film TOP in order from the lower layer.
The bottom dielectric film BTM is formed, for example, by forming an oxide film and nitriding it. The film thickness of the bottom dielectric film BTM can be determined within a range of 4 nm to 9.0 nm, for example, and is set to 4 to 6 nm here. When the semiconductor substrate is made of silicon, the barrier height of the bottom dielectric film BTM on the conductor side with respect to the silicon substrate is set lower than the barrier height of silicon dioxide (SiO ₂ ) and silicon (Si).

  Here, the injection efficiency P of DAHC (drain avalanche hot carrier), which is not the charia itself due to the two-dimensional ionization collision, is shown in the following equation (1).

[Formula 1]
P = A · exp {− (B · q · φc) / (k · Te)} (1)
In the formula (1), A and B are constants, q is an absolute value of electronic charge (= 1.6 × 10 ⁻¹⁹ C), φc is a barrier height, k is a Boltzmann constant, and Te is an absolute temperature.

The barrier height on the conduction band side with the silicon substrate of silicon dioxide calculated from the formula (1) is 3.2 V, whereas the barrier height on the conduction band side with the silicon substrate of the oxynitride film is 2.0 V, which is a low value. Have. As another material of the bottom dielectric film BTM that satisfies the condition of the barrier height, a film made of aluminum, tantalum, titanium, zirconium, hafnium, lanthanum oxide, silicate, or the like is used as described later. be able to. The approximate values of the barrier height on the conductive band side of these materials with the silicon substrate are as follows: aluminum oxide (Al ₂ O ₃ ): 2.8 eV, tantalum oxide (Ta ₂ O ₅ ): 1.45 eV, titanium oxide (TiO ₂ ) : 1.1 eV, zirconium oxide (ZrO ₂ ): 1.4 eV, hafnium oxide (HfO ₂ ): 1.5 eV, yttrium oxide (Y ₂ O ₃ ): 2.3 eV, zirconium silicate (ZrSiO ₄ ): 1.5 eV Barium zirconate (BaZrO ₃ ): 0.8 eV, both of which are set lower than the barrier height of 3.2 V on the conduction band side with the silicon dioxide silicon substrate.

The main charge storage film CHS is composed of, for example, an 8.0 nm silicon nitride (Si _x N _y (0 <x <1, 0 <y <1)) film. The main charge storage film CHS is produced, for example, by low pressure CVD (LP-CVD), and contains many carrier traps. The main charge storage film CHS exhibits Frenkel pool type (FP type) electrical conduction characteristics.
The top dielectric film TOP needs to form deep carrier traps at high density near the interface with the main charge storage film CHS. For this reason, the main charge storage film CHS is formed, for example, by thermally oxidizing a nitride film after film formation. The top dielectric film TOP may be a high temperature CVD oxide film (HTO). When the top dielectric film TOP is formed by CVD, this trap is formed by heat treatment. The film thickness of the top dielectric film TOP is at least 3.0 nm, preferably 3 in order to effectively prevent hole injection from the gate electrode (word line WL) and prevent a decrease in the number of times data can be rewritten. .5 nm or more is required.

  In manufacturing the memory transistor having such a configuration, the element isolation insulating layer ISO and the P well W (not shown in FIG. 7) are formed on the prepared semiconductor substrate SUB. Impurity regions (first and second source / drain regions) to be the drain region D and the source region S are formed by ion implantation. The high concentration channel region HR is formed by an oblique ion implantation method or the like. If necessary, ion implantation for adjusting the threshold voltage is performed.

Next, the charge storage film GD is formed on the semiconductor substrate SUB on which the P well W and the element isolation insulating layer ISO are formed.
Specifically, heat treatment is performed at 1000 ° C. for 10 seconds by a short time high temperature heat treatment method (RTO method) to form an oxynitride film (bottom dielectric film BTM). The film thickness of the bottom dielectric film BTM is desirably 4 to 9 nm, and is 5 nm in this embodiment. The bottom dielectric film BTM is a film made of a material other than silicon dioxide (SiO ₂ ) in the sense of lowering the barrier height on the conduction band side with the silicon substrate as described above. For example, as described above, for example, a silicon oxynitride (SiON) film In addition, various silicate films such as a silicon nitride (SiN) film and an alumina film, and other films made of a material having a high dielectric constant may be used.
On the bottom dielectric film BTM, a silicon nitride film (main charge storage film CHS) is deposited by LP-CVD so as to have a final film thickness of 8 nm. This CVD is performed at a substrate temperature of 730 ° C. using a gas in which dichlorosilane (DCS) and ammonia are mixed, for example.
The surface of the formed silicon nitride film is oxidized by a thermal oxidation method to form, for example, a silicon oxide film (top dielectric film TOP) of 4.5 nm. This thermal oxidation is performed, for example, in an H ₂ O atmosphere and a furnace temperature of 950 ° C. As a result, deep carrier traps having a trap level (energy difference from the conduction band of the silicon nitride film) of about 2.0 eV or less are formed at a density of about 1 to 2 × 10 ¹³ / cm ² . In addition, a thermal silicon oxide film (top dielectric film TOP) is formed to a thickness of 1.5 nm with respect to 1 nm of the silicon nitride film (main charge storage film CHS), and the underlying silicon nitride film thickness is reduced at this rate. The final film thickness is 8 nm.

A laminated film of a conductive film to be a gate electrode (word line WL) and an offset insulating layer (not shown) is laminated, and the laminated film is processed in the same pattern all together.
Subsequently, in order to obtain the memory cell array structure of FIG. 7, a self-aligned contact portion is formed together with the sidewall insulating layer, and the bit contact plug BC is formed on the drain region D and the source region S exposed by the self-aligned contact portion. Then, a plug to be the source contact plug SC is formed.
The periphery of these plugs is filled with an interlayer insulating film, and after the bit line BL and the source line SL are formed on the interlayer insulating film, the interlayer insulating layer is deposited, contacts are formed, and the upper wiring is formed as necessary. Finally, the nonvolatile memory cell array is completed through an overcoat film formation process, a pad opening process, and the like.

Next, a bias setting example and operation of the source-separated NOR type nonvolatile memory cell array illustrated in FIG. 5 will be described.
FIG. 9A is a conceptual diagram of the data writing operation, that is, a conceptual diagram of hot electron injection, and FIG. 9B is a diagram showing an acceleration electric field E of electrons in the channel direction. In the present embodiment, writing is performed by hot electron injection generated by secondary ionization collision, which is a kind of ionization collision phenomenon.
Specifically, as shown in FIG. 9A, the gate (word line WL) is 3 to 4 V and the drain (drain region D) is Vsd = 3.3 V with reference to the voltage of 0 V at the source (source region S). Is applied. Further, as a back bias, a PN junction between the P well W and the sub source line (first source / drain region) SSL or the sub bit line (second source / drain region) SBL is reverse-biased as a back bias. A voltage Vwell, for example, -3V, is applied. At this time, a voltage value smaller than the breakdown voltage between the second source / drain region and the well is selected as the voltage applied between the second source / drain region and the well.

  Under this bias condition, electrons e that are supplied from the source region S and travel through the channel collide with the silicon lattice in the depletion layer on the drain region D side, or are scattered to generate a pair of high energy holes HH and electron HE. Let Among these, the hot hole HH is accelerated in the depletion layer of the PN junction and collides with the secondary ionization to generate a pair of electrons and holes. The electrons generated by the secondary ionization collision become hot electrons HE and drift while being partially accelerated toward the word line WL by a vertical electric field. Hot electrons HE having high energy overcome the potential barrier of the bottom dielectric film BTM and are captured by carrier traps in the main charge storage film CHS. This charge trapping region (memory portion) is limited to a part on the drain side.

Hot electron HE generated by ionization collision is generated at a lower electric field than the CHE injection method in which the channel is simply accelerated to increase energy.
In this embodiment, since the high-concentration channel region HR is provided, as shown in FIG. 9B, the concentration of electric field in the channel direction is higher than in the case where the high-concentration channel region HR indicated by the broken line is not provided. As a result, the energy that the channel traveling electrons e collide with the silicon lattice increases. Alternatively, the voltage between the source and drain regions for obtaining the same energy may be low. In the present embodiment, the formation of the high concentration channel region HR is not essential, but for the above reason, it is more desirable to form the high concentration channel region HR.
Further, the PN junction between the P well W and the N ⁺ impurity region forming the sub-bit line is reverse-biased by the back bias, and the depletion layer is easily spread with a lower drain voltage. Also, even if the voltage applied to the gate electrode is lower than when no back bias is applied, the required hot electron injection efficiency can be easily obtained.

As described above, in this embodiment, the maximum operating voltage is reduced as compared with the conventional case.
For example, in the conventional channel hot electron injection method, the bias conditions for injecting the same amount of charge into the main charge storage film CHS in the same amount of time are required as the drain voltage 4.5V and the gate voltage 9V.
On the other hand, in this embodiment, the drain voltage is 2.5 to 3.3 V and the gate voltage is 3.3 V.

Data reading may be performed bit by bit or page reading. Further, either the forward read method or the reverse reverse method in which the source-drain voltage application direction is the same as that at the time of writing may be employed.
In the forward read method and the reverse read method, the source and the drain are reversed with respect to the storage unit in which charges are accumulated, but it is not necessary to change the bias voltage value itself. In general, the reverse read method is more sensitive. However, a forward read method in which a change in the potential of the bit line is small is preferable for verification reading after writing. As gate length scaling progresses, sufficient sensitivity is likely to be obtained even with the forward read method.

Various voltages necessary for each operation of the memory cell array are supplied from various drivers of the memory peripheral circuit.
The memory peripheral circuit has a first polarity voltage (3 to 4 V) and a second polarity voltage (−) that cause a potential difference between the gate and the substrate to be a second voltage (6 to 7 V) to be applied between the gate and the substrate during data writing. 3V) respectively. A first polarity voltage (3 to 4 V) is applied to the gate electrode, for example, the word line WL, and a second polarity voltage (-3 V) is applied to the semiconductor substrate, for example, the P well W.
In the memory peripheral circuit, the second voltage (6～7V) in the circuit dealing with the normal power supply voltage V _CC based transistor or logic circuitry little breakdown voltage than the transistor is high transistor (hereinafter, for convenience, that medium-voltage transistor) is necessary It was. However, in this embodiment, the second voltage divided into a first polarity voltage (3 to 4V) and the second polarity voltage (-3 V), to each of the absolute value and the voltage about power supply voltage V _CC In addition, by eliminating the use of erasing for the above-described data rewrite, the intermediate voltage transistor can be eliminated. Incidentally, when the power supply voltage _{V CC} is 2.5V and low, it is necessary to generate a boosting circuit higher 4~6V voltage of about.

The nonvolatile memory according to the present embodiment uses hot electron injection by secondary ionization collision, which has higher charge injection efficiency than conventional source side CHE injection at the time of data writing. In addition, by eliminating erasing when rewriting data, it is possible to suppress the withstand voltage of the transistors in the memory peripheral circuit to about 4 to 6 V at the maximum.
In the conventional nonvolatile memory, a transistor with a high breakdown voltage exceeding 10V, sometimes called a so-called _VPP system, is required in some cases. Such formation of the transistor after less common of the process of the V _CC based transistor or logic circuit transistor, scale of the booster circuit becomes large to generate this was achieved, greater power consumption. In these respects, the nonvolatile memory of the present embodiment is excellent.

Meanwhile, the breakdown voltage of about 4~6V is required in the circuit of a general V _CC system. In other words, an I / O transistor that is used in the input / output (I / O) stage of a _VCC system circuit and that is affected by an external signal is another transistor even if the normal operating voltage is the power supply voltage _VCC. Usually, it is designed to have a higher pressure resistance. Alternatively, the process parameters such as the gate insulating film thickness may be changed from those of other high-speed logic transistors. And the burn-in voltage of an I / O transistor is about 6V, and it is often said that the reliability specification does not break when applied for several seconds. The breakdown voltage of the I / O transistor is higher than the burn-in voltage.

In this embodiment, at least the process of the I / O transistor is the same as that of the intermediate voltage transistor with an offset in the memory peripheral circuit. The I / O transistor may be slightly different from the case where the process is the same as other logic transistors. However, in any case, the processes of the memory peripheral circuit and the logic unit are shared by at least a part, more preferably all.
This is possible with the adoption of the writing method described above. In other words, the above writing method enables high-speed writing of 100 μs, and considering the maximum number of rewrites necessary for practical use of the flash memory is several tens of times, the integration application time is several milliseconds (actually, program data This is a use environment much more gradual than the burn-in condition of the I / O transistor. Even when a sufficient margin is desired, the process itself is made common to I / O transistors and normal logic circuit transistors. In the present embodiment, at least the gate insulating film specifications are common and a difference is made in the impurity distribution profile on the drain side, for example, when a margin is desired.

Next, an example of manufacturing a nonvolatile memory device will be described with reference to the drawings.
FIG. 10 is a cross-sectional view of a nonvolatile memory device showing a memory cell array formation region and a memory peripheral circuit or logic circuit block formation region.
In the illustrated structure, the memory cell array and the memory peripheral circuit or logic circuit block formation region are both separated in a well-in-well (WIW) structure. Around the P-well W where the memory transistor is formed, an N-well NWa formed of a deep N ⁺ impurity region 10a in the deep part of the substrate and an N-type impurity region 11 reaching the substrate surface is formed. Similarly, in the formation region of the memory peripheral circuit or logic circuit block, an N well NWb composed of an N ⁺ impurity region 10b deep in the substrate deep portion and an N type impurity region 13 reaching the substrate surface is formed around the P well 12. Is formed.

On the P well 12, for example, a gate electrode 18 made of doped polycrystalline silicon is formed via a gate insulating film 17 made of thermally oxidized silicon having a thickness of several nanometers to several tens of nanometers. A gate electrode 19 made of doped polycrystalline silicon, for example, doped with an impurity having the opposite conductivity type is formed on the N well 13 through a similar gate insulating film 17.
N-type source / drain impurity regions 20 are formed on the surface of the P well 12 on both sides of the gate electrode 18. P-type source / drain impurity regions 21 are formed on the surface of the N well 13 on both sides of the gate electrode 19.
Sidewall insulating layers 22 made of a silicon oxide insulating film are formed on both side surfaces of the laminated pattern of the gate electrodes 18 and 19 and the gate insulating film 17.

  Although not specifically illustrated on the gate electrodes 18 and 19 of the transistor, the periphery of the gate electrodes 18 and 19 is covered with an insulating layer by an offset insulating layer provided as necessary and an interlayer insulating film formed on the entire surface. It has been broken. Further, contacts connected to the source / drain impurity regions 20 and 21 are formed. The wiring layer is in contact with the contact, and is formed from the same aluminum wiring layer as the bit line of the memory transistor.

In the manufacture of this nonvolatile memory device, first, a semiconductor substrate SUB such as a P-type silicon wafer is prepared, and an element isolation insulating layer ISO is formed on the semiconductor substrate SUB as necessary by, for example, a trench isolation method. In the formation of the element isolation insulating layer ISO, an etching mask layer is formed on the substrate, the substrate is dug to a predetermined depth by anisotropic etching, and the trench is filled with an insulator. After partially removing the insulator on the substrate surface between the trenches by, for example, etching using a resist as a mask, CMP (Chemical Mechanical Polishing) is performed. In the case of partial removal of the insulator, the amount of polishing depends on the area of the protrusions of the insulating film during CMP, or it is easy to cause polishing nonuniformity such as dishing at the protrusions of a large area. In order to correct the problem due to the size of this, it is performed in advance to remove most of the insulating film protruding between the trenches, leaving only the edge of the projection before CMP.
In these steps, two photomasks are required, which are a first mask “TER” for forming the trench etching mask layer and a second mask “AIM” for partially removing the buried insulating film.

A resist pattern is formed on the semiconductor substrate SUB using a third mask “DNW”. Using this resist pattern as a mask, ion implantation is performed to form deep N ⁺ impurity regions 10a and 10b in the deep portion of the substrate below the opening.
After removing the resist pattern, resist formation and ion implantation with different patterns and conditions are performed to form a P-well. In this resist patterning, a fourth mask “PWL” is used. As a result, the P well W for the memory transistor and the P well 12 for the peripheral circuit and the logic circuit are simultaneously formed in different regions of the wafer.

After removing the resist, resist formation and ion implantation with different patterns and conditions are performed in the same procedure to form an N well. In this resist patterning, a fifth mask “NWL” is used. As a result, the N well NWa for the memory transistor is formed around the P well W, and the N well NWb for the peripheral circuit and the logic circuit is simultaneously formed in different regions of the wafer.
After removing the resist, resist formation and ion implantation with different patterns and conditions are repeated twice. Thus, the threshold voltages of the memory transistor and the select transistor are adjusted respectively. The sixth mask “MVA” is used for adjusting the threshold voltage of the memory transistor, and the seventh mask “SEL-VA” is used for adjusting the threshold voltage of the select transistor.

In these steps, a bottom dielectric film BTM made of silicon oxide is formed by thermal oxidation, and a nitride film (charge storage film) CHS is deposited thereon by LP-CVD or the like. A top dielectric film TOP is formed on the main charge storage film CHS by a method such as thermally oxidizing the surface of the main charge storage film CHS.
A resist pattern that covers the memory transistor region is formed on the formed top dielectric film TOP by using an eighth mask “GTET (ONO-ET)”. Using the resist as a mask, the ONO film on the peripheral circuit and logic circuit side is removed by etching.

After removing the resist, the exposed substrate and the surface of the well W are thermally oxidized by about several nm to several tens nm to form a gate insulating film 17a common to the peripheral circuit and the logic circuit.
A resist pattern is formed in the active region of the P well sandwiched between the element isolation insulating layers SIO of the memory transistor by using the ninth mask “BN”, and ion implantation is performed. Thereby, for example, a drain region D and a source region S made of N ⁺ impurity regions are formed.
By the resist formation and ion implantation using the tenth mask “BN2 (N + II)”, an additional impurity is further implanted into the length of a part of the drain region D and the source region S, for example, the half of the side where the bit contact is formed. . As a result, the variation in transistor characteristics due to the wiring resistance of the impurity region is reduced.

After removing the resist, a gate conductive film made of doped polycrystalline silicon is formed on the entire surface. A resist is formed on the gate conductive film using the eleventh mask “1PS”, and anisotropic etching is performed to form the word line WL and the gate electrodes 18 and 19.
After removing the resist, a resist opening only in the memory transistor region is formed using a twelfth mask “Ch-stp”. P-type impurities are shallowly ion-implanted using a resist as a mask. At this time, the word line WL and the element isolation insulating layer ISO serve as a self-alignment mask, and a P-type impurity region for channel stop is formed on the P well surface between the word lines WL.

After removing the resist, a resist opening around the gate electrode on the NMOS side of the peripheral circuit and logic circuit is formed using a thirteenth mask “HV-NLD”, and ion implantation is performed. As a result, N ⁺ type source / drain impurity regions 20 for the NMOS transistors of the memory peripheral circuit and logic circuit are formed.
Similarly, the P ⁺ -type source / drain impurity region 21 on the PMOS side is formed using the fourteenth mask “HV-PLD”.

  Further, high-concentration source / drain impurity regions are formed on the NMOS side and the PMOS side of the peripheral circuit and logic circuit, respectively, using the fifteenth mask “NSD” and the sixteenth mask “PSD”. Among these, when high-concentration N-type impurities are introduced, impurities are additionally implanted into the portion where the contact of the memory transistor is formed in order to reduce contact resistance.

  Thereafter, simultaneous formation of the bit contact and source contact using the seventeenth mask “1AC”, formation of the bit line BL and source line SL and other wiring using the eighteenth mask “1Al”, film formation of an overcoat film, The electrode pad is opened using the nineteenth mask “PAD” to complete the nonvolatile memory device.

  The low breakdown voltage / high speed transistor for the logic circuit is formed in the well 103 or 104 having the optimized concentration for both the NMOS transistor NLT and the PMOS transistor PLT. The source / drain impurity regions 105 and 106 are highly concentrated and thinned to the limit. The gate insulating film thickness is scaled to 3 to 8 nm and the gate length is about 0.25 μm.

As described above, in the method for manufacturing the nonvolatile memory device according to the present embodiment, the memory peripheral circuit and the memory transistor of the logic circuit are simultaneously formed in the same size, so that the manufacturing process is simple due to the high commonality of the manufacturing process. It is easy to improve the yield. Specifically, in the above example, seven masks, seven resist pattern forming steps, six ion implantation steps, and one anisotropic etching step are unnecessary. As a result of actual cost calculation, it was confirmed that the chip cost can be reduced by about 25% compared with the MNOS type semiconductor memory device manufactured by the conventional manufacturing method.
As described above, an I / O transistor of a logic circuit having a breakdown voltage of about 6V can be employed. In this case, the thirteenth mask and the fourteenth mask related to the optimization of the impurity concentration are not necessary, and the steps of forming the resist pattern and ion implantation are reduced, and as a result, further cost reduction can be achieved.

In this embodiment, it is desirable that a pinch-off point exists in the middle of a part of the channel formation region below the injection charge holding region because forward reading can be performed more effectively.
For this purpose, for example, by adjusting the voltage value and application time applied at the time of writing, the gate insulating film GD is separated from the boundary between the drain-side N-type impurity region (drain region D) and the high-concentration channel region HR. Hot electrons may be injected to the center side of the channel to at least 20 nm or more. In this case, it is desirable to previously set the neutral threshold voltage, that is, the threshold voltage below the region where there is no injection charge depending only on channel doping, to an average value of 1.5 V or less.
In this way, since all of the channel formation region below the injection charge holding region is not pinched off and the neutral threshold voltage is sufficiently low, a threshold voltage change due to charge injection can be easily detected by forward reading.

  In order to reduce the off-leakage current from the non-selected cell, it is preferable to slightly bias the non-selected word line with a negative voltage during reading. Alternatively, the source line may be slightly biased in the positive direction. For example, 0V may be applied to the unselected word line, and a voltage higher than 0V and 0.5V or less, for example, 0.3V, for example, may be applied to all the source lines instead.

Many system LSIs intended to realize one system or subsystem itself with one LSI are equipped with a non-volatile memory. Nonvolatile memories for system LSI use are required to have various high performances based on commonality with CMOS processes and high speed.
The nonvolatile memory device of this embodiment realizes high-speed operation without using a special gate structure such as an FG type floating gate or a source side injection type MONOS type. Therefore, there are advantages that the number of process steps and the number of photomasks are small, the commonality with the CMOS process is high, and the high performance is obtained as a non-volatile memory for mixed use such as a system LSI.

Hereinafter, modifications related to the memory cell array system, the transistor structure, and the like will be described.
FIG. 11 shows an example of a circuit configuration of the memory cell array (MCA) 1. This array configuration has hierarchical bit lines and source lines, and is called a so-called SSL (Separated Source Line) type. FIG. 12 shows a plan view of this memory cell array. FIG. 13 shows a bird's-eye view seen from the cross-sectional side along the line BB ′ of FIG.
In this memory cell array, bit lines are hierarchized into main bit lines and sub-bit lines, and source lines are hierarchized into main source lines and sub-source lines.
As shown in FIG. 11, the sub bit line SBL1 is connected to the main bit line MBL1 via the select transistor S11, and the sub bit line SBL2 is connected to the main bit line MBL2 via the select transistor S21. Further, the sub source line SSL1 is connected to the main source line MSL1 via the select transistor S12, and the sub source line SSL2 is connected to the main source line MSL2 via the select transistor S22.

  Memory transistors M11 to M1n (for example, n = 64) are connected in parallel between sub-bit line SBL1 and sub-source line SSL1, and memory transistors M21 to M2n are connected between sub-bit line SBL2 and sub-source line SSL2. Are connected in parallel. The n memory transistors connected in parallel to each other and the two select transistors (S11 and S12 or S21 and S22) constitute a unit block constituting the memory cell array.

The gates of the memory transistors M11 and M21 adjacent in the word direction are connected to the word line WL1. Similarly, the gates of the memory transistors M12 and M22 are connected to the word line WL2, and the gates of the memory transistors M1n and M2n are connected to the word line WLn.
The select transistor S11 adjacent in the word direction is controlled by the select gate line SG11, and the select transistor S21 is controlled by the select gate line SG21. Similarly, the select transistor S12 adjacent in the word direction is controlled by the select gate line SG12, and the select transistor S22 is controlled by the select gate line SG22. The main source lines MSL1 and MSL2 may be shared, and the select transistors SG11 and SG21 may be controlled by a common selection gate line.

In the memory cell array, as illustrated in FIG. 13, a P well W is formed on the surface of the semiconductor substrate SUB. The P well W is insulated and isolated in the row direction by, for example, an element isolation insulating layer ISO having a parallel stripe pattern shape formed by burying an insulator in a trench. A well-in-well (WIW) structure can also be adopted.
Each P well portion separated by the element isolation insulating layer ISO becomes an active region of the memory transistor. N-type impurities are introduced into the well portions of the parallel stripes spaced from each other in the width direction in the active region at a high concentration, whereby sub-bit lines SBL1 and SBL2 (hereinafter referred to as second source / drain regions) , SBL), and sub-source lines SSL1 and SSL2 (hereinafter referred to as SSL) as first source / drain regions.
A stacked insulating film (charge storage film) having a parallel stripe pattern shape perpendicular to the sub-bit line SBL and the sub-source line SSL and including charge storage means is formed inside. On the charge storage film, word lines WL1, WL2, WL3, WL4,... (Hereinafter referred to as WL) that also serve as gate electrodes are formed.
Of the portion of the P-well W between the sub-bit line SBL and the sub-source line SSL, the portion that intersects each word line WL is a channel formation region of the memory transistor. The portion of the sub bit line (second source / drain region) in contact with the channel formation region functions as a drain, and the portion of the sub source line (first source / drain region) in contact with the channel formation region functions as a source.
The upper surface and side walls of the word line WL are covered with an offset insulating layer and a sidewall insulating layer (in this example, a normal interlayer insulating layer is also acceptable).
In these insulating layers, a bit contact plug BC reaching the sub bit line SBL at a predetermined interval and a source contact plug SC reaching the sub source line SSL are formed. These contact plugs BC and SC are conductors, for example, plugs made of, for example, polysilicon or refractory metal, and are provided for every 64 memory transistors in the bit direction.
Main bit lines MBL1, MBL2,... (Hereinafter referred to as MBL) in contact with the bit contact plug BC on the insulating layer, and main source lines MSL1, MSL2,... (Hereinafter referred to as MSL) in contact with the source contact plug SC. Are written alternately. The main bit line and the main source line have a parallel stripe pattern shape that is long in the column direction.

  In the illustrated memory cell array, bit lines and source lines are hierarchized, and there is no need to form bit contact plugs BC and source contact plugs SC for each memory cell. Therefore, there is basically no variation in contact resistance between cells. Bit contact plug BC and source contact plug SC are provided for every 64 memory cells, for example. When the bit contact plug BC and the source contact plug SC are not formed in a self-aligning manner, the offset insulating layer and the sidewall insulating layer are not necessary. In this case, after a normal interlayer insulating film is deposited thickly to embed a memory transistor, a contact is opened by normal photolithography and etching, and a conductive material is embedded in the contact.

It has a pseudo contactless structure in which the sub-bit line (second source / drain region) SBL and the sub-source line (first source / drain) SSL are constituted by impurity regions. For this reason, since there is almost no useless space, when each layer is formed with the minimum dimension F of the wafer process limit, a very small cell area close to 8F ² can be realized.
The bit lines and source lines are hierarchized, and the select memory S11 or S21 separates the parallel memory transistor group in the unselected unit block from the main bit line MBL. For this reason, the capacity of the main bit line MBL is significantly reduced, which is advantageous for high speed and low power consumption. The sub-source line SSL can be separated from the main source line MSL by the action of the select transistor S12 or S22, and the capacitance can be reduced.
In order to further increase the speed, it is preferable that the sub bit line SBL and the sub source line SSL are formed in an impurity region to which silicide is attached, and the main bit line MBL and the main source line MSL are metal wirings.

Various modifications can be made to the memory transistor structure. Hereinafter, these modifications will be described.
The memory transistor is not necessarily formed on the semiconductor substrate. The “semiconductor substrate in which a channel formation region is defined as a surface region” of the present invention includes a well in addition to a substrate bulk. In the case of an SOI type substrate structure, an insulating film is formed on the substrate, and an SOI semiconductor layer is formed on the insulating film. The SOI semiconductor layer in this case can be used as a “semiconductor substrate in which a channel formation region is defined as a surface region” in the present invention.

FIG. 14 is a cross-sectional view showing a modification of the memory transistor structure.
In the memory transistor illustrated in FIG. 14, an N-type low-concentration impurity region LDD having a lower concentration is formed at the inner end of the drain region D and the source region S (only the drain region D side can be formed). have. The high concentration channel region HR is formed, for example, in contact with the channel center side end of the low concentration impurity region LDD on the drain region D side.

For example, in the memory cell array shown in FIG. 13, the low concentration impurity region LDD is formed in the drain region D (corresponding to the sub bit line SBL in FIG. 13) and the source region S (in FIG. 13, in the sub source line SSL). Can be formed in the well in a parallel line shape. That is, a parallel line-shaped mask layer is formed on a well, and first, a low concentration impurity region LDD is formed by ion-implanting N-type impurities at a low concentration on the well surface around the mask layer. Next, sidewall-shaped spacer layers are formed on the two side surfaces in the width direction of the mask layer, and N-type impurities are ion-implanted at a higher concentration into the well surface around the spacer layer to form the drain region D and the source. Region S is formed.
The high-concentration channel region HR can be formed by introducing P-type impurities below the one end of the mask layer by an oblique ion implantation method immediately after the mask layer is formed or after ion implantation at the time of forming the low-concentration impurity region LDD.

It is not essential to have the high-concentration channel region HR, but when the high-concentration channel region HR is formed, electron injection efficiency is higher than that of an element structure that does not have the high-concentration channel region HR.
It is further desirable when both the high concentration channel region HR and the low concentration impurity region LDD are formed. In this case, since the low concentration impurity region LDD functions as a low resistance region for channel traveling carriers (electrons), the relative resistance ratio of the adjacent high concentration channel region HR becomes high, and in the high concentration channel region HR, A larger voltage drop is likely to occur. Therefore, the steepness of the channel direction electric field is further increased in the high concentration channel region HR, and the electron injection efficiency is increased correspondingly. Therefore, further high-speed writing becomes possible.

  A discretized conductor may be used for the charge storage means of the memory transistor. Here, a memory transistor using a large number of mutually insulated conductors (hereinafter referred to as small grain conductors) embedded in the gate dielectric film and having a grain size of, for example, 10 nm or less is used as the charge storage means. explain.

FIG. 15 is a cross-sectional view showing the structure of a memory transistor using a small particle size conductor as charge storage means.
In the memory transistor illustrated in FIG. 15, the gate dielectric film GD includes a bottom dielectric film BTM, discrete small particle conductors MC as charge storage means formed thereon, and small particle conductors. It consists of a dielectric film DF covering the MC.
Other configurations, that is, P well W, channel formation region CH, (high concentration channel region HR), second source / drain region (drain region D or sub-bit line SBL), first source / drain region (source region) S or the sub-source line SSL) and the gate electrode (word line WL) are the same as those in FIG.

The small particle conductor MC is composed of a conductor such as fine amorphous Si _X Ge _1-X (0 ≦ x ≦ 1) or polycrystalline Si _X Ge _1-X (0 ≦ x ≦ 1), for example. Has been. The size (diameter) of the small particle size conductor MC is preferably 10 nm or less, for example, about 4.0 nm. Individual small grain size conductors are spatially separated by a dielectric film DF, for example, at intervals of about 4 nm.
The bottom dielectric film BTM in this example can be appropriately selected within the range from 2.6 nm to 5.0 nm depending on the intended use. Here, the film thickness is about 4.0 nm.

A method of manufacturing the memory transistor illustrated in FIG. 15 will be described.
After forming the P well W, the drain region D, and the source region S (and the high concentration channel region HR), the bottom dielectric film BTM is formed by the same method as described above.
For example, an assembly of Si _X Ge _1-X small-diameter conductors MC generated in the initial process of Si _X Ge _1-X film formation using LP-CVD is formed on the bottom dielectric film BTM. The Si _X Ge _1-X small particle size conductor MC uses silane (SiH ₄ ) or dichlorosilane (DCS), germane (GeH ₄ ), and hydrogen as source gases at a film forming temperature of about 500 ° C. to 900 ° C. It is formed. The density and size of the small particle size conductor MC can be controlled by adjusting the partial pressure or flow rate ratio of silane or dichlorosilane and hydrogen. The higher the hydrogen partial pressure, the higher the density of nuclei that is the basis of the small particle size conductor MC. Alternatively, a non-stoichiometric composition of SiO _X is formed using silane or dichlorosilane and dinitrogen oxide (N ₂ O) as raw material gas at a film forming temperature of about 500 ° C. to 800 ° C., and then high temperature of 900 ° C. to 1100 ° C. By annealing at, SiO ₂ and the small particle conductor phase are separated, and an aggregate of small particle conductors MC embedded in SiO ₂ is formed.
A dielectric film DF is formed by LP-CVD, for example, with a thickness of about 7 nm so as to embed the small-diameter conductor MC. In this LP-CVD, the source gas is a mixed gas of dichlorosilane (DCS) and dinitrogen oxide (N ₂ O), and the substrate temperature is 700 ° C., for example. At this time, the small particle conductor MC is embedded in the dielectric film DF.
Thereafter, a conductive film to be the word line WL is formed, and the memory transistor is completed through a process of patterning the conductive film collectively.

  The small particle conductor MC formed in this way functions as a carrier trap discretized in the plane direction. Each small particle conductor MC can hold several injection electrons. Note that the small particle conductor MC may be further reduced to hold a single electron.

By the way, the structure of the gate dielectric film GD of the memory transistor is not limited to the three-layer dielectric film mainly used in the MONOS type described in the embodiment and the above-described small grain size conductor type. The requirement of the gate dielectric film is that the charge storage means such as charge traps are discretized, and various other configurations that satisfy these requirements can be adopted.
For example, a so-called MNOS type or the like may have a two-layer structure of a bottom dielectric film BTM made of silicon dioxide or the like and a film CHS made of silicon nitride or the like and having a charge holding ability. Good.

It is also known that dielectric films made of metal oxides such as aluminum oxide Al ₂ O ₃ , tantalum oxide Ta ₂ O ₅ , zirconium oxide ZrO _2, etc. also contain many traps. In a similar film structure, the film can be used as a film CHS having a charge holding capability.
Further, when other metal oxides are raised as the material of the bottom dielectric film, for example, there are films made of oxides of titanium, hafnium, lanthanum, or films made of tantalum, titanium, zirconium, hafnium, lanthanum silicates. Can also be adopted.
When aluminum oxide (Al ₂ O ₃ ) is selected as the material for the bottom dielectric film, for example, aluminum chloride (AlCl ₃ ), carbon dioxide (CO ₂ ), and hydrogen (H ₂ ) are used as gas raw materials. CVD method or thermal decomposition of aluminum alkoxide (Al (C ₂ H ₅ O) ₃ , Al (C ₃ H ₇ O) ₃ , Al (C ₄ H ₉ O) _3, etc.) is used.
When tantalum oxide (Ta ₂ O ₅ ) is selected as the material for the bottom dielectric film, for example, tantalum chloride (TaCl ₅ ), carbon dioxide (CO ₂ ), and hydrogen (H ₂ ) are used as gas raw materials. CVD method, or thermal decomposition of TaCl ₂ (OC ₂ H ₅ ) ₂ C ₅ H ₇ O ₂ or Ta (OC ₂ H ₅ ) ₅ is used.
When zirconium oxide (ZrO _x ) is selected as the material for the bottom dielectric film, for example, a method of sputtering Zr in an oxygen atmosphere is used.

Similarly, the charge storage film is not limited to silicon dioxide, silicon nitride, and silicon oxynitride. For example, the charge storage film may be selected from any material of aluminum oxide Al ₂ O ₃ , tantalum oxide Ta ₂ O ₅ , and zirconium oxide ZrO _2. Good. The method for forming these metal oxides is as described above.
Further, the top dielectric film TOP may be a film made of an oxide of titanium, hafnium, lanthanum, or a film made of tantalum, titanium, zirconium, hafnium, lanthanum silicate as another metal oxide film. You can also.

According to the present embodiment, the so-called erasing data rewriting method eliminates the need to consider the reduction of the erasing voltage, and the voltage of the entire operation can be lowered only by reducing the voltage at the time of writing. . For lowering the voltage at the time of writing, hot electron injection using ionization collision is used, the barrier height is reduced by selecting the material of the bottom dielectric film BTM, and the concentration of the high concentration channel region HR is increased to some extent. By doing so, it is possible to operate with a single power supply voltage. When the back bias is performed, the charge injection efficiency is further increased, and driving with a power supply voltage of about 2.5 to 3.3 V is possible. In the above description, data writing is performed by selectively injecting electrons. However, other operations such as extracting electrons, injecting holes, or extracting holes can be performed. Corresponding to these, data may be erased by operations such as injecting electrons, extracting holes, or injecting holes.
Adopting such a data rewriting method without erasing can be realized by selecting an appropriate application.

1 is a block diagram showing a schematic configuration of a memory block of a nonvolatile memory device according to an embodiment The figure which shows the data storage area of a memory cell array typically A diagram schematically showing a data storage area in units of word line sectors of a memory cell array Schematic diagram when data storage area of memory cell array is specified by block Equivalent circuit diagram of source isolated NOR type memory cell array Plan view of source isolated NOR type memory cell array Bird's-eye view seen from the cross-sectional side along line A-A 'in FIG. Enlarged sectional view of the memory transistor in the channel direction Conceptual diagram of data writing operation and diagram showing acceleration electric field of electrons in the channel direction Sectional drawing of the non-volatile memory device which shows the formation area of a memory cell array, and the formation area of a memory peripheral circuit or a logic circuit block Equivalent circuit diagram showing a modification of the memory cell array Plan view of a memory cell array of a modification example Bird's eye view seen from the cross-sectional side along the line BB 'in FIG. Sectional drawing which shows the modification of memory transistor structure Sectional drawing which shows the modification of the memory transistor structure using the small particle size conductor as a charge storage means

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2a-9 ... Memory peripheral circuit, BL1, etc. Bit line, BTM ... Bottom dielectric film (lowermost dielectric film), CH ... Channel formation region, CHS ... Main charge storage film, TOP ... Top Dielectric film, GD ... charge storage film, HR ... high concentration channel region, M11, etc .... memory transistor, S ... source region, D ... drain region, MBL1, etc .... main bit line, MSL1, etc .... main source line, SBL1, etc. Sub-bit line, SL1, etc .... Source line, SSL1, etc. Sub-source line, SUB ... Semiconductor substrate, W ... P well, WL1, etc. Word line

Claims (11)

A memory cell array in which memory cells made of nonvolatile memory transistors are arranged in a matrix; and
A memory peripheral circuit for controlling rewriting of data stored in the memory cell array at most N times (N: a positive integer),
The memory peripheral circuit stores an initial value of the data in an arbitrary M-bit memory cell group in a storage area having a capacity of (N + 1) times the number of bits M required for storing the data, When there is a rewrite instruction, instead of erasing the initial value and writing a new data value in the same memory cell group, another unused M-bit memory in the (N + 1) × M-bit storage area A cell group is selected and a new data value is written, and each time a data rewrite instruction is issued, selection of the other unused M-bit memory cell group and new data to the unused memory cell group are selected. A non-volatile semiconductor memory device that controls the memory cell array such that value writing is repeated at most N times in the storage area of (N + 1) × M bits. Each time the memory peripheral circuit is instructed to rewrite data to the memory cell array, the memory peripheral circuit is dedicated to the data according to the number of bits M of data to be newly written and the maximum number N of possible rewrites ( The nonvolatile semiconductor memory device according to claim 1, wherein control for securing a storage area of (N + 1) × M bits is performed. The memory peripheral circuit reads a value from an M-bit memory cell group written last in the (N + 1) × M-bit storage area corresponding to data for which a read instruction has been received when reading data. A nonvolatile semiconductor memory device according to claim 1. The nonvolatile semiconductor memory device according to claim 1, wherein the memory peripheral circuit is configured to be able to change a maximum number of rewrites N for each data in accordance with an input signal. Each of the memory transistors is
A channel formation region of a first conductivity type defined in the surface region of the semiconductor substrate;
A first source / drain region formed on one side of the channel formation region and electrically connected to the memory peripheral circuit;
A second source / drain region formed on the other side of the channel formation region and electrically connected to the memory peripheral circuit;
A charge storage film formed of at least a plurality of dielectric films on the channel formation region;
A gate electrode formed on the charge storage film and electrically connected to the memory peripheral circuit,
The barrier height on the conduction band side formed between the lowermost dielectric film constituting the charge storage film and the semiconductor substrate is set lower than the barrier height of silicon dioxide and silicon,
The memory peripheral circuit generates a first voltage and a second voltage at the time of writing data, and the generated second voltage is based on the potential of the first source / drain region. Applying to the drain region, applying the generated second voltage to the gate electrode, generating hot electrons by ionization collision on the second source / drain region side, and generating the generated hot electrons in the first region; The nonvolatile semiconductor memory device according to claim 1, wherein the charge storage film is injected from the source / drain region side of 2. 6. The channel formation region has a high-concentration channel region of a first conductivity type having a higher concentration than other regions of the channel formation region at least at an end portion on the second source / drain region side. A nonvolatile semiconductor memory device according to claim 1. The semiconductor substrate is electrically connected to the memory peripheral circuit;
The memory peripheral circuit generates a voltage for reverse-biasing a PN junction formed between the semiconductor substrate and the second source / drain region when the hot electrons are injected, and the generated voltage is used for the semiconductor The nonvolatile semiconductor memory device according to claim 5, wherein the nonvolatile semiconductor memory device is applied to a substrate. The semiconductor substrate is electrically connected to the memory peripheral circuit;
The memory peripheral circuit generates a first polarity voltage and a second polarity voltage whose potential difference is equal to the second voltage when writing data, and the generated first polarity voltage is applied to the gate electrode. The nonvolatile semiconductor memory device according to claim 5, wherein the second polarity voltage generated by applying the voltage is applied to the semiconductor substrate. A memory block including the memory cell array and the memory peripheral circuit;
A logic circuit block;
The film thickness of the thickest gate insulating film of the transistor in the memory peripheral circuit is set to be the same as the film thickness of the gate insulating film of the input / output transistor in the logic circuit block,
Each of the absolute value of the first polarity voltage and the absolute value of the second polarity voltage generated when the memory peripheral circuit writes data is less than the absolute value of the withstand voltage of the input / output transistor and / or the burn-in voltage. The nonvolatile semiconductor memory device according to claim 8, wherein the nonvolatile semiconductor memory device is set. This is a method of operating a nonvolatile semiconductor memory device that rewrites data stored in a memory cell array in which memory cells made of nonvolatile memory transistors are arranged in a matrix at most N times (N is a positive integer). And
A write step of storing an initial value of the data in an arbitrary M-bit memory cell group in a storage area having a capacity of (N + 1) times the number of bits M required for storing the data;
When there is an instruction to rewrite the data, instead of erasing the initial value and writing a new data value in the same memory cell group, another unused M in the storage area of (N + 1) × M bits. A bit memory cell group is selected and a new data value is written, and each time a data rewrite instruction is issued, the other unused M bit memory cell group is selected and the unused memory cell group is selected. A rewriting step of repeating writing of a new data value at most N times in the storage area of (N + 1) × M bits;
A method for operating a nonvolatile semiconductor memory device including: Each of the memory transistors is
A channel formation region of a first conductivity type defined in the surface region of the semiconductor substrate;
A first source / drain region formed on one side of the channel formation region and electrically connected to the memory peripheral circuit;
A second source / drain region formed on the other side of the channel formation region and electrically connected to the memory peripheral circuit;
A charge storage film formed of at least a plurality of dielectric films on the channel formation region;
A gate electrode formed on the charge storage film and electrically connected to the memory peripheral circuit,
The barrier height on the conduction band side formed between the lowermost dielectric film constituting the charge storage film and the semiconductor substrate is set lower than the barrier height of silicon dioxide and silicon,
The memory peripheral circuit generates a first voltage and a second voltage at the time of writing data, and the generated second voltage is based on the potential of the first source / drain region. Applying to the drain region, applying the generated second voltage to the gate electrode, generating hot electrons by ionization collision on the second source / drain region side, and generating the generated hot electrons in the first region; The operation method of the non-volatile semiconductor memory device according to claim 10, wherein the charge storage film is injected from the source / drain region side of 2.

Images