KR20090075953A - Method for manufacturing semiconductor device - Google Patents

Abstract

A manufacturing method of the semiconductor device is provided, which prevents the weak point problem by forming a word line. In the active area, the tunnel insulating layer and the first conductive film(114) are formed. In the element isolation region, the element isolation film(116) is formed. The dielectric film and the second conductive film(120) are formed in the first electric conduction membrane upper part including the element isolation film. The second conductive film of the dummy cell pattern region is removed. The gate of the real cell pattern region is patterned while removing the second conductive film of the dummy cell pattern region. The width of the element isolation film formed in the dummy cell pattern region is widely formed wider than the width of the element isolation film formed in the real cell pattern region.

Description

Method for manufacturing semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, a semiconductor device capable of solving the problem of lowering the reliability of a device generated as the effective field height (EFH) is lowered in a region having a low pattern density. It relates to a method for producing.

Among the semiconductor devices, a flash memory device may include a cell region and a peripheral circuit region. The cell region includes a plurality of memory cells and select transistors, and the peripheral circuit region includes a plurality of high voltage and low voltage transistors.

In general, the cell region has a higher pattern density than the peripheral circuit region because a plurality of memory cells in which data is stored are densely packed. On the other hand, since transistors in the peripheral circuit region use a higher voltage than elements in the cell region, such as applying a voltage, the width of the transistor is wider than that of the memory cell. Wider Due to the difference in pattern density, if the planarization process is performed after forming the insulating film for device isolation, a difference in polishing rate between the cell region and the peripheral circuit region may occur. That is, the polishing rate in the cell region where the density of the pattern is denser than the peripheral circuit region is slower than the peripheral region.

The cell region may include a real cell pattern region and a dummy cell pattern region at an edge of the real cell pattern region. In this case, dummy patterns may be formed in the dummy cell pattern region to reduce a difference in pattern density from the real cell pattern region. That is, in the dummy cell pattern region in which the dummy patterns are formed, a space of the active region is wider than that of the real cell pattern region, and thus, a space of the device isolation region may also be wider. When the etching process for adjusting the effective field height (EFH) is performed on the dummy cell pattern region in which the dummy patterns are formed and the device isolation layer in the real cell pattern region in which the real cell patterns are formed, a dummy cell having a large space in the device isolation region is formed. Since dishing occurs in the device isolation layer of the pattern region, the EFH may be lower than that of the real cell pattern region.

That is, even though the patterns formed in the dummy cell pattern region are dummy patterns, since the dummy patterns share a control gate with the real cell patterns formed in the real cell pattern region, the EFH of the dummy cell pattern region is lowered as described above. As the distance between the gate and the active region of the substrate becomes closer, the presence of a weak point in the control gate and the well increases the capacitance at the weak point, resulting in a bias drop and Due to the leakage phenomenon, a problem may occur in all operations in which a bias is applied to the control gate, for example, a program, erase, and read operation.

In addition, when the EFH of the dummy cell pattern region decreases and the variation of the EFH between the real cell pattern region and the dummy cell pattern region increases, the variation of the coupling ratio in the floating gate increases, thereby greatly increasing the cell distribution. In addition, a problem occurs that causes cell failure by causing a fail through the weak point.

In order to solve the above-described problem, the present invention can solve the problem of lowering the reliability of the device caused by the low effective field height (EFH) in the cell edge region having a low pattern density. An object of the present invention is to provide a method for preparing the same.

According to an aspect of the present invention, there is provided a semiconductor substrate including a real cell pattern region and a dummy cell pattern region, a tunnel insulating layer and a first conductive layer are formed in an active region, and a device substrate is formed in an element isolation region. ; Forming a dielectric film and a second conductive film on the first conductive film including the device isolation film; And removing the second conductive layer in the dummy cell pattern region.

In the present invention, the gate of the real cell pattern region is patterned while the second conductive layer of the dummy cell pattern region is removed.

In the present invention, the width of the device isolation layer formed in the dummy cell pattern region is wider than the width of the device isolation layer formed in the real cell pattern region.

According to the present invention, a word line WL is formed by forming a control gate material only in a region excluding a portion where a weak point exists, that is, in a real cell pattern region, when forming a stacked gate pattern of a flash memory device. As the EFH is lowered, a problem caused by the variation of the EFH between the real cell pattern region and the dummy cell pattern region is increased, thereby preventing the weak point problem. Accordingly, the overall cell operation can be improved, thereby improving cell reliability and yield.

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

Descriptions of technical contents that are well known in the art to which the present invention pertains and are not directly related to the present invention will be omitted. This is to more clearly communicate without obscure the subject matter of the present invention by omitting unnecessary description.

1 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1, a tunnel insulating layer 112 and a first conductive layer 114 are formed in an active region, and a device isolation layer is formed in an isolation region, including a real cell pattern region A and a dummy cell pattern region B. There is provided a semiconductor substrate 110 on which 116 is formed. In this case, memory cells in which actual data is stored are formed in the real cell pattern region A. FIG.

Hereinafter, the steps in which the semiconductor substrate 110 is provided will be briefly described.

The tunnel insulating layer 112 and the first conductive layer 114 are sequentially formed on the semiconductor substrate 110. The tunnel insulating film 112 is formed of an oxide film, and the first conductive film is formed of a polysilicon film for a floating gate.

Subsequently, after the device isolation mask (not shown) is formed on the first conductive film 114, an exposure and development process is performed on the device isolation mask to form a photoresist pattern (not shown). The device isolation mask may be patterned according to the photoresist pattern to form an device isolation mask pattern (not shown). Subsequently, after the photoresist layer pattern is removed, an etching process is performed according to the device isolation mask pattern to form the first conductive layer 114 and the tunnel insulation layer 112, and a portion of the semiconductor substrate 110 is removed to form a trench (not shown). ). As a result, a trench is formed in the isolation region of the real cell pattern region A and the dummy cell pattern region B. Since the plurality of memory cells are included in the real cell pattern region A, the trench is formed in the dummy cell pattern region B. In comparison, the pattern density of the trench can be denser.

Subsequently, in order to alleviate the etching damage generated during the trench formation, an oxidation process may be performed to form a wall oxide film (not shown) on the sidewalls and the bottom of the trench. In addition, a liner insulating layer (not shown) may be formed on the sidewalls and the bottom of the trench including the wall oxide layer using high density plasma oxide (HDP). The liner insulating layer may include a function capable of maximally suppressing contact between the tunnel insulating layer 112 and the insulating layer to be subsequently formed in the device isolation region.

Next, an insulating film (not shown) is formed on the semiconductor substrate 110 to fill the trench. In this case, the insulating film may be formed by a coating method using a spin on glass (SOG) film. Thereafter, a conventional chemical mechanical polishing (CMP) process is performed on the insulating layer so that the insulating layer remains only in the region where the trench is formed, thereby forming the device isolation layer 116.

Subsequently, an etching process using a dry or wet method is performed on the resultant as described above to adjust the effective field height (EFH) of the device isolation layer 116. At this time, the difference of the etching rate according to the pattern density difference between the real cell pattern region A and the dummy cell pattern region B, that is, the variation of the EFH is increased due to the loading effect, thereby increasing the dummy cell pattern region B. ) Can lower the EFH. However, the problem that the EFH of the dummy cell pattern region B is lowered in a subsequent process according to the present invention can be improved.

Subsequently, a dielectric film 118 is formed over the entire structure of the semiconductor substrate 110 including the surface of the first conductive film 114. The dielectric film 118 may be formed of an ONO (Oxide / Nitride / Oxide) film. Thereafter, the second conductive film 120 is formed on the semiconductor substrate 110 including the dielectric film 118. The second conductive layer 120 may be formed of a stacked structure of a control gate polysilicon layer and a metal layer. Here, in the etching process for controlling the EFH, the variation of the EFH increases due to the difference in the etch rate according to the pattern density difference between the real cell pattern region A and the dummy cell pattern region B, so that the dummy cell pattern region B Since the EFH is lowered, the distance between the second conductive layer 120 and the active region of the semiconductor substrate 110 in the dummy cell pattern region B is closer to the weak point between the second conductive layer and the well. ) May be present.

Accordingly, in the present invention, in order to prevent a problem in which cell characteristics deteriorate due to an increase in capacitance in a portion where the weak point exists as described above, an area excluding the area where the weak point exists, that is, a real cell pattern. A word line is formed only in the region A. FIG.

That is, in order to form the word line WL only in the real cell pattern region A, the second conductive layer 120 and the dielectric layer 118 of the dummy cell pattern region B are removed from the resultant as described above. . In this case, the gate of the real cell pattern region A is patterned while the second conductive layer 120 and the dielectric layer 118 of the dummy cell pattern region B are removed. That is, the second conductive film 120 and the dielectric film 118 in the real cell pattern region A may be patterned. As a result, as the second conductive layer 120 (that is, the word line) remains only in the real cell pattern region A, the weak point problem may be prevented.

Next, FIG. 2 is a plan view seen from the top of FIG. 1. 1 is a cross-sectional view taken along the line AA ′ of FIG. 2.

Conventionally, although the word line 120 is formed to the dummy cell pattern region B, the word line 120 is formed long. However, in the present invention, the word line 120 is formed only in the real cell pattern region A. In this case, the connection between the shortened word line 120 and an external circuit can be made by forming a metal wire longer than before, and as a result, the weak point problem can be solved without changing the operation of the device.

As a result, the word line can be prevented in advance by forming a word line only in an area except the portion where the weak point problem exists, that is, the real cell pattern area A, thereby improving overall cell operation. This can improve the reliability and yield of the cell.

Although specific embodiments of the present invention have been described with reference to the drawings, this is intended to be easily understood by those skilled in the art and is not intended to limit the technical scope of the present invention. Therefore, the technical scope of the present invention is determined by the matters described in the claims, and the embodiments described with reference to the drawings may be modified or modified as much as possible within the technical spirit and scope of the present invention.

1 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

FIG. 2 is a plan view seen from the top of FIG. 1.

110 semiconductor substrate 112 tunnel insulating film

114: first conductive film 116: device isolation film

118 dielectric film 120 second conductive film, word line

Claims (3)

Providing a semiconductor substrate including a real cell pattern region and a dummy cell pattern region, a tunnel insulating layer and a first conductive layer formed in an active region, and a device isolation layer formed in a device isolation region; Forming a dielectric film and a second conductive film on the first conductive film including the device isolation film; And And removing the second conductive film of the dummy cell pattern region. The method of claim 1, And patterning a gate of the real cell pattern region while removing the second conductive film of the dummy cell pattern region. The method of claim 1, And a width of the device isolation layer formed in the dummy cell pattern region is larger than a width of the device isolation layer formed in the real cell pattern region.

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