US20110256723A1 - Method for forming semiconductor device - Google Patents

Method for forming semiconductor device Download PDF

Info

Publication number
US20110256723A1
US20110256723A1 US12/981,414 US98141410A US2011256723A1 US 20110256723 A1 US20110256723 A1 US 20110256723A1 US 98141410 A US98141410 A US 98141410A US 2011256723 A1 US2011256723 A1 US 2011256723A1
Authority
US
United States
Prior art keywords
spacer
forming
hard mask
pattern
sacrificial hard
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/981,414
Inventor
Ki Lyoung Lee
Cheol Kyu Bok
Jung Hyung Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
SK Hynix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to KR10-2010-0034748 priority Critical
Priority to KR1020100034748A priority patent/KR101159954B1/en
Application filed by SK Hynix Inc filed Critical SK Hynix Inc
Assigned to HYNIX SEMICONDUCTOR INC. reassignment HYNIX SEMICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BOK, CHEOL KYU, LEE, JUNG HYUNG, LEE, KI LYOUNG
Publication of US20110256723A1 publication Critical patent/US20110256723A1/en
Application status is Abandoned legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11517Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate
    • H01L27/11519Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11517Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate
    • H01L27/11526Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region
    • H01L27/11529Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region of memory regions comprising cell select transistors, e.g. NAND

Abstract

A method for forming a semiconductor device is disclosed. A method for forming a semiconductor device includes forming a first sacrificial hard mask layer over a semiconductor substrate including an etch layer, forming a first spacer over the first sacrificial hard mask layer, forming a first sacrificial hard mask pattern by etching the first sacrificial hard mask layer using the first spacer as an etch mask, forming a second spacer at both sidewalls of the first sacrificial hard mask pattern, partially isolating the second spacer, and forming a pad pattern over the second spacer. As a result, a line-and-space pattern such as a control gate of the NAND flash memory and a pad portion coupled to a drain contact in an X-decoder of a peripheral circuit region can be easily implemented.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • The priority of Korean patent application No. 10-2010-0034748 filed on 15 Apr. 2010, the disclosure of which is hereby incorporated in its entirety by reference, is claimed.
  • BACKGROUND OF THE INVENTION
  • Embodiments of the present invention relate to a method for forming a semiconductor device, and more particularly to a method for forming a semiconductor device using double spacer patterning technology.
  • Recently, most of electronic appliances comprise a semiconductor device. The semiconductor device comprises electronic elements such as a transistor, a resistor and a capacitor. These electronic elements are designed to perform a partial function of electronic elements, and are integrated on a semiconductor substrate. For example, electronic elements such as a computer or a digital camera include a memory chip for storing information and a processing chip for controlling information. The memory chip and the processing chip include electronic elements integrated on a semiconductor substrate.
  • The semiconductor devices have a need for an increase in an integration degree thereof, in order to satisfy consumer demands for superior performance and low prices. Such an increase in the integration degree of a semiconductor device entails a reduction in a design rule, causing patterns of a semiconductor device to be increasingly reduced. Although an entire chip area is increased in proportion to an increase in memory capacity as a semiconductor device is becoming super miniaturized and highly integrated, a unit cell area where patterns of a semiconductor device are actually formed is decreased. Accordingly, since a greater number of patterns should be formed in a limited cell area in order to achieve a desired memory capacity, there is a need for formation of microscopic (fine) patterns having a reduced critical dimension scale.
  • A representative method for forming such a fine pattern is a Double Patterning Technology (DPT). The DPT may be classified into a Double Expose Etch Technology (DE2T) and a Spacer Patterning Technology (SPT) that uses a spacer. The DE2T forms first patterns with a first distance subject to a given critical dimension scale and then forms a second pattern between neighboring first patterns. Thus, the distance between neighboring second patterns are within the given critical dimension scale but the distance between neighboring the first and the second patterns surpasses the given critical dimension scale.
  • Meanwhile, as semiconductor devices are becoming highly integrated, it is more difficult to form a line-and-space pattern of 40 nm or less using a one-time exposure process due to the limitation of ArF immersion exposure tools having a numerical aperture (NA) of 1.35. In order to solve such problems, a technology for employing a hyper numerical aperture (Hyper NA) using a high index fluid (HIF) material has recently been proposed. However, it is very difficult to apply the aforementioned technology to a semiconductor fabrication process. For an alternative proposal, a method for forming a fine pattern of 30 nm or less using an extreme ultra violet (EUV) exposure light source having a wavelength of 13.4 nm has been proposed. Up to now, the EUV has many technical limitations in exposure source, tool, photoresist film, etc., so that it is difficult to develop a device using an EUV exposure light source.
  • In conclusion, it is necessary to propose and develop a method for forming a fine pad pattern which can be connected to a control gate of a NAND flash memory or a drain contact of an X-decoder of a peripheral circuit region.
  • BRIEF SUMMARY OF THE INVENTION
  • Various embodiments of the present invention are directed to providing a method for forming a semiconductor device that substantially obviates one or more problems due to limitations and disadvantages of the related art.
  • An object of the present invention is to provide a method for forming a semiconductor device, which can solve the problems of the related art. According to the related art, it is difficult to implement a semiconductor device due to limitations in the ArF immersion exposure device and difficulty in the EUV exposure device.
  • In accordance with an aspect of the present invention, a method for forming a semiconductor device includes forming a first sacrificial hard mask layer over a semiconductor substrate including an underlying layer ,the underlying layer being provided below the first sacrificial hard mask, forming a first spacer over the first sacrificial hard mask layer, forming a first sacrificial hard mask pattern by etching the first sacrificial hard mask layer using the first spacer as an etch mask, forming a second spacer at sidewalls of the first sacrificial hard mask pattern, partially isolating the second spacer, forming a pad mask pattern over the second spacer, and forming a pad pattern by etching the etch layer using the pad mask pattern.
  • The method may further include, after forming the first sacrificial hard mask layer, forming a sub hard mask layer over the first sacrificial hard mask layer.
  • The sub hard mask layer may include polysilicon.
  • The forming of the first sacrificial hard mask pattern may include forming a sub hard mask pattern by etching the sub hard mask layer using the first spacer as an etch mask, removing the first spacer, and etching the first sacrificial hard mask layer using the sub hard mask pattern as an etch mask.
  • The removing of the first spacer may be performed by wet-etching.
  • The removing of the first spacer may use a hydrofluoric acid (HF)-based etching solution or a H3PO4-based etching solution.
  • The forming of the first spacer may include forming a second sacrificial hard mask pattern over the first sacrificial hard mask layer, forming a first spacer material over the second sacrificial hard mask pattern, performing a first etch-back process on the first spacer material, and removing the second sacrificial hard mask pattern.
  • The forming of the first spacer material may be performed at a temperature substantially 20° C.˜substantially 400° C.
  • The forming of the second spacer may include forming a second spacer material over the first sacrificial hard mask pattern, performing a secondary etch-back process on the second spacer material, and removing the first sacrificial hard mask pattern.
  • The forming of the second spacer material may be performed at a temperature substantially 20° C.˜substantially 400° C.
  • The partially isolating of the second spacer may include forming a cutting mask to expose some parts of the second spacer, and etching the second spacer using the cutting mask as an etch mask.
  • The method may further include forming a target hard mask layer over the underlying layer.
  • The target hard mask layer may include a polysilicon layer.
  • In accordance with another aspect of the present invention, a method for forming a semiconductor device includes forming an underlying layer over a semiconductor substrate, forming a first spacer pattern defining a drain select line (DSL) over the underlying layer, the DSL extending from a cell region to a peripheral region in the semiconductor substrate defining a pad contact region coupled to the first spacer pattern in the peripheral region, forming a mask pattern at a sidewall of the first spacer pattern in the pad contact region to obtain a pad mask pattern, patterning the underlying layer using the first spacer pattern and the pad mask pattern as an etch mask to form a DSL extending from the cell region to the peripheral region and a pad contact pattern coupled to the DSL in the peripheral region.
  • The pad mask pattern may be wider than the first spacer pattern.
  • Distance between neighboring first spacer patterns in the pad contact region may be larger than the distance between neighboring first spacer patterns in the cell region.
  • Distance between neighboring first spacer patterns in the pad contact region may be larger than the distance between neighboring first spacer patterns in a non-pad contact region of the peripheral region.
  • The first spacer pattern may be formed using any of a Double Expose Etch Technology (DE2T), a Spacer Patterning Technology (SPT) and a Double Patterning Technology (DPT).
  • The peripheral region may include a plurality of pad contact regions, the plurality of pad contact regions are zigzagged in arrangement.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1A to 1N illustrate a method for forming a semiconductor device according to the present invention. In each of FIGS. 1A to 1N, (i) is a plan view illustrating a method for forming a semiconductor device according to an embodiment of the present invention, and (ii) is a cross-sectional view taken along the line x-x′ of the semiconductor device shown in (i).
  • DESCRIPTION OF EMBODIMENTS
  • Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
  • FIGS. 1A to 1N illustrate a method for forming a semiconductor device according to the present invention. In each of
  • FIGS. 1A to 1N, (i) is a plan view illustrating a method for forming a semiconductor device according to an embodiment of the present invention, and (ii) is a cross-sectional view taken along the line x-x′ of the semiconductor devices shown in (i) according to an embodiment of the present invention.
  • Prior to describing the method for forming the semiconductor device according to the present invention, a method for forming a pad region coupled to a drain contact for an X-decoder in a peripheral circuit region according to one embodiment of the present invention will be described in detail. The scope or spirit of the present invention is not limited to the method for forming a pad region coupled to the drain contact for the X-decoder. A method for forming a semiconductor device according to the present invention may also be applied to any patterning method for forming a microscopic device, especially for a device at a 10 nm level or so.
  • Referring to FIG. 1A, an underlying layer 102 to be etched, a target hard mask layer 104, a first sacrificial hard mask layer 109, a sub hard mask layer 110, and a second sacrificial hard mask layer 115 are sequentially deposited over the semiconductor substrate 100, and a first sacrificial photo resist pattern 116 is finally formed. Preferably, the first sacrificial hard mask layer 109 may be a stacked structure of a first sacrificial film 106 and a silicon oxide nitride film 108. Preferably, the second sacrificial hard mask layer 115 may be a stacked structure of a second sacrificial film 112 and a silicon oxide nitride film 114. In this case, a NAND flash control gate, that includes an Oxide/Nitride/Oxide (ONO) dielectric film, a gate poly, tungsten, and a capping silicon nitride film, may be additionally disposed under the underlying layer 102. However, the scope or spirit of the present invention is not limited thereto and can be modified by those skilled in the art in various ways.
  • Preferably, the underlying layer 102 to be etched may be an oxide layer, and a target hard mask layer 104 and a sub hard mask layer 110 may be formed of polysilicon. If the target hard mask layer 104 is formed of polysilicon, production cost of polysilicon is lower than amorphous carbon, and a wiggling phenomenon in which a high-aspect-ratio pattern is wiggled while being etched is prevented from being generated in fine pattern formation. However, although the target hard mask layer 104 is exemplarily formed of polysilicon for convenience of description, the target hard mask layer 104 may also be formed of other materials as necessary.
  • Preferably, the first sacrificial film 106 and the second sacrificial film 112 may be formed of amorphous carbon or spin on carbon (SOC) material. Both forms of carbon are easily removed by O2 ashing, so that only spacers formed at sidewalls of the first and second sacrificial films 106 and 112 remain.
  • In addition, a pitch of the first photoresist pattern 116 may be changed according to a pitch of a target pattern, i.e., a pad pattern 104 a shown in FIG. 1 n. For example, if the target pattern has a pitch of X, it is preferable that a pitch of the first photoresist pattern 116 be set to 4X. In this case, the silicon oxide nitride film 108 and the silicon oxide nitride film 114 are not limited only to the above-mentioned materials, and may also be formed of various materials serving as a hard mask as necessary. Therefore, application of materials other than the silicon oxide nitride film 108 and the silicon oxide nitride film 114 may be readily used by those skilled in the art without departing from the scope and spirit of this invention.
  • Referring to FIG. 1B, a second sacrificial hard mask layer 115 is etched using the first photoresist pattern 116 as an etch mask, so that a stacked structure of the second sacrificial film pattern 112 a and the silicon nitride film pattern 114 a is formed. In this case, the second sacrificial film pattern 112 a decides the height of a spacer, so that it is preferable that the second sacrificial film pattern 112 a has a predetermined height defining the spacer.
  • Referring to FIG. 1C, a first spacer material 118 is formed over the entire surface. Preferably, the first spacer material 118 may be formed of a material that can be formed at a temperature (e.g., 20° C.˜400° C.) lower than that of the second sacrificial film 112, so that the first spacer material 118 cannot experience lifting due to thermal stress and can prevent a profile of the second sacrificial film pattern 112 a from being distorted. For example, it is preferable that the first spacer material 118 be formed of a low-temperature oxide film or low-temperature nitride film having good step coverage.
  • Referring to FIGS. 1D and 1E, a first etch-back process is performed on the first spacer material 118, the first spacer material 118 is etched to expose the top surface of the second sacrificial film pattern 112 a, so that a first spacer 118 a is formed (See FIG. 1D). During the etching process, a silicon nitride film pattern 114 a, which was formed over the second sacrificial film pattern 112 a, is also removed. Subsequently, it is preferable that the second sacrificial film pattern 112 a be removed by O2 ashing (See FIG. 1E). In this case, the first spacer 118 a may be formed in a horn shape.
  • Referring to FIG. 1F, the sub hard mask layer 110 is etched using the first spacer 118 a as an etch mask, so that a sub hard mask pattern 110 a is formed. When a structure underlying the sub hard mask layer 110 is etched using the horn-shaped first spacer 118 a as an etch mask, the formation of the sub hard mask pattern 110 a may prevent the underlying structure from being asymmetrically etched. That is, after the sub hard mask pattern 110 a is configured in a horizontal symmetric form by first etching the sub hard mask layer 110 using the first spacer 118 a as an etch mask, the lower structure can be etched in a symmetrical form using the sub hard mask pattern 110 a as an etch mask. As a result, a spacer pattern to be formed in a subsequent process can be easily formed.
  • Next, the first spacer 118 a is removed, preferably by wet-etching. If the first spacer material is a low-temperature oxide layer, it is preferable that the first spacer be etched using hydrofluoric acid (HF)-based etching solution. If the spacer material is a low-temperature nitride layer, it is preferable that the spacer be etched using H3PO4-based etching solution.
  • Referring to FIG. 1G, a second photoresist pattern 120 is formed over the sub hard mask pattern 110 a. In a subsequent process, a pad pattern is formed at both ends of the second photoresist pattern 120, so it is preferable that the second photoresist pattern 120 be formed to have enough width for separation of the pad pattern.
  • Referring to FIG. 1H, the first sacrificial hard mask layer 109 is etched using the sub hard mask pattern 110 a and the second photoresist pattern 120 as an etch mask, so that the first sacrificial hard mask pattern including the silicon oxide nitride film pattern 108 a and the first sacrificial film pattern 106 a is formed.
  • Referring to FIG. 1I, a second spacer material 122 is formed over the entire surface. Preferably, the second spacer material 122 may be formed of a material that can be formed at a temperature lower than that of the first sacrificial film 106, e.g., 20° C.˜400° C., so that the second spacer material 122 is not lifted due to thermal stress and a profile of the first sacrificial film pattern 106 a is not distorted. For example, it is preferable that the second spacer material 122 be formed of a low-temperature oxide film or low-temperature nitride film having good step coverage.
  • Referring to FIGS. 1J and 1K, an etch-back process is performed on the second spacer material 122, wherein the second spacer material 122 is etched to expose the top surface of the first sacrificial film pattern 106 a, so that a second spacer 122 a is formed (See FIG. 1J). During the etching process, a silicon oxide nitride film pattern 108 a formed over the first sacrificial film pattern 106 a is also removed. Subsequently, it is preferable that the first sacrificial film pattern 106 a be removed by O2 ashing (See FIG. 1K).
  • Referring to FIG. 1L, a third photoresist pattern 124 is selectively formed to expose an edge of the upper surface, and an end of the second spacer 122 a is removed using the third photoresist pattern 124 as an etch mask. In this case, the third photoresist pattern 124 is used as a cutting mask. In order to isolate the second spacers 122 a, it is preferable that an end of the second spacer 122 a is exposed. Subsequently, the third photoresist pattern 124 is removed.
  • Referring to FIG. 1M, a photoresist film is deposited over the second spacer 122 a, and a fourth photoresist pattern 126 is formed using an etch mask. Preferably, the fourth photoresist pattern 126 may define a pad pattern.
  • Referring to FIG. 1N, the hard mask layer 104 is etched using the fourth photoresist pattern 126 and the second spacer 122 a as an etch mask, thus forming a hard mask pattern 104 a.
  • Although not shown in the drawings, the underlying layer 102 is etched using the target hard mask pattern 104 a as a mask, so that a select transistor located at both ends of a string, a Source Select Line (SSL), and a Drain Select Line (DSL) are defined in a cell region, and a pad pattern coupled to a drain contact is defined in a peripheral circuit region.
  • As is apparent from the above description, a method for forming a semiconductor device according to the embodiment of the present invention can use a double spacer patterning (DPT) technology differently from the related art, so that a select transistor located at both ends of the string, a Source Select Line (SSL) and a Drain Select Line (DSL) can be readily formed in a cell region, and a pad pattern coupled to a drain contact can be readily formed in a peripheral circuit region.
  • The above embodiments of the present invention are illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the type of deposition, etching polishing, and patterning steps described herein. Nor is the invention limited to any specific type of semiconductor device. For example, the present invention may be implemented in a dynamic random access memory (DRAM) device or a non-volatile memory device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.

Claims (19)

1. A method for forming a semiconductor device comprising:
forming a first sacrificial hard mask layer over a semiconductor substrate including an underlying layer, the underlying layer being provided below the first sacrificial hard mask;
forming a first spacer over the first sacrificial hard mask layer;
forming a first sacrificial hard mask pattern by etching the first sacrificial hard mask layer by using the first spacer as an etch mask;
forming a second spacer over sidewalls of the first sacrificial hard mask pattern;
partially isolating the second spacer;
forming a pad mask pattern over the second spacer; and
forming a pad pattern by etching the underlying layer using the pad mask pattern.
2. The method according to claim 1, further comprising:
forming a sub hard mask layer over the first sacrificial hard mask layer.
3. The method according to claim 2, wherein the sub hard mask layer includes polysilicon.
4. The method according to claim 2, wherein the forming of the first sacrificial hard mask pattern includes:
forming a sub hard mask pattern by etching the sub hard mask layer using the first spacer as an etch mask;
removing the first spacer; and
etching the first sacrificial hard mask layer using the sub hard mask pattern as an etch mask.
5. The method according to claim 4, wherein the removing of the first spacer is performed by wet-etching.
6. The method according to claim 4, wherein the removing of the first spacer uses a hydrofluoric acid (HF)-based etching solution or a H3PO4-based etching solution.
7. The method according to claim 1, wherein the forming of the first spacer includes:
forming a second sacrificial hard mask pattern over the first sacrificial hard mask layer;
forming a first spacer material over the second sacrificial hard mask pattern;
performing a first etch-back process on the first spacer material; and
removing the second sacrificial hard mask pattern.
8. The method according to claim 7, wherein the forming of the first spacer material is performed at a temperature substantially 20° C.˜substantially 400° C.
9. The method according to claim 1, wherein the forming of the second spacer includes:
forming a second spacer material over the first sacrificial hard mask pattern;
performing a secondary etch-back process on the second spacer material; and
removing the first sacrificial hard mask pattern.
10. The method according to claim 9, wherein the forming of the second spacer material is performed at a temperature substantially 20° C.˜substantially 400° C.
11. The method according to claim 1, wherein the partially isolating of the second spacer includes:
forming a cutting mask to expose some parts of the second spacer; and
etching the second spacer by using the cutting mask as an etch mask.
12. The method according to claim 1, further comprising:
forming a target hard mask layer over the underlying layer.
13. The method according to claim 12, wherein the target hard mask layer includes polysilicon.
14. A method for forming a semiconductor device comprising:
forming an underlying layer over a semiconductor substrate;
forming a first spacer pattern defining a drain select line (DSL) over the underlying layer, the DSL extending from a cell region to a peripheral region in the semiconductor substrate;
defining a pad contact region coupled to the first spacer pattern in the peripheral region;
forming a mask pattern at a sidewall of the first spacer pattern in the pad contact region to obtain a pad mask pattern; and
patterning the underlying layer using the first spacer pattern and the pad mask pattern as an etch mask to form a DSL extending from the cell region to the peripheral region and a pad contact pattern coupled to the DSL in the peripheral region.
15. The method of claim 14, wherein the pad mask pattern is wider than the first spacer pattern.
16. The method of claim 14, wherein distance between neighboring first spacer patterns in the pad contact region is larger than the distance between neighboring first spacer patterns in the cell region.
17. The method of claim 14, wherein distance between neighboring first spacer patterns in the pad contact region is larger than the distance between neighboring first spacer patterns in a non-pad contact region of the peripheral region.
18. The method of claim 14, wherein the first spacer pattern is formed using any of a Double Expose Etch Technology (DE2T), a Spacer Patterning Technology (SPT) and a Double Patterning Technology (DPT).
19. The method of claim 14, wherein the peripheral region includes a plurality of pad contact regions,
wherein the plurality of pad contact regions are zigzagged in arrangement.
US12/981,414 2010-04-15 2010-12-29 Method for forming semiconductor device Abandoned US20110256723A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR10-2010-0034748 2010-04-15
KR1020100034748A KR101159954B1 (en) 2010-04-15 2010-04-15 Method for forming semiconductor device

Publications (1)

Publication Number Publication Date
US20110256723A1 true US20110256723A1 (en) 2011-10-20

Family

ID=44788512

Family Applications (1)

Application Number Title Priority Date Filing Date
US12/981,414 Abandoned US20110256723A1 (en) 2010-04-15 2010-12-29 Method for forming semiconductor device

Country Status (2)

Country Link
US (1) US20110256723A1 (en)
KR (1) KR101159954B1 (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120083126A1 (en) * 2010-10-05 2012-04-05 Hynix Semiconductor Inc. Method for forming semiconductor device
US20120241834A1 (en) * 2011-03-24 2012-09-27 Fumiharu Nakajima Semiconductor device and method of manufacturing the same
US8921034B2 (en) 2012-09-28 2014-12-30 Micron Technology, Inc. Patterned bases, and patterning methods
US8975178B2 (en) 2011-12-27 2015-03-10 Kabushiki Kaisha Toshiba Method of manufacturing a memory device using fine patterning techniques
US9034765B2 (en) 2012-08-27 2015-05-19 Samsung Electronics Co., Ltd. Methods of forming a semiconductor device
US9812351B1 (en) 2016-12-15 2017-11-07 Globalfoundries Inc. Interconnection cells having variable width metal lines and fully-self aligned continuity cuts
US9818640B1 (en) 2016-09-21 2017-11-14 Globalfoundries Inc. Apparatus and method of forming self-aligned cuts in a non-mandrel line of an array of metal lines
US9818623B2 (en) 2016-03-22 2017-11-14 Globalfoundries Inc. Method of forming a pattern for interconnection lines and associated continuity blocks in an integrated circuit
US9818641B1 (en) 2016-09-21 2017-11-14 Globalfoundries Inc. Apparatus and method of forming self-aligned cuts in mandrel and a non-mandrel lines of an array of metal lines
US9852986B1 (en) * 2016-11-28 2017-12-26 Globalfoundries Inc. Method of patterning pillars to form variable continuity cuts in interconnection lines of an integrated circuit
US9887127B1 (en) 2016-12-15 2018-02-06 Globalfoundries Inc. Interconnection lines having variable widths and partially self-aligned continuity cuts
US10002786B1 (en) 2016-12-15 2018-06-19 Globalfoundries Inc. Interconnection cells having variable width metal lines and fully-self aligned variable length continuity cuts
US10043703B2 (en) 2016-12-15 2018-08-07 Globalfoundries Inc. Apparatus and method for forming interconnection lines having variable pitch and variable widths

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060046422A1 (en) * 2004-08-31 2006-03-02 Micron Technology, Inc. Methods for increasing photo alignment margins
US20060046484A1 (en) * 2004-09-02 2006-03-02 Abatchev Mirzafer K Method for integrated circuit fabrication using pitch multiplication
US20070077743A1 (en) * 2005-09-30 2007-04-05 Rao Rajesh A Multiple fin formation
US20090263972A1 (en) * 2008-04-04 2009-10-22 Applied Materials, Inc. Boron nitride and boron-nitride derived materials deposition method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090001080A (en) * 2007-06-29 2009-01-08 주식회사 하이닉스반도체 Method of forming fine pattern of semiconductor device
KR101061316B1 (en) * 2007-09-28 2011-08-31 주식회사 하이닉스반도체 Method of forming fine pattern of semiconductor device
KR101139460B1 (en) * 2008-03-26 2012-05-02 에스케이하이닉스 주식회사 Method of Manufacturing Semiconductor Device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060046422A1 (en) * 2004-08-31 2006-03-02 Micron Technology, Inc. Methods for increasing photo alignment margins
US20060046484A1 (en) * 2004-09-02 2006-03-02 Abatchev Mirzafer K Method for integrated circuit fabrication using pitch multiplication
US20070077743A1 (en) * 2005-09-30 2007-04-05 Rao Rajesh A Multiple fin formation
US20090263972A1 (en) * 2008-04-04 2009-10-22 Applied Materials, Inc. Boron nitride and boron-nitride derived materials deposition method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Machine Translation of KR 10-2009-0001080 A *

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8216938B2 (en) * 2010-10-05 2012-07-10 Hynix Semiconductor Inc. Method for forming semiconductor device
US20120083126A1 (en) * 2010-10-05 2012-04-05 Hynix Semiconductor Inc. Method for forming semiconductor device
US9177854B2 (en) * 2011-03-24 2015-11-03 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device using sidewall films for pitch multiplication in forming interconnects
US20120241834A1 (en) * 2011-03-24 2012-09-27 Fumiharu Nakajima Semiconductor device and method of manufacturing the same
US20140017887A1 (en) * 2011-03-24 2014-01-16 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US9917049B2 (en) 2011-03-24 2018-03-13 Toshiba Memory Corporation Semiconductor device having contacts in drawing area and the contacts connected to word lines extending from element formation area
US8975178B2 (en) 2011-12-27 2015-03-10 Kabushiki Kaisha Toshiba Method of manufacturing a memory device using fine patterning techniques
US9034765B2 (en) 2012-08-27 2015-05-19 Samsung Electronics Co., Ltd. Methods of forming a semiconductor device
US9293342B2 (en) 2012-09-28 2016-03-22 Micron Technology, Inc. Patterned bases, and patterning methods
US8921034B2 (en) 2012-09-28 2014-12-30 Micron Technology, Inc. Patterned bases, and patterning methods
US9818623B2 (en) 2016-03-22 2017-11-14 Globalfoundries Inc. Method of forming a pattern for interconnection lines and associated continuity blocks in an integrated circuit
US9818640B1 (en) 2016-09-21 2017-11-14 Globalfoundries Inc. Apparatus and method of forming self-aligned cuts in a non-mandrel line of an array of metal lines
US9818641B1 (en) 2016-09-21 2017-11-14 Globalfoundries Inc. Apparatus and method of forming self-aligned cuts in mandrel and a non-mandrel lines of an array of metal lines
US9852986B1 (en) * 2016-11-28 2017-12-26 Globalfoundries Inc. Method of patterning pillars to form variable continuity cuts in interconnection lines of an integrated circuit
US9812351B1 (en) 2016-12-15 2017-11-07 Globalfoundries Inc. Interconnection cells having variable width metal lines and fully-self aligned continuity cuts
US9887127B1 (en) 2016-12-15 2018-02-06 Globalfoundries Inc. Interconnection lines having variable widths and partially self-aligned continuity cuts
US10002786B1 (en) 2016-12-15 2018-06-19 Globalfoundries Inc. Interconnection cells having variable width metal lines and fully-self aligned variable length continuity cuts
US10043703B2 (en) 2016-12-15 2018-08-07 Globalfoundries Inc. Apparatus and method for forming interconnection lines having variable pitch and variable widths
US10083858B2 (en) 2016-12-15 2018-09-25 Globalfoundries Inc. Interconnection lines having variable widths and partially self-aligned continuity cuts

Also Published As

Publication number Publication date
KR101159954B1 (en) 2012-06-25
KR20110115312A (en) 2011-10-21

Similar Documents

Publication Publication Date Title
CN104051257B (en) spacer etching process for integrated circuit design
US9136106B2 (en) Method for integrated circuit patterning
US8012674B2 (en) Efficient pitch multiplication process
US7151040B2 (en) Methods for increasing photo alignment margins
CN101542685B (en) Methods to reduce the critical dimension of semiconductor devices and partially fabricated semiconductor devices having reduced critical dimensions
JP5093623B2 (en) Semiconductor structure, method for forming a plurality of lines, and method for forming a high density structure and a low density structure with a single photomask
EP2011141B1 (en) Simplified pitch doubling process flow
US7312158B2 (en) Method of forming pattern
JP4921723B2 (en) Manufacturing method of semiconductor device
US8889020B2 (en) Process for improving critical dimension uniformity of integrated circuit arrays
US7352018B2 (en) Non-volatile memory cells and methods for fabricating non-volatile memory cells
US20110294075A1 (en) Patterning method
US7651951B2 (en) Pitch reduced patterns relative to photolithography features
EP1864320B1 (en) Integrated circuit fabrication
US8216949B2 (en) Method for integrated circuit fabrication using pitch multiplication
TWI628715B (en) Feature size reduction
US6579757B2 (en) Method for fabricating semiconductor device which prevents gates of a peripheral region from being oxidized
US7838996B2 (en) Semiconductor device
KR20100084164A (en) Method for integrating nvm circuitry with logic circuitry
KR20090029521A (en) Method for forming fine pattern of semiconductor device
KR101099948B1 (en) Method of fabricating semiconductor device
US7442607B2 (en) Method of manufacturing transistor having recessed channel
CN101013653A (en) Method for forming micro pattern in semiconductor device
JP4271243B2 (en) Method for forming integrated circuit pattern
KR20050066176A (en) Method for forming pattern and gate electrode in semiconductor processing

Legal Events

Date Code Title Description
AS Assignment

Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, KI LYOUNG;BOK, CHEOL KYU;LEE, JUNG HYUNG;REEL/FRAME:025556/0521

Effective date: 20101227

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION