TWI767844B - Semiconductor structure and method of forming the same - Google Patents

Abstract

A semiconductor structure includes: a plurality of calibration reference features on a substrate and disposed from each other in a first direction; and a plurality of columns of first active features and a plurality of columns of second active features disposed on opposite sides of the calibration reference features respectively, wherein each column of the first active features is disposed in a second direction and spaced apart from each other, and each column of the first active features includes a plurality of first active features disposed in the first direction and spaced apart from each other, wherein the first direction is not parallel to the second direction, wherein each column of the second active features is disposed in the second direction and spaced apart from each other, and each column of the second active features includes a plurality of second active features disposed in the first direction and spaced apart from each other, wherein the calibration reference features, the first active features, and the second active features are disposed on a same layer and are a portion of the substrate.

Description

Semiconductor structure and method of forming the same

Embodiments of the present invention relate to semiconductor structures, and more particularly, to semiconductor structures having calibration reference features and methods of forming the same.

In the process of fabricating semiconductor devices (eg, memory devices or transistor devices), various patterning processes (including lithography and etching, etc.) are often used to transfer the pattern of components in the structure to form the desired semiconductor structure . However, as component sizes continue to shrink, many challenges arise. For example, there may be offsets or errors between various patterning processes, which can adversely affect semiconductor structures, thereby reducing device reliability or performance.

An embodiment of the present invention provides a semiconductor structure, comprising: a plurality of calibration reference components, located on a substrate and spaced along a first direction; and a plurality of rows of first active components and a plurality of rows of second active components, respectively disposed on the calibration reference components two sides of the device, wherein each row of first active parts is spaced apart from each other in a second direction and each row of first active parts includes a plurality of first active parts spaced in a first direction, wherein the first direction is not parallel to the second direction, each row of the second active parts is spaced apart from each other in the second direction and each row of the second active part row includes a plurality of second active parts spaced along the first direction, wherein the calibration reference part, the first active part and the first active part are The two active components are disposed on the same layer and are part of the substrate, wherein the width of the calibration reference component is greater than the width of the first active component and greater than the width of the second active component, and the length of the calibration reference component is greater than the length of the first active component and greater than that of the second active component. 2. The length of the active part.

An embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate with an active layer thereon, wherein the active layer is a part of the substrate; forming a mask layer stacked on the active layer; forming a sacrificial layer on the mask layer stack ; form patterned spacers on the sacrificial layer, the patterned spacers include a calibration reference pattern and an active area pre-pattern; perform a first patterning process to transfer the calibration reference pattern and active area pre-pattern of the patterned spacers to masking layer stacking; after the first patterning process, performing a second patterning process, patterning the masking layer stack with the active region pre-pattern into an active region pattern; and after the second patterning process, performing a second patterning process The third patterning process is to transfer the calibration reference pattern and the active region pattern stacked on the mask layer to the active layer to form a plurality of calibration reference components and a plurality of rows of active components, respectively.

1A illustrates a top view of the semiconductor structure 10, and FIGS. 1A-1 and 1A-2 illustrate cross-sectional views of the semiconductor structure 10 along the lines A-A' and B-B' of FIG. 1A, respectively. In order to simplify the drawing, FIG. 1A only shows the top view of the first active part G1 in a plurality of rows, the second active part G2 in a plurality of rows, and the calibration reference part 102C. The semiconductor structure 10 includes a substrate 100 , a plurality of rows of first active components G1 , a plurality of rows of second active components G2 , and a plurality of calibration reference components 102C.

Referring to FIG. 1A, a plurality of calibration reference components 102C are located on the substrate 100, and the plurality of calibration reference components 102C are arranged at intervals along the first direction d1. In some embodiments, the correction reference member 102C has a ring shape. In some embodiments, the width W4 of one side of the annular shape may be equal to the width W1 of the first active part 102A and equal to the width W2 of the second active part 102B. A plurality of rows of first active components G1 and a plurality of rows of second active components G2 are respectively disposed on both sides of the calibration reference component 102C. The first active parts G1 of each row are spaced apart from each other in the second direction d2 and each row of the first active parts G1 includes a plurality of first active parts 102A spaced along the first direction d1. In some embodiments, the first direction d1 is not parallel to the second direction d2. Each row of the second active parts G2 is spaced apart from each other in the second direction d2 and each row of the second active part row G2 includes a plurality of second active parts 102B spaced in the first direction d1. 1A-1 and 1A-2, the calibration reference part 102C, the first active part 102A, and the second active part 102B are provided on the same layer. In some embodiments, the first active component 102A, the second active component 102B, and the calibration reference component 102C may comprise the same material. For example, the first active part 102A, the second active part 102B and the calibration reference part 102C are part of the substrate 100, wherein the first active part 102A, the second active part 102B and the calibration reference part 102C are formed through the substrate 100 to perform a patterning process. Therefore, the first active part 102A, the second active part 102B, the calibration reference part 102C and the substrate 100 are continuous and composed of the same material.

The calibration reference part 102C can be used to measure the offset between different processes to improve device reliability and/or process margin. For example, the patterns of the calibration reference part 102C and the active parts (eg, the first active part 102A and the second active part 102B) are formed in different patterning processes, respectively. Therefore, by measuring the offset between the calibration reference part 102C and the active parts (eg, the first active part 102A and the second active part 102B), the patterning process for forming the active part and the patterning process for forming the calibration reference part 102C can be determined Is there any offset between. Then, according to the measured offset, the parameters of the patterning process for the next-level semiconductor structure can be optimized or the subsequent process parameters can be adjusted, thereby improving device reliability and/or process margin. In some embodiments, the calibration reference part 102C and the active parts (eg, the first active part 102A and the second active part 102B) can be integrated into the alignment mark area of the semiconductor device or disposed in the memory array area, so that the active parts ( For example, the pattern of the first active part 102A and the second active part 102B) is formed in the same process as the active region of the semiconductor device, and is formed in a different process from the pattern of the calibration reference part 102C. In some embodiments, by measuring the offset between the reference component 102C and the active components (eg, the first active component 102A and the second active component 102B), it can be determined whether the active region of the semiconductor device is offset, and can be determined according to The measured offset optimizes process parameters for forming the active region of the semiconductor device or adjusts subsequent process parameters. In some embodiments of the present invention, the semiconductor device is a dynamic random access memory.

In some embodiments, the width W3 of the calibration reference member 102C is greater than the width W1 of the first active member 102A and greater than the width W2 of the second active member 102B, and the length L3 of the calibration reference member 102C is greater than the length L1 of the first active member 102A and greater than the length L2 of the second active part 102B. In some embodiments, the width W3 of the calibration reference part 102C is at least twice the width W1 of the first active part 102A and at least twice the width W2 of the second active part 102B, and the length L3 of the calibration reference part 102C is at least Twice the length L1 of the first active part 102A and at least twice the length L2 of the second active part 102B, ie W3 ≧ 2*W1, W3 ≧ 2*W2, L3 ≧ 2*L1, and L3 ≧ 2 *L2.

In some embodiments, two adjacent rows of first active components 102A are staggered with each other and two adjacent rows of second active components 102B are staggered with each other. For example, two adjacent rows of first active components 102A have a first offset distance S1 in the first direction d1 and two adjacent rows of second active components 102B have a second offset distance in the first direction d1 Move the distance S2. The offset distance here is defined as the distance between the corresponding positions of the adjacent two rows of active components in the first direction d1, for example, the distance between the adjacent two rows of the first active components 102A indicated by arrows 114 and 116 in FIG. 1A. The distance S1 of the corresponding position in the first direction d1. In some embodiments, the first offset distance S1 may be equal to the second offset distance S2.

In some embodiments, the longitudinal lengths of the calibration reference part 102C, the first active part 102A, and the second active part 102B are all along the first direction. For example, the length L3 of the calibration reference part 102C, the length L1 of the first active part 102A, and the length L2 of the second active part 102B are all along the first direction d1 and parallel to each other.

In some embodiments, the outer contours of the calibration reference part 102C, the first active part 102A, and the second active part 102B have the same or similar shapes, which can make the offset measurement between the calibration reference part 102C and the active part more accurate. faster or more precise. For example, the outer contours of the calibration reference part 102C, the first active part 102A, and the second active part 102B can all be parallelograms, as shown in FIG. 1A .

1A , in some embodiments, the distance E1 between the calibration reference component 102C and the plurality of rows of first active components G1 is equal to the distance E2 between the reference component 102C and the plurality of rows of second active components G2 . In some embodiments, two adjacent rows of the first active components 102A have the same distance D3 and two adjacent rows of the second active components 102B have the same distance D4. In other embodiments, the distance D3 is equal to the distance D4. In some embodiments, the distance D5 between adjacent two first active components 102A in each row of first active components G1 is equal to the distance D6 between adjacent two second active components 102B in each row of second active components G2. In some embodiments, the distance D7 between two adjacent calibration reference components 102C is not equal to the distance D5 and not equal to the distance D6.

FIGS. 2A-8A are schematic diagrams illustrating a process for forming the semiconductor structure 10 . FIGS. 2A-1 to 8A-1 illustrate cross-sectional views of the semiconductor structure along line AA' of FIGS. 2A to 8A; FIGS. 2A-2 to 8A-2 illustrate A cross-sectional view of the semiconductor structure along the line BB'. Referring to Figures 2A-1 and 2A-2, a substrate 100 is provided with an active layer 102 thereon. In some embodiments, the active layer 102 is part of the substrate 100 and thus the active layer 102 and the substrate 100 comprise the same material. In one embodiment, the material of the active layer 102 includes silicon.

Next, a mask layer stack 104 is formed on the active layer 102 . In some embodiments, the mask layer stack 104 is a stack of a plurality of film layers, the materials of which may each include: an oxide (eg, tetraethyl orthosilicate (TEOS) oxide) , nitride (eg: silicon nitride), oxynitride (eg: silicon oxynitride (SiON)), polysilicon, amorphous silicon, carbon-containing mask materials, or a combination of the foregoing. In some embodiments, the mask layer stack 104 includes a first mask layer 104A, a second mask layer 104B on the first mask layer 104A, and a third mask layer on the second mask layer 104B 104C, and the first mask layer 104A, the second mask layer 104B and the third mask layer 104C may include different materials. In such an embodiment, the material of the first mask layer 104A may include tetraethoxysilane (TEOS) oxide, and the material of the second mask layer 104B may include polysilicon or amorphous silicon , and the material of the third mask layer 104C may include a carbon-containing hard mask material. In other embodiments, the mask layer stack 104 is a single-layer structure, such as a polysilicon layer, an amorphous silicon layer, or a single-layer structure of the foregoing materials.

A sacrificial layer 106 is then formed on the mask layer stack 104 . The material of the sacrificial layer 106 may include: oxynitride (eg, silicon oxynitride (SiON)), nitride, polysilicon, amorphous silicon, carbide, or a combination thereof. In some embodiments, the sacrificial layer 106 is a multi-layer structure including a first sacrificial material layer 106A and a second sacrificial material layer 106B on the first sacrificial material layer 106A. In such an embodiment, the material of the first sacrificial material layer 106A may include silicon oxynitride (SiON), and the material of the second sacrificial material layer 106B is different from that of the first sacrificial material layer 106A, and may include polysilicon and amorphous silicon. In other embodiments, the sacrificial layer 106 is a single-layer structure.

Referring to FIGS. 2A , 2A-1 and 2A-2 , a patterned layer 108 is formed on the sacrificial layer 106 . The patterned layer 108 has a rail-shaped profile. Specifically, the patterned layer 108 includes a plurality of strips 108A and a plurality of connecting members 108B between adjacent strips 108A. The connecting member 108B connects two adjacent long bars 108A. The adjacent strips 108A and the connecting members 108B define a plurality of openings 109 , and the openings 109 expose the sacrificial layer 106 . According to some embodiments, the patterned layer 108 includes a photoresist layer, an anti-reflection layer (eg, an organic dielectric layer (ODL)), or a combination thereof.

3A, 3A-1 and 3A-2, a spacer layer 110' is formed on the patterned layer 108 and the sacrificial layer 106. The material of the spacer layer 110' may include oxides, nitrides, oxynitrides, carbides, or combinations thereof. In some embodiments, the spacer layer 110' is conformally formed on the patterned layer 108 and the sacrificial layer 106.

Referring to Figures 4A, 4A-1 and 4A-2, the spacer layer 110' is etched back to expose the top surface of the patterned layer 108 and the top surface of the sacrificial layer 106. In some embodiments, the etching process includes reactive ion etching (RIE), neutral beam etching (NBE), or inductive coupled plasma etch.

Referring to Figures 5A, 5A-1 and 5A-2, the patterned layer 108 is removed. The remaining spacer layer 110' forms the patterned spacer 110. The patterned spacer 110 includes a calibration reference pattern P1 and an active area pre-pattern P2, and the calibration reference pattern P1 includes a plurality of annular shapes.

Referring to Figures 6A, 6A-1, 6A-2, 7A, 7A-1 and 7A-2, a first patterning process is then performed to transfer the calibration reference pattern P1 and the active area pre-pattern P2 of the patterned spacers 110 to the mask layer stack 104 . As shown in FIGS. 6A, 6A-1 and 6A-2, the sacrificial layer 106 is etched using the patterned spacer 110 as a mask, and then the patterned spacer 110 is removed. In embodiments where the sacrificial layer 106 includes a first sacrificial material layer 106A and a second sacrificial material layer 106B, the first sacrificial material layer 106A may serve as an etch stop layer, the etch sacrificial layer 106 being etched through the second sacrificial material layer 106B without passing through the first sacrificial material layer 106A. In such an embodiment, the first sacrificial material layer 106A may serve as an etch stop layer. In the embodiment in which the sacrificial layer 106 is a single-layer structure, the sacrificial layer 106 is etched through the sacrificial layer 106 , and the mask structure 104 below can serve as an etch stop layer. The process of etching the sacrificial layer 106 may include wet etching, dry etching (eg, reactive ion etching, neutral particle beam etching, inductively coupled plasma etching, or other suitable etching processes).

As shown in FIGS. 7A, 7A-1 and 7A-2, the sacrificial layer 106 is used as an etching mask to etch through the first sacrificial material layer 106A (if present, that is, if the sacrificial layer 106 is a multilayer structure), the third The mask layer 104C and the second mask layer 104B, the sacrificial layer 106 and the third mask layer 104C are removed after etching, so as to transfer the calibration reference pattern P1 and the active area pre-pattern P2 of the patterned spacer 110 to the mask layer The mask layer stack 104 (eg, transferred to the second mask layer 104B). The first mask layer 104A can serve as an etch stop layer and can protect the underlying active layer from damage during the etching process. In some embodiments, the process used to etch the mask layer stack 104 may be the same or similar to the etch process described above. In other embodiments, the first patterning process uses the patterned spacer 110 as a mask to etch the sacrificial layer 106 and the mask layer stack 104 , so as to calibrate the reference pattern P1 of the patterned spacer 110 and the active region pre-pattern P2 is transferred to the mask layer stack 104 and the patterned spacers 110 and sacrificial layer 106 are removed after etching.

8A, 8A-1, 8A-2 and 9, after the first patterning process, a second patterning process is performed to form the patterned photoresist layer 112 on the second mask layer 104B having the calibration reference pattern P1 and expose part of the second mask layer 104B.

Referring to FIG. 9, the exposed part of the second mask layer 104B is then removed to pattern the second mask layer 104B having the active region pre-pattern P2 into an active region pattern P3, and then the photoresist layer is patterned 112 removed. The second patterning process is performed to cut the mask layer stack 104 having the active area pre-pattern P2 into active area patterns P3 having a plurality of portions spaced apart from each other in the first direction d1. In such an embodiment, the patterned photoresist layer 112 can be changed to adjust the shape of the exposed portion of the second mask layer 104B, so as to achieve the desired active region pattern P3. In some embodiments, during removal of the exposed portion of the second mask layer 104B, since the patterned photoresist layer 112 is on the second mask layer 104B with the correction reference pattern P1, the second mask layer 104B with the correction reference pattern P1 may be protected The second mask layer 104B is not affected by the process. Therefore, the calibration reference pattern P1 defined before the second patterning process (eg, by the patterned spacers and/or the first patterning process) can be well retained on the second mask layer 104B. After the second patterning process is performed, the second mask layer 104B has the calibration reference pattern P1 and the active region pattern P3. In other embodiments, such as the embodiment in which the mask layer stack 104 is a single-layer structure, the calibration reference pattern P1 and the active region pattern P3 may be transferred to the mask layer stack 104 of a single-layer structure and the mask layer Below the stack 104 is the active layer 102 .

Referring to FIG. 10, after the second patterning process, a third patterning process is performed to transfer the calibration reference pattern P1 and the active region pattern P3 of the mask layer stack 104 to the active layer 102 to form a plurality of calibration reference components respectively 102C and the plurality of rows of active components G1 and G2, then the mask layer stack 104 is removed. The semiconductor structure 10 includes a calibration reference part 102C having a calibration reference pattern P1 defined before the second patterning process (eg, by patterning spacers and/or the first patterning process), and a plurality of rows of active parts G1 and G2, There is an active region pattern P3 defined in the second patterning process. By measuring the offset of the calibration reference part 102C and the plurality of rows of active parts G1 and G2 and comparing it with a predetermined offset value (the ideal state offset value is 0), it can be determined whether the second patterning process is different from the second patterning process. Whether there is an offset between processes prior to the process (eg, the process of forming the patterned spacers and/or the first patterning process). For example, if the offset between the measured calibration reference part 102C and the plurality of rows of active parts G1 and G2 is equal to 0, it means that there is no offset between the processes; if the measured calibration reference part 102C and the plurality of rows of active parts G1 If the offset of G2 and G2 is not equal to 0, it means that there may be offsets between processes and the positions of the active components G1 and G2 of the plurality of rows may be offset. In some embodiments, process parameters of the first patterning process and/or the second patterning process can be optimized according to the measured offset, thereby improving device reliability and/or process margin. In some embodiments, the semiconductor structure 10 may be integrated into a semiconductor device, eg, the calibration reference part 102C, the plurality of rows of active parts G1 and G2 , and processes thereof (eg, including a second patterning process) and the semiconductor device The active region and its process integration, and after the components are formed, the offset between the reference component 102C and the plurality of rows of active components G1 and G2 is measured and corrected, and the plurality of rows of active components G1 and G2, and the Whether there is an offset in the active area, and optimize the process according to the offset to improve device reliability and/or performance.

In some embodiments, the outer contours of the calibration reference pattern P1 and the active region pattern P3 have the same or similar shapes, for example, may have a parallelogram outer contour, an elliptical outer contour or a rounded rectangular outer contour. For example, in the embodiment shown in FIG. 11, the outer contours of the first active part 102A, the second active part 102B and the calibration reference part 102C are all oval. In the embodiment shown in FIG. 12, the outer contours of the first active part 102A, the second active part 102B and the calibration reference part 102C are all rounded and rectangular.

Some embodiments of the present invention provide semiconductor structures and methods of forming the same with calibration reference features that can be used to measure inter-process offsets to improve device reliability and/or process margins. In some embodiments, the measured offset can be used to determine whether the active component has offset, so as to further optimize the process, thereby improving device reliability and/or process margin. In addition, the semiconductor structure provided by the embodiments of the present invention can be integrated into a semiconductor device, and the reliability and/or performance of the device can be improved by using the measured offset.

Although the present invention is disclosed in the foregoing embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope of the appended patent application.

10: Semiconductor structure 100: Substrate 102: Active layer 102A: First Active Part 102B: Second Active Part 102C: Calibration Reference Parts 104: Mask Layer Stacking 104A: first mask layer 104B: Second mask layer 104C: Third mask layer 106: Sacrificial Layer 106A: first sacrificial material layer 106B: Second sacrificial material layer 108: Patterning Layers 108A: long strip 108B: Connecting parts 109: Opening 110: Spacer 110': Spacer Layer 112: Patterned photoresist layer d1: first direction d2: the second direction E1, E2, D3, D4, D5, D6, D7: Spacing G1: first active part row G2: Second Active Part Row L1, L2, L3: length P1: Correction reference pattern P2: Active area front pattern P3: Active area pattern S1: first offset distance S2: Second offset distance W1,W2,W3,W4: width

Embodiments of the present invention are best understood from the following detailed description in conjunction with the accompanying drawings. Figures 1A-8A, 9 and 10 are top views illustrating semiconductor structures according to some embodiments of the present invention. FIGS. 1A-1 to 8A-1 are cross-sectional views of the semiconductor structure along line A-A' of FIGS. 1A to 8A, respectively, according to some embodiments of the present invention. FIGS. 1A-2 through 8A-2 are cross-sectional views of semiconductor structures along lines B-B' of FIGS. 2A through 8A, respectively, according to some embodiments of the present invention. FIGS. 11 and 12 are top views of semiconductor structures according to other embodiments of the present invention.

10: Semiconductor structure

100: Substrate

102A: First Active Part

102B: Second Active Part

102C: Calibration Reference Parts

E1, E2, D3, D4, D5, D6, D7: Spacing

G1: first active part row

G2: Second Active Part Row

L1, L2, L3: length

S1: first offset distance

S2: Second offset distance

W1,W2,W3,W4: width

Claims (11)

A semiconductor structure, comprising: a plurality of calibration reference components, located on a substrate and spaced along a first direction; and a plurality of rows of first active components and a plurality of rows of second active components, respectively disposed on two of the calibration reference components. side, wherein each row of first active parts is spaced apart from each other in a second direction and each row of first active parts includes a plurality of first active parts spaced along the first direction, wherein the first direction is not parallel to the first active part Two directions, each row of second active components is spaced apart from each other in the second direction, and each row of second active components includes a plurality of second active components spaced along the first direction, wherein the calibration reference components, the The first active components and the second active components are disposed on the same layer and are part of the substrate, wherein the width of the calibration reference components is greater than the width of the first active components and greater than the width of the second active components , the lengths of the calibration reference components are greater than the lengths of the first active components and greater than the lengths of the second active components. The semiconductor structure of claim 1, wherein the width of the calibration reference components is at least twice the width of the first active components and at least twice the width of the second active components, and the calibration reference components have a width The length is at least twice the length of the first active components and at least twice the length of the second active components. The semiconductor structure of claim 1, wherein two adjacent rows of first active components are staggered with each other and two adjacent rows of second active components are staggered with each other, wherein The distance between adjacent two first active components in each row of the first active components is equal to the distance between adjacent two second active components in each row of second active components. The semiconductor structure of claim 1, wherein outer contours of the calibration reference components, the first active components, and the second active components have the same shape. The semiconductor structure of claim 4, wherein the shape of the outer contour includes a parallelogram, an ellipse, or a rounded rectangle. The semiconductor structure of claim 1, wherein the calibration reference components have an annular shape, wherein a width of one side of the annular shape is equal to the width of the first active components and equal to the width of the second active components. A method for forming a semiconductor structure, comprising: providing a substrate with an active layer thereon, wherein the active layer is a part of the substrate; forming a mask layer stacked on the active layer; forming a sacrificial layer on the mask layer stacking; forming a patterned spacer on the sacrificial layer, the patterned spacer includes a calibration reference pattern and an active area pre-pattern; performing a first patterning process, the patterned spacer The calibration reference pattern and the active area pre-pattern are transferred to the mask layer stack; after the first patterning process, a second patterning process is performed to pattern the mask layer stack with the active area pre-pattern into an active region pattern; and After the second patterning process, a third patterning process is performed to transfer the calibration reference pattern and the active region pattern of the mask layer stack to the active layer to form a plurality of calibration reference parts and a plurality of rows, respectively Active parts. The method for forming a semiconductor structure according to claim 7, wherein the calibration reference components are arranged at intervals along a direction, and the plurality of rows of active components include a plurality of rows of first active components and a plurality of rows of second active components, which are respectively disposed on the calibration reference components. Both sides of the reference part. The method for forming a semiconductor structure as claimed in claim 7, wherein forming the patterned spacers on the sacrificial layer comprises: forming a patterned layer on the sacrificial layer, wherein the patterned layer comprises a plurality of strips, and between A plurality of connecting parts between adjacent strips, the adjacent strips and the connecting parts define a plurality of openings and the openings expose the sacrificial layer; a spacer layer is formed on the patterned layer and on the sacrificial layer; etching the spacer layer to expose the top surface of the patterned layer and the top surface of the sacrificial layer; and removing the patterned layer. The method for forming a semiconductor structure of claim 7, wherein performing the first patterning process comprises: using the patterned spacer as a mask, etching the sacrificial layer; removing the patterned spacer; and using the sacrificial layer as a mask mask, etch the mask layer stack. The method for forming a semiconductor structure of claim 7, wherein performing the second patterning process comprises: forming a patterned photoresist layer on the mask layer stack having the calibration reference pattern and exposing a portion of the mask layer stack ; and removing the exposed portion of the mask layer stack.

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