TWI809140B - Method of manufacturing semiconductor devices - Google Patents

Abstract

A method of manufacturing a semiconductor device includes forming first sacrificial cores on a first region of a lower structure and second sacrificial cores on a second region of the lower structure, forming spacers on side walls of the first sacrificial cores and side walls of the second sacrificial cores, forming a protective pattern covering the second sacrificial cores on the second region of the lower structure, removing the first sacrificial cores from the first region, and etching the lower structure using the spacers on the first region, and the second sacrificial cores and the spacers on the second region.

Description

Method for manufacturing semiconductor element

The present disclosure relates to a method of manufacturing a semiconductor device.

[CROSS-REFERENCE TO RELATED APPLICATIONS]

Korean Patent Application No. 10-2018-0137287 filed on November 9, 2018 at the Korea Intellectual Property Office and entitled "Method of Manufacturing Semiconductor Devices" is hereby incorporated by reference in its entirety.

As semiconductor elements become highly integrated, the size of patterns forming the semiconductor elements becomes smaller and smaller. There are limitations in forming fine patterns due to optical resolution limitations of the photolithography equipment used to form such patterns. Therefore, methods for forming fine patterns have been proposed.

According to an exemplary embodiment, a method of manufacturing a semiconductor element includes: forming a first sacrificial core on a first region of a lower structure, and A second sacrificial core is formed on the second region of the structure; a spacer wall is formed on the side walls of the first sacrificial core and the side walls of the second sacrificial core; the second sacrificial core covering the lower structure is formed. protecting pattern of the second sacrificial core on the area; removing the first sacrificial core from the first area; and using the spacer on the first area and the second area on the The second sacrificial core and the spacer etch the lower structure.

According to an exemplary embodiment, a method of manufacturing a semiconductor element includes: preparing a lower structure having a first region, a second region, and a third region; forming a first sacrificial core having a first width on the first region, A second sacrificial core with a second width is formed on the second region, and a third sacrificial core with a third width larger than the first width and the second width is formed on the third region. A core body; a spacer is formed on the first region of the lower structure, and a first mask including the second sacrificial core and the spacer is formed on the second region of the lower structure structure, and forming a second mask structure including the third sacrificial core and the spacer on the third region of the lower structure; and using the spacer, the first mask structure and etching the lower structure by the second mask structure.

According to an exemplary embodiment, a method of manufacturing a semiconductor device includes: stacking a lower sacrificial layer and an upper sacrificial layer on a lower structure having a first region, a second region, and a third region; A first upper sacrificial core is formed on the first region and a second upper sacrificial core is formed on the second region; on the sidewall of the first upper sacrificial core and on the second upper sacrificial core A first spacer wall is formed on the side wall of the core; the first upper sacrificial core and the second upper sacrificial core are removed; a photoresist pattern having a wide width of the core; forming a first lower sacrificial layer on the first region by using the first spacer and the photoresist pattern as an etch mask to etch the lower sacrificial layer core, forming a second lower sacrificial core on the second region and forming a third lower sacrificial core on the third region; on the sidewall of the first lower sacrificial core, the second lower sacrificial core forming a second spacer on the side wall of the body and the side wall of the third lower sacrificial core; forming a protection pattern covering the second area and the third area; removing the formed on the first area a first lower sacrificial core; and using the second spacer on the first region, the second lower sacrificial core and the second spacer on the second region and the first The third lower sacrificial core and the second spacer on the third region are used to etch the lower structure.

101: Substrate

103: Component isolation layer

111: gate insulating layer

113: gate conductive layer

115, 116: hard mask layer

121: sacrificial layer/lower sacrificial layer

125: Anti-reflection layer/lower anti-reflection layer

141: sacrificial layer/upper sacrificial layer

145: anti-reflection layer/upper anti-reflection layer

150: spacer/second spacer

155: the first gap wall

180, 184: photoresist pattern

182, 186, 194: protection patterns

190: the first photoresist pattern

192: Second photoresist pattern

AT1, AT1': the first active area

AT2, AT2': the second active area

AT3, AT3': the third active area

GE1: the first gate electrode layer

GE2: The second gate electrode layer

GE3: third gate electrode layer

GS1: first gate structure

GS2: Second gate structure

GS3: third gate structure

GT1: first gate pattern

GT2: Second gate pattern

GT3: Third gate pattern

I-I': line

IN1: The first gate insulating layer

IN2: The second gate insulating layer

IN3: The third gate insulating layer

P1, P11, Pa: the first pitch

P1', P4, Pd: fourth pitch

P2, P12, Pb: second pitch

P2', P5, Pe: the fifth pitch

Pa', Pb': pitch

R1, R1': the first region

R2, R2': the second area

R3, R3': the third area

S1, S11: first interval

S1', S4: the fourth interval

S2, S12, Sb: second interval

S2', S5, Se: the fifth interval

Sa: interval/first interval

Sa', Sb': Interval

SC1: The first sacrificial core

SC1': the first upper sacrificial core

SC1”: the first lower sacrificial core

SC2: Second Sacrificial Core

SC2': Second upper sacrificial core

SC2”: the second lower sacrificial core

SC3: The third sacrificial core

SC3”: the third lower sacrificial core

SC4: The fourth sacrificial core

SC5: fifth sacrificial core

SC6: The sixth sacrificial core

Sd: interval/fourth interval

SM1, SM1': the first mask structure

SM2, SM2': the second mask structure

SM3, SM3': the third mask structure

SM4: Fourth mask structure

SM5: fifth mask structure

SM6: Sixth mask structure

W1, W11: first width

W1', W4: fourth width

W2, W12, Wb: second width

W2', W5, We: fifth width

W3, Wc: third width

W3', W6: sixth width

W13: Width / third width

Wa: width/first width

Wa', Wb', Wc', Ws, Ws': Width

Wd: width/fourth width

Wf: sixth width

X, Y: direction

Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which: FIGS. A plan view and a cross-sectional view of a semiconductor element manufactured by the method of the example.

3 to 8 illustrate cross-sectional views of stages in a method of manufacturing a semiconductor element according to example embodiments.

9 to 14 illustrate a method of manufacturing a semiconductor element according to an exemplary embodiment Cutaway view of the stage in .

15 to 23 illustrate cross-sectional views of stages in a method of manufacturing a semiconductor element according to example embodiments.

Hereinafter, exemplary embodiments will be explained in detail with reference to the accompanying drawings.

1 and 2 are plan views and cross-sectional views illustrating a semiconductor element manufactured by a method of manufacturing a semiconductor element according to an exemplary embodiment. Fig. 2 is a sectional view taken along line I-I' shown in Fig. 1 .

Referring to FIG. 1 and FIG. 2 , the substrate 101 may have a first region R1 , a second region R2 and a third region R3 . The first region R1 may be a region in which a core transistor having a fin-type field effect transistor (finFET) structure is formed. The second region R2 may be an input/output (I/O) transistor having a FinFET structure and/or a laterally diffused metal oxide semiconductor field effect transistor (laterally diffused MOSFET, LDMOS) transistor having a FinFET structure (using A region of higher voltage than that of the core transistor). The third region R3 may be a region in which a planar transistor is formed.

A first active region AT1 extending in one direction may be formed on the first region R1 of the substrate 101, a second active region AT2 extending in one direction may be formed on the second region R2, and a second active region AT2 extending in one direction may be formed on the third region R3. At least a single third active area AT3 extending in one direction may be formed. For example, as shown in FIG. 1, the first active area AT1, the second active area AT2, and the third active area AT3 can be in the same One direction extends upwards, for example, extends along the Y direction. In another example, the first active area AT1 , the second active area AT2 and the third active area AT3 may extend in different directions from each other in a manner different from that shown in FIG. 1 .

The first active area AT1 may be a first active fin, and the second active area AT2 may be a second active fin. The first active areas AT1 may be arranged at a first pitch Pa, and the second active areas AT2 may be arranged at a second pitch Pb greater than the first pitch Pa. The second width Wb of the second active area AT2 may be greater than the first width Wa of the first active area AT1, and the third width Wc of the third active area AT3 may be greater than the second width Wb of the second active area AT2. The second width Wb of the second active area AT2 may be greater than twice the first width Wa of the first active area AT1. The second interval Sb of the second active area AT2 may be equal to the first interval Sa of the first active area AT1, or may be greater than the first interval Sa of the first active area AT1. As shown in FIG. 1, the first pitch Pa is equal to the sum of the first width Wa of a single first active area AT1 and the first interval Sa (ie, the interval between two adjacent first active areas AT1), and The second pitch Pb is equal to the sum of the second width Wb of the single second active area AT2 and the second interval Sb (ie, the interval between two adjacent second active areas AT2 ).

As shown in FIG. 2 , an element isolation layer 103 may be formed between adjacent active regions among the first to third active regions AT1 , AT2 and AT3 . Upper portions of the first to third active regions AT1 , AT2 and AT3 may protrude over the upper surface of the element isolation layer 103 . The element isolation layer 103 may cover side surfaces of lower portions of the first to third active regions AT1 , AT2 and AT3 .

A first gate structure GS1 may be formed on the first region R1 of the substrate 101, A second gate structure GS2 may be formed on the second region R2, and a third gate structure GS3 may be formed on the third region R3. The first gate structure GS1 may extend in a direction intersecting the first active area AT1, the second gate structure GS2 may extend in a direction intersecting the second active area AT2, and the third gate structure GS3 may extend in an intersecting direction with the second active area AT2. The third active area AT3 extends in the intersecting direction. For example, the first gate structure GS1 , the second gate structure GS2 and the third gate structure GS3 may extend along the X direction.

The first gate structures GS1 may be arranged at a fourth pitch Pd, and the second gate structures GS2 may be arranged at a fifth pitch Pe greater than the fourth pitch Pd. The fifth width We of the second gate structure GS2 may be greater than the fourth width Wd of the first gate structure GS1, and the sixth width Wf of the third gate structure GS3 may be greater than the fifth width We of the second gate structure GS2. . The fifth width We of the second gate structure GS2 may be greater than twice the fourth width Wd of the first gate structure GS1 . The fifth interval Se of the second gate structure GS2 may be equal to the fourth interval Sd of the first gate structure GS1 , or may be greater than the fourth interval Sd of the first gate structure GS1 . In an exemplary embodiment, the first gate structure GS1 and the second gate structure GS2 may have equal widths and intervals to each other.

Source/drain regions may be formed, for example, on both sides (eg, opposite sides) of each of the first gate structure GS1 , the second gate structure GS2 and the third gate structure GS3 . The source/drain regions can be grown from the first active region AT1, the second active region AT2 and the third active region AT3 by using a selective epitaxial growth (SEG) process, or by using an ion implantation process (ion implantation process) is formed in the upper regions of the first active area AT1, the second active area AT2, and the third active area AT3.

The first gate structure GS1 includes a first gate insulating layer IN1 and a first gate electrode layer GE1, the second gate structure GS2 includes a second gate insulating layer IN2 and a second gate electrode layer GE2, and the third gate structure GS3 It includes a third gate insulating layer IN3 and a third gate electrode layer GE3.

The thickness of the second gate insulating layer IN2 may be greater than the thickness of the first gate insulating layer IN1. The thickness of the third gate insulating layer IN3 may be greater than the thickness of the first gate insulating layer IN1. Each of the first gate insulating layer IN1, the second gate insulating layer IN2, and the third gate insulating layer IN3 may include, for example, silicon oxide, silicon oxynitride, high-k oxide or a combination thereof. The high-k oxide can be, for example, alumina (Al ₂ O ₃ ), tantalum oxide (Ta ₂ O ₃ ), titanium oxide (TiO ₂ ), yttrium oxide (Y ₂ O ₃ ), zirconia (ZrO ₂ ), zirconia Silicon ( _ZrSix O _y ), hafnium oxide (HfO ₂ ), hafnium silicon oxide ( _HfSix O _y ), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminum oxide (LaAl _x O _y ), lanthanum hafnium oxide (LaHf _x One of O _y ), hafnium aluminum oxide (HfAl _x O _y ) and manganese oxide (Pr ₂ O ₃ ).

Each of the first gate electrode layer GE1 , the second gate electrode layer GE2 and the third gate electrode layer GE3 may include, for example, metal, metal nitride, doped polysilicon, or a combination thereof. In an exemplary embodiment, the first gate electrode layer GE1, the second gate electrode layer GE2 and the third gate electrode layer GE3 may include, for example, titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN) At least one of tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), titanium aluminum carbide (TiAlC), tungsten nitride (WCN) and tungsten (W).

According to an exemplary embodiment, since the width of the second active region AT2 of the second region R2 can be further increased compared to the width of the first active region AT1 of the first region R1, the I/O transistor having a FinFET structure or with FinFET The reliability of the hot carrier immunity (HCI) of the laterally diffused MOSFET (LDMOS) transistor of the structure (using a higher voltage than that of the core transistor) can be improved.

3 to 8 are cross-sectional views illustrating stages in a method of manufacturing a semiconductor element according to an exemplary embodiment. The sectional views in FIGS. 3 to 8 correspond to the sectional views shown in FIG. 2 .

Referring to FIG. 3 , a hard mask layer 115 , a sacrificial layer 121 and an anti-reflection layer 125 may be sequentially formed on the substrate 101 .

The substrate 101 may have a first region R1 , a second region R2 and a third region R3 . The first region R1 may be a region in which a core transistor having a finFET structure is formed. The second region R2 may be a region where I/O transistors having a FinFET structure or laterally diffused MOSFET (LDMOS) transistors having a FinFET structure (using a higher voltage than that of the core transistor) are formed. The third region R3 may be a region in which planar transistors are formed.

The substrate 101 can be a semiconductor substrate such as a silicon wafer. For example, the substrate 101 may be a Silicon-On-Insulator (SOI) substrate.

The hard mask layer 115 can be made of silicon-containing material (eg, silicon oxide (SiO _x ), silicon oxynitride (SiON), silicon nitride ( _Six N _y ) or polysilicon), carbon-containing material (eg, amorphous carbon layer ( At least one of amorphous carbon layer (ACL) or spin-on hardmask (SOH)) and metal is formed. For example, hard mask layer 115 may include multiple layers.

The sacrificial layer 121 may comprise, for example, polysilicon, amorphous carbon layer (ACL) or spin At least one of the hard masks (SOH) is applied. The sacrificial layer 121 may be located between the hard mask layer 115 and the antireflection layer 125 .

The anti-reflection layer 125 may be at least one layer for preventing light reflection during a lithography process. The anti-reflection layer 125 can be formed of, for example, silicon oxynitride (SiON).

The hard mask layer 115 , the sacrificial layer 121 and the anti-reflection layer 125 can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), spin coating, etc., for example. Depending on the material, a bake process or a curing process may additionally be performed.

Next, a photoresist may be formed on the anti-reflection layer 125 . Photoresist patterns 180 , for example in the form of lines spaced apart from each other, may be formed on the anti-reflection layer 125 by a lithography process.

A first pattern of the photoresist pattern 180 may be formed on the first region R1 while having a first width W1 to have a first space S1 therebetween. The first pattern of the photoresist pattern 180 may be formed on the first region R1 with a first pitch P1. The first pitch P1 may be defined as the sum of the first width W1 and the first interval S1.

A second pattern of the photoresist pattern 180 may be formed on the second region R2 with a second space S2 therebetween while having the second width W2. The second pattern of the photoresist pattern 180 may be formed on the second region R2 with a second pitch P2. The second pitch P2 may be defined as the sum of the second width W2 and the second interval S2. The second width W2 may be different from the first width W1. The second interval S2 may be different from the first interval S1.

The third pattern of the photoresist pattern 180 may have a third width W3 while formed on the third region R3. The first width W1 can be determined by considering the interval Sa between the first active regions ( AT1 , see FIG. 8 ) to be finally formed. The interval Sa between the first active regions AT1 to be finally formed may be narrower than the resolution limit of commercially available lithography equipment.

Referring to FIG. 4, the antireflection layer 125 and the sacrificial layer 121 may be anisotropically etched using the photoresist pattern 180 as an etching mask. Accordingly, a first sacrificial core SC1 may be formed on the first region R1, a second sacrificial core SC2 may be formed on the second region R2, and a third sacrificial core SC3 may be formed on the third region R3. The first sacrificial cores SC1 may be formed on the first region R1 with a first width W1 and a first interval S1 (ie, a first pitch P1 ) therebetween. The second sacrificial cores SC2 may be formed on the second region R2 with a second width W2 and a second space S2 (ie, a second pitch P2 ) therebetween. The third sacrificial core SC3 may have a third width W3 on the third region R3. The third width W3 of the third sacrificial core SC3 may be greater than each of the second width W2 of the second sacrificial core SC2 and the first width W1 of the first sacrificial core SC1 .

Referring to FIG. 5 , a spacer wall 150 may be formed on a sidewall of the first sacrificial core SC1 , a sidewall of the second sacrificial core SC2 , and a sidewall of the third sacrificial core SC3 . Therefore, the first mask structure SM1 may be formed on the first region R1, the second mask structure SM2 may be formed on the second region R2 and the third mask structure SM3 may be formed on the third region R3. Each of the first mask structure SM1 , the second mask structure SM2 and the third mask structure SM3 may include a sacrificial layer 121 , an anti-reflection layer 125 and a pair of spacers 150 .

In detail, a spacer material layer conformally covering the first sacrificial core body SC1 , the second sacrificial core body SC2 , and the third sacrificial core body SC3 may be formed. Then, an etchback process may be performed to form the opposite sidewalls of each of the first sacrificial cores SC1, each of the second sacrificial cores SC2, and the third sacrificial cores. Spacers 150 are formed on opposite sidewalls of SC3.

The thickness of the spacer material layer, that is, the thickness of the spacer 150 , can be determined by considering the width Wa of the first active region ( AT1 , see FIG. 8 ) to be finally formed. The width Wa of the first active area AT1 to be finally formed may be narrower than the resolution limit of commercially available lithography equipment.

The spacer material layer may be formed of a material having etch selectivity with respect to the material of the sacrificial layer 121 . For example, when the sacrificial layer 121 is formed of one of polysilicon, amorphous carbon layer (ACL) and spin-on-hard-mask (SOH), the spacer material layer may be formed of silicon oxide or silicon nitride. The layer of spacer material may be formed using atomic layer deposition (ALD).

Referring to FIG. 6 , a protection pattern 182 covering the second region R2 and the third region R3 may be provided. The protection pattern 182 may be formed of, for example, a photoresist material. The protection pattern 182 covers the second mask structure SM2 in the second region R2 and the third mask structure SM3 in the third region R3, so that the first mask structure SM1 can be exposed on the first region R1.

Next, the first sacrificial core SC1 can be removed from the exposed first region R1 , so that the spacer 150 can remain on the hard mask layer 115 in the first region R1 . The spacers 150 may be disposed on the first region R1 to be spaced apart from each other by a distance equal to the first width W1 of the first sacrificial core SC1 .

Referring to FIG. 7, the protection pattern 182 may be removed. Then, the spacers 150 on the first region R1, the second mask structure SM2 on the second region R2, and the third mask structure SM3 on the third region R3 can be used as etching masks to anisotropically etch the hard disk. mask layer 115 . While the hard mask layer 115 may be anisotropically etched, part or all of the spacer 150 , the second mask structure SM2 and the third mask structure SM3 may be consumed.

Referring to FIG. 8, the substrate 101 may be anisotropically etched using the patterned hard mask layer 115 as an etching mask to form a first active region AT1 on the first region R1 of the substrate 101 and a second active region AT1 on the second region R2. The second active area AT2 and the third active area AT3 are formed on the third area R3. The first active area AT1 may be a first active fin, and the second active area AT2 may be a second active fin. The second width Wb of the second active area AT2 may be greater than the first width Wa of the first active area AT1, and the third width Wc of the third active area AT3 may be greater than the second width Wb of the second active area AT2. The second width Wb of the second active area AT2 may be greater than twice the first width Wa of the first active area AT1. The second interval Sb of the second active area AT2 may be equal to the first interval Sa of the first active area AT1, or may be greater than the first interval Sa of the first active area AT1.

In an exemplary embodiment, when the first width W1 of the first sacrificial core SC1 can be equal to the second width W2 of the second sacrificial core SC2 and the width Ws of the spacer 150 can be equal to the first width Ws of the first sacrificial core SC1. When the width is W1, the second width Wb of the second active area AT2 may be equal to three times the first width Wa of the first active area AT1. In other words, referring to FIGS. 7 to 8 , each of the second active areas AT2 The second width Wb ( FIG. 8 ) may be equal to the sum of the second width W2 of the second sacrificial core SC2 and the two widths Ws of the two spacers 150 on the sidewalls of the second sacrificial core SC2 ( FIG. 7 ).

After the anisotropic etching of the substrate 101 is completed, part of the hard mask layer 115 may remain on the first to third active regions AT1 , AT2 and AT3 . The element isolation layer 103 may be formed such that upper portions of the first to third active regions AT1, AT2, and AT3 can protrude. In detail, the device isolation layer 103 can be used to fill the space between the adjacent active regions among the first active region to the third active region AT1 , AT2 and AT3 . The hard mask layer 115 remaining on the first to third active regions AT1, AT2, and AT3 may be removed, and then part of the device isolation layer 103 may be etched to a predetermined depth, so that the first to third active regions The upper parts of the three active areas AT1, AT2 and AT3 can protrude.

According to an exemplary embodiment, the first to third active regions AT1, AT2 and AT3 having different widths may be simultaneously formed in the first to third regions R1, R2 and R3, and the width of the second active region AT2 It may be increased in the second region R2 where an I/O transistor having a FinFET structure or a laterally diffused MOSFET (LDMOS) transistor having a FinFET structure (using a higher voltage than that of the core body transistor) is formed. Therefore, the reliability of hot carrier immunity (HCI) of I/O transistors or laterally diffused MOSFET (LDMOS) transistors can be improved.

9 to 14 are cross-sectional views illustrating stages in a method of manufacturing a semiconductor element according to an exemplary embodiment. The sectional views in FIGS. 9 to 14 correspond to the sectional views shown in FIG. 2 .

Referring to FIG. 9 , a gate insulating layer 111 , a gate conductive layer 113 , a hard mask layer 116 , a sacrificial layer 121 and an anti-reflection layer 125 may be sequentially formed on a substrate 101 . Next, a photoresist may be formed on the sacrificial layer 121 , and then a photoresist pattern 184 in the form of a line is formed by a lithography process.

The first pattern of the photoresist pattern 184 may be formed on the first region R1 with a fourth space S4 therebetween while having a fourth width W4. The first pattern of the photoresist pattern 184 may be formed on the first region R1 at a fourth pitch P4. A second pattern of the photoresist pattern 184 may be formed on the second region R2 with a fifth interval S5 therebetween while having a fifth width W5. The second pattern of the photoresist pattern 184 may be formed on the second region R2 at a fifth pitch P5. The fifth width W5 may be different from the fourth width W4. The fifth interval S5 may be different from the fourth interval S4. A third pattern of the photoresist pattern 184 may be formed on the third region R3 while having the sixth width W6. The fourth width W4 may be determined by considering the interval Sd between the first gate patterns ( GT1 , see FIG. 14 ) to be finally formed. The interval Sd between the first gate patterns GT1 to be finally formed may be narrower than the resolution limit of commercially available lithography equipment.

Referring to FIG. 10, the anti-reflection layer 125 and the sacrificial layer 121 can be anisotropically etched using the photoresist pattern 184 as an etching mask to form a fourth sacrificial core SC4 on the first region R1 and a fourth sacrificial core SC4 on the second region R2. A fifth sacrificial core SC5 is formed and a sixth sacrificial core SC6 is formed on the third region R3. The fourth sacrificial core SC4 may be formed on the first region R1 with a fourth width W4 and a fourth interval S4 (ie, a fourth pitch P4). The fifth sacrificial core SC5 may be formed on the second region R2 with a fifth width W5 and a fifth interval S5 (ie, a fifth pitch P5). The sixth sacrificial core body SC6 can be used in the third The region R3 has a sixth width W6. The sixth width W6 of the sixth sacrificial core SC6 may be greater than the fourth width W4 of the fourth sacrificial core SC4 and the fifth width W5 of the fifth sacrificial core SC5 .

Referring to FIG. 11 , a spacer wall 150 may be formed on the sidewalls of the fourth sacrificial core SC4 , the fifth sacrificial core SC5 , and the sixth sacrificial core SC6 . Therefore, the fourth mask structure SM4 may be formed on the first region R1, the fifth mask structure SM5 may be formed on the second region R2 and the sixth mask structure SM6 may be formed on the third region R3. Each of the fourth mask structure SM4 , the fifth mask structure SM5 and the sixth mask structure SM6 may include a sacrificial layer 121 , an anti-reflection layer 125 and a pair of spacers 150 .

In detail, a spacer material layer conformally covering the fourth sacrificial core body SC4 , the fifth sacrificial core body SC5 , and the sixth sacrificial core body SC6 may be formed. Next, an etch-back process may be performed to form spacers 150 on the sidewalls of the fourth sacrificial core SC4 , the fifth sacrificial core SC5 , and the sixth sacrificial core SC6 .

The thickness of the spacer material layer, that is, the thickness of the spacer 150 can be determined by considering the width Wd of the first gate pattern ( GT1 , see FIG. 14 ) to be finally formed. The width Wd between the first gate patterns GT1 to be finally formed may be narrower than the resolution limit of commercially available lithography equipment.

Referring to FIG. 12 , a protection pattern 186 covering the second region R2 and the third region R3 may be provided. The protection pattern 186 may be formed of, for example, a photoresist material. The protection pattern 186 covers the fifth mask structure SM5 in the second region R2 and the sixth mask structure SM6 in the third region R3, and exposes the fourth mask structure SM4.

By removing the fourth sacrificial core SC4, the spacers 150 remaining on the hard mask layer 116 of the first region R1 may be provided. The spacers 150 may be arranged at intervals equal to the fourth width W4 of the fourth sacrificial core SC4.

Referring to FIG. 13, the spacer 150 on the first region R1, the fifth mask structure SM5 on the second region R2, and the sixth mask structure SM6 on the third region R3 can be used as etching masks to anisotropically The hard mask layer 116 is etched. While the hard mask layer 116 may be anisotropically etched, part or all of the spacer 150 , the fifth mask structure SM5 and the sixth mask structure SM6 may be consumed.

Referring to FIG. 14, the gate conductive layer 113 and the gate insulating layer 111 can be anisotropically etched using the patterned hard mask layer 116 as an etching mask to form a first gate on the first region R1 of the substrate 101. pattern GT1, a second gate pattern GT2 is formed on the second region R2 and a third gate pattern GT3 is formed on the third region R3. The fifth width We of the second gate pattern GT2 may be greater than the fourth width Wd of the first gate pattern GT1, and the sixth width Wf of the third gate pattern GT3 may be greater than the fifth width We of the second gate pattern GT2. . The fifth width We of the second gate pattern GT2 may be greater than twice the fourth width Wd of the first gate pattern GT1. The fifth interval Se of the second gate pattern GT2 may be equal to the fourth interval Sd of the first gate pattern GT1, or may be greater than the fourth interval Sd of the first gate pattern GT1.

According to exemplary embodiments, first to third gate patterns GT1, GT2 and GT3 having different widths may be simultaneously formed in the first to third regions R1, R2 and R3. By performing a gate replacement process, the first to third gate patterns GT1, GT2, and GT3 can be replaced by It is replaced by the first gate structure to the third gate structure GS1, GS2 and GS3 shown in FIG. 1 and FIG. 2 .

15 to 23 are cross-sectional views illustrating stages in a method of manufacturing a semiconductor element according to an exemplary embodiment. The sectional views in FIGS. 15 to 23 correspond to the sectional views shown in FIG. 2 .

Referring to FIG. 15 , a hard mask layer 115 , a sacrificial layer 121 , an antireflection layer 125 , an upper sacrificial layer 141 and an upper antireflection layer 145 may be sequentially formed on a substrate 101 .

The substrate 101 can be a semiconductor substrate such as a silicon wafer. For example, the substrate 101 may be a silicon-on-insulator (SOI) substrate.

The hard mask layer 115 can be made of silicon-containing material (eg, silicon oxide (SiO _x ), silicon oxynitride (SiON), silicon nitride ( _Six N _y ) or polysilicon), carbon-containing material (eg, amorphous carbon layer ( ACL) or spin-on-hard-mask (SOH)) and metal. For example, hard mask layer 115 may include multiple layers.

The sacrificial layer 121 and the upper sacrificial layer 141 may each include, for example, at least one of polysilicon, an amorphous carbon layer (ACL), and a spin-on hard mask (SOH).

The anti-reflection layer 125 and the upper anti-reflection layer 145 may be layers for preventing light reflection during the lithography process. The anti-reflection layer 125 and the upper anti-reflection layer 145 can be formed of, for example, a silicon oxynitride film (SiON).

The hard mask layer 115, the sacrificial layers 121 and 141, and the anti-reflection layers 125 and 145 may be formed using, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), spin coating, and the like. Depending on the material, a baking process or a curing process may additionally be performed. Then, a photoresist can be formed on the upper sacrificial layer 141, and then a lithography process can be used to form a line form the first photoresist pattern 190 .

The substrate 101 may have a first region R1', a second region R2' and a third region R3'. The first region R1' may be a region where core transistors are formed, and the second region R2' may be a region where I/O transistors or laterally diffused MOSFET (LDMOS) transistors are formed using a voltage higher than that of the core transistors. crystal region, and the third region R3' may be a region where a planar transistor is formed.

A first pattern of the first photoresist pattern 190 may be formed on the first region R1' at a first interval S11 while having a first width W11. A first pattern of the first photoresist pattern 190 may be formed on the first region R1' at a first pitch P11. The first pitch P11 may be defined as the sum of the first width W11 and the first interval S11. The second pattern of the first photoresist pattern 190 may be formed on the second region R2' with the second interval S12 while having the second width W12. The second pattern of the first photoresist pattern 190 may be formed on the second region R2' at a second pitch P12. The second pitch P12 may be defined as the sum of the second width W12 and the second interval S12. The second width W12 may be different from the first width W11. The second interval S12 may be different from the first interval S11.

Referring to FIG. 16, the upper anti-reflection layer 145 and the upper sacrificial layer 141 may be anisotropically etched using the first photoresist pattern 190 as an etching mask to form a first upper sacrificial core SC1' on the first region R1'. And a second upper sacrificial core body SC2' is formed on the second region R2'. The first upper sacrificial core SC1' may be formed on the first region R1' with a first width W11 and a first interval S11 (ie, a first pitch P11). The second upper sacrificial core SC2' may be formed on the second region R2' with a second width W12 and a second interval S12 (ie, a second pitch P12).

Referring to FIG. 17 , a first spacer wall 155 may be provided on a sidewall of the first upper sacrificial core SC1' and a sidewall of the second upper sacrificial core SC2'. Specifically, a first spacer material layer conformally covering the first upper sacrificial core body SC1 ′ and the second upper sacrificial core body SC2 ′ may be formed, and then an etch-back process is performed to form a layer on the first upper sacrificial core body SC1 ′. ' and the sidewalls of the second upper sacrificial core body SC2' are formed with a first spacer wall 155.

The thickness of the first spacer material layer can be determined by considering the interval Sa' between the first active regions (AT1', see FIG. 23 ) to be finally formed. The interval Sa' between the first active regions AT1' to be finally formed may be narrower than the resolution limit of commercially available lithography equipment.

The first spacer material layer may be formed of a material having etch selectivity with respect to the material of the upper sacrificial layer 141 . For example, when the upper sacrificial layer 141 can be formed of, for example, one of polysilicon, amorphous carbon layer (ACL) and spin-on hard mask (SOH), the first spacer material layer can be formed of, for example, silicon oxide or silicon nitride form. The first layer of spacer material may be formed using atomic layer deposition (ALD).

Referring to FIG. 18 , the first upper sacrificial core SC1' and the second upper sacrificial core SC2' can be selectively removed relative to the first spacer 155, and the first spacer independently retained on the sacrificial layer 121 can be provided. 155. In addition, a second photoresist pattern 192 having a third width W13 wider than the first width W11 of the first upper sacrificial core SC1' may be formed on the third region R3'. The third width W13 of the second photoresist pattern 192 may be a component that ultimately determines the width Wc' of the third active region AT3'. In this regard, the width W13 of the second photoresist pattern 192 can be adjusted, thereby freely adjusting the third active region. Width Wc' of domain AT3'.

Referring to FIG. 19 , a first lower sacrificial core SC1 ″ may be formed on the first region R1 ′, a second lower sacrificial core SC2 ″ may be formed on the second region R2 ′, and may be formed on the third region R3 ′. The third lower sacrificial core body SC3 ". The antireflection layer 125 and the sacrificial layer 121 can be etched using the first spacer 155 and the second photoresist pattern 192 as an etching mask. Therefore, the first hard mask layer 115 can be formed on the hard mask layer 115. The first lower sacrificial core body SC1", the second lower sacrificial core body SC2" and the third lower sacrificial core body SC3". The first lower sacrificial core SC1 ″ and the second lower sacrificial core SC2 ″ may be formed in a position corresponding to the position of the first spacer 155 , and the third lower sacrificial core SC3 ″ may be formed in a position corresponding to the position of the second optical spacer 155 . In the position corresponding to the position of the resist pattern 192 .

The first lower sacrificial cores SC1 ″ may be formed on the first region R1 ′ at a fourth interval S1 ′ while having a fourth width W1 ′. The first lower sacrificial cores SC1 ″ may have a fourth pitch P1 ′. form. The second lower sacrificial cores SC2" may be formed on the second region R2' at a fifth interval S2' while having a fifth width W2'. The second lower sacrificial cores SC2" may be formed at a fifth pitch P2'. The third lower sacrificial core SC3" may have a sixth width W3' greater than the fourth width W1' and the fifth width W2'.

Referring to FIG. 20 , second spacer walls 150 may be formed on the sidewalls of the first lower sacrificial core SC1 ″, the second lower sacrificial core SC2 ″, and the third lower sacrificial core SC3 ″. Therefore, , the first mask structure SM1' can be formed on the first region R1', the second mask structure SM2' can be formed on the second region R2', and the third mask structure SM3 can be formed on the third region R3' '. Each of the first mask structure SM1', the second mask structure SM2' and the third mask structure SM3' may include a lower sacrificial layer 121 , a lower anti-reflection layer 125 and a pair of second spacers 150 .

In particular, a second spacer material layer conformally covering the first lower sacrificial core SC1 ″, the second lower sacrificial core SC2 ″, and the third lower sacrificial core SC3 ″ may be formed, and then a return step may be performed. etch process to form the second spacers 150 on the sidewalls of the first lower sacrificial core SC1 ″, the second lower sacrificial core SC2 ″ and the third lower sacrificial core SC3 ″.

The thickness of the second spacer material layer, that is, the width Ws' of the second spacer 150 can be determined by considering the width Wa' of the first active region (AT1', see FIG. 23 ) to be finally formed. The width Wa' of the first active area AT1' to be finally formed may be smaller than the resolution limit of commercially available lithography equipment.

The second spacer material layer may be formed of a material having etch selectivity with respect to the material of the lower sacrificial layer 121 . For example, when the lower sacrificial layer 121 may be formed of one of polysilicon, amorphous carbon layer (ACL) and spin-on-hard-mask (SOH), the second spacer material layer may be formed of silicon oxide or silicon nitride. The second spacer material layer may be formed using atomic layer deposition (ALD).

Referring to FIG. 21 , a protection pattern 194 covering the second region R2' and the third region R3' may be provided. The protection pattern 194 may be formed of, for example, a photoresist material. The protection pattern 194 covers the second mask structure SM2' in the second region R2' and the third mask structure SM3' in the third region R3', and exposes the first mask structure SM1'.

By removing the first lower sacrificial core SC1 ″, the second spacer 150 remaining on the hard mask layer 115 of the first region R1 ′ can be provided. The second spacer 150 can be separated from the first lower sacrificial core The fourth width W1' of the body SC1" is equally spaced for matching place.

Referring to FIG. 22, the second spacer 150 on the first region R1', the second mask structure SM2' on the second region R2', and the third mask structure SM3' on the third region R3' can be used as etching mask to anisotropically etch the hard mask layer 115. While the hard mask layer 115 may be anisotropically etched, part or all of the second spacer 150, the second mask structure SM2' and the third mask structure SM3' may be consumed.

Referring to FIG. 23, the substrate 101 may be anisotropically etched using the patterned hard mask layer 115 as an etching mask to form a first active region AT1' on the first region R1' of the substrate 101, and a first active region AT1' on the second region R2. The second active region AT2' is formed on ', and the third active region AT3' is formed on the third region R3'. After the anisotropic etching of the substrate 101 is completed, portions of the hard mask layer 115 may remain on the first to third active regions AT1', AT2' and AT3'. As shown in FIG. 23, the pitch Pa' is equal to the sum of the width Wa' and the interval Sa' of the single first active area AT1', and the pitch Pb' is equal to the width Wb' and the interval Sb' of the single second active area AT2' of and.

The element isolation layer 103 may be formed such that upper portions of the first to third active regions AT1', AT2', and AT3' can protrude. In detail, the device isolation layer 103 can be used to fill the space between the first active region to the third active region AT1', AT2' and AT3'. The hard mask layer 115 remaining on the first to third active regions AT1', AT2' and AT3' may be removed, and then part of the device isolation layer 103 may be etched to a predetermined depth, so that the first active region The upper parts of the areas to the third active areas AT1 ′, AT2 ′ and AT3 ′ can protrude.

In summary, the exemplary embodiments provide a method capable of forming widths different from each other A method of manufacturing semiconductor elements with different fine patterns. That is, according to exemplary embodiments, fine patterns including fine patterns (eg, active regions and gate patterns) having different widths (eg, in which I/O transistors can be formed) can be fabricated without removing the mandrel. Or a laterally diffused MOSFET (LDMOS) where the active fin of the region can be wider than the active fin of the region where the core transistor can be formed). In other words, while using the same mandrel (ie, using the spacer formed on the side of the mandrel as a mask for the wider pattern), fine patterns having different widths can be formed simultaneously. Therefore, a single mandrel with two spacers in its sidewalls can be used as an etch mask for a dry etch process, thereby improving the manufacturing process and providing semiconductor devices with excellent reliability.

Exemplary embodiments have been disclosed herein, and although specific terms are employed, such terms are used and interpreted in a generic, descriptive sense only, and not of limitation. In some cases, as will be apparent to those of ordinary skill in the art, as of the filing of this application, unless specifically indicated otherwise, features, characteristics, and/or components described in connection with a particular embodiment may be independently described Use or combine features, characteristics and/or components described in connection with other embodiments. Accordingly, those of ordinary skill in the art will understand that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.

101: Substrate

115: Hard mask layer

150: spacer/second spacer

182: protection pattern

P2: second pitch

R1: the first region

R2: second region

R3: the third area

S2: second interval

SM2: Second mask structure

SM3: Third mask structure

W1: first width

W2: second width

W3: third width

Ws: width

Claims (19)

A method of manufacturing a semiconductor element, the method comprising: forming a first sacrificial core on a first region of a lower structure, and forming a second sacrificial core on a second region of the lower structure; A spacer wall is formed on the side wall of the sacrificial core and the side wall of the second sacrificial core; a protective pattern covering the second sacrificial core on the second region of the lower structure is formed; from the first removing the first sacrificial core in an area; and etching the lower structure using the spacer on the first area and the second sacrificial core and the spacer on the second area , wherein the width of the first sacrificial core is equal to the width of the second sacrificial core. The method for manufacturing a semiconductor element as described in claim 1 of the scope of the patent application, wherein: the lower structure includes a semiconductor substrate, and etching the lower structure includes: forming a first active area with a first width in the first region region; and forming a second active region having a second width in the second region such that the second width is greater than the first width. The method of manufacturing semiconductor elements as described in item 2 of the scope of patent application method, wherein the second width is greater than twice the first width. The method for manufacturing a semiconductor device as described in claim 1 of the patent scope, wherein: the lower structure includes a gate conductive layer, and etching the lower structure includes: forming a first region having a third width in the first region a gate pattern; and a second gate pattern having a fourth width greater than the third width formed in the second region. The method for manufacturing a semiconductor device as described in claim 4, wherein the fourth width is greater than twice the third width. The method for manufacturing a semiconductor device as described in claim 1, wherein the width of the spacer is equal to the width of the first sacrificial core. The method for manufacturing a semiconductor element as described in claim 1 of the patent scope, wherein forming the first sacrificial core and the second sacrificial core includes forming a third sacrificial core on the third region of the lower structure , causing the third sacrificial core to have a width wider than each of the width of the second sacrificial core and the width of the first sacrificial core. The method for manufacturing a semiconductor element as described in claim 7 of the patent scope, wherein forming the spacer on the sidewall of the first sacrificial core and the sidewall of the second sacrificial core includes forming the spacer on the third sacrificial core. The spacers are formed on the sidewalls of the sacrificial core. The method of manufacturing a semiconductor device according to claim 8, wherein forming the protective pattern covering the second sacrificial core on the second region of the lower structure includes forming a covering pattern covering the third area on the protection pattern of the third sacrificial core. The method of manufacturing a semiconductor element as described in claim 9, wherein etching the lower structure includes using the spacer on the first region, the second sacrificial core on the second region and the third sacrificial core and the spacer on the spacer and the third region to etch the lower structure. The method for manufacturing a semiconductor device as described in claim 10 of the scope of the patent application, wherein: the lower structure includes a semiconductor substrate, and etching the lower structure includes: forming a first active area with a first width in the first region region; forming a second active region having a second width greater than the first width in the second region; and forming a second active region having a third width greater than the second width in the third region The third active area. The method for manufacturing a semiconductor element as described in item 10 of the scope of the patent application, wherein: the lower structure includes a gate conductive layer, and etching the lower structure includes: A first gate pattern having a fourth width is formed in the first region; a second gate pattern having a fifth width greater than the fourth width is formed in the second region; and A third gate pattern having a sixth width larger than the fifth width is formed in the third region. A method of manufacturing a semiconductor element, the method comprising: preparing a lower structure having a first region, a second region and a third region; forming a first sacrificial core with a first width on the first region, and A second sacrificial core with a second width is formed on the second area, and a third sacrificial core with a third width larger than the first width and the second width is formed on the third area forming a spacer on the first region of the lower structure, forming a first mask structure including the second sacrificial core and the spacer on the second region of the lower structure, and forming a second mask structure including the third sacrificial core and the spacer on the third region of the lower structure; and using the spacer, the first mask structure and the The second mask structure etches the lower structure, wherein the first width is equal to the second width, and the width of the spacer is equal to the first width. The method for manufacturing a semiconductor device as described in item 13 of the scope of the patent application, wherein forming the spacer, the first mask structure, and the second mask structure includes: The gap wall is formed on the side wall of the first sacrificial core body, the side wall of the second sacrificial core body and the side wall of the third sacrificial core body; The protection pattern of the third sacrificial core on the second sacrificial core and the third region; removing the first sacrificial core from the first region; and removing the protection pattern. The method for manufacturing a semiconductor element according to claim 13, wherein: the lower structure includes a semiconductor substrate, and etching the lower structure includes: forming a plurality of first an active region, and the first active region has a width equal to the width of the spacer; a plurality of second active regions are formed with intervals equal to the second width, and the second active region has a smaller a width greater than the width of the first active region; and forming a third active region having a width greater than the width of the second active region. The method for manufacturing a semiconductor element as described in claim 13 of the patent application, wherein: the lower structure includes a semiconductor substrate, and etching the lower structure includes: A first active region having the first width is formed in the first region; a second active region having a width equal to three times the first width is formed in the second region; and A third active region having a width larger than the width of the second active region is formed in the third region. A method of manufacturing a semiconductor element, the method comprising: stacking a lower sacrificial layer and an upper sacrificial layer on a lower structure having a first region, a second region, and a third region; A first upper sacrificial core is formed on the first area and a second upper sacrificial core is formed on the second area; on the side wall of the first upper sacrificial core and the side wall of the second upper sacrificial core forming a first spacer; removing the first upper sacrificial core and the second upper sacrificial core; wide photoresist pattern; forming a first lower sacrificial core on the first region by etching the lower sacrificial layer using the first spacer and the photoresist pattern as an etch mask, A second lower sacrificial core is formed on the second area and a third lower sacrificial core is formed on the third area; on the sidewall of the first lower sacrificial core, the second lower sacrificial core A second spacer wall is formed on the side wall of the body and the side wall of the third lower sacrificial core; forming a protection pattern covering the second region and the third region; removing the first lower sacrificial core formed on the first region; and using the first lower sacrificial core formed on the first region Two spacers, the second lower sacrificial core body and the second spacer wall on the second region, and the third lower sacrificial core body and the second spacer wall on the third region The lower structure is etched, wherein the first lower sacrificial core and the second lower sacrificial core have the same width. The method for manufacturing a semiconductor device as described in claim 17 of the scope of the patent application, wherein: the lower structure includes a semiconductor substrate, and etching the lower structure includes: forming a first active area with a first width in the first region region; forming a second active region having a second width greater than the first width in the second region; and forming a second active region having a third width greater than the second width in the third region The third active area. The method of manufacturing a semiconductor device according to claim 18, wherein the second width is greater than twice the first width.