CN113299597A - Method for forming shallow trench isolation structure - Google Patents
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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Abstract
The invention provides a method for forming a shallow trench isolation structure, which is applied to the field of semiconductors. In the method for forming the shallow trench isolation structure, the process of the back etching process flow for forming the shallow trench isolation structure in the NAND flash memory in the prior art is adjusted, so that the floating gate layer in the gate stack structure is protected by using the hard mask layer in the process of forming the shallow trench isolation structure, the loss of the back etching process to the floating gate layer is avoided, the back etching depth and the appearance of the shallow trench isolation structure are ensured, the uniformity of the height of the floating gate in the finally formed gate structure is improved, and the purpose of improving the storage characteristic uniformity of the NAND flash memory is finally realized.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a shallow trench isolation structure.
Background
With the development of semiconductor process technology, flash memories (flash memories) with faster access speed have been developed for memory devices. Flash memory has the characteristics of being capable of storing, reading and erasing information for many times, and the stored information does not disappear after power failure, so flash memory has become a nonvolatile memory widely used in personal computers and electronic devices. NAND flash memory is widely used in the field where read/write requirements are high due to its large storage capacity and relatively high performance.
At present, with the continuous reduction of the critical dimension of NAND flash memory devices, the problem of mutual interference between floating gates (floating gates) of adjacent memory cells in NAND flash memory arrays occurs. In view of this problem, the prior art has been to reduce the mutual interference between floating gates in adjacent memory cells by increasing the etch-back depth of shallow trench isolation structures used to isolate different memory cells in a NAND flash memory array.
FIG. 1 is a schematic flow chart of a prior art process for forming shallow trench isolation structures of adjacent memory cells in a NAND flash memory array. As shown in fig. 1, the conventional process for forming the shallow trench isolation structure of the device includes: providing a semiconductor substrate 100, and forming a gate oxide layer 110, a floating gate layer 120 and a hard mask layer 130 on the semiconductor substrate 100; the semiconductor substrate 100 is subjected to an etching process to form a plurality of shallow trenches for isolating the memory cells on the semiconductor substrate, and the shallow trenches are filled with an insulating material so that the top surfaces of the insulating material are flush with the top surface of the hard mask layer 130, and then the insulating material filled in the shallow trenches is subjected to back etching so that the top surfaces of the insulating material after the back etching are flush with the top surface of the floating gate layer 120. And then, removing the hard mask layer 130, and further performing a back etching process on the back etched insulating material to form a shallow trench isolation structure which finally meets the design requirements.
However, in the existing process of forming the shallow trench isolation structure, after the hard mask layer covering the top surface of the floating gate layer is removed, and then the insulating material filled in the shallow trench is etched back, the top of the floating gate layer does not have any mask protection film layer, so that the loss of the floating gate layer is caused in the etching process, the difference of the loss of a plurality of floating gates in the NAND flash memory array is further aggravated by the line width floating of the floating gate layer, and finally, the performance of a final device is affected by the overlarge height difference of the floating gates.
Disclosure of Invention
The invention aims to provide a method for forming a shallow trench isolation structure, which aims to realize the purpose of improving the height uniformity of a floating gate in a gate structure while ensuring the etch-back depth and the appearance of the shallow trench isolation structure.
In a first aspect, to solve the above technical problem, the present invention provides a method for forming a shallow trench isolation structure, where the method may include:
providing a semiconductor substrate, wherein a plurality of discrete gate stack structures and shallow trenches positioned between the adjacent gate stack structures are formed on the semiconductor substrate, each gate stack structure comprises a gate oxide layer, a floating gate layer and a hard mask layer which are sequentially stacked along the direction far away from the semiconductor substrate, insulating material layers are filled in the shallow trenches, and the shallow trenches are at least filled with the insulating material layers;
taking the hard mask layer as a mask, and etching back the insulating material layer by adopting a first isotropic etching process so as to enable the top surface of the insulating material layer in the shallow trench to be lower than the floating gate layer;
taking the hard mask layer as a mask, and adopting a first anisotropic etching process to etch the insulating material layer in the shallow trench again so as to enable the top surface of the insulating material layer left in the shallow trench to be flat;
removing the hard mask layer by adopting a second isotropic etching process so as to respectively expose the top surfaces of the floating gate layers in the gate stack structures;
etching the floating gate layer by adopting a second anisotropic etching process to adjust the top of the floating gate layer to be a dome;
and etching the insulating material layer in the shallow trench again by adopting a third isotropic etching process so as to enable the top height and the appearance of the insulating material layer in the shallow trench to meet the target design requirements.
Further, the first isotropic etching process, the second isotropic etching process and the third isotropic etching process may be wet etching processes or gas phase etching processes, and the first anisotropic etching process and the second anisotropic etching process may be dry etching processes.
Further, the etching solution of the first isotropic etching process may include: hydrofluoric acid, the etching selection ratio of the hydrofluoric acid to the insulating material layer can be greater than: 40:1.
Further, the etching gas of the first anisotropic etching process may include: the insulating material layer is formed by an etching gas, the insulating material layer is formed by an etching gas and an etching gas, wherein the etching gas comprises the following etching gases: 2:1.
Further, after the insulating material layer in the shallow trench is etched back again by using the third isotropic etching process, the top surface of the remaining insulating material layer may be higher than the bottom surface of the floating gate layer, and the height of the top surface of the remaining insulating material layer higher than the bottom surface of the floating gate layer may be:
further, after the insulating material layer in the shallow trench is etched back again by adopting a third isotropic etching process, the top of the remaining insulating material layer is made to be V-shaped or U-shaped.
Further, the step of forming the gate stack structure, the shallow trench and the insulating material layer on the semiconductor substrate may include:
forming the gate oxide layer, the floating gate layer and the hard mask layer on the semiconductor substrate from bottom to top in sequence;
etching the floating gate layer, the gate oxide layer and the semiconductor substrate with partial thickness by using the hard mask layer as a mask and adopting a self-alignment type double-pattern process to form a plurality of gate stack structures, wherein the shallow trenches are arranged between the adjacent gate stack structures;
depositing an insulating material layer in the shallow trench, wherein the insulating material layer at least fills the trench;
and performing top planarization on the insulating material layer until the top surface of the insulating material layer is flush with the top surface of the gate stack structure.
Further, the method for forming the shallow trench isolation structure provided by the present invention may further include:
and sequentially forming an inter-gate dielectric layer and a control gate layer on the semiconductor substrate, wherein the inter-gate dielectric layer covers the surface of each floating gate layer, and the control gate layer covers the surface of the inter-gate dielectric layer.
Further, the hard mask layer may be a single-layer structure of a nitride layer or an oxide layer, or the hard mask layer may be a multi-layer structure of an ONO stack.
Further, before the floating gate layer is etched by adopting a second anisotropic etching process, the side wall of the floating gate layer is covered with a residual insulating material layer; and when the top surface of the floating gate layer is etched by adopting a second anisotropic etching process, removing the redundant insulating material layer covered on the side wall of the floating gate layer, and further etching the exposed side wall of the floating gate layer to reduce the line width of the floating gate layer.
Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:
in the method for forming the shallow trench isolation structure, the process of the back etching process flow for forming the shallow trench isolation structure in the NAND flash memory in the prior art is adjusted, so that the floating gate layer in the gate stack structure is protected by using the hard mask layer in the process of forming the shallow trench isolation structure, the loss of the back etching process to the floating gate layer is avoided, the back etching depth and the appearance of the shallow trench isolation structure are ensured, the uniformity of the height of the floating gate in the finally formed gate structure is improved, and the purpose of improving the storage characteristic uniformity of the NAND flash memory is finally realized.
Furthermore, under the condition that the hard mask layer comprises a floating gate in a gate structure, the insulating material layer filled in the shallow trench is firstly subjected to a wet etching process with high etching selectivity, so that the etching amount of the insulating material layer removed in the direction vertical to the semiconductor substrate is larger than that of the insulating material layer removed in the direction vertical to the floating gate layer, and then the dry etching process with the etching selection ratio smaller than that of the previous step is carried out, while exposing the sidewall of the floating gate layer with a target height, ensuring the uniformity of the surface of the insulating material layer remaining after the first anisotropic etching process, and furthermore, the integrity of the floating gate layer is protected, and meanwhile, the uniformity of an insulating material layer filled in the shallow trench is improved, so that the shallow trench isolation structure meeting the design requirement is finally formed.
Drawings
FIG. 1 is a schematic flow chart of a prior art process for forming shallow trench isolation structures of adjacent memory cells in a NAND flash memory array.
FIG. 2 is a flow chart of a method for forming a shallow trench isolation structure in a NAND flash memory array according to the present invention.
FIGS. 3 a-3 f are schematic structural diagrams illustrating a shallow trench isolation structure of adjacent memory cells in a NAND array during a manufacturing process according to an embodiment of the present invention.
Wherein the reference numbers are as follows:
100/200-a semiconductor substrate; 110/210-gate oxide layer;
120/220/220' -floating gate layer; 130/230-hard mask layer;
140/140 '/240 "/240"'/240 "" -a layer of insulating material;
251-gate stack structure.
Detailed Description
As described in the background, with the continuous reduction of the critical dimension of NAND flash memory devices, the problem of mutual interference between floating gates (floating gates) of adjacent memory cells in NAND flash memory arrays is present. In view of this problem, the prior art has been to reduce the mutual interference between floating gates in adjacent memory cells by increasing the etch-back depth of shallow trench isolation structures used to isolate different memory cells in a NAND flash memory array.
As shown in fig. 1, the conventional process for forming the shallow trench isolation structure of the device includes: providing a semiconductor substrate 100, and forming a gate oxide layer 110, a floating gate layer 120 and a hard mask layer 130 on the semiconductor substrate 100; the semiconductor substrate 100 is subjected to an etching process to form a plurality of shallow trenches for isolating the memory cells on the semiconductor substrate, and the shallow trenches are filled with an insulating material so that the top surfaces of the insulating material are flush with the top surface of the hard mask layer 130, and then the insulating material filled in the shallow trenches is subjected to back etching so that the top surfaces of the insulating material after the back etching are flush with the top surface of the floating gate layer 120. And then, removing the hard mask layer 130, and further performing a back etching process on the back etched insulating material to form a shallow trench isolation structure which finally meets the design requirements.
However, in the existing process of forming the shallow trench isolation structure, after the hard mask layer covering the top surface of the floating gate layer is removed, and then the insulating material filled in the shallow trench is etched back, the top of the floating gate layer is not provided with any mask protection film layer, so that the loss of the floating gate layer is caused in the etching process, the difference of the loss of a plurality of floating gates in the NAND flash memory array is further aggravated by the line width floating of the floating gate layer, and finally, the performance of a final device is affected by the overlarge height difference of the floating gates.
Therefore, the invention provides a method for forming a shallow trench isolation structure, which aims to realize the purpose of improving the height uniformity of a floating gate in a gate structure while ensuring the etch-back depth and the appearance of the shallow trench isolation structure.
Referring to fig. 2, fig. 2 is a flowchart illustrating a method for forming a shallow trench isolation structure in a NAND flash memory array according to an embodiment of the present invention. Specifically, the method for forming the shallow trench isolation structure may include the following steps:
step S100, providing a semiconductor substrate, forming a plurality of discrete gate stack structures and shallow trenches between adjacent gate stack structures on the semiconductor substrate, wherein each gate stack structure comprises a gate oxide layer, a floating gate layer and a hard mask layer which are sequentially stacked along a direction far away from the semiconductor substrate, insulating material layers are filled in the shallow trenches, and the shallow trenches are at least filled with the insulating material layers;
step S200, with the hard mask layer as a mask, etching back the insulating material layer by adopting a first isotropic etching process so as to enable the top surface of the insulating material layer in the shallow trench to be lower than the floating gate layer;
step S300, with the hard mask layer as a mask, adopting a first anisotropic etching process to etch back the insulating material layer in the shallow trench again so as to enable the top surface of the residual insulating material layer in the shallow trench to be flat;
step S400, removing the hard mask layer by adopting a second isotropic etching process so as to respectively expose the top surfaces of the floating gate layers in the gate stack structures;
step S500, etching the floating gate layer by adopting a second anisotropic etching process to adjust the top of the floating gate layer to be a dome;
and step S600, re-etching the insulating material layer in the shallow trench by adopting a third isotropic etching process so as to enable the top height and the appearance of the insulating material layer in the shallow trench to meet the target design requirements.
That is, in the method for forming a shallow trench isolation structure provided by the present invention, the process of the back-etching process flow for forming a shallow trench isolation structure in a NAND flash memory in the prior art is adjusted, so that the floating gate layer in the gate stack structure is protected by using the hard mask layer in the process of forming the shallow trench isolation structure, and further, the loss of the back-etching process to the floating gate layer is avoided, so that the back-etching depth and morphology of the shallow trench isolation structure are ensured, the uniformity of the height of the floating gate in the finally formed gate structure is improved, and the purpose of improving the uniformity of the storage characteristics of the NAND flash memory is finally realized.
The method for forming the shallow trench isolation structure according to the present invention is further described in detail with reference to the accompanying drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 3a to fig. 3f are schematic structural diagrams illustrating a method for forming a shallow trench isolation structure between adjacent memory cells in a NAND flash memory array in a manufacturing process according to an embodiment of the present invention.
In step S100, specifically referring to fig. 3a, a semiconductor substrate 200 is provided, a plurality of discrete gate stack structures 251 and shallow trenches located between adjacent gate stack structures 251 are formed on the semiconductor substrate 200, the gate stack structures 251 include a gate oxide layer 210, a floating gate layer 220 and a hard mask layer 230 stacked in sequence along a direction away from the semiconductor substrate 200, the shallow trenches are filled with an insulating material layer 240, and the insulating material layer 240 at least fills the shallow trenches.
The gate oxide layer 210 may be an oxide, such as silicon dioxide, the floating gate layer 220 may be a polysilicon layer, and the hard mask layer 230 may be a single-layer structure of a nitride layer or an oxide layer, such as silicon nitride or silicon dioxide, or the hard mask layer 230 may be a multi-layer structure of an ONO stack.
In addition, the semiconductor substrate 200 provides a process platform for the subsequent formation of flash memory. In the embodiment of the present invention, the semiconductor substrate 200 is used to form a NAND Flash (NAND Flash) device.
In this embodiment, the semiconductor substrate 200 is a silicon substrate. In other embodiments, the material of the semiconductor substrate 200 may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the semiconductor substrate 200 may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the semiconductor substrate 200 may be a material suitable for process requirements or easy integration.
Further, an embodiment of the present invention further provides a specific manner for forming the gate stack structure 251, the shallow trench, and the insulating material layer 240 on the semiconductor substrate 200, which may include the following steps:
firstly, forming the gate oxide layer 210, the floating gate layer 220 and the hard mask layer 230 on the semiconductor substrate 200 from bottom to top in sequence;
then, using the hard mask layer 230 as a mask, etching the floating gate layer 220, the gate oxide layer 210 and a part of the thickness of the semiconductor substrate 200 by using a self-aligned dual patterning process SADP to form a plurality of gate stack structures 251, wherein the shallow trenches (not shown) are located between adjacent gate stack structures 251;
secondly, depositing an insulating material layer 240 in the shallow trench, wherein the insulating material layer 240 at least fills the trench;
finally, the insulating material layer 240 is top planarized until the top surface of the insulating material layer 240 is flush with the top surface of the gate stack 251 to form the pattern shown in fig. 3 a.
In step S200, referring specifically to fig. 3b, the insulating material layer 240 is etched back by using the hard mask layer 230 as a mask and a first isotropic etching process, so that the top surface of the insulating material layer 240' in the shallow trench is lower than the floating gate layer 220.
In this embodiment, the first isotropic etching process may be a wet etching process or may also be a vapor etching process. For example, when the first isotropic etching process is a wet etching process, the etching solution of the first isotropic etching process may include: hydrofluoric acid, and the etching selectivity ratio of the hydrofluoric acid to the insulating material layer 240 and to the hard mask layer 230 may be greater than: 40:1, while the etch selectivity of the hydrofluoric acid to the insulating material layer 240 and to the floating gate layer 220 may be greater than 50: 1. Since in the embodiment of the present invention, the etching rate of the insulating material layer 240 by the first isotropic etching process is faster than that of the hard mask layer 230, the insulating material layer 240 can be removed approximately along the direction perpendicular to the semiconductor substrate 200 within a certain period of time, and the floating gate layer 220 is not removed along the direction perpendicular to the sidewall of the gate stack 251, so that the insulating material layer 240 is etched back on the basis of ensuring that the floating gate layer 220 is not damaged.
In step S300, referring to fig. 3c specifically, with the hard mask layer 230 as a mask, the insulating material layer 240' in the shallow trench is etched back again by using a first anisotropic etching process, so that the top surface of the insulating material layer 240 ″ remaining in the shallow trench is planarized.
The first anisotropic etching process may be a dry etching process, and etching gas of the dry etching process may include: the insulating material layer is formed by six-fluorine butadiene, argon and oxygen, and the etching selection ratio of the etching gas to the insulating material layer is as follows: 2:1.
In this embodiment, compared with the prior art, the step of removing a part of the insulating material layer in the shallow trench by the one-step dry or wet etching back process after filling the insulating material layer in the shallow trench in the prior art is divided into two etching processes, that is, the step S100 and the step S200 described above, so that a problem that when the one-step etching process is used to remove a part of the insulating material layer in the shallow trench in the prior art, an etching rate of the insulating material layer by the dry etching back process is not high enough, so that a sidewall or a top of the floating gate layer is etched while the insulating material layer is etched, and further, a height and a morphology of the floating gate layer do not meet target design requirements is avoided.
In other words, in the method for forming the shallow trench isolation structure provided by the invention, the process of the back-etching process flow for forming the shallow trench isolation structure in the NAND flash memory in the prior art is adjusted, so that the floating gate layer in the gate stack structure is protected by using the hard mask layer in the process of forming the shallow trench isolation structure, the loss of the back-etching process to the floating gate layer is further avoided, the back-etching depth and the shape of the shallow trench isolation structure are ensured, the uniformity of the height of the floating gate in the finally formed gate structure is improved, and the purpose of improving the storage characteristic uniformity of the NAND flash memory is finally realized.
In step S400, referring to fig. 3d specifically, the hard mask layer 230 is removed by a second isotropic etching process to expose the top surface of the floating gate layer 220 in each of the gate stack structures 251.
The second isotropic etching process may be a wet etching process, an etching solution of the wet etching process may include triphosphoric acid, an etching selection ratio of the etching solution to the hard mask layer 230 and to the insulating material layer 240 may be greater than 40:1, and an etching selection ratio of the etching solution to the hard mask layer 230 and to the floating gate layer 220 may be greater than 30: 1.
In this embodiment, after removing a portion of the insulating material layer 240 in the shallow trench through steps S200 and S300 as described above to form the insulating material layer 240 ″ with a flat top surface as shown in fig. 3c, the hard mask layer 230 covering the top surface of the floating gate layer 220 for protecting the floating gate layer 220 from being damaged in the etching process of steps S200 and S300 may be removed first, and then the exposed top of the floating gate layer 220 is trimmed to meet the design requirement through step S500 as follows.
In step S500, referring to fig. 3e specifically, a second anisotropic etching process is used to etch floating gate layer 220 to adjust the top of floating gate layer 220 to be a dome.
In this embodiment, the second anisotropic etching process may be a dry etching process, and specifically, in practical applications, in order to meet various application scenarios, a NAND memory structure is generally required to be designed into a specific shape, so that a certain amount of etching gas may be introduced onto the surface of the semiconductor substrate 200 to adjust the top of the floating gate layer 220 into a certain pattern, for example, in an embodiment of the present invention, in order to avoid a tip discharge phenomenon of a memory cell, the top of the floating gate layer 220 is trimmed into a dome.
It is to be understood that, in the embodiment of the present invention, it is proposed that the top shape of floating gate layer 220 can be adjusted by means of a dry etching process, and in other embodiments, any other trimming process, such as mechanical grinding, etc., may be used, and the present invention is not limited in this respect.
Further, before the floating gate layer 220 is etched by the second anisotropic etching process (dry etching process), the sidewalls of the floating gate layer 220 may be covered with a remaining insulating material layer 240 ″. Therefore, while the top surface of floating gate layer 220 is etched by the second anisotropic etching process (dry etching process), the excess insulating material layer 240 ″ covering the sidewalls of floating gate layer 220 may be removed to obtain an insulating material layer 240 ' ″ as shown in fig. 3e, and the exposed sidewalls of floating gate layer 220 ' are further etched to reduce the line width of floating gate layer 220 '.
In step S600, referring to fig. 3f in particular, the insulating material layer 240 "'in the shallow trench is etched back again by using a third isotropic etching process, so that the top height and the morphology of the insulating material layer 240"' in the shallow trench meet the target design requirements.
In this embodiment, the third isotropic etching process may be a wet etching process, and an etching solution of the wet etching process may be phosphoric acid. Specifically, after the floating gate layer 220 'meeting the target design requirement is formed in step S500, an inter-gate dielectric layer (not shown) and a control gate layer (not shown) need to be formed on the floating gate layer 220'. For example, in the embodiment of the present invention, in order to form a NAND flash memory array structure similar to a fin structure, after the step S500, the third isotropic etching process is adopted to etch back the insulating material layer 240 ' ″ in the shallow trench again, so that the top height and the morphology of the insulating material layer 240 ' ″ in the shallow trench meet the target design requirements, thereby avoiding the problem that the insulating material layer 240 ' ″ filled in the shallow trench cannot well isolate adjacent memory cells and cause leakage of the memory cells due to too large aspect ratio of the shallow trench between the adjacent memory cells in the NAND flash memory array structure when the inter-gate dielectric layer and the control gate layer are formed in subsequent steps.
Specifically, after the insulating material layer 240 '"in the shallow trench is etched back again by using the third isotropic etching process (wet etching process), the top surface of the remaining insulating material layer 240" "is higher than the bottom surface of the floating gate layer 220', and the height of the top surface of the remaining insulating material layer 240" "higher than the bottom surface of the floating gate layer may be:
further, after the insulating material layer 240 '″ in the shallow trench is etched back again by using a third isotropic etching process (wet etching process), the top of the remaining insulating material layer 240' ″ is made to be V-shaped or U-shaped.
In addition, in the method for forming the shallow trench isolation structure provided in the embodiment of the present invention, after the step S600, the method may further include the following steps:
an inter-gate dielectric layer (not shown) and a control gate layer (not shown) are sequentially formed on the semiconductor substrate 200, the inter-gate dielectric layer covers the surface of each floating gate layer 220', and the control gate layer covers the surface of the inter-gate dielectric layer.
In summary, in the method for forming a shallow trench isolation structure provided by the present invention, the back-etching process flow of the shallow trench isolation structure in the NAND flash memory is adjusted in the prior art, so that the floating gate layer in the gate stack structure is protected by the hard mask layer in the process of forming the shallow trench isolation structure, and further, the loss of the back-etching process to the floating gate layer is avoided, so that while the back-etching depth and morphology of the shallow trench isolation structure are ensured, the uniformity of the height of the floating gate in the finally formed gate structure is improved, and the purpose of improving the uniformity of the storage characteristics of the NAND flash memory is finally achieved.
Furthermore, under the condition that the hard mask layer comprises a floating gate in a gate structure, the insulating material layer filled in the shallow trench is firstly subjected to a wet etching process with high etching selectivity, so that the etching amount of the insulating material layer removed in the direction vertical to the semiconductor substrate is larger than that of the insulating material layer removed in the direction vertical to the floating gate layer, and then the dry etching process with the etching selection ratio smaller than that of the previous step is carried out, while exposing the sidewall of the floating gate layer with a target height, ensuring the uniformity of the surface of the insulating material layer remaining after the first anisotropic etching process, and furthermore, the integrity of the floating gate layer is protected, and meanwhile, the uniformity of an insulating material layer filled in the shallow trench is improved, so that the shallow trench isolation structure meeting the design requirement is finally formed.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the present invention.
It should be noted that, although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated. The meaning of "and/or" herein is either or both.
It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.
Claims (10)
1. A method for forming a shallow trench isolation structure is characterized by comprising the following steps:
providing a semiconductor substrate, wherein a plurality of discrete gate stack structures and shallow trenches positioned between the adjacent gate stack structures are formed on the semiconductor substrate, each gate stack structure comprises a gate oxide layer, a floating gate layer and a hard mask layer which are sequentially stacked along the direction far away from the semiconductor substrate, insulating material layers are filled in the shallow trenches, and the shallow trenches are at least filled with the insulating material layers;
taking the hard mask layer as a mask, and etching back the insulating material layer by adopting a first isotropic etching process so as to enable the top surface of the insulating material layer in the shallow trench to be lower than the floating gate layer;
taking the hard mask layer as a mask, and adopting a first anisotropic etching process to etch the insulating material layer in the shallow trench again so as to enable the top surface of the insulating material layer left in the shallow trench to be flat;
removing the hard mask layer by adopting a second isotropic etching process so as to respectively expose the top surfaces of the floating gate layers in the gate stack structures;
etching the floating gate layer by adopting a second anisotropic etching process to adjust the top of the floating gate layer to be a dome;
and etching the insulating material layer in the shallow trench again by adopting a third isotropic etching process so as to enable the top height and the appearance of the insulating material layer in the shallow trench to meet the target design requirements.
2. The method for forming a shallow trench isolation structure of claim 1, wherein the first isotropic etching process, the second isotropic etching process and the third isotropic etching process are wet etching processes or gas phase etching processes, and the first anisotropic etching process and the second anisotropic etching process are dry etching processes.
3. The method of forming a shallow trench isolation structure of claim 2 wherein the etching solution of the first isotropic etching process comprises: hydrofluoric acid, wherein the etching selection ratio of the hydrofluoric acid to the insulating material layer is greater than: 40:1.
4. The method of forming a shallow trench isolation structure of claim 2 wherein the etching gas of the first anisotropic etching process comprises: the etching selectivity ratio of the etching gas to the insulating material layer is greater than: 2:1.
5. The method of forming a shallow trench isolation structure of claim 1 wherein after said re-etching back said layer of insulating material in said shallow trench using a third isotropic etch process, the top surface of said remaining layer of insulating material is higher than the bottom surface of said floating gate layer,and the height of the top surface of the remaining insulating material layer above the bottom surface of the floating gate layer is:
6. the method for forming the shallow trench isolation structure according to claim 1, wherein after the third isotropic etching process is used to etch back the insulating material layer in the shallow trench again, the top of the remaining insulating material layer is made to be V-shaped or U-shaped.
7. The method of forming a shallow trench isolation structure of claim 1 wherein the step of forming the gate stack, shallow trench, insulating material layer on the semiconductor substrate comprises:
forming the gate oxide layer, the floating gate layer and the hard mask layer on the semiconductor substrate from bottom to top in sequence;
etching the floating gate layer, the gate oxide layer and the semiconductor substrate with partial thickness by using the hard mask layer as a mask and adopting a self-alignment type double-pattern process to form a plurality of gate stack structures, wherein the shallow trenches are arranged between the adjacent gate stack structures;
depositing an insulating material layer in the shallow trench, wherein the insulating material layer at least fills the trench;
and performing top planarization on the insulating material layer until the top surface of the insulating material layer is flush with the top surface of the gate stack structure.
8. The method of forming a shallow trench isolation structure of claim 1, further comprising:
and sequentially forming an inter-gate dielectric layer and a control gate layer on the semiconductor substrate, wherein the inter-gate dielectric layer covers the surface of each floating gate layer, and the control gate layer covers the surface of the inter-gate dielectric layer.
9. The method for forming a shallow trench isolation structure according to claim 1, wherein the hard mask layer is a single layer structure of a nitride layer or an oxide layer, or the hard mask layer is a multi-layer structure of an ONO stack.
10. The method of forming the shallow trench isolation structure of any of claims 1-9 wherein prior to etching the floating gate layer using the second anisotropic etch process, sidewalls of the floating gate layer are covered with a remaining layer of insulating material; and when the top surface of the floating gate layer is etched by adopting a second anisotropic etching process, removing the redundant insulating material layer covered on the side wall of the floating gate layer, and further etching the exposed side wall of the floating gate layer to reduce the line width of the floating gate layer.
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| US20020020887A1 (en) * | 2000-08-01 | 2002-02-21 | Keum-Joo Lee | Shallow trench isolation type semiconductor device and method of forming the same |
| KR20090000987A (en) * | 2007-06-29 | 2009-01-08 | 주식회사 하이닉스반도체 | Method of manufacturing a flash memory device |
| CN109216259A (en) * | 2018-09-20 | 2019-01-15 | 武汉新芯集成电路制造有限公司 | A kind of production method of memory |
| CN110854120A (en) * | 2019-11-27 | 2020-02-28 | 上海华力微电子有限公司 | Method for forming semiconductor |
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| US20020020887A1 (en) * | 2000-08-01 | 2002-02-21 | Keum-Joo Lee | Shallow trench isolation type semiconductor device and method of forming the same |
| KR20090000987A (en) * | 2007-06-29 | 2009-01-08 | 주식회사 하이닉스반도체 | Method of manufacturing a flash memory device |
| CN109216259A (en) * | 2018-09-20 | 2019-01-15 | 武汉新芯集成电路制造有限公司 | A kind of production method of memory |
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Application publication date: 20210824 |