CN102637645B - Preparation method of memory - Google Patents
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- CN102637645B CN102637645B CN 201110035566 CN201110035566A CN102637645B CN 102637645 B CN102637645 B CN 102637645B CN 201110035566 CN201110035566 CN 201110035566 CN 201110035566 A CN201110035566 A CN 201110035566A CN 102637645 B CN102637645 B CN 102637645B
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Abstract
The invention provides a preparation method of a memory, and belongs to the technical field of semiconductors. The method comprises the following steps: preparing a memory word line, as well as a control grid and a floating gate of a memory bit unit on a semiconductor substrate sequentially; etching a second coupling conductive layer in steps; and preparing extraction electrodes of other semiconductors on the substrate under a condition of not destroying and influencing the structure of the memory. In the method, a split-gate flash memory realizes that the chip area can be effectively reduced, and the problem of over erase can be avoided, under a condition of constant electric isolation performance of the chip by memories sharing the word line. Furthermore, the preparation method of the memory can be used for preparing the extraction electrodes of other semiconductor devices on the chip without damaging or influencing the extraction electrode of the memory, and the process difficulty is not increased.
Description
Technical field
The present invention relates to a kind of memory preparation method, be specifically related to gate-division type flash memory memory preparation method, belong to technical field of semiconductors.
Background technology
Flash memory is convenient with it, and storage density is high, and the advantages such as good reliability become the focus of studying in the non-volatility memorizer.Since first flash memory products comes out from the 1980s, development and the demand of each electronic product to storing along with technology, flash memory is widely used in mobile phone, notebook, in the movement such as palmtop PC and USB flash disk and the communication apparatus, flash memory is a kind of non-volatility memory, its operation principles is to control the switch of gate pole passage to reach the purpose of storage data by the critical voltage that changes transistor or memory cell, make the data that are stored in the memory can be because power interruptions does not disappear, and flash memory be a kind of special construction of electric erasable and programmable read-only memory.Nowadays flash memory has occupied most of market share of non-volatile semiconductor memory, becomes non-volatile semiconductor memory with fastest developing speed.
Yet existing flash memory is in the high storage density of marching toward more, owing to be subject to the restriction of program voltage, improve storage density by reduction of device size and will face very large challenge, thereby the flash memory of development high storage density is the important impetus of flash memory technology development.Traditional flash memory owing to be subject to the restriction of structure, realizes that the program voltage of device further reduces to be faced with very large challenge in the high storage density of marching toward more.Generally speaking, flash memory is the combination of grid dividing structure or stacking gate structure or two kinds of structures.Gate-division type flash memory is because its special structure, compare the stacking gate flash memory and all embody its unique performance advantage in programming with when wiping, therefore minute grid formula structure is owing to have high programming efficiency, and the structure of word line can be avoided advantages such as " cross and wipe ", uses particularly extensive.Thereby but since gate-division type flash memory with respect to the stacking gate flash memory many word line so that the area of chip also can increase, for the memory cell than high assembled density is introduced semiconductor storage unit, the layout of memory device circuit also must adopt more and more less size thereupon.In order to solve by the caused variety of issue of the High Density Packaging of memory cell, must improve the structure of semiconductor storage unit.
In addition, in the improved while of memory device structures, because each bit line must connect a conducting metal contact wire in the memory array, therefore quite highdensity metal wire must be arranged on disk.And the density that increases the unit will increase the density of metal wire, and is so very difficult on making, because required covering with etch step will need to produce very careful line.Therefore, increase the scheme of its density to the requirement height very of technique by the mode that increases number of memory cells, be not suitable for popularizing and promoting.
Summary of the invention
The technical problem to be solved in the present invention is: a kind of memory preparation method is provided, it can be in the constant situation of the electric isolation performance that keeps chip, effectively dwindle the area of chip, also can avoid simultaneously the problem of wiping, when improving density of memory arrays, ensureing the extraction electrode quality, finish the preparation of other semiconductor device extraction electrodes on memory extraction electrode and the chip.
For solving the problems of the technologies described above, memory preparation method provided by the invention may further comprise the steps:
(1) provides semi-conductive substrate, have active device region on it;
(2) on Semiconductor substrate, form successively first medium layer, the first conducting shell, second medium layer, the second conducting shell and the first etching barrier layer;
(3) the first etching barrier layer uplifting window mouth in active device region, and form the first spacer medium layer at its sidewall;
(4) make mask with the first etching barrier layer and the first spacer medium layer, etching the second conducting shell, second medium layer, the first conducting shell obtain being positioned at first groove on semiconductor structure surface to exposing first medium layer surface successively;
(5) in the first groove, fill the first coupling conducting shell and extremely remain basically stable with the first etching barrier layer surface, and at its surface deposition the second etching barrier layer;
(6) remove the first etching barrier layer, and make mask with the second etching barrier layer and the first spacer medium layer, remove successively the second conducting shell of being positioned at semiconductor substrate surface, second medium layer, the first conducting shell, first medium layer to exposing semiconductor substrate surface;
(7) body structure surface that obtains in step (6) deposits the 3rd dielectric layer, the 3rd etching barrier layer successively, and photoetching composition is removed active device region outer the 3rd dielectric layer, the 3rd etching barrier layer;
(8) body structure surface that obtains in step (7) deposits the 4th dielectric layer, the second coupling conducting shell successively, and photoetching composition is removed the second coupling conducting shell, the 3rd etching barrier layer that covers the active device region surface successively;
(9) photoetching composition forms the electrode that is connected with external power.
Further, step (2) also comprises the step that forms the STI fleet plough groove isolation structure, and it specifically comprises:
(201) on Semiconductor substrate, form successively first medium layer, the first conducting shell, STI etching barrier layer;
(202) at STI etching barrier layer uplifting window mouth, etching the first conducting shell, first medium layer and part semiconductor substrate form the sti trench groove successively;
(203) fill insulant in the sti trench groove, and remove STI etching barrier layer and unnecessary packing material, obtain the STI fleet plough groove isolation structure;
(204) body structure surface that obtains in step (203) forms second medium layer, the second conducting shell and the first etching barrier layer successively.
Further, step (4) comprising:
(401) etching the second conducting shell, second medium layer are to exposing the first conducting shell surface; (402) form the second spacer medium layer at the second conducting shell sidewall;
(403) etching the first conducting shell, first medium layer are to exposing semiconductor substrate surface;
(404) form the 3rd spacer medium layer at first medium layer, the first conducting shell sidewall, the first spacer medium layer, the second spacer medium layer and the semiconductor substrate surface that exposes.
Further, first medium layer and the 4th dielectric layer are gate oxide, and its thickness is
Further, second medium layer, the second spacer medium layer are insulating medium layer, and its dielectric material is a kind of or any several composite construction in silicon dioxide, silicon nitride, silicon oxynitride, the carbon containing Si oxide.Wherein, the second medium layer thickness is
The second spacer medium layer at the width range of orientation is
Further, the 3rd buffer layer is tunnel oxide, and its dielectric material is silica or silicon nitride or the composite construction of the two, and its width range in orientation is
Its thickness is
Further, the first conducting shell dielectric material is polysilicon or silicon nitride or nano crystal material with conductivity; The second conducting shell dielectric material is polysilicon or metal; The first coupling conducting shell, the second coupling conducting shell dielectric material are polysilicon or metal.
Further, the first etching barrier layer, the 3rd etching barrier layer dielectric material are silicon nitride.
Further, the first spacer medium layer, the second etching barrier layer, the 3rd dielectric layer are silicon dioxide, and wherein, the 3rd thickness of dielectric layers is
Further, first is coupled conducting shell as the word line, and forms simultaneously the grid of memory cell; Remaining the first conducting shell, the second conducting shell are respectively as floating boom and the control gate of memory in the step (6).
Technique effect of the present invention is, this memory preparation method uses same word line by two storage bit unit are shared, with to the word line, two control gates and memory source drain region apply different operating voltages and realize storage bit unit read, wipes and adopt the programming action that the hot electron injection mode is carried out.In the method, the memory of shared word line so that gate-division type flash memory its can in the constant situation of the electric isolation performance that keeps chip, effectively dwindle chip area, also can avoid the problem of wiping simultaneously.In addition, memory preparation method provided by the invention has realized the preparation of other semiconductor device extraction electrodes on the chip, and has not increased technology difficulty in the situation on memory extraction electrode injury and impact not.
Description of drawings
Fig. 1 is memory preparation method flow chart provided by the invention;
Fig. 2 is step (2) flow chart among the memory preparation method provided by the invention;
Fig. 3 is step (4) flow chart among the memory preparation method provided by the invention;
Fig. 4-Figure 21 is the cross-sectional view of each step of memory preparation method provided by the invention;
Figure 22 is the memory construction schematic diagram that memory preparation method provided by the invention obtains.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
Fig. 1 is memory preparation method flow chart provided by the invention.
As shown in Figure 1, the memory preparation method that provides of this embodiment comprises:
Step S1: semi-conductive substrate 100 is provided.
In this step, Semiconductor substrate is generally silicon substrate or SOI substrate.As shown in Figure 4, have active device area 010 and other device areas 020 on the Semiconductor substrate 100.
Step S2: 100 form first medium layer 101, the first conducting shell 110, second medium layer 102, the second conducting shell 120 and the first etching barrier layer 111 successively on Semiconductor substrate.
This step also comprises the step that forms STI fleet plough groove isolation structure 200 or ACT isolation structure.
Fig. 2 is step S2 flow chart among the memory preparation method provided by the invention.
As shown in Figure 2, to form the STI fleet plough groove isolation structure as example, step S2 specifically comprises:
Step S201: on Semiconductor substrate 100, form successively first medium layer 101, the first conducting shell 110, STI etching barrier layer 131;
Step S202: at STI etching barrier layer 131 uplifting window mouths, etching the first conducting shell 110, first medium layer 101 and part semiconductor substrate 100 form sti trench groove 132 successively;
Step S203: fill insulant in sti trench groove 132, and remove STI etching barrier layer 131 and unnecessary packing material, obtain STI fleet plough groove isolation structure 200;
Step S204: the body structure surface that obtains at step S203 forms second medium layer 102, the second conducting shell 120 and the first etching barrier layer 111 successively.
Among the step S201, as shown in Figure 5, first medium layer 101 is gate oxide, and its dielectric material is generally silicon dioxide or silicon oxynitride.Along with further dwindling of device feature size, the material of first medium layer 101 is preferably the high dielectric constant materials such as hafnium oxide, zirconia, aluminium oxide, to reduce the leakage current of device.The preparation technology of first medium layer 101 can be chemical vapour deposition (CVD) (CVD), plasma enhanced chemical vapor deposition (PECVD) or thermal oxidation method etc.In this embodiment, the thickness of first medium layer 101 is
More excellent, the thickness of first medium layer 101 is
In this step, the first conducting shell 110 is in order to preparing the floating boom FG of memory, and its dielectric material is polysilicon or silicon nitride or nano crystal material with conductivity, for obtaining preferably electric property, usually impurity particle in polycrystalline silicon material, as: N-type foreign matter of phosphor or p type impurity boron.The method that forms the first conducting shell 110 comprises: chemical vapour deposition (CVD) (CVD), physical vapour deposition (PVD) (PVD), plasma enhanced chemical vapor deposition (PECVD) etc.In this embodiment, the thickness of the first conducting shell 110 is
More excellent, the thickness of the first conducting shell 110 is
In this step; STI etching barrier layer 131 is used for forming STI fleet plough groove isolation structure 200 processes as mask layer; protection active device area 010 and during other each film layer structure of area 0 20 be not etched; its dielectric material is a kind of or any several composite construction in silicon nitride, carborundum, silicon oxynitride, the carbon containing Si oxide, and its preparation technology can be chemical vapour deposition (CVD) (CVD).
Among the step S202, as shown in Figure 6, at the boundary of active device region 010 and other device areas 020, at STI etching barrier layer 131 surperficial windowings, and remove successively the first conducting shell 110, first medium layer 101 and part semiconductor substrate 100 take it as mask, form sti trench groove 132.In this step, STI etching barrier layer 131 windowings adopt the method for chemical wet etching to realize, the removal of second medium layer 102, the first conducting shell 110, first medium layer 101 and on the Semiconductor substrate 100 that exposes etching to form groove volume technique be any prior art well known to those skilled in the art.
Among the step S203, as shown in Figure 7, fill insulant in sti trench groove 132 forms STI fleet plough groove isolation structure 200, and removes STI etching barrier layer 131 and unnecessary packing material.In this step, the insulating material of filling in the sti trench groove 132 is any material for the preparation of the STI/ACT isolation structure well known to those skilled in the art.The removal of STI etching barrier layer 131 adopts wet corrosion technique to carry out, and unnecessary packing material is removed and the formation of complete S TI fleet plough groove isolation structure 200 also comprises the planarization process that adopts cmp method etc.
Step S204, as shown in Figure 8, the body structure surface that obtains at step S203 forms second medium layer 102, the second conducting shell 120 and the first etching barrier layer 111 successively.
In this step, second medium layer 102 is the insulation interlayer dielectric layer, its dielectric material is a kind of or any several composite construction in silicon dioxide, silicon nitride, silicon oxynitride, the carbon containing Si oxide, and its preparation technology can be chemical vapour deposition (CVD) (CVD).In this embodiment, the thickness of second medium layer 102 is
More excellent, the thickness of second medium layer 102 is
In this step, the second conducting shell 120 is in order to prepare the control gate CG of memory, its dielectric material is polysilicon or metal, when its material is polysilicon, the doping type of the polysilicon in principle doping type with Semiconductor substrate is identical, and its preparation technology can be chemical vapour deposition (CVD) (CVD) etc.In this embodiment, the thickness of the second conducting shell 120 is
More excellent, the thickness of the second conducting shell 120 is
In this step, the first etching barrier layer 111 is used at subsequently etching technics as mask layer, protects the rete below it not to be etched, and its dielectric material is silicon nitride, and its preparation technology can be chemical vapour deposition (CVD) (CVD).In this embodiment, the thickness of the first etching barrier layer 111 is
More excellent, the thickness of the first etching barrier layer 111 is
In concrete preparation technology, this step is selected corresponding STI or ACT isolation structure according to different components size and semiconductor technology.
Step S3: the first etching barrier layer 111 uplifting window mouths in active device region 010, and form the first spacer medium layer 201 at its sidewall.
In this step, as shown in Figure 9, the technique of the first etching barrier layer 111 uplifting window mouths is any prior art well known to those skilled in the art in active device region 010, for example: adopt spin coating proceeding to form photoresist layer at the first etching barrier layer 111, then adopt exposure, developing process to process, remove the photoresist on the setting regions, form the photoresist opening, at last take photoresist as mask, etching the first etching barrier layer 111 is transferred to the patterns of openings on the photoresist on the first etching barrier layer 111.
In this step, as shown in figure 10, the sidewall of institute's windowing forms the first spacer medium layer 201 on the first etching barrier layer 111.This first spacer medium layer 201 is positioned at two sidewalls of window, peripheral profile is arc, its formation technique that forms side wall in technique and the semiconductor preparing process is approximate, can for: in institute's windowing the deposition the first spacer medium material, adopt this first spacer medium material of plasma etching industrial etching, and in plasma etch process, carry out simultaneously chemical etching and physical bombardment, remove the first spacer medium material of window mid portion, after etching technics is finished, namely form the first spacer medium layer 201 of arc at two sidewalls of window.In this embodiment, the dielectric material of the first spacer medium layer 201 is silicon dioxide.
Step S4: make mask with the first etching barrier layer 111 and the first spacer medium layer 201, be etched to and expose first medium layer 101 surface, obtain being positioned at first groove 210 on semiconductor structure surface.
Fig. 3 is step S4 flow chart among the memory preparation method provided by the invention.
As shown in Figure 3, step S4 specifically may further comprise the steps:
Step S401: etching the second conducting shell 120, second medium layer 102 are to exposing the first conducting shell 110 surfaces;
Step S402: form the second spacer medium layer 202 at the second conducting shell 120 sidewalls;
Step S403: etching the first conducting shell 110, first medium layer 101 are to exposing Semiconductor substrate 100 surfaces;
Step S404: form the 3rd spacer medium layers 203 at first medium layer 101, the first conducting shell 110 sidewalls, the first spacer medium layer 201, the second spacer medium layer 202 and Semiconductor substrate 100 surface that exposes.
Among step S401, the step S402, as shown in figure 11, make mask with the first etching barrier layer 111 and the first spacer medium layer 201, etching the second conducting shell 120, second medium layer 102 are to exposing the first conducting shell 110 surfaces successively.The etching technics of the second conducting shell 120, second medium layer 102 is any prior art well known to those skilled in the art.After etching is finished, form the second spacer medium layer 202 at the second conducting shell 120 sidewalls.This second spacer medium layer is positioned at the second conducting shell 120 sidewalls, peripheral profile is arc, its formation technique that forms side wall in technique and the semiconductor preparing process is approximate, can be in the groove that etching forms deposition the second spacer medium material, adopt this second spacer medium material of plasma etching industrial etching, and in plasma etch process, carry out simultaneously chemical etching and physical bombardment, remove the second spacer medium material of window mid portion, after etching technics is finished, namely form the second spacer medium layer 202 of arc at the second conducting shell 120 sidewalls.
In this step, the second spacer medium layer 202 is insulating medium layer, be used for the second conducting shell 120 and the first coupling conducting shell 211 that forms are subsequently kept apart, its dielectric material is a kind of or any several composite construction in silicon dioxide, silicon nitride, silicon oxynitride, the carbon containing Si oxide.In this embodiment, the second spacer medium layer 202 at the width range of orientation is
More excellent, the second spacer medium layer 202 at the width range of orientation is
Among step S403, the step S404, as shown in figure 12, make mask with the first etching barrier layer 111 and the first spacer medium layer 201, the second spacer medium layer 202, etching the first conducting shell 110, first medium layer 101 are to exposing Semiconductor substrate 100 surfaces, wherein, the etching technics of the first conducting shell 110, first medium layer 101 is any prior art well known to those skilled in the art.After etching is finished, form the 3rd spacer medium layers 203 at the first conducting shell 110 sidewalls and Semiconductor substrate 100 surface that exposes.The 3rd spacer medium layer is positioned at first medium layer 101, the first conducting shell 110 sidewalls and the first spacer medium layer 201, the second spacer medium layer 202 side surface, peripheral profile is arc, and cover and to be positioned at the first groove 210 bottoms, Semiconductor substrate 100 surfaces that expose, its formation technique that forms side wall in technique and the semiconductor preparing process is approximate, can be in the groove that etching forms deposition the 3rd spacer medium material, adopt plasma etching industrial etching the 3rd spacer medium material, and in plasma etch process, carry out simultaneously chemical etching and physical bombardment, remove the 3rd unnecessary spacer medium material of window mid portion, after etching technics is finished, namely at first medium layer 101, the first conducting shell 110 sidewalls and the first spacer medium layer 201, the second spacer medium layer 202 surface forms the 3rd spacer medium layers 203 of arcs, and covers and be positioned at the first groove 210 bottoms, Semiconductor substrate 100 surfaces that expose.
In this step, the 3rd spacer medium layer 203 is tunnel oxide, and the first coupling conducting shell 211 that is used for forming is subsequently kept apart with the first conducting shell 110 and Semiconductor substrate 100, and realizes the programming operations such as read-write of memory.The dielectric material of the 3rd spacer medium layer 203 is silica or silicon nitride or the composite construction of the two.In this embodiment, the 3rd spacer medium layer 203 at the width range of orientation is
More excellent, the 3rd spacer medium layer 203 at the width range of orientation is
Its thickness is
In this step, related etching technics is dry plasma etch or reactive ion etching, also can select wet corrosion technique.According to the variation of dielectric layer material, the etching agent that conversion is different is prior art well known to those skilled in the art in the etching process.
Step S5: at interior fillings the first coupling conducting shells 211 of the first groove 210 to remaining basically stable with the first etching barrier layer 111 surfaces, and at its surface deposition the second etching barrier layer 112.
In this step, as shown in figure 13, in the first groove 210, fill the first coupling conducting shell 211, its preparation technology is: at first adopt chemical vapour deposition (CVD) (CVD) technique to fill the first coupling conducting shell 211 in the first groove 210, adopt subsequently chemico-mechanical polishing (CMP) technique to carry out planarization to exposing part the first spacer medium layer 201, thus guarantee the first coupling conducting shell 211 surfaces planarization and with the remaining basically stable of the first etching barrier layer 111 surfaces.
This first coupling conducting shell 211 is the word line WL in the memory array, and forms the grid G of memory cell, and its material is polysilicon or metal.
In this step, as shown in figure 14, form the second etching barrier layer 112 on the first coupling conducting shell 211 surfaces.The second etching barrier layer 112 plays the effect of protective layer; in etching technics subsequently the protected storage structure and be positioned at wherein first the coupling conducting shell 211; its dielectric material is silicon dioxide, and the thickness of the second etching barrier layer 112 is greater than first medium layer 101 thickness and second medium layer 102 thickness sum.
Step S6: remove the first etching barrier layer 111, make mask etching to exposing Semiconductor substrate 100 surfaces with the second etching barrier layer 112 and the first spacer medium layer 201
In this step, as shown in figure 15, at first remove the first etching barrier layer 111, this process adopts wet corrosion technique to carry out, and optional corrosive agent is hot phosphoric acid etc.
In this step, as shown in figure 16, make mask with the second etching barrier layer 112 and the first spacer medium layer 201, remove successively the second conducting shell 120, second medium layer 102, the first conducting shell 110 and the first medium layer 101 of other positions, to exposing Semiconductor substrate 100 surfaces.The first conducting shell 110 that keeps after the etching is the floating boom FG of gate-division type flash memory memory, and the second conducting shell 120 that keeps after the etching is the control mountain CG of gate-division type flash memory memory.In this step, the technique that etching is removed above-mentioned dielectric layer is any prior art well known to those skilled in the art.
In this step, because the second etching barrier layer 112 is silicon dioxide, in the process of the second medium layer 102 of removing other positions take it as mask, first medium layer 101, the second etching barrier layer 112 also is removed, after this step is finished, removed fully synchronously or removed substantially fully as the second etching barrier layer 112 of mask.
Step S7: the body structure surface that obtains at step S6 deposits the 3rd dielectric layer 103, the 3rd etching barrier layer 113 successively, and photoetching composition is removed the 3rd dielectric layer 103, the 3rd etching barrier layer 113 of other area 0s 20 on the Semiconductor substrate 100.
In this step, as shown in figure 17, the 3rd dielectric layer 103 is silicon dioxide layer, and its preparation technology can be chemical vapour deposition (CVD) (CVD), plasma enhanced chemical vapor deposition (PECVD) or thermal oxidation method etc.In this implementation, the 3rd dielectric layer 103 thickness are
More excellent, the thickness of the 3rd dielectric layer 103 is
The 3rd etching barrier layer 113 dielectric materials are silicon nitride, and its preparation technology can be chemical vapour deposition (CVD) (CVD).In this embodiment, the thickness of the 3rd etching barrier layer 113 is
More excellent, the thickness of the 3rd etching barrier layer 113 is
In this step, as shown in figure 18, photoetching composition will cover the 3rd etching barrier layer 113 and the 3rd dielectric layer 103 of other area 0s 20 on the Semiconductor substrate 100 and remove, and photoetching, etching/techniques such as corrosion that this process adopts are prior art well known to those skilled in the art.The 3rd etching barrier layer 113 on covering active device region 010 surface and the 3rd dielectric layer 103 are not damaged for the memory construction that has prepared in the protection of subsequent technique process and are affected.
Step S8: the body structure surface that obtains at step S7 deposits the 4th dielectric layer 104, the second coupling conducting shell 212 successively, and photoetching composition is removed the second coupling conducting shell 212, the 3rd etching barrier layer 113, the 4th dielectric layer 104 that covers active device region 010 surface successively.
In this step, as shown in figure 19, the body structure surface that obtains at step S7 deposits the 4th dielectric layer 104, the second coupling conducting shell 212 successively, and its preparation technology is chemical vapour deposition (CVD) (CVD) method.Wherein, the 4th dielectric layer 104 is gate oxide, and its thickness is
The dielectric material of the second coupling conducting shell 212 is polysilicon or metal, for the preparation of extraction electrode.
In this step, as shown in figure 20, photoetching composition is removed the second coupling conducting shell 212, the 3rd etching barrier layer 113, the 4th dielectric layer 104 that covers active device region 010 surface successively.The method of dry etching realizes that using plasma etching or reactive ion etching process are etched to and expose the 3rd etching barrier layer 113 surfaces behind the available photoetching composition of removal of the second coupling conducting shell 212; The removal of the 3rd etching barrier layer 113 and the 4th dielectric layer 104 can adopt wet corrosion technique subsequently to carry out, and optional corrosive agent is hot phosphoric acid, hydrofluoric acid etc.
Step S9: photoetching composition forms the electrode that is connected with external power.
In this step, as shown in figure 21, other area 0s 20 on Semiconductor substrate 100 are interior according to the project organization photoetching composition, and remove unnecessary the second coupling conducting shell 212, the 4th dielectric layer 104, form other semiconductor device are connected with external power on the Semiconductor substrate 100 electrode and gate oxide thereof.In this process, the removal technique of unnecessary the second coupling conducting shell 212 and the 4th dielectric layer 104 is prior art well known to those skilled in the art.
Among the memory preparation method that this embodiment provides, also comprise form the memory cell source dopant region, leak doped region and with the bit line that the source/leakages doped region is connected, the spacer side wall of word line WL/ grid side and the processes such as metal connection of routine, the realization of these structures can be adopted any prior art well known to those skilled in the art.
Figure 22 is the memory construction schematic diagram that memory preparation method provided by the invention obtains.
As shown in figure 22, have active device region 010 and other area 0s 20 of STI shallow trench 200 isolation on the Semiconductor substrate 100, memory Cell 1, Cell 2 are positioned at active device region 010.The memory construction that the memory preparation method that this embodiment provides obtains is the gate-division type flash memory memory, each memory cell comprises two storage bit unit, floating boom FG and interval that each storage bit unit has respectively 110 formation of the first conducting shell arrange the control gate CG that the second conducting shell 120 on it forms, and two storage bit unit share word lines 211.In this memory construction, be provided with tunnel oxide (that is: the 3rd spacer medium layer 203) between word line 211 and floating boom FG (that is: the first conducting shell 110) and the Semiconductor substrate 100; Be provided with gate oxide between floating boom FG (that is: the first conducting shell 110) and the Semiconductor substrate 100; Be provided with interlayer dielectric layer (that is: the second medium layer 102) between floating boom FG (that is: the first conducting shell 110) and the control gate CG (i.e. the second conducting shell 120).Storage bit unit is wiped electric charge by adding high pressure at word line 211, and the programming action then adopts the hot electron injection mode to carry out.
As shown in figure 22, be provided with some memory cells in Semiconductor substrate 100 active device regions 010, has groove between the neighbor memory cell, therefore, other area 0s 20 form in the extraction electrode process of other semiconductor device on the substrate on Semiconductor substrate 100, when the second coupling conducting shell 212 is carried out etching, have some grooves on the active device region 010, other area 0s 20 relatively flat then on the Semiconductor substrate 100, two regional structure patterns have than big difference, etching is removed unnecessary the second coupling conducting shell 212 required process conditions and also is not quite similar, therefore, among the memory preparation method that this embodiment provides, the etching of the second coupling conducting shell 212 is carried out in two steps, all satisfied for different etching conditions thereby make in the etching process, and can be on not prepared semiconductor structure injury and the impacts such as memory of finishing on the Semiconductor substrate 100.
As shown in figure 22, on the Semiconductor substrate 100 on other area 0s 20 word line 211 sides of other semiconductor device extraction electrodes 212 and memory Cell 1, Cell 2 all have spacer side wall 213, its preparation method can be any method well known to those skilled in the art, and its dielectric material is silica or porous silica.
As most preferred embodiment, among the memory preparation method that this embodiment provides, first medium layer 101, second medium layer 102, the 3rd dielectric layer 103, the second etching barrier layer 112, the first spacer medium layer 201, the second spacer medium layer 202, the 3rd spacer medium layer 203 are silicon dioxide; The first conducting shell 110, the second conducting shell 120, the first coupling conducting shell 211, the second coupling conducting shell 212 are polysilicon; The first etching barrier layer 111, the 3rd etching barrier layer 113 are silicon nitride.Wherein, the thickness of first medium layer 101 is
The thickness of second medium layer 102 is
The thickness of the 3rd dielectric layer 103 is
The thickness of the first conducting shell 110 is
The thickness of the second conducting shell 120 is
The thickness of the first etching barrier layer 111 is
The thickness of the 3rd etching barrier layer 113 is
The second spacer medium layer 202 at the width of trench length direction is
The 3rd spacer medium layer 203 at the width range of orientation is
Thickness is
At this moment, wipe electric charge by applying high pressure at word line 211 on the storage bit unit, and adopt polysilicon then to adopt the hot electron injection mode to carry out the erase mode between the polysilicon to reduce erasing voltage, to programme to move.
As optional embodiment, among the memory preparation method that this embodiment provides, first medium layer 101 is silicon dioxide for, second medium layer 102, the 3rd dielectric layer 103, the second etching barrier layer 112, the first spacer medium layer 201, the second spacer medium layer 202, the 3rd spacer medium layer 203; The first conducting shell 110, the second conducting shell 120 are polysilicon, and the first coupling conducting shell 211, the second coupling conducting shell 212 are metal; The first etching barrier layer 111, the 3rd etching barrier layer 113 are silicon nitride.Wherein, the thickness of first medium layer 101 is
The thickness of second medium layer 102 is
The thickness of the 3rd dielectric layer 103 is
The thickness of the first conducting shell 110 is
The thickness of the second conducting shell 120 is
The thickness of the first etching barrier layer 111 is
The thickness of the 3rd etching barrier layer 113 is
The second spacer medium layer 202 at the width of trench length direction is
The 3rd spacer medium layer 203 at the width range of orientation is
Thickness is
At this moment, wipe electric charge by applying high pressure at word line 211 on the storage bit unit, the programming action then adopts the hot electron injection mode to carry out.
The memory preparation method that this embodiment provides, by being shared, two storage bit unit use same word line 211, realize storage bit unit read, wipes and adopt the programming action that the hot electron injection mode is carried out 211, two control gates of word line (that is: the second conducting shell 120) and memory source drain region are applied different operating voltages.In the method, the memory of shared word line 211 so that gate-division type flash memory its can in the constant situation of the electric isolation performance that keeps chip, effectively dwindle chip area, also can avoid the problem of wiping simultaneously.In addition, memory preparation method provided by the invention has realized the preparation of other semiconductor device extraction electrodes on the chip, and has not increased technology difficulty in the situation on memory extraction electrode injury and impact not.
In situation without departing from the spirit and scope of the present invention, can also consist of many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the specific embodiment described in the specification.
Claims (10)
1. memory preparation method, step comprises:
(1) provides semi-conductive substrate, have active device region on it;
(2) on described Semiconductor substrate, form successively first medium layer, the first conducting shell, second medium layer, the second conducting shell and the first etching barrier layer;
(3) the first etching barrier layer uplifting window mouth in described active device region, and form the first spacer medium layer at its sidewall;
(4) make mask with the first etching barrier layer and the first spacer medium layer, described the second conducting shell of etching, second medium layer, the first conducting shell and first medium layer obtain being positioned at first groove on semiconductor structure surface until expose the surface of Semiconductor substrate successively;
(5) fill successively the 3rd spacer medium layer and the first coupling conducting shell in described the first groove, described the first coupling conducting shell and described the first etching barrier layer surface maintain an equal level, and at its surface deposition the second etching barrier layer;
(6) remove described the first etching barrier layer, and make mask with described the second etching barrier layer and the first spacer medium layer, remove successively the second conducting shell of being positioned at described semiconductor substrate surface, second medium layer, the first conducting shell, first medium layer to exposing described semiconductor substrate surface;
(7) body structure surface that obtains in step (6) deposits the 3rd dielectric layer, the 3rd etching barrier layer successively, and photoetching composition is removed described active device region outer the 3rd dielectric layer, the 3rd etching barrier layer;
(8) body structure surface that obtains in step (7) deposits the 4th dielectric layer, the second coupling conducting shell successively, and photoetching composition is removed the second coupling conducting shell, the 4th dielectric layer and the 3rd etching barrier layer that covers described active device region surface successively;
(9) photoetching composition is removed outer the second unnecessary coupling conducting shell and the 4th dielectric layer of described active device region, forms the electrode that is connected with external power.
2. memory preparation method according to claim 1 is characterized in that, described step (2) comprises the step that forms the STI fleet plough groove isolation structure, and it specifically comprises:
(201) on described Semiconductor substrate, form successively first medium layer, the first conducting shell and STI etching barrier layer;
(202) at described STI etching barrier layer uplifting window mouth, etching the first conducting shell, first medium layer and part semiconductor substrate form the sti trench groove successively;
(203) fill insulant in described sti trench groove, and remove described STI etching barrier layer and unnecessary packing material, obtain the STI fleet plough groove isolation structure;
(204) body structure surface that obtains in step (203) forms second medium layer, the second conducting shell and the first etching barrier layer successively.
3. memory preparation method according to claim 1 and 2 is characterized in that, described step (4) comprising:
(401) described the second conducting shell of etching, second medium layer are to exposing the first conducting shell surface;
(402) form the second spacer medium layer at described the second conducting shell sidewall;
(403) described the first conducting shell of etching, first medium layer are to exposing described semiconductor substrate surface;
(404) form the 3rd spacer medium layer at described first medium layer, the first conducting shell sidewall, described the first spacer medium layer, the second spacer medium layer and the semiconductor substrate surface that exposes.
4. memory preparation method according to claim 3 is characterized in that, described first medium layer and the 4th dielectric layer are gate oxide, and its thickness is
5. memory preparation method according to claim 3, it is characterized in that, described second medium layer, the second spacer medium layer are insulating medium layer, and its dielectric material is a kind of or any several composite construction in silicon dioxide, silicon nitride, silicon oxynitride, the carbon containing Si oxide; Wherein, described second medium layer thickness is
Described the second spacer medium layer at the width range of orientation is
6. memory preparation method according to claim 3 is characterized in that, described the 3rd buffer layer is tunnel oxide, and its dielectric material is silica or silicon nitride or the composite construction of the two, and its width range in orientation is
Its thickness is
7. memory preparation method according to claim 3 is characterized in that, the material of described the first conducting shell is polysilicon or silicon nitride or nano crystal material with conductivity; The material of described the second conducting shell is polysilicon or metal; Described the first coupling conducting shell, the second coupling conducting shell dielectric material are polysilicon or metal.
8. memory preparation method according to claim 3 is characterized in that, described the first etching barrier layer, the 3rd etching barrier layer dielectric material are silicon nitride.
9. memory preparation method according to claim 3 is characterized in that, described the first spacer medium layer, the second etching barrier layer, the 3rd dielectric layer are silicon dioxide, and wherein, described the 3rd thickness of dielectric layers is
10. memory preparation method according to claim 3 is characterized in that, described first is coupled conducting shell as the word line, and forms simultaneously the grid of memory cell; Remaining the first conducting shell, the second conducting shell are respectively as floating boom and the control gate of memory in the described step (6).
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109524406A (en) * | 2018-10-15 | 2019-03-26 | 上海华虹宏力半导体制造有限公司 | A kind of forming method of embedded flash memory structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104112656B (en) * | 2013-04-18 | 2016-11-02 | 中芯国际集成电路制造(上海)有限公司 | A kind of method improving flash memories peripheral circuit region reliability of the gate oxide |
| CN103413786B (en) * | 2013-08-22 | 2016-06-01 | 上海华虹宏力半导体制造有限公司 | The driving method of storage unit and forming method thereof, storage unit |
| CN103426826B (en) * | 2013-08-22 | 2016-09-28 | 上海华虹宏力半导体制造有限公司 | Flash cell and forming method thereof |
| CN104157616B (en) * | 2014-08-26 | 2017-02-22 | 上海华虹宏力半导体制造有限公司 | Flash memory unit and formation method thereof |
| CN104465525B (en) * | 2014-12-30 | 2017-12-08 | 上海华虹宏力半导体制造有限公司 | The forming method of embedded flash memory |
| CN105826273B (en) * | 2016-05-11 | 2019-03-08 | 上海华虹宏力半导体制造有限公司 | Flush memory device and its manufacturing method |
| CN105977208A (en) * | 2016-07-27 | 2016-09-28 | 上海华虹宏力半导体制造有限公司 | Control gate contact window region morphology improvement method |
| CN106024590A (en) * | 2016-07-27 | 2016-10-12 | 上海华虹宏力半导体制造有限公司 | Method for reducing size of control gate contact window region |
| CN109768046B (en) * | 2019-01-22 | 2021-01-29 | 上海华虹宏力半导体制造有限公司 | Method for forming embedded flash memory structure |
| CN110534412A (en) * | 2019-09-09 | 2019-12-03 | 上海华虹宏力半导体制造有限公司 | Avoid the method for phosphor doped polysilicon defect and the manufacturing method of memory cell |
| CN113809005B (en) * | 2021-09-17 | 2023-11-07 | 恒烁半导体(合肥)股份有限公司 | Manufacturing method and circuit of NOR flash memory and application of NOR flash memory |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1855442A (en) * | 2005-04-25 | 2006-11-01 | 联华电子股份有限公司 | Non-volatile memory unit and its production |
| CN1945798A (en) * | 2005-08-17 | 2007-04-11 | 三星电子株式会社 | Method of manufacturing a non-volatile memory device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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-
2011
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1855442A (en) * | 2005-04-25 | 2006-11-01 | 联华电子股份有限公司 | Non-volatile memory unit and its production |
| CN1945798A (en) * | 2005-08-17 | 2007-04-11 | 三星电子株式会社 | Method of manufacturing a non-volatile memory device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109524406A (en) * | 2018-10-15 | 2019-03-26 | 上海华虹宏力半导体制造有限公司 | A kind of forming method of embedded flash memory structure |
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